Memristive cross array voltage drop compensation method and device and computer equipment

Abstract

The invention relates to a memristor cross array voltage drop compensation method and device and computer equipment. The method comprises the following steps: acquiring an output current deviation between a column ideal output current of the memristor cross array and a column output current with introduced voltage drop, and determining the number of differential memristor adjustment rows required by each column according to the output current deviation and an adjustment voltage output by the last iteration, and setting conductance values of all memristive devices in the differential memristive adjustment rows, compensating the current deviation of each column according to the conductance values, and when the compensated maximum output current deviation of each column meets a threshold value, outputting the final row number and adjustment voltage of the differential memristive adjustment rows. According to the method, the rows can be adjusted through the multiple rows of differential memristors, and deviation current compensation can be achieved through low adjusting voltage.

Description

Technical Field

[0001] The present application relates to the technical field of memristor crossbar arrays, and in particular to a memristor crossbar array voltage drop compensation method, device and computer equipment. Background Art

[0002] In the von Neumann architecture, the storage component and the computing component are physically separated from each other, so when performing computing tasks, data needs to be transferred between the two. And compared with the computing component, which focuses on speed improvement, the development of the storage component is mainly about capacity improvement, resulting in a mismatch between the speeds of the two. In the past few decades, the performance improvement rate of the processor has been 5 to 6 times that of the memory. This performance development difference has caused the data access speed to lag seriously behind the computing speed. The data transmission between the storage component and the computing component has become one of the most critical performance and energy consumption bottlenecks of the von Neumann structure, which is the "storage wall" problem.

[0003] The von Neumann architecture can no longer meet the needs of neural networks for energy-efficient computing due to the constraints of problems such as the "storage wall". It is necessary to study new architectures that support neural network computing, such as in-memory computing. The crossbar array structure composed of memristors such as phase change memory (PCM) can complete single-step matrix multiplication and addition operations while storing data based on Kirchhoff's laws of physics, realizing an analog in-memory computing paradigm, and is a strong candidate for accelerating the neural network computing process.

[0004] The memristor consists of a top electrode, a metal oxide layer, and a bottom electrode. Taking a binary memristor as an example, its resistance state is divided into a high resistance state (HRS) and a low resistance state (LRS), representing logic "0" and logic "1" respectively. By changing the voltage across the device, its resistance state can be converted. The process of converting the device from a high resistance state to a low resistance state by applying a sufficiently large voltage across the memristor is called a SET operation, and the process of applying a reverse voltage to cause a reverse conversion is called a RESET operation. When no voltage is applied or when the voltage is small, the resistance state of the memristor remains relatively stable and can be regarded as a two-terminal passive resistance element. The readout process satisfies Ohm's law. Therefore, the result of the multiplication operation between the input voltage and the memristor conductance can be obtained by recording the current value flowing through the memristor. At the same time, in order to improve the integration of memristor chips, they generally appear in a cross array structure in practical applications.

[0005] To date, the idea of ​​using memristor crossbar arrays to accelerate the neural network computing process has been proven and demonstrated on a variety of physical array platforms, and a variety of neural network acceleration architectures based on memristor crossbar arrays have been proposed. Deploying trained neural network weights to the memristor crossbar array, and using the memristor crossbar array platform for accelerators for tasks such as image recognition, has become an important application direction for memristor neural networks. However, studies have found that in practical applications, there are a large number of non-ideal factors from devices and arrays in the memristor crossbar array, which seriously affect the calculation accuracy of the memristor crossbar array neural network accelerator. It is necessary to explore ways to solve the impact of non-ideal factors from multiple levels such as algorithms and circuit design to promote the practical application of memristor neural network accelerators. Summary of the invention

[0006] Based on this, it is necessary to provide a method, device and computer equipment for compensating voltage drop of a memristor crossbar array in order to solve the above technical problems.

[0007] A memristor cross array voltage drop compensation method is applied to a memristor cross array voltage drop compensation circuit, wherein the output ends of the forward array and the reverse array of the memristor cross array in the memristor cross array voltage drop compensation circuit are cascaded with a plurality of memristor adjustment rows respectively, so as to compensate for the deviation of the forward current of the forward array and the reverse current of the reverse array; the method comprises:

[0008] Obtaining an output current deviation between an ideal column output current of the memristor crossbar array and a column output current with a voltage drop introduced;

[0009] Determining the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage outputted in the previous round of iteration;

[0010] Setting a differential memristor to adjust the conductance value of all memristor devices in a row, and compensating for the current deviation of each column according to the conductance value;

[0011] When the maximum output current deviation of each column after compensation meets the threshold, the final number of differential memristor adjustment rows and the adjustment voltage are output.

[0012] In one embodiment, the method further includes: determining the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage outputted in the previous iteration:

[0013]

[0014] Among them, ΔI out [j] represents the output current deviation, V tune Indicates the regulation voltage, G max is the maximum conductance of the memristor, G minis the minimum conductance of the memristor, symbol represents rounding down, num[jn] represents the number of required differential memristor adjustment rows calculated in the current iteration, and m represents the number of maximum differential memristor adjustment rows.

[0015] In one embodiment, the invention further comprises: for the jth column, if the output voltage deviation is positive, adjusting the memristor conductance of the memristor row by the reverse differential memristor of the reverse array Set to G min ; The forward differential memristor of the forward array adjusts the memristor conductance of the row Adjust to:

[0016]

[0017] Among them, i and j are row and column coordinates respectively, G near represents the conductivity state;

[0018] If the output voltage deviation is negative, the opposite adjustment method is used to compensate the memristor conductance and memristor conductance

[0019] In one embodiment, the method further includes: determining the output current I[j] of the jth column after compensation as:

[0020]

[0021] After compensation, the output current deviation of the jth column is:

[0022] ΔI[j]=I ideal [j]-I[j]

[0023] Among them, I ideal [j] is the ideal output current of the jth column, I out [j] is the actual output current of the jth column of the memristor crossbar array with voltage drop introduced;

[0024] Determine whether the maximum output current deviation max{ΔI[j]} of each column after compensation meets the threshold. If not, reduce the adjustment voltage for the next round of iteration. If yes, return the final differential memristor adjustment row number m and the adjustment voltage V tune .

[0025] In one of the embodiments, it also includes: in a simulation framework, training a neural network based on an ideal memristor cross array to obtain a weight model of the ideal memristor cross array; inputting a pre-constructed test set into the weight model for reasoning to obtain the classification accuracy of the neural network and the ideal output current of the column under ideal conditions; adding a preset voltage drop to the simulation framework for reasoning to obtain the classification accuracy of the neural network and the column deviation output current when the voltage drop exists.

[0026] A memristor cross array voltage drop compensation device is applied to a memristor cross array voltage drop compensation circuit, wherein the output ends of the forward array and the reverse array of the memristor cross array in the memristor cross array voltage drop compensation circuit are cascaded with a plurality of memristor adjustment rows respectively, so as to compensate for the deviation of the forward current of the forward array and the reverse current of the reverse array;

[0027] The device comprises:

[0028] A current acquisition module, used to acquire an output current deviation between an ideal column output current of the memristor crossbar array and a column output current with a voltage drop introduced;

[0029] An adjustment module, used to determine the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage output in the previous round of iteration;

[0030] The compensation module is used to set the conductance value of all memristor devices in the differential memristor adjustment row, compensate the current deviation of each column according to the conductance value, and output the final number of differential memristor adjustment rows and the adjustment voltage when the maximum output current deviation of each column after compensation meets the threshold.

[0031] In one embodiment, the adjustment module is further used to determine the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage output in the previous round of iteration:

[0032]

[0033] Among them, ΔI out [j] represents the output current deviation, V tune Indicates the regulation voltage, G max is the maximum conductance of the memristor, G min is the minimum conductance of the memristor, symbol represents rounding down, num[jn] represents the number of required differential memristor adjustment rows calculated in the current iteration, and m represents the number of maximum differential memristor adjustment rows.

[0034] In one embodiment, the compensation module is further configured to adjust the memristor conductance of the row of the reverse differential memristor of the reverse array for the jth column if the output voltage deviation is positive. Set to G min ; The forward differential memristor of the forward array adjusts the memristor conductance of the row Adjust to:

[0035]

[0036] Among them, i and j are row and column coordinates respectively, G near represents the conductivity state;

[0037] If the output voltage deviation is negative, the opposite adjustment method is used to compensate the memristor conductance and memristor conductance

[0038] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0039] Obtaining an output current deviation between an ideal column output current of the memristor crossbar array and a column output current with a voltage drop introduced;

[0040] Determining the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage outputted in the previous round of iteration;

[0041] Setting a differential memristor to adjust the conductance value of all memristor devices in a row, and compensating for the current deviation of each column according to the conductance value;

[0042] When the maximum output current deviation of each column after compensation meets the threshold, the final number of differential memristor adjustment rows and the adjustment voltage are output.

[0043] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps:

[0044] Obtaining an output current deviation between an ideal column output current of the memristor crossbar array and a column output current with a voltage drop introduced;

[0045] Determining the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage outputted in the previous round of iteration;

[0046] Setting a differential memristor to adjust the conductance value of all memristor devices in a row, and compensating for the current deviation of each column according to the conductance value;

[0047] When the maximum output current deviation of each column after compensation meets the threshold, the final number of differential memristor adjustment rows and the adjustment voltage are output.

[0048] The above-mentioned memristor cross array voltage drop compensation method, device and computer equipment use multiple differential memristor adjustment rows to share the adjustment voltage, effectively compensate for the current deviation caused by the voltage drop, so as to restore the accuracy loss caused by the cross array voltage drop in the memristor neural network calculation. The present invention needs to iterate the adjustment row to select the most suitable adjustment voltage, memristor device conductance value and number of rows. Multiple differential memristor adjustment rows introduce additional current components to compensate for the output current deviation caused by the voltage drop in the memristor neural network calculation. The size of the adjustment voltage, the resistance value of the memristor device in the adjustment row and the number of adjustment rows are determined based on the size of the current deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A memristor crossbar array voltage drop compensation circuit diagram in one embodiment;

[0050] Figure 2 It is a schematic flow chart of a voltage drop compensation method of a memristor crossbar array in one embodiment;

[0051] Figure 3 A schematic flow chart of a voltage drop compensation method for a memristor crossbar array in another embodiment;

[0052] Figure 4 It is a structural block diagram of a memristor crossbar array voltage drop compensation device in one embodiment;

[0053] Figure 5 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] Figure 1 The invention discloses a memristor cross array voltage drop compensation circuit, in which the output ends of the forward array and the reverse array of the memristor cross array are cascaded with multiple memristor adjustment rows respectively, for compensating for the deviation of the forward current of the forward array and the reverse current of the reverse array.

[0056] In one embodiment, Figure 2 As shown, a method for compensating voltage drop of a memristor crossbar array is provided, and the method is applied to Figure 1 The memristor crossbar array voltage drop compensation circuit in the embodiment is taken as an example to illustrate, including the following steps:

[0057] Step 202 : obtaining an output current deviation between an ideal column output current of a memristor crossbar array and a column output current with a voltage drop introduced.

[0058] In this step, the ideal output current of the column of the memristor cross array is first calculated under ideal conditions, and then the column output current of the memristor cross array after the voltage drop is introduced is calculated, and finally the output current deviation is calculated by the difference between the two.

[0059] Step 204 : determining the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage outputted in the previous iteration.

[0060] Step 206: Setting the differential memristor to adjust the conductance of all memristor devices in the row, and compensating the current deviation of each column according to the conductance.

[0061] By introducing multiple memristor adjustment rows, cascading them at the output ends of the forward array and the reverse array respectively, and setting the conductance value and the number of rows of the memristor adjustment rows for compensation, the output current deviation can be minimized, thereby reducing the difference between the column deviation output current and the column ideal output current.

[0062] Step 208: When the maximum output current deviation of each column after compensation meets the threshold, the final number of differential memristor adjustment rows and the adjustment voltage are output.

[0063] In the above-mentioned memristor cross array voltage drop compensation method, multiple differential memristor adjustment rows are used to share the adjustment voltage, effectively compensating for the current deviation caused by the voltage drop, so as to restore the accuracy loss caused by the cross array voltage drop in the memristor neural network calculation. The present invention needs to iterate the adjustment row to select the most suitable adjustment voltage, memristor device resistance value and number of rows. Multiple differential memristor adjustment rows introduce additional current components to compensate for the output current deviation caused by the voltage drop in the memristor neural network calculation. The size of the adjustment voltage, the resistance value of the memristor device in the adjustment row and the number of adjustment rows are determined based on the size of the current deviation.

[0064] In one embodiment, the number of differential memristor adjustment rows is calculated as follows: according to the output current deviation and the adjustment voltage output in the previous iteration, the number of differential memristor adjustment rows required for each column is determined as:

[0065]

[0066] Among them, ΔI out [j] represents the output current deviation, V tune Indicates the regulation voltage, G max is the maximum conductance of the memristor, G min is the minimum conductance of the memristor, symbol represents rounding down, num[jn] represents the number of required differential memristor adjustment rows calculated in the current iteration, and m represents the number of maximum differential memristor adjustment rows.

[0067] In one embodiment, the step of compensating the current deviation includes: for the jth column, if the output voltage deviation is positive, adjusting the conductance of the memristor of the reverse differential memristor of the reverse array Set to G min ; The forward differential memristor of the forward array adjusts the memristor conductance of the row Adjust to:

[0068]

[0069] Among them, i and j are row and column coordinates respectively, Gnear represents the conductance state. If the output voltage deviation is negative, the opposite adjustment method is used to compensate the memristor conductance. and memristor conductance

[0070] In this embodiment, the first num[j] rows of the forward j-th column output terminal are set to G max To compensate for the current deviation in a coarse-grained manner, the last row of devices is set to the state closest to the conduction state G near Fine-grained compensation is performed uniformly, where G near Calculated as MOD(ΔI out [j]-(G max -G min )×V tune ,G max -G min )+G min The remaining devices on the forward regulation row are set to G min This results in differential cancellation with the reverse array.

[0071] In one embodiment, the output current I[j] of the jth column after compensation is determined as:

[0072]

[0073] After compensation, the output current deviation of the jth column is:

[0074] ΔI[j]=I ideal [j]-I[j]

[0075] Among them, I ideal [j] is the ideal output current of the jth column, I out [j] is the actual output current of the jth column of the memristor crossbar array with voltage drop introduced; determine whether the maximum output current deviation max{ΔI[j]} of each column after compensation meets the threshold value. If not, reduce the adjustment voltage for the next round of iteration. If yes, return the final number of differential memristor adjustment rows m and the adjustment voltage V tune .

[0076] In one of the embodiments, in a simulation framework, a neural network is trained based on an ideal memristor cross array to obtain a weight model of the ideal memristor cross array; a pre-constructed test set is input into the weight model for reasoning to obtain the classification accuracy of the neural network and the ideal output current of the column under ideal conditions; a voltage drop is added to the simulation framework for reasoning to obtain the classification accuracy of the neural network and the column deviation output current when the voltage drop exists.

[0077] In this embodiment, the ideal column output current and the column deviation output current are obtained by simulation and recorded for subsequent iterative solution of the memristor adjustment row.

[0078] Specifically, in one embodiment, Figure 3 As shown, the execution process of the voltage drop compensation method of the memristor crossbar array is as follows:

[0079] The first step is to train the neural network based on the ideal memristor crossbar array in the simulation framework to obtain the weight model;

[0080] In the second step, the test set is input into the weight model for inference to obtain the ideal classification accuracy and record the ideal column output current.

[0081] The third step is to add the voltage drop (IR-Drop) into the simulation framework, perform reasoning, obtain the classification accuracy in the presence of IR-Drop, and count the output current;

[0082] Step 4: According to the output current data collected in steps 2 and 3, calculate the average output current deviation and determine the appropriate initial value of the regulation voltage V tune [m];

[0083] Step 5: Based on the average output current deviation and the regulation voltage V tune [m], iterative solution to determine the final regulation voltage V tune The number of rows m and the conductance value are adjusted by differential memristor

[0084] In the sixth step, multiple differential memristor adjustment rows are added to the simulation framework to perform inference calculations to obtain the classification accuracy after compensation.

[0085] In the above embodiment, since the output ends of the forward array and the reverse array are both cascaded with memristor adjustment rows, the forward current and the reverse current are compensated respectively before the differential analog-to-digital converter (ADC), and the memristor adjustment row is adjusted based on the current deviation obtained by the inference process statistics, and the weight distribution of the memristor cross array does not need to be adjusted, so the accuracy loss caused by the voltage drop (IR-Drop) of the cross array in the memristor neural network calculation can be restored without retraining. In addition, by using multiple memristor adjustment rows to share the adjustment voltage V tune , you can use a smaller V tune The current deviation is compensated in the case of

[0086] The following is a specific embodiment to illustrate the compensation steps of the present invention:

[0087] S1: Get the ideal output current I of the column of the memristor crossbar array ideal [j] Column output current I with introduced voltage drop out The current deviation ΔI between [j] out [j], that is:

[0088] ΔI out [j]=I ideal [j]-I out [j]

[0089] Where j is the column index of the memristor crossbar array, I ideal [j] is the ideal output current of the jth column, I out [j] is the actual output current of the jth column of the memristor crossbar array with voltage drop, ΔI out [j] is the output current deviation of the jth column.

[0090] S2: Determine an initial value of the regulation voltage V tune , the initial value must be smaller than the minimum value of the absolute value of the set voltage and the absolute value of the reset voltage of the memristor;

[0091] S3: Output current deviation ΔI according to the ideal column output current and the column deviation output current out [j] and V tune Determine the number of differential memristor adjustment rows num[jn] required for each column, and select the maximum value of num[j] plus 1 as the number of differential memristor adjustment rows m:

[0092]

[0093] Where j is the column index of the memristor crossbar array, G max is the maximum conductance of the memristor, G min is the minimum conductance of the memristor, symbol Indicates rounding down.

[0094] S4: Setting the differential memristor to adjust the conductance of all memristor devices in the row, so as to compensate for the current deviation of each column. Using the rule of setting by column, for the jth column, if the current deviation ΔI out [j] is positive, the reverse differential memristor adjusts the device conductance Set to G min , while the device conductance of the forward regulation row is set according to the following rule:

[0095] Set the first num[j] rows of the forward j-th column output to G max To compensate for the current deviation in a coarse-grained manner, the last row of devices is set to be closest to MOD (ΔI out [j]-(G max -G min )×V tune ,G max -G min )+G min The conductivity state G near Fine-grained compensation is performed uniformly, and the devices on the remaining positive regulation lines are all set to G min Thus, the difference is offset with the reverse array, that is:

[0096]

[0097] Where i and j are row and column coordinates respectively, and are the device conductances of the coordinates of the forward adjustment row and the reverse adjustment row respectively. out If [j] is negative, the device conductance of the forward and reverse regulation lines can be adjusted in the same way. and

[0098] S5 calculates whether the output current deviation after compensation meets the requirements. According to the adjustment voltage determined by S2, S3 and S4, the number of differential memristor adjustment rows and the device conductance value on the adjustment row, the output current I[j] of the jth column after compensation is calculated as:

[0099]

[0100] Then the output current deviation ΔI[j] of the jth column after compensation is:

[0101] ΔI[j]=I ideal [j]-I[j]

[0102] Determine whether the maximum output current deviation max{ΔI[j]} of each column after compensation meets the threshold. If not, reduce the regulation voltage V by a certain step. tune, and jump to S3; if satisfied, stop and return to m and V tune As compensation voltage and differential memristor are used to adjust the number of rows.

[0103] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0104] In one embodiment, Figure 4 As shown, a memristor crossbar array voltage drop compensation device is provided, which is applied to Figure 1 The memristor crossbar array voltage drop compensation circuit includes: a current acquisition module 402, a regulation module 404 and a compensation module 406, wherein:

[0105] A current acquisition module 402, used to acquire an output current deviation between an ideal column output current of the memristor crossbar array and a column output current with a voltage drop introduced;

[0106] The adjustment module 404 is used to determine the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage output in the previous round of iteration;

[0107] The compensation module 406 is used to set the conductance value of all memristor devices in the differential memristor adjustment row, compensate the current deviation of each column according to the conductance value, and output the final number of differential memristor adjustment rows and the adjustment voltage when the maximum output current deviation of each column after compensation meets the threshold.

[0108] In one embodiment, the adjustment module 404 is further configured to determine the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage outputted in the previous iteration:

[0109]

[0110] Among them, ΔI out [j] represents the output current deviation, V tune Indicates the regulation voltage, G max is the maximum conductance of the memristor, G min is the minimum conductance of the memristor, symbol represents rounding down, num[jn] represents the number of required differential memristor adjustment rows calculated in the current iteration, and m represents the number of maximum differential memristor adjustment rows.

[0111] In one embodiment, the compensation module 406 is further configured to adjust the memristor conductance of the row of the reverse differential memristor of the reverse array for the jth column if the output voltage deviation is positive. Set to G min ; The forward differential memristor of the forward array adjusts the memristor conductance of the row Adjust to:

[0112]

[0113] Among them, i and j are row and column coordinates respectively, G near represents the conductivity state;

[0114] If the output voltage deviation is negative, the opposite adjustment method is used to compensate the memristor conductance and memristor conductance

[0115] In one embodiment, the compensation module 406 is further configured to determine the j-th column output current I[j] after compensation as:

[0116]

[0117] After compensation, the output current deviation of the jth column is:

[0118] ΔI[j]=I ideal [j]-I[j]

[0119] Among them, I ideal [j] is the ideal output current of the jth column, I out [j] is the actual output current of the jth column of the memristor crossbar array with voltage drop introduced;

[0120] Determine whether the maximum output current deviation max{ΔI[j]} of each column after compensation meets the threshold. If not, reduce the adjustment voltage for the next round of iteration. If yes, return the final differential memristor adjustment row number m and the adjustment voltage V tune .

[0121] In one of the embodiments, the current acquisition module 402 is also used to train a neural network based on an ideal memristor cross array in a simulation framework to obtain a weight model of the ideal memristor cross array; input a pre-constructed test set into the weight model for reasoning to obtain the classification accuracy of the neural network and the ideal output current of the column under ideal conditions; add a preset voltage drop to the simulation framework for reasoning to obtain the classification accuracy of the neural network and the column deviation output current when the voltage drop exists.

[0122] For the specific definition of the memristor cross array voltage drop compensation device, please refer to the definition of the memristor cross array voltage drop compensation method above, which will not be repeated here. Each module in the above-mentioned memristor cross array voltage drop compensation device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0123] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 5 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for compensating for voltage drop of a memristor cross array is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0124] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0125] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method in the above embodiment when executing the computer program.

[0126] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method in the above embodiment are implemented.

[0127] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0128] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for compensating voltage drop in a memristor crossbar array, characterized in that: Applied to a memristor cross array voltage drop compensation circuit, the output ends of the forward array and the reverse array of the memristor cross array in the memristor cross array voltage drop compensation circuit are cascaded with multiple memristor adjustment rows respectively, so as to compensate for the deviation of the forward current of the forward array and the reverse current of the reverse array; The method comprises: Obtaining an output current deviation between an ideal column output current of the memristor crossbar array and a column output current with a voltage drop introduced; Determining the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage outputted in the previous round of iteration; Setting a differential memristor to adjust the conductance value of all memristor devices in a row, and compensating for the current deviation of each column according to the conductance value; When the maximum output current deviation of each column after compensation meets the threshold, the final number of differential memristor adjustment rows and the adjustment voltage are output.

2. The method according to claim 1, characterized in that Determining the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage outputted in the previous round of iterations, including: According to the output current deviation and the regulation voltage outputted in the previous round of iteration, the number of differential memristor regulation rows required for each column is determined as: Among them, ΔI out [j] represents the output current deviation, V tune Indicates the regulation voltage, G max is the maximum conductance of the memristor, G min is the minimum conductance of the memristor, symbol represents rounding down, num[jn] represents the number of required differential memristor adjustment rows calculated in the current iteration, and m represents the number of maximum differential memristor adjustment rows.

3. The method according to claim 2, characterized in that Setting the differential memristor to adjust the conductance of all memristor devices in the row, and compensating the current deviation of each column according to the conductance, includes: For the jth column, if the output voltage deviation is positive, the reverse differential memristor of the reverse array adjusts the memristor conductance of the row Set to G min ; The forward differential memristor of the forward array adjusts the memristor conductance of the row Adjust to: Among them, i and j are row and column coordinates respectively, G near represents the conductivity state; If the output voltage deviation is negative, the opposite adjustment method is used to compensate the memristor conductance and memristor conductance 4. The method according to claim 3, characterized in that When the maximum output current deviation of each column after compensation meets the threshold, the final number of differential memristor adjustment rows and the adjustment voltage are output, including: The output current I[j] of the jth column after compensation is determined as: After compensation, the output current deviation of the jth column is: ΔI[j]=I ideal [j]-I[j] Among them, I ideal [j] is the ideal output current of the jth column, I out [j] is the actual output current of the jth column of the memristor crossbar array with voltage drop introduced; Determine whether the maximum output current deviation max{ΔI[j]} of each column after compensation meets the threshold. If not, reduce the adjustment voltage for the next round of iteration. If yes, return the final differential memristor adjustment row number m and the adjustment voltage V tune .

5. The method according to any one of claims 1 to 4, characterized in that: Obtaining the ideal column output current of the memristor crossbar array and the column deviation output current with voltage drop added, including: In the simulation framework, the neural network is trained based on the ideal memristor crossbar array to obtain the weight model of the ideal memristor crossbar array; Inputting a pre-built test set into the weight model for inference, and obtaining the classification accuracy of the neural network and the ideal output current of the column under ideal conditions; The preset voltage drop is added into the simulation framework for inference, and the classification accuracy of the neural network and the column deviation output current when the voltage drop exists are obtained.

6. A memristor crossbar array voltage drop compensation device, characterized in that: Applied to a memristor cross array voltage drop compensation circuit, the output ends of the forward array and the reverse array of the memristor cross array in the memristor cross array voltage drop compensation circuit are cascaded with multiple memristor adjustment rows respectively, so as to compensate for the deviation of the forward current of the forward array and the reverse current of the reverse array; The device comprises: A current acquisition module, used to acquire an output current deviation between an ideal column output current of the memristor crossbar array and a column output current with a voltage drop introduced; An adjustment module, used to determine the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage output in the previous round of iteration; The compensation module is used to set the conductance value of all memristor devices in the differential memristor adjustment row, compensate the current deviation of each column according to the conductance value, and output the final number of differential memristor adjustment rows and the adjustment voltage when the maximum output current deviation of each column after compensation meets the threshold.

7. The device according to claim 6, characterized in that The adjustment module is further used to determine the number of differential memristor adjustment rows required for each column according to the output current deviation and the adjustment voltage output in the previous round of iteration: Among them, ΔI out [j] represents the output current deviation, V tune Indicates the regulation voltage, G max is the maximum conductance of the memristor, G min is the minimum conductance of the memristor, symbol represents rounding down, num[jn] represents the number of required differential memristor adjustment rows calculated in the current iteration, and m represents the number of maximum differential memristor adjustment rows.

8. The device according to claim 7, characterized in that The compensation module is also used for adjusting the memristor conductance of the row of the reverse differential memristor of the reverse array for the jth column if the output voltage deviation is positive. Set to G min ; The forward differential memristor of the forward array adjusts the memristor conductance of the row Adjust to: Among them, i and j are row and column coordinates respectively, G near represents the conductivity state; If the output voltage deviation is negative, the opposite adjustment method is used to compensate the memristor conductance and memristor conductance 9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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