Low thermal resistance and low stress multi-chip embedded board level packaging method and packaging structure thereof

Abstract

The application belongs to the technical field of chip packaging, and particularly relates to a low-thermal-resistance and low-stress multi-chip embedded board-level packaging method and a packaging structure thereof. The chip layout of the multi-chip embedded board-level packaging structure is as follows: the chips and copper blocks are symmetrically distributed, the copper blocks are arranged at the upper and lower boundaries of the structure respectively, and the z-shaped grooves are placed in the middle; the chips are four in total, two in a group, and the chips in the same group are placed vertically in the longitudinal direction; the copper blocks are eight in total, four in a group, and the copper blocks in the same group are placed horizontally and closely; the grooves, the chips and the copper blocks are symmetrically arranged in the center as a whole; the chip is composed of a chip region, and the copper block realizes circuit connection; the chip and the copper block are respectively provided with multiple blind holes arranged uniformly, which are used for realizing the structure for longitudinal electrical connection, the carrier substrate material is copper; and the grooves are used for realizing electrical insulation and dividing electrode regions. The application can reduce the packaging size of power devices, realize more uniform heat distribution on the basis of low inductance and low stress, and improve the heat-power characteristics of the devices.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip packaging. Specifically, it relates to a low-thermal-resistance and low-stress multi-chip embedded board-level packaging method and a packaging structure thereof. BACKGROUND

[0002] With the development of electronic devices towards higher performance and smaller size, the traditional single-chip packaging technology has been unable to meet the increasing power density and heat dissipation requirements. Multi-chip FOPLP has become a development trend due to its excellent electrical and thermal performance and cost-effectiveness. However, the thermal management and mechanical stress problems brought by multi-chip layout have posed challenges to the reliability of the packaging structure. Currently, the thermal mechanical stress distribution of a four-chip FOPLP sample is uneven, and the present application proposes a new layout to uniform the thermal mechanical properties of the four chips.

[0003] The process of multi-chip board-level packaging is similar to that of single-chip board-level packaging. Face up (Face up) and face down (Face down) process flow can be realized in multi-chip packaging [1]. However, due to the connection of multiple chips in half-bridge circuit topology and the vertical structure of SiC MOSFET, Face down is usually adopted in multi-chip board-level packaging [2]. The packaging process of Face down starts with fixing the chips on the carrier board. The packaging of half-bridge topology requires the carrier board to be differentiated in terms of electrodes and the current flow path to be designed. The height difference between the source of the upper bridge arm and the drain of the lower bridge arm in the packaging needs to be eliminated by a copper block on the carrier board. The copper block is processed in the same way as the chip and is fixed on the carrier board by solder at the same time. The redistribution layer (RDL) is also applied to the copper block to realize the connection of the circuit in the half-bridge topology. These technologies have been applied in large-scale production, but there are still problems such as high thermal resistance, serious heat dissipation path coupling, etc.

[0004] FOPLP packaging technology can effectively reduce the electrical interconnection length and thermal conduction distance, thereby reducing parasitic inductance and thermal resistance. There are some embedded power module solutions based on copper lead frame and PCB, but further improvement is needed in terms of parasitic parameter and thermal performance optimization. The face-down SiC MOSFET configuration can reduce the common-source inductance of the drive circuit and the power circuit, thereby improving the switching performance. The copper connecting block can overcome the limitations of vias, realize double-sided heat dissipation, and improve the current carrying capacity and thermal conductivity. The current research on double-sided heat dissipation packaging of parallel multi-chips mainly focuses on the design of low-inductance and low-thermal-resistance packaging form [3], and there is no much optimization research on the layout of the chips.

[0005] At present, the manufacturing process and packaging form of FOPLP are rich in research content, which obviously improves the thermal resistance stress of the whole package. However, in the application of the multi-chip module, the thermal coupling caused by the simultaneous heating of the chips will have a bad influence on the temperature characteristics and stress characteristics of the device. Therefore, it is very important to reasonably layout the chips in the multi-chip module for the uniform distribution of temperature and stress. SUMMARY

[0006] The purpose of the present application is to provide a multi-chip board-level packaging method and packaging structure capable of optimizing the layout of FOPLP chips, which have excellent temperature uniformity and stress uniformity.

[0007] The multi-chip board-level packaging process has similarities with the single-chip board-level packaging process, and both can adopt face-up and face-down assembly processes. However, due to the complex half-bridge circuit topology and the vertical structure of SiC MOSFET, the multi-chip board-level packaging structure usually adopts a face-down process. The present application adopts a face-down packaging process, and the flow is shown in Figure 1 The specific steps are as follows:

[0008] Step 1, half-etching the carrier substrate 4; that is, performing half-etching on the prepared carrier substrate, dividing the area on the carrier substrate into electrical regions through half-etching, and forming positioning grooves 5 of the chip 1 and the copper block 2; since the carrier substrate is used for fixing the device during the entire packaging process, it is not completely etched.

[0009] The overall size of the carrier substrate is greater than 200mm*200mm and less than 2m*2m, and the material is pure copper; the size of a single packaging unit is determined according to the design.

[0010] Step 2, mounting the chip 1 and the copper block 2 on the carrier substrate 4; specifically, adopting a reflow soldering process, the material is tin paste / SnSb10 (ES-1100, EarlySun), the temperature is raised to above 250℃ (the specific value is determined according to the material properties, generally, the temperature is raised to 250-290℃), and the entire tin paste solidification time lasts for more than 30min (the specific value is determined according to the material properties, generally, the solidification time is 30-300min). For half-bridge topology packaging, it is crucial to design the current path and distinguish the electrodes on the substrate. In order to solve the problem of inconsistent height of the source and the drain, a copper block needs to be placed on the carrier plate to ensure balanced and effective electrical interconnection.

[0011] Step 3, sequentially pressing the plastic packaging material and the copper sheet on the carrier plate; the plastic packaging material is used to provide mechanical support, laying the foundation for subsequent press-packaging of the chip. The copper sheet (layer) is pressed on the plastic packaging material to form a redistribution layer (RDL).

[0012] The pressing process in this step is achieved by a vacuum fast pressing machine. The pressing process requires vacuuming, a temperature of 40-50°C, a time of 1-5 minutes, and an applied pressure of less than 10Kgf / cm 2 (The specific value is determined by the material properties. Generally, the applied pressure is 5-10Kgf / cm 2 Pressure). After lamination, it needs to be leveled, pre-baked, and cured; the leveling process also requires vacuuming, and the temperature should be higher than the lamination process temperature (for example, the temperature is 100-125℃), and the applied pressure is less than 10Kgf / cm 2 (The specific value is determined by the material properties. Generally, the applied pressure is 5-10Kgf / cm 2 pressure); pre-bake in a nitrogen environment at a temperature of 90-110°C; curing needs to be carried out at a high temperature (for example, 170-200°C) and last for more than 60 minutes (the specific value is determined according to the properties of the material, generally, the curing time is 60-120 minutes).

[0013] Step 4, making blind holes 3; blind holes are made on the surfaces of the chip 1 and the copper block 2 by combining computer numerical control (CNC) engraving and laser processing. The blind holes are used to achieve vertical interconnection; the aperture of the blind holes is greater than 0.1 mm and less than 1 mm.

[0014] Step 5: Forming the electrical connection structure. Specifically, a copper layer is deposited on the blind hole walls using a chemical deposition method. Then, the blind hole is completely filled with copper material through electroplating. This step completes the interconnection process and ensures a seamless electrical connection between chip 1 and copper block 2.

[0015] Step 6: Etching the circuit pattern. To achieve a specific current path, the top redistribution layer (RDL) needs to be divided into several areas. Specifically, by applying photoresist, photolithography, and etching technology, the copper layer is complexly etched into a predefined circuit pattern to meet the requirements of the half-bridge topology circuit.

[0016] Step 7: Laminating the polypropylene (PP) material and heat sink: After the etching process is complete, a layer of polypropylene (PP) material and heat sink is attached to the bottom of the structure to enhance thermal management and structural stability. The lamination process in this step is performed using a vacuum fast press.

[0017] Step 8: Solder Mask Lamination: Subsequently, a layer of solder mask is applied to the top surface of the RDL to provide protection and ensure the reliability of the soldering process. The lamination process in this step is performed using a vacuum fast press.

[0018] Step 9, developing the solder mask layer; that is, applying photoresist on top of the solder mask layer to achieve surface patterning for easy connection with external circuits.

[0019] Step 10, graphic processing; finally, the surface of the sample is silver plated to realize the formation of the solder pad. Silver plating not only ensures good electrical conductivity, but also helps to improve the durability and oxidation resistance of the contact pad.

[0020] After the above multi-chip board-level packaging method, a multi-chip board-level packaging structure, i.e. a multi-chip FOPLP half-bridge module, is obtained, the chip layout of the multi-chip board-level packaging structure is as shown in Figure 2 The chip 1 (large square in the figure) and the copper block 2 (small square in the figure) are symmetrically distributed, the copper block 2 is arranged at the upper and lower boundaries of the structure respectively, and the groove 5 is centrally placed in a “z” shape; the chip 1 is a total of four, two in a group, and the chips in the same group are vertically placed, the spacing between the chips is equal to 0.6 mm at the minimum and does not exceed the packaging size at the maximum; the copper block 2 is a total of eight, four in a group, and the copper blocks in the same group are horizontally closely placed, the spacing is equal to 0.6 mm at the minimum and does not exceed the packaging size at the maximum. The groove 5, the four chips 1 and the eight copper blocks 2 are centrally symmetrically arranged as a whole; wherein the chip 1 constitutes a chip region, and the copper block 2 realizes circuit connection; the blind hole 3 (small circular dot position uniformly arranged on the chip and the copper block in the figure) is used to realize the structure (through copper sinking on the blind hole wall and copper filling in the blind hole) for longitudinal electrical connection, and is realized by using the electroplating method to realize surface copper sinking and then filling. The material of the substrate 4 is copper. The groove 5 (white area in the figure) is used to realize electrical insulation to divide the electrode region, and the epoxy resin plastic packaging material 6 (black area in the figure) is used for the whole device packaging. The distance between the chips has passed the simulation verification.

[0021] The board-level fan-out packaging provided by the present application reduces the packaging size of the power device, realizes more uniform heat distribution on the basis of low stray inductance and low stress, and improves the thermal-mechanical characteristics of the whole device. Under certain conditions, the highest junction temperature of the chip can be reduced by 3-4℃. The temperature difference between the parallel chips is reduced from about 3℃ (0.5℃) to about 1℃ (0.3℃). The present application provides a low-thermal-resistance board-level half-bridge power module packaging structure with low thermal resistance and high integration, and through the symmetric layout of the chip, it provides a new possibility for fully releasing the performance of silicon carbide chips.

[0022] The chip layout provided by the present application can realize uniform temperature distribution and stress distribution, further optimize the thermal-mechanical performance of the FOPLP on the basis of low stray inductance, effectively solve the thermal-mechanical performance problem caused by the chip layout in multi-chip packaging, and provide a new solution for large-scale application of SiC devices. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The present application is a multi-chip embedded board-level packaging method flow chart.

[0024] Figure 2Chip layout diagram in multi-chip board level package structure (multi-chip half-bridge FOPLP module) of the application.

[0025] Figure 3 Different layer structure slice structure diagram of multi-chip half-bridge FOPLP.

[0026] Figure 4 FOPLP chip layer cross-section blind hole diagram.

[0027] Figure 5 Optimized temperature distribution and stress distribution of FOPLP.

[0028] Figure 6 Double-interface method thermal resistance test curve.

[0029] Figure label: 1 is a chip, 2 is a copper block, 3 is a blind hole, 4 is a substrate 4, 5 is a groove, and 6 is a filling material. DETAILED DESCRIPTION

[0030] The application will be further described below with examples in conjunction with the accompanying drawings.

[0031] The method flow of the application is shown in Figure 1 The specific steps are as follows:

[0032] (1) Prepare a board level carrier with a thickness of 230um, overall dimensions of 508*203*0.1mm, and a material of pure copper. The size of a single packaging unit is 20*20*0.1mm. Perform half-etching on the prepared carrier substrate.

[0033] (2) Install the chips and copper blocks on the carrier board. The chips and copper blocks are symmetrically distributed, and the copper blocks are arranged at the upper and lower boundaries of the structure, respectively, and the grooves are placed in the center in a "z" shape. There are a total of four chips, two in a group, and the chips in the same group are placed vertically, with a spacing of 3.95mm between the chips. There are a total of eight copper blocks, four in a group, and the copper blocks in the same group are placed horizontally and closely, with a spacing of 0.6mm. Among them, 1 is a large square for the chip area, and 2 is a small square for the copper block to realize circuit connection. The small dots 3 in the structure are the positions of the blind holes above the chips and copper blocks. The blind holes are structures for realizing longitudinal electrical connection and are realized by electroplating method to realize surface copper deposition and then filling. The black area is the carrier substrate 4, which is made of copper. The white grooves 5 realize the part of the electrode area that is electrically insulated and divided, and are filled with plastic encapsulation material 6 in the entire packaging. The entire layout is symmetrically distributed, and the distance between the chips has passed the simulation verification. The chip size is 3.7mm*4.1mm.

[0034] The copper block size is 2mm*2mm. Reflow soldering process is used, and the material is tin paste / SnSb10 (ES-1100, EarlySun). The temperature rises to 285℃. The entire tin paste solidification time lasts for 300min.

[0035] (3) Press the encapsulation material on the carrier board, thickness 200um+80um. Then press a whole piece of copper layer on the encapsulation material, thickness 70um, to form the redistribution layer (RDL). The pressing process in this step is realized by a vacuum fast pressing machine. The pressing process needs to be vacuumized, temperature 45℃, time 1min, pressure 5Kgf / cm 2 . The flattening process also needs to be vacuumized, temperature 120℃, time 5min, pressure 6Kgf / cm 2 . The pre-baking temperature is 100℃, in a nitrogen environment, time 30min. The curing temperature is 180℃, time 120min.

[0036] (4) In order to realize vertical interconnection, the surface of the chip and the copper block is made into a blind hole by combining computer numerical control (CNC) engraving and laser processing, hole diameter 200um, depth 80um.

[0037] (5) After cleaning, copper is deposited on the wall of the blind hole by chemical deposition method. Then the blind hole is completely filled by electroplating process.

[0038] (6) In order to realize a specific current path, the top RDL needs to be divided into several areas. Through the technology of applying photoresist, photoetching and etching, the copper layer is etched into a complex circuit pattern as predefined, to meet the requirements of half-bridge topology circuit.

[0039] (7) After the etching process is completed, a layer of polypropylene (PP) material with a thickness of 130um and a heat sink with a thickness of 30um is attached to the bottom of the structure to enhance heat management and structural stability. The pressing process in this step is realized by a vacuum fast pressing machine. The pressing process needs to be vacuumized, temperature 180℃, time 7min, pressure 6Kgf / cm 2 . The curing temperature is 160℃, time 120min.

[0040] (8) Subsequently, a layer of solder resist with a thickness of 20um is attached to the upper surface to provide protection and ensure the reliability of the soldering process. The pressing process in this step is realized by a vacuum fast pressing machine.

[0041] (9) Apply photoresist on the top to realize the patterning of the surface.

[0042] (10) Finally, the surface of the sample is treated with silver plating.

[0043] The cross-section of the prepared FOPLP sample is examined to determine the structure and thickness of each component layer. As Figure 3As shown, different layers can be observed with the Axioscope 5 metallographic microscope. The sample contains four embedded SiC MOSFETs. The chip size is 3.74 mm x 4.13 mm, and the copper block size is 2 mm x 2 mm. The overall package size is 20 mm x 20 mm. Considering the insulation between different electrode areas and the filling of the plastic package material, the spacing between different potential structures needs to be greater than 0.6 mm. Figure 4 A cross-sectional perspective view of the blind via layer is shown, where the diameter of the blind via is over 170 pm. Although the blind vias are very common in this layer, their individual diameters are relatively small. Therefore, the copper area of the blind vias located above the chip is much smaller compared to the surface area of the chip.

[0044] Figure 5 The temperature and top surface displacement distribution is shown under the condition that the optimized layout alternately works on the upper and lower bridge arms with a duty cycle of 50%, a switching frequency of 100 kHz, and a constant on-current of 10 A. The maximum junction temperature of the chip decreases from 82.10 °C to 79.56 °C. In addition, the temperature non-uniformity caused by the thermal coupling between the chips is also improved. In the original package, the average temperatures of the two parallel chips are 80.15 °C and 76.83 °C, respectively. After optimization, the average temperatures of the two parallel chips are 77.41 °C and 76.18 °C, respectively, and the temperature difference between the chips decreases from 3.32 °C to 1.23 °C. The displacement in the Z direction is reduced by 6%. In addition, the uniformity is also significantly improved. These improvements confirm the advantages of the optimized layout design.

[0045] As Figure 6 shown, the thermal resistance of the FOPLP sample is measured using the two-interface method. By determining the inflection point of the two curves, the thermal resistance of the FOPLP is determined to be 1.15 K / W.

[0046] The thermomechanical performance of the board-level package sample produced by the present application is excellent, especially the maximum junction temperature of the chip decreases from 82.10 °C to 79.56 °C. In addition, the temperature non-uniformity caused by the thermal coupling between the chips is also improved. In the original package, the average temperatures of the two parallel chips are 80.15 °C and 76.83 °C, respectively. After optimization, the average temperatures of the two parallel chips are 77.41 °C and 76.18 °C, respectively, and the temperature difference between the chips decreases from 3.32 °C to 1.23 °C. The displacement in the Z direction is reduced by 6%. In addition, the uniformity is also significantly improved. These improvements confirm the advantages of the optimized layout design. At the same time, the thermal resistance of the FOPLP sample is measured using the two-interface method. By determining the inflection point of the two curves, the thermal resistance of the FOPLP is determined to be 1.15 K / W. The low thermal resistance and low stress characteristics of the proposed packaging structure are proved.

[0047] References:

[0048] [1] J. N. Sharma and R. Kaur, “Flexural response of thermoelastic thin beam resonators due to thermal and mechanical loads,” International Journal of Mechanical Sciences, vol. 101-102, pp. 170-179, Oct. 2015, doi: 10.1016 / j.ijmecsci.2015.07.014.

[0049] 10.1016 / j.ijmecsci.2015.07.014.

[0050] [2] D. “ Forced Vibration Responses of Axially Functionally Graded Beams by using Ritz Method,” Journal of Applied and Computational Mechanics, vol. 7,

[0051] no. 1, pp. 109-115, Jan. 2021, doi: 10.22055 / jacm.2020.34865.2491.

[0052] [3] K. Xie, Y. Wang, X. Fan, and T. Fu, “Nonlinear free vibration analysis of functionally graded beams by using different shear deformation theories,”

[0053] Applied Mathematical Modelling, vol. 77, pp. 1860-1880, Jan. 2020, doi:

[0054] 10.1016 / j.apm.2019.09.024.

Claims

1. A low thermal resistance and low stress multi-chip embedded board-level packaging method, characterized in that: The face-down packaging process is adopted, and the specific steps are as follows: Step 1, half-etching the carrier substrate (4); that is, performing half-etching on the carrier substrate, dividing the area on the carrier substrate into electrical areas by half-etching, and forming positioning grooves (5) for the chip (1) and the copper block (2); Step 2, mounting the chip (1) and the copper block (2) on a carrier substrate (4); Step 3: laminating a plastic encapsulation material and a copper sheet onto the carrier board in sequence; the plastic encapsulation material is used to provide mechanical support and lay the foundation for subsequent press-fit packaging of the chip; and a copper sheet is laminated onto the plastic encapsulation material to form a redistribution layer (RDL). Step 4, making blind holes (3); that is, making blind holes on the surface of the chip (1) and the copper block (2) by combining computer numerical control engraving and laser processing, and the blind holes are used to achieve vertical interconnection; Step 5, forming an electrical connection structure; specifically, depositing a copper layer on the blind hole wall using a chemical deposition method; then completely filling the blind hole with copper material through an electroplating process; ensuring a seamless electrical connection between the chip (1) and the copper block (2); Step 6, etching the circuit pattern; dividing the top redistribution layer (RDL) into several areas, and etching the copper layer into a predefined circuit pattern by applying photoresist, photolithography, and etching technology to meet the requirements of the half-bridge topology circuit; Step 7: Pressing the polypropylene (PP) material and the heat sink; After the etching process is completed, a layer of polypropylene (PP) material and heat sink are attached to the bottom of the structure to enhance thermal management and structural stability; Step 8, solder mask lamination; Apply a layer of solder mask on the upper surface of RDL; Step 9, developing the solder mask layer; That is, photoresist is applied on top of the solder mask layer to achieve patterning of the surface, making it easier to connect to external circuits; Step 10, patterning: silver plating the sample surface to form a pad; The chip layout is as follows: the chip (1) and the copper block (2) are symmetrically distributed, the copper blocks (2) are arranged at the upper and lower boundaries of the structure, and the groove (5) is placed in the middle in a "z" shape; there are four chips (1) in a group of two, and the chips in the same group are placed vertically, and the spacing between the chips is greater than or equal to 0.6 mm; there are eight copper blocks (2) in a group of four, and the copper blocks in the same group are placed horizontally and closely, and the spacing is greater than or equal to 0.6 mm; the groove (5), the four chips (1), and the eight copper blocks (2) are generally arranged in a central symmetrical layout; wherein, the chip (1) constitutes a chip area, and the copper block (2) realizes circuit connection; the chip (1) and the copper block (2) are respectively provided with a plurality of blind holes (3) arranged evenly for realizing a longitudinal electrical connection structure, and the material of the carrier substrate (4) is copper; the groove (5) is used to realize electrical insulation to divide the electrode area, and the filling material (6) is used for the entire device packaging.

2. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: The overall size of the carrier substrate in step 1 is greater than 200mm*200mm and less than 2m*2m, and the material is pure copper; the size of a single packaging unit is determined according to the design.

3. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: In step 2, the chip (1) and the copper block (2) are mounted on the carrier substrate (4), specifically using a reflow soldering process, with the material being tin paste SnSb10, the temperature being raised to above 250° C., and the entire tin paste curing time being above 30 minutes.

4. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: The pressing process described in step 3 is achieved by a vacuum fast pressing machine. The pressing process is vacuumed, the temperature is 40-50°C, the time is 1-5 minutes, and the applied pressure is less than 10Kgf / cm 2 After lamination, it is leveled, pre-baked and cured. The leveling process is also vacuumed, the temperature is 100-125℃, and the applied pressure is less than 10Kgf / cm 2 ; Pre-baking is carried out in a nitrogen environment at a temperature of 90-110°C; curing is carried out under high temperature conditions and lasts for more than 60 minutes.

5. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: The blind hole diameter in step 4 is greater than 0.1 mm and less than 1 mm.

6. The low thermal resistance and low stress multi-chip embedded board-level packaging method according to claim 1, characterized in that: The pressing process described in step 7 is achieved by a vacuum fast pressing machine.

7. A low thermal resistance and low stress multi-chip embedded board-level packaging structure obtained by the method according to any one of claims 1 to 6.

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