Method for monitoring height of epitaxial layer step of CMOS (complementary metal oxide semiconductor) device

Abstract

The invention discloses a CMOS device epitaxial layer SH monitoring method. According to a CMOS device needing to be monitored, a measurement reference device is manufactured, and AAamp of the reference device is measured; the STI structure is the same as the CMOS device needing to be monitored; measuring AAamp of the reference device; polycrystalline silicon strips are formed on the STI structures, the polycrystalline silicon strips on the AA are connected in series to obtain a first polycrystalline silicon strip string, and the polycrystalline silicon strips on the STI are connected in series to obtain a second polycrystalline silicon strip string; applying a test voltage U to measure a current I1 flowing through the first polycrystalline silicon strip string and a current I2 flowing through the second polycrystalline silicon strip string; and the epitaxial layer SH of the measurement reference device is calculated according to the I1 and the I2 to serve as the epitaxial layer SH of the CMOS device needing to be monitored. According to the monitoring method, epitaxial layer SH problems corresponding to different CMOS device structures are tested through the electrical structure, difference SH monitoring can be achieved, the SH difference of different device structures can be reflected, and the cost is low.

Description

Technical Field

[0001] The present invention relates to integrated circuit manufacturing technology, and in particular to a monitoring method for the SH (step high) of an epitaxial layer of a CMOS device. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a monolithic integration process technology that can produce Bipolar, CMOS and DMOS devices on the same chip. Since the BCD process combines the advantages of the above three devices, it allows BCD-based products to integrate complex control functions, making it the mainstream process technology for power integrated circuits. In the BCD platform process, the doped buried layer process or deep well process is usually the basic process step in the BCD process flow.

[0003] At present, in the doped buried layer process of the related technology, the ion implantation process is usually adopted. Compared with the deep well process, the doped buried layer adopts the ion implantation method, which can adjust the ion implantation process parameters to make the implantation concentration of the doped buried layer higher and the implantation depth deeper. Therefore, in terms of suppressing the latch-up effect (Latch-up), isolation (isolation) and other performances, the doped buried layer process is superior to the deep well process. After the doped ions are implanted into the substrate, the substrate part corresponding to the ion implantation has a higher ion concentration than other parts of the substrate, resulting in the oxidation rate of silicon in the substrate part corresponding to the ion implantation area in the subsequent oxidation process. Partial oxide layer is formed in the doped buried layer. After this part of the oxide layer is stripped off and epitaxial growth is carried out, it will cause the epitaxial layer to form a step (step), that is, the epitaxial layer has a step height (step high). In the subsequent process, there will be a problem that the step height affects the exposure process window.

[0004] SH (step height) is an important key parameter in the CMOS process, which affects the performance of MOS devices. Conventional processes use dense OCD (Optical Critical Dimension) structures to monitor inline SH. For different device structures, due to the loading effect of processes such as CMP (Chemical Mechanical Polishing), the SH of different device structures varies greatly. The inline optical critical dimension step height (inline OCD SH) cannot reflect the SH difference of different device structures. Therefore, there is currently a lack of SH monitor methods for different device structures. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a monitoring method for the SH (step height) of the epitaxial layer of a CMOS device, which uses an electrical structure to test the SH problems of the epitaxial layer corresponding to different CMOS device structures, can realize differential SH monitoring (monitor), can reflect the step height (SH) differences of different device structures, and has low cost.

[0006] In order to solve the above technical problems, the present invention provides a method for monitoring the step height of an epitaxial layer of a CMOS device, which comprises the following steps:

[0007] S1. Determine the CMOS device to be monitored and prepare the measurement reference device;

[0008] The active area and shallow trench isolation structure of the measurement reference device are the same as those of the CMOS device to be monitored;

[0009] Polysilicon strips are formed on the active area and shallow trench isolation structure of the measurement reference device;

[0010] The polysilicon strips on the active area of ​​the measurement reference device have the same front-to-back length and the same left-to-right width;

[0011] The polysilicon strips on the shallow trench isolation of the measurement reference device have the same front-to-back length and the same left-to-right width;

[0012] The polysilicon strips on the active area of ​​the measurement reference device are connected in series through a back-end connection to obtain a first polysilicon strip string;

[0013] The polysilicon strips on the shallow trench isolation of the measurement reference device are connected in series through a back-end connection to obtain a second polysilicon strip string;

[0014] S2. Apply a test voltage U to the first polysilicon string and the second polysilicon string of the measurement reference device, respectively, and measure the current I1 flowing through the first polysilicon string and the current I2 flowing through the second polysilicon string;

[0015] S3. Calculate the step height SH of the epitaxial layer of the measurement reference device:

[0016] SH=ρ*L2*I2 / (W2*U)-ρ*L1*I1 / (W1*U);

[0017] ρ is the resistivity of polysilicon, L2 is the front-to-back length of the polysilicon strip on the shallow trench isolation of the measurement reference device, W2 is the left-right width of the polysilicon strip on the shallow trench isolation of the measurement reference device, L1 is the length of the polysilicon strip on the active area of ​​the measurement reference device, and W1 is the left-right width of the polysilicon strip on the active area of ​​the measurement reference device;

[0018] S4. Using the epitaxial layer step height of the measurement reference device as the epitaxial layer step height of the CMOS device to be monitored.

[0019] Preferably, in step S1, the monitored CMOS device and the measured reference device are prepared in the same process.

[0020] Preferably, the critical dimension of the polysilicon strip on the active area of ​​the measurement reference device is 30% to 90% of the left and right width of the active area;

[0021] The length of the polysilicon strip on the active area of ​​the measurement reference device is 60% to 90% of the front-to-back length of the active area;

[0022] The critical dimension of the polysilicon strip on the shallow trench isolation of the measurement reference device is 30% to 90% of the left and right widths of the shallow trench isolation;

[0023] The length of the polysilicon strip on the shallow trench isolation of the measurement reference device is 60% to 90% of the length before and after the shallow trench isolation.

[0024] Preferably, the CMOS device to be monitored and the measurement reference device are both distributed with the active region and the shallow trench isolation, and the length direction of the active region and the shallow trench isolation are both the front-to-back direction;

[0025] The measurement reference device has polysilicon strips on each active area arranged along the length direction with their front ends aligned; polysilicon strips on each shallow trench isolation arranged along the length direction with their rear ends aligned;

[0026] In the measurement reference device, the front end of the polysilicon strip on each shallow trench isolation is located behind the front end of the polysilicon strip on the active area; the rear end of the polysilicon strip on each shallow trench isolation is located in front of the rear end of the polysilicon strip on the active area.

[0027] Preferably, the back-end connection on the active area of ​​the measurement reference device and the back-end connection on the shallow trench isolation both include a polysilicon contact hole, a first metal layer, a metal layer connection hole and a second metal layer;

[0028] The first metal layer is short-connected to the polysilicon strip through the polysilicon contact hole;

[0029] The second metal layer is short-connected to the first metal layer through the metal layer connection hole.

[0030] Preferably, the back-end connection lines on the active area of ​​the measurement reference device and the back-end connection lines on the shallow trench isolation are distributed in a mirror-symmetrical manner.

[0031] The present invention discloses a method for monitoring the SH (step high) of an epitaxial layer of a CMOS device. A novel TSK (Test Socket Kit) is designed to test the SH problems of the epitaxial layer corresponding to different CMOS device structures with an electrical structure, thereby realizing differential SH monitoring, reflecting the step height (SH) differences of different device structures, making up for the limitation of inline measurement of the step height (SH) of the epitaxial layer and reducing the analysis cost of TEM (Transmission electron microscope). BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 It is a schematic diagram of the AA&STI structure of a reference device and a CMOS device to be monitored according to an embodiment of a monitoring method for an epitaxial layer SH of a CMOS device of the present invention;

[0034] Figure 2 It is a schematic diagram of the structure of a measurement reference device for forming a polysilicon strip according to an embodiment of a monitoring method for an epitaxial layer SH of a CMOS device of the present invention;

[0035] Figure 3 This is a schematic diagram of an embodiment of a monitoring method for an epitaxial layer SH of a CMOS device of the present invention, in which a first metal layer M1 is short-connected to a polysilicon strip P1 through a polysilicon contact hole CT;

[0036] Figure 4 It is a schematic diagram of a first polysilicon strip string and a second polysilicon strip string in an embodiment of a monitoring method of an epitaxial layer SH of a CMOS device of the present invention;

[0037] Figure 5 yes Figure 4 A schematic diagram of a longitudinal section at line A;

[0038] Figure 6 yes Figure 4 Schematic diagram of the longitudinal section at line B. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "front", "back" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0041] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0042] Embodiment 1

[0043] A method for monitoring the step height (SH) of an epitaxial layer of a CMOS device comprises the following steps:

[0044] S1. Determine the CMOS device to be monitored, and prepare the monitored CMOS device and the measurement reference device in the same process;

[0045] The AA&STI (active area&shallow trench isolation) structure of the measurement reference device is the same as that of the CMOS device to be monitored, such as Figure 1 As shown;

[0046] The AA & STI (active area & shallow trench isolation) structures of the measurement reference device are both formed with polysilicon strips (Poly lines, PL), such as Figure 2 As shown;

[0047] The polysilicon strip (Poly line, PL) on the active area (AA) of the measurement reference device has the same length from front to back and the same width from left to right;

[0048] The polysilicon strips (Poly line, PL) on the shallow trench isolation (STI) of the measurement reference device have the same length from front to back and the same width from left to right;

[0049] The polysilicon strips (Poly line, PL) on the active area (AA) of the measurement reference device are connected in series through the back-end connection to obtain a first polysilicon strip string, such as Figure 4 As shown;

[0050] The polysilicon strips (Poly lines, PL) on the shallow trench isolation (STI) of the measurement reference device are connected in series through the back-end connection to obtain a second polysilicon strip string, such as Figure 4 As shown;

[0051] S2. A test voltage (force voltage) U is applied to the first polysilicon string and the second polysilicon string of the measurement reference device, respectively, and a current I1 flowing through the first polysilicon string and a current I2 flowing through the second polysilicon string are measured;

[0052] S3. Calculate the step height SH of the epitaxial layer of the measurement reference device:

[0053] SH=ρ*L2*I2 / (W2*U)-ρ*L1*I1 / (W1*U);

[0054] ρ is the resistivity of polysilicon, L2 is the front-to-back length of the polysilicon strip on the shallow trench isolation of the measurement reference device, W2 is the left-right width of the polysilicon strip on the shallow trench isolation of the measurement reference device, L1 is the length of the polysilicon strip on the active area of ​​the measurement reference device, and W1 is the left-right width of the polysilicon strip on the active area of ​​the measurement reference device;

[0055] S4. Taking the epitaxial layer step height SH of the measurement reference device as the epitaxial layer step height SH of the CMOS device to be monitored.

[0056] Preferably, in step S1, the monitored CMOS device and the measured reference device are prepared in the same process.

[0057] According to the resistance calculation formula R = U / I and the resistance determination formula R = ρ*L / (W*h), h = ρ*L*I / (W*U) can be deduced. R is resistance, U is voltage, I is current, ρ is the resistivity of polysilicon, L is the length of polysilicon, W is the width of polysilicon, and h is the thickness of polysilicon. The epitaxial layer SH of the measured reference device is SH = h2-h1 = ρ*L2*I2 / (W2*U)-ρ*L1*I1 / (W1*U).

[0058] In the monitoring method of the epitaxial layer SH (step high) of a CMOS device of the first embodiment, a measurement reference device is manufactured according to the CMOS device to be monitored, the AA&STI (active area&shallow trench isolation) structure of the measurement reference device is the same as that of the CMOS device to be monitored; polysilicon strips (Poly lines, PL) are formed on the AA&STI (active area&shallow trench isolation) structure of the measurement reference device, the polysilicon strips (Poly lines) on the active area (AA) have the same front-to-back length and the same left-to-right width; the polysilicon strips (Poly lines) on the shallow trench isolation (STI) have the same front-to-back length and the same left-to-right width; the polysilicon strips (Poly lines) on the active area (AA) of the measurement reference device are connected in series through a back-end connection to obtain a first polysilicon strip string, and the polysilicon strips (Poly lines) on the shallow trench isolation (STI) are connected in series to obtain a first polysilicon strip string. line) are connected in series through the back-end connection to obtain the second polysilicon string; the test voltage U is applied to the first polysilicon string and the second polysilicon string respectively to measure the current I1 flowing through the first polysilicon string and the current I2 flowing through the second polysilicon string; the epitaxial layer SH of the measurement reference device is calculated according to the current I1 flowing through the first polysilicon string and the current I2 flowing through the second polysilicon string as the epitaxial layer SH of the CMOS device to be monitored. The monitoring method of the epitaxial layer SH (step high) of the CMOS device of the first embodiment designs a new TSK (Test Socket Kit), uses the electrical structure to test the epitaxial layer SH problems corresponding to different CMOS device structures, realizes differential SH monitoring (monitor), can reflect the difference in step height (SH) of different device structures, make up for the limitation of inline measurement of epitaxial layer step height (SH) and reduce the TEM (Transmission electron microscope) analysis cost.

[0059] Embodiment 2

[0060] Based on the monitoring method of epitaxial layer SH (step high) of a CMOS device in the first embodiment, the critical dimension of the polysilicon strip on the active area (AA) of the measurement reference device is 30% to 90% of the left and right width of the active area (AA);

[0061] The length of the polysilicon strip on the active area (AA) of the measurement reference device is 60% to 90% of the front-to-back length of the active area (AA);

[0062] The critical dimension of the polysilicon strip on the shallow trench isolation (STI) of the measurement reference device is 30% to 90% of the width of the shallow trench isolation (STI);

[0063] The length of the polysilicon strip on the shallow trench isolation (STI) of the measurement reference device is 60% to 90% of the front and rear lengths of the shallow trench isolation (STI).

[0064] The second embodiment of the monitoring method of the epitaxial layer SH (step high) of the CMOS device measures the polysilicon (Poly) CD & length (critical dimension and length) of the reference device according to the specific AA & STI size definition.

[0065] Embodiment 3

[0066] Based on the monitoring method of the epitaxial layer SH (step high) of the CMOS device of the first embodiment, the CMOS device to be monitored and the measurement reference device are both arranged with the active area (AA) and the shallow trench isolation (STI) spaced apart, and the length direction of the active area (AA) and the shallow trench isolation (STI) are both the front-to-back direction;

[0067] The measurement reference device has polysilicon strips on each active area (AA) arranged along the length direction and aligned at the front end; polysilicon strips on each shallow trench isolation (STI) are arranged along the length direction and aligned at the rear end;

[0068] In the measurement reference device, the front end of the polysilicon strip on each shallow trench isolation (STI) is located behind the front end of the polysilicon strip on the active area (AA); the rear end of the polysilicon strip on each shallow trench isolation (STI) is located in front of the rear end of the polysilicon strip on the active area (AA).

[0069] Better, such as Figure 3 , Figure 4 , Figure 5 , Figure 6 As shown, the back-end connection on the active area (AA) of the measurement reference device and the back-end connection on the shallow trench isolation (STI) both include a polysilicon contact hole (contact hole) CT, a first metal layer M1, a metal layer connection hole (via) V1 and a second metal layer M2, etc.;

[0070] The first metal layer M1 is short-connected to the polysilicon strip (Polyline) through the polysilicon contact hole (contact hole) CT, as shown;

[0071] The second metal layer M2 is short-connected to the first metal layer M1 through a metal layer via V1.

[0072] Preferably, the back-end connection lines on the active area (AA) of the measurement reference device and the back-end connection lines on the shallow trench isolation (STI) are distributed in a mirror-symmetrical manner.

[0073] A monitoring method for the step high (SH) of an epitaxial layer of a CMOS device is implemented in step three, wherein the spacing distribution between an active area (AA) and a shallow trench isolation (STI) of a reference device is measured, wherein the length directions of the active area (AA) and the shallow trench isolation (STI) are both in the front-to-back direction, and the polysilicon strips (Poly line) on the active area (AA) of the reference device and the polysilicon strips (Poly line) on the shallow trench isolation (STI) are measured to maintain a left-right spacing staggered distribution in the left-right direction, so that the subsequent connecting lines can be connected in series to obtain a first polysilicon strip and a second polysilicon strip string.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for monitoring the step height of an epitaxial layer of a CMOS device, characterized in that: The following steps are involved: S1. Determine the CMOS device to be monitored and prepare the measurement reference device; The active area and shallow trench isolation structure of the measurement reference device are the same as those of the CMOS device to be monitored; Polysilicon strips are formed on the active area and shallow trench isolation structure of the measurement reference device; The polysilicon strips on the active area of ​​the measurement reference device have the same front-to-back length and the same left-to-right width; The polysilicon strips on the shallow trench isolation of the measurement reference device have the same front-to-back length and the same left-to-right width; The polysilicon strips on the active area of ​​the measurement reference device are connected in series through a back-end connection to obtain a first polysilicon strip string; The polysilicon strips on the shallow trench isolation of the measurement reference device are connected in series through a back-end connection to obtain a second polysilicon strip string; S2. Apply a test voltage U to the first polysilicon string and the second polysilicon string of the measurement reference device, respectively, and measure the current I1 flowing through the first polysilicon string and the current I2 flowing through the second polysilicon string; S3. Calculate the step height SH of the epitaxial layer of the measurement reference device: SH=ρ*L2*I2 / (W2*U)-ρ*L1*I1 / (W1*U); ρ is the resistivity of polysilicon, L2 is the front-to-back length of the polysilicon strip on the shallow trench isolation of the measurement reference device, W2 is the left-right width of the polysilicon strip on the shallow trench isolation of the measurement reference device, L1 is the length of the polysilicon strip on the active area of ​​the measurement reference device, and W1 is the left-right width of the polysilicon strip on the active area of ​​the measurement reference device; S4. Using the epitaxial layer step height of the measurement reference device as the epitaxial layer step height of the CMOS device to be monitored.

2. The method for monitoring the step height of the epitaxial layer of a CMOS device according to claim 1, characterized in that: In step S1, a monitored CMOS device and a measurement reference device are prepared in the same process.

3. The method for monitoring the step height of the epitaxial layer of a CMOS device according to claim 1, characterized in that: The critical dimension of the polysilicon strip on the active area of ​​the measurement reference device is 30% to 90% of the left and right width of the active area; The length of the polysilicon strip on the active area of ​​the measurement reference device is 60% to 90% of the front-to-back length of the active area; The critical dimension of the polysilicon strip on the shallow trench isolation of the measurement reference device is 30% to 90% of the left and right widths of the shallow trench isolation; The length of the polysilicon strip on the shallow trench isolation of the measurement reference device is 60% to 90% of the length before and after the shallow trench isolation.

4. The method for monitoring the step height of the epitaxial layer of a CMOS device according to claim 1, characterized in that: The CMOS device to be monitored and the measurement reference device are both distributed with the active area and shallow trench isolation, and the length direction of the active area and the shallow trench isolation is the front-to-back direction; The measurement reference device has polysilicon strips on each active area arranged along the length direction with their front ends aligned; polysilicon strips on each shallow trench isolation arranged along the length direction with their rear ends aligned; In the measurement reference device, the front end of the polysilicon strip on each shallow trench isolation is located behind the front end of the polysilicon strip on the active area; the rear end of the polysilicon strip on each shallow trench isolation is located in front of the rear end of the polysilicon strip on the active area.

5. The method for monitoring the step height of the epitaxial layer of a CMOS device according to claim 1, characterized in that: The back-end connection on the active area of ​​the measurement reference device and the back-end connection on the shallow trench isolation both include a polysilicon contact hole, a first metal layer, a metal layer connection hole and a second metal layer; The first metal layer is short-connected to the polysilicon strip through the polysilicon contact hole; The second metal layer is short-connected to the first metal layer through the metal layer connection hole.

6. The method for monitoring the step height of the epitaxial layer of a CMOS device according to claim 1, characterized in that: The back-end connection lines on the active area of ​​the measurement reference device and the back-end connection lines on the shallow trench isolation are distributed in a mirror-symmetrical manner.

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