Method for manufacturing air slot isolation structure

Abstract

The present invention proposes a method for manufacturing an air groove isolation structure, which belongs to the field of integrated circuit manufacturing. The method comprises the following steps: forming an ONO hard mask layer on a semiconductor substrate by thermal oxidation or deposition; photolithography and exposure on the upper surface of the ONO hard mask layer, and etching to form an air groove position; dry etching the semiconductor substrate to form a deep groove structure; sacrificial oxidation and sacrificial oxidation rinsing of the deep groove structure to form a deep groove structure after sacrificial oxidation; thermal oxidation of the sidewalls and bottom surface of the oxidized deep groove structure to form a thermal oxidation buffer layer of silicon dioxide; depositing a sealing oxide layer to fill the surface of the deep groove structure; using CMP flattening to remove the silicon dioxide on the top of the ONO hard mask layer; wet rinsing to remove the silicon nitride layer and the silicon dioxide pad oxide layer to form a complete air groove isolation structure. The present invention realizes a complete air groove isolation structure with a simple process, reduces process costs and improves production efficiency; realizes simple and reliable process control; and reduces surface stress risks.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit manufacturing, and in particular relates to a manufacturing method of an air slot isolation structure. Background Art

[0002] Power integrated circuits usually integrate high-voltage power devices with control circuits, peripheral interface circuits, and protection circuits on the same chip, serving as a bridge between the signal processing and execution parts of the system. Power integration technology mainly achieves process compatibility between high-voltage and low-voltage devices, especially the selection of appropriate vertical isolation technology to meet the isolation between high and low voltages. Common vertical isolation technologies include vertical PN junction isolation and DTI (deep trench isolation) isolation. Among them, PN junction isolation is limited in high-end and high-reliability applications due to reliability issues such as large isolation area, high leakage at high temperature, poor high-frequency performance, and complex working conditions.

[0003] Air-Gap technology is a DTI technology that can effectively solve the above-mentioned PN isolation problem and has the characteristics of high withstand voltage and suitable for high-frequency applications. The US20140291767A1 patent introduces the back-end air-gap technology. Although the air-gap isolation structure is also realized in the back-end process, since the front-end well layer and buried layer injection, thermal annealing and lateral diffusion processes have been completed, in order to prevent the unrelated well layers or buried layers on both sides of the DTI groove from affecting each other, a relatively large isolation rule is still required; there are two core problems in the process implementation of the front-end air-gap isolation structure: one is the oxide layer sealing problem on the surface of the deep groove. In order to prevent moisture or photoresist from falling into the subsequent process and causing defects, the oxide layer sealing on the surface of the deep groove needs special control; the other is the deep groove stress problem. In order to prevent stress defects in the process, the structure of the deep groove needs to be strictly controlled. The currently disclosed methods for front-end air slot isolation structures require special control of the processing technology to minimize the process fluctuations of the sealing position and the height of the oxide layer on the surface of the deep slot, which leads to high requirements for process processing and difficult process processing. In addition, the currently disclosed technology will further lead to the risk of surface stress due to the presence of STI coverage on the surface of the deep slot. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing an air slot isolation structure to solve the technical problems in the prior art that the manufacturing process of the air slot isolation has high processing requirements, is difficult to process, and has the risk of surface stress.

[0005] In order to solve the above technical problems, the manufacturing method of the air slot isolation structure of the present invention comprises the following steps:

[0006] Step S01: On a semiconductor substrate, a silicon dioxide pad oxide layer is formed by thermal oxidation or deposition, and then a silicon nitride layer is deposited on the pad oxide layer, and a silicon dioxide dielectric film layer is deposited on the silicon nitride; an ONO film layer structure composed of the silicon dioxide pad oxide layer, silicon nitride and silicon dioxide dielectric film layer forms an ONO hard mask layer for trench etching;

[0007] Step S02: photoresist coating and exposing the upper surface of the ONO hard mask layer, then etching the ONO hard mask layer, and then removing the photoresist to define the position of the air groove;

[0008] Step S03: utilizing the ONO hard mask layer to block, dry-etching the semiconductor substrate at the position of the air groove to form a deep groove structure;

[0009] Step S04: performing sacrificial oxidation and sacrificial oxidation rinsing on the deep trench structure to form a deep trench structure after sacrificial oxidation, wherein the trench width of the deep trench structure after sacrificial oxidation in the semiconductor is wider than the trench width of the deep trench structure;

[0010] Step S05: thermally oxidizing the oxidized sidewalls and bottom of the deep trench structure to form a thermal oxidation buffer layer of silicon dioxide on the sidewalls and bottom of the deep trench;

[0011] Step S06: depositing a sealing oxide layer on the upper surface of the deep trench structure and the ONO hard mask layer to fill the surface of the deep trench structure and form an air gap in the deep trench;

[0012] Step S07: using CMP planarization to remove the silicon dioxide on the top of the ONO hard mask layer; then wet rinsing to remove the silicon nitride layer; wet rinsing to remove the silicon dioxide pad oxide layer at the bottom of the ONO hard mask layer; thereby forming a complete air trench isolation structure;

[0013] Step S08: adding STI or LOCOS lateral isolation on the basis of the air trench isolation structure to form a final air trench isolation structure.

[0014] Furthermore, in the step S01, the thickness of the bottom oxide layer of the ONO hard mask layer is 1-100 nm; the thickness of the silicon nitride in the middle layer of the hard mask layer is 100-1000 nm; and the thickness of the silicon dioxide at the top of the hard mask layer structure is 1000-2000 nm.

[0015] Furthermore, in the step S03, the dry etching adopts reactive ion etching technology, the etching angle of the deep groove structure is 88°-90°; the width of the deep groove structure is 0.5-2.0 μm, and the depth of the deep groove structure is 15.0-25.0 μm.

[0016] Furthermore, in step S04, sacrificial oxidation may be performed by thermal oxidation followed by rinsing, or dry etching may be performed to directly repair the sidewalls.

[0017] Furthermore, in the step S05, the thickness of the thermal oxidation buffer layer is 100nm-1000nm.

[0018] Furthermore, in step S06, the sealing oxide layer adopts TEOS (Tetraethyl Orthosilicate) technology, such as PETEOS (plasma enhanced TEOS) or LPTEOS (low pressure TEOS).

[0019] Furthermore, in step S06, the gas in the air gap is air, nitrogen or argon.

[0020] Furthermore, in step S06, the width of the air gap is 50nm-1000nm.

[0021] Compared with the prior art, the present invention has the following beneficial technical effects:

[0022] 1) In the method described in the present invention, the benefits brought by the ONO hard mask layer are: first, benefiting from the blocking effect of the ONO structure, the subsequent sacrificial oxidation and buffer layer oxidation will not affect the semiconductor substrate or the semiconductor epitaxial surface, so that the opening size of the deep groove surface is smaller than the internal size of the groove, which is beneficial to the subsequent deep groove surface oxide layer sealing; second, benefiting from the ONO structure and its subsequent dielectric removal process, the oxide layer sealing position and the height of the sealed oxide layer on the deep groove surface can be accurately controlled, thereby achieving simpler and more reliable process control.

[0023] 2) The air slot isolation method of the present invention only requires simple processes to achieve a complete isolation structure. Compared with the existing technology, the present invention does not require complex control of the processes such as the oxide layer deposition of the slot, thereby reducing process costs and improving production efficiency.

[0024] 3) The air groove isolation method of the present invention can accurately control the sealing position and height of the sealing oxide layer on the surface of the deep groove, so that the subsequent LOCOS (field oxide layer) or STI (shallow trench isolation) process does not need to be placed on the groove, thereby effectively alleviating the stress risk of the air groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0026] Figure 1a It is a cross-sectional schematic diagram of step S01 of the air isolation structure manufacturing method according to an embodiment of the present invention.

[0027] Figure 1b It is a cross-sectional schematic diagram of step S02 of the air isolation structure manufacturing method according to an embodiment of the present invention.

[0028] Figure 1c It is a cross-sectional schematic diagram of step S03 of the air isolation structure manufacturing method according to an embodiment of the present invention.

[0029] Figure 1d It is a cross-sectional schematic diagram of step S04 of the air isolation structure manufacturing method according to an embodiment of the present invention.

[0030] Figure 1e It is a cross-sectional schematic diagram of step S05 of the air isolation structure manufacturing method according to an embodiment of the present invention.

[0031] Figure 1f It is a cross-sectional schematic diagram of step S06 of the air isolation structure manufacturing method according to an embodiment of the present invention.

[0032] Figure 1g It is a cross-sectional schematic diagram of step S07 of the air isolation structure manufacturing method according to an embodiment of the present invention.

[0033] Figure 1h Schematic diagram of an air isolation structure according to an embodiment of the present invention.

[0034] Figure 2a Schematic diagram of an SEM of an air isolation structure according to an embodiment of the present invention.

[0035] Figure 2b It is a SEM schematic diagram of the air trench isolation structure in the prior art, wherein the oxide layer sealing on the surface of the deep trench is achieved by a special process and the trench surface is covered with an STI dielectric layer.

[0036] Figure 3a It is a diagram of the isolation structure between two different BN buried layers; Figure 3b Isolation diagram between buried layer BN and P-epi (or other P-type impurities).

[0037] Figure 4a This is a graph showing the variation trend of the punch-through voltage between two different buried layers BN of the polycrystalline trench isolation structure and the air trench isolation structure as the trench bottom implantation dose changes.

[0038] Figure 4b This is a trend chart of the breakdown voltage between the buried layer BN and P-epi of the polycrystalline trench isolation structure and the air trench isolation structure as the trench bottom implantation dose changes.

[0039] Figure 5 This is the structure diagram of the NPN tube used in high-frequency DC-DC converters. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0042] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0043] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that there are other layers or regions between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be on the other layer or region.

[0044] a layer, layer below, or area beneath another layer.

[0045] If the purpose is to describe a situation where it is directly above another layer or area, this article will use “directly on…”

[0046] The expression "on the surface of" or "on and adjacent to..."

[0047] Example 1

[0048] As a preferred embodiment of the present invention, the present invention discloses a method for manufacturing an air slot isolation structure, referring to Figure 1a to Figure 1g1 is a schematic cross-sectional view of each stage of a method for manufacturing an air trench isolation structure according to an embodiment of the present invention. The method for manufacturing an air trench isolation structure according to an embodiment of the present application comprises the following steps:

[0049] Step S01: Reference Figure 1a On the semiconductor substrate 101, a silicon dioxide pad oxide layer 1021 is formed by thermal oxidation or deposition, and then a silicon nitride layer 1022 is deposited on the pad oxide layer 1021, and a silicon dioxide dielectric film layer 1023 is deposited on the silicon nitride;

[0050] An ONO (Oxide-Nitride-Oxide) film layer structure composed of a silicon dioxide pad oxide layer 1021 , a silicon nitride layer 1022 and a silicon dioxide dielectric film layer 1023 forms an ONO hard mask layer 102 for trench etching.

[0051] Specifically, the thickness of the bottom oxide layer 1021 of the ONO hard mask layer 102 is 1-100nm, and its main purpose is to serve as the silicon nitride buffer layer; the thickness of the silicon nitride 1022 in the middle layer of the hard mask layer 102 is 100-1000nm, and the thickness of the silicon nitride will affect the height of the oxide layer on the surface of the deep groove; the silicon dioxide 1023 at the top of the hard mask layer 102 structure mainly plays the role of etching hard mask, and considering the loss during dry etching of the semiconductor substrate, its thickness is 1000-2000nm.

[0052] Alternatively, the semiconductor substrate may be replaced with a semiconductor epitaxial layer.

[0053] Step S02: Reference Figure 1b , photoresist coating and exposure are performed on the upper surface of the ONO hard mask layer 102, and then the ONO hard mask layer 102 is etched, and then the photoresist is removed to define and form the air groove position 103.

[0054] Step S03: Reference Figure 1c , utilizing the blocking function of the ONO hard mask layer 102 , dry-etching the semiconductor substrate 101 at the air groove position 103 to form a deep groove structure 104 .

[0055] Specifically, the dry etching may adopt reactive ion etching (RIE) technology, and the etching angle of the deep groove structure 104 is 88°-90°; the width of the deep groove structure is 0.5-2.0 μm, and the depth of the deep groove structure is 15.0-25.0 μm.

[0056] Step S04: Reference Figure 1d Then, the deep trench structure 104 is subjected to sacrificial oxidation and sacrificial oxidation rinsing to form a deep trench structure 105 after sacrificial oxidation. The deep trench structure after sacrificial oxidation is located within the trench width (eg Figure 1dW2 in the ONO hard mask layer) is wider than the trench width (e.g. Figure 1d W1) in the deep groove structure is wider, that is, the opening size on the surface of the deep groove structure is smaller than the opening size inside the deep groove structure.

[0057] Sacrificial oxidation removes the risk of etching defects caused by dry deep trench etching. During the sacrificial oxidation and rinsing process, the surface of the semiconductor substrate will not be affected due to the blocking of the ONO hard mask layer.

[0058] Sacrificial oxidation can be achieved by thermal oxidation followed by rinsing, or by dry etching to directly repair the sidewalls.

[0059] Step S05: Reference Figure 1e , thermally oxidizing the sidewalls and bottom of the oxidized deep trench structure to form a thermal oxidation buffer layer 106 of silicon dioxide on the sidewalls and bottom of the deep trench;

[0060] The growth quality of thermal oxidation is good, and the side defects and interface states of the deep trench can be effectively controlled;

[0061] The thermal oxidation process will eat away part of the epitaxial or substrate of the sidewall of the deep trench structure, and the surface of the semiconductor substrate will not be affected due to the blocking of the ONO hard mask layer. The opening size (such as Figure 1e W1) is smaller than the opening size inside the deep groove structure (such as Figure 1e W2), which is beneficial to the subsequent deep trench structure oxide layer sealing.

[0062] The thermal oxidation buffer layer 106 has a thermal oxidation thickness of 100 nm to 1000 nm;

[0063] Step S06: Reference Figure 1f , depositing a sealing oxide layer 107 on the upper surface of the deep trench structure and the ONO hard mask layer to fill the surface of the deep trench structure and form an air gap in the deep trench;

[0064] The oxide layer sealing position on the surface of the deep groove structure (such as Figure 1f The distance between point A1 and the surface of the semiconductor substrate (such as Figure 1f The height of point A2 in the middle (such as Figure 1f H1) is subject to the thickness of the oxide layer of the seal and the deep trench etching angle; the thickness of the oxide layer of the seal will also affect the size of the air remaining in the air gap of the air groove (such as Figure 1f W3), which in turn affects the stress of the deep groove.

[0065] The gas in the air gap can be air or other gases, such as nitrogen or argon with a lower dielectric constant. The width of the air gap is 50nm-1000nm.

[0066] The sealing oxide layer 107 may adopt TEOS (Tetraethyl Orthosilicate) technology, such as PETEOS (Plasma Enhanced TEOS) or LPTEOS (Low Pressure TEOS), etc., and no special process control is required to achieve the groove surface sealing.

[0067] Step S07: Reference Figure 1g , using CMP (Chemical Mechanical Polishing) to planarize and remove the silicon dioxide 1023 on the top of the ONO hard mask layer;

[0068] The silicon nitride layer and the silicon dioxide layer of the ONO hard mask layer have a large difference in etching selectivity and can be used as a CMP stop layer; then the silicon nitride layer 1022 is wet rinsed off; the silicon dioxide pad oxide layer 1021 at the bottom of the ONO hard mask layer is wet rinsed off; and then a complete air trench isolation structure 100 is formed, and finally the oxide layer sealing position on the surface of the deep trench (such as Figure 1g The distance between point A1 and the top of the oxide layer on the deep groove surface (such as Figure 1g The height of point A3 in the middle (such as Figure 1g The H2) is precisely controlled after the silicon nitride and pad oxide layers are removed.

[0069] Step S08: Reference Figure 1h On the basis of the air trench isolation structure, STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon) lateral isolation is formed to form a final air trench isolation structure 100, and the position of the STI or LOCOS lateral isolation does not overlap with the deep trench isolation structure.

[0070] Example 2

[0071] The method for manufacturing the air slot isolation structure of the present invention is described in Example 1, which is applied to a power integrated circuit. The schematic diagram of the structure formed after the process of the present invention is as follows: Figure 1h Its SEM schematic diagram is shown in Figure 2a shown. Figure 2b FIG. 4 shows a SEM schematic diagram of a conventional air groove isolation structure.

[0072] By comparison Figure 2a and Figure 2b We can see that the thickness of the sealing oxide layer of the slot of the prior art (such as Figure 2bT1 in the figure is obviously thicker than the oxide layer thickness in the middle and bottom of the groove. Special deposition process control is required to achieve this morphology. In addition, the surface of the air groove isolation structure in the prior art is covered with STI. The main purpose is to prevent moisture or photoresist from falling into the groove in the subsequent process and causing defects. However, this approach also increases the stress risk on the groove surface.

[0073] Figure 2a The schematic diagram and SEM diagram of the air groove isolation structure of the present invention are shown, and the thickness of the sealing oxide layer on the surface of the deep groove (such as Figure 2a The thickness of the oxide layer in the middle and bottom of the groove can be made almost the same without complicated deposition process and process control. Thanks to the creative manufacturing method in the process of steps S01-S08 of Example 1 of the present invention, the present invention can also achieve better sealing and accurately control the height of the sealing oxide layer; in addition, the air groove isolation structure of the present invention technology benefits from the accurate control of the thickness of the sealing oxide layer of the groove, and the groove surface does not need to be covered with STI (such as Figure 1h As shown, the STI or LOCOS may not overlap with the deep trench isolation structure, thereby reducing the risk of trench surface stress.

[0074] The method for manufacturing the air trench isolation structure of the present invention is preferably used in power integrated circuits.

[0075] On the one hand, a complete air groove isolation structure can be realized with a relatively simple process, thereby reducing process costs and improving production efficiency; on the other hand, the oxide layer sealing position on the deep groove surface and the height of the sealing oxide layer can be precisely controlled, thereby achieving simpler and more reliable process control; on the other hand, the groove surface can be free of STI or LOCOS coverage, which can reduce the risk of surface stress.

[0076] Example 3

[0077] The two most common isolation forms in conventional BCD processes are isolation between two different buried layers BN, such as Figure 3a As shown, as well as the isolation between the buried layer BN and P-epi (or other P-type impurities), such as Figure 3b shown.

[0078] For the isolation between two different buried layers BN, the punch-through voltage on both sides of the trench is required to be greater than the maximum voltage difference between the BN on both sides during operation. Generally, the polycrystalline trench isolation structure will add an injection process at the bottom of the trench to increase the punch-through voltage on both sides of the NBL. For the isolation between BN and P-epi (or other P-type impurities), P-epi is always at zero potential. It is necessary to ensure that the breakdown voltage on both sides meets the isolation requirements and is greater than the maximum operating voltage of the internal device.

[0079] Higher breakdown voltage and punch-through voltage help improve the isolation between different devices within the chip and expand the maximum operating voltage range of internal devices, thereby increasing its scope of application.

[0080] Figure 4a The punch-through voltage between two different buried layers BN of the polycrystalline groove isolation structure and the air groove isolation structure changes with the groove bottom injection dose. The punch-through voltage between the two buried layers increases with the increase of the groove bottom injection dose. Since the polycrystalline of the polycrystalline groove isolation structure is floating in the groove, it will increase with the increase of the voltage on both sides when the device is working, and it is easy to induce carriers on the side wall of the groove to form a conductive path, thereby causing the punch-through of the BN on both sides, that is, the field-on phenomenon. Therefore, in the absence of groove bottom injection, the punch-through voltage of the device is very low, but even if the groove bottom injection is added, it is difficult to obtain a higher punch-through voltage due to the influence of the floating polycrystalline. In contrast, due to the absence of the influence of the floating polycrystalline groove, the punch-through voltage of the air groove isolation structure is also greater than that of the polycrystalline groove isolation structure in the absence of groove bottom injection.

[0081] Figure 4b The breakdown voltage between the buried layer BN and P-epi of the polycrystalline trench isolation structure and the air trench isolation structure varies with the trench bottom injection dose. Due to the influence of the trench bottom injection, the breakdown voltage of the NBL and PSUB junction is reduced. However, the floating polycrystalline in the polycrystalline trench isolation structure plays the role of a field plate when the device is working, resulting in more concentrated electric field lines between the NBL and PSUB junction near the polycrystalline trench, and the breakdown voltage drops more significantly, while the air trench isolation structure does not have this problem. Therefore, under the same conditions, the breakdown voltage of the polycrystalline trench isolation structure BN and PW (or other P-type impurities) is lower than that of the air trench isolation structure.

[0082] Therefore, the air trench isolation structure has a higher isolation effect than the polycrystalline trench isolation structure.

[0083] Example 4

[0084] Figure 5 This is a NPN tube structure diagram for high frequency DC-DC converters. It uses air slot isolation technology to meet the needs of modern DC-DC converters, which require higher switching frequencies to meet the requirements of miniaturization, high performance and high efficiency.

[0085] In traditional polycrystalline trench isolation structures, the filling material usually introduces a certain amount of parasitic capacitance, because insulating materials such as polysilicon or silicon oxide have a certain dielectric constant, which will cause capacitance to form between different conductive layers. Compared with the polycrystalline trench isolation structure, since the dielectric constant of gas is usually much smaller than that of solid insulating materials, and the thickness of the oxide layer is thicker than that of the polycrystalline trench isolation structure, the air trench isolation structure can reduce or completely eliminate these parasitic capacitances. Figure 5The parasitic capacitance C2 is smaller. Since the air slot isolation structure reduces the parasitic capacitance and achieves a lower capacitance value, the circuit performance can be improved, especially in high-frequency applications.

[0086] In addition, the air gap of the air slot isolation structure can also help prevent signal cross-interference between different conductive layers, which is especially important in complex integrated circuits. By introducing air gaps between different conductive layers, the possibility of signal interference can be reduced, thereby improving the reliability and performance of the circuit.

[0087] Therefore, the air slot isolation structure reduces parasitic capacitance, improves the high-frequency performance of the transistor, and reduces signal cross-interference, which are very important factors in high-performance electronic devices. This technology helps improve the performance of devices such as complementary bipolar transistors, especially in high-frequency DC-DC converters and other high-speed electronic devices.

[0088] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A method for manufacturing an air slot isolation structure, characterized in that: The steps include: Step S01: On a semiconductor substrate, a silicon dioxide pad oxide layer is formed by thermal oxidation or deposition, and then a silicon nitride layer is deposited on the pad oxide layer, and a silicon dioxide dielectric film layer is deposited on the silicon nitride; an ONO film layer structure composed of the silicon dioxide pad oxide layer, silicon nitride and silicon dioxide dielectric film layer forms an ONO hard mask layer for trench etching; Step S02: photoresist coating and exposing the upper surface of the ONO hard mask layer, then etching the ONO hard mask layer, and then removing the photoresist to define the position of the air groove; Step S03: utilizing the ONO hard mask layer to block, dry-etching the semiconductor substrate at the position of the air groove to form a deep groove structure; Step S04: performing sacrificial oxidation and sacrificial oxidation rinsing on the deep trench structure to form a deep trench structure after sacrificial oxidation; the trench width of the deep trench structure after sacrificial oxidation in the semiconductor is wider than the trench width in the ONO hard mask layer; Step S05: thermally oxidizing the oxidized sidewalls and bottom of the deep trench structure to form a thermal oxidation buffer layer of silicon dioxide on the sidewalls and bottom of the deep trench; Step S06: depositing a sealing oxide layer on the upper surface of the deep trench structure and the ONO hard mask layer to fill the surface of the deep trench structure and form an air gap in the deep trench; Step S07: using CMP planarization to remove the silicon dioxide on the top of the ONO hard mask layer; then wet rinsing to remove the silicon nitride layer; wet rinsing to remove the silicon dioxide pad oxide layer on the bottom of the ONO hard mask layer; thereby forming a complete air trench isolation structure; the height of the oxide layer sealing position on the surface of the deep trench from the top of the oxide layer on the surface of the deep trench is precisely controlled after the silicon nitride and pad oxide layers are removed, the height of the top of the oxide layer on the surface of the deep trench is higher than the height of the surface of the semiconductor substrate, and the width of the oxide layer in the semiconductor layer is wider than the width of the oxide layer outside the semiconductor layer; Step S08: adding STI or LOCOS lateral isolation on the basis of the air trench isolation structure to form a final air trench isolation structure; the position of the STI or LOCOS lateral isolation does not overlap with the deep trench isolation structure, thereby reducing the risk of trench surface stress.

2. The method for manufacturing an air slot isolation structure according to claim 1, characterized in that: In the step S01, the thickness of the bottom oxide layer of the ONO hard mask layer is 1-100 nm; the thickness of the silicon nitride in the middle layer of the hard mask layer is 100-1000 nm; and the thickness of the silicon dioxide at the top of the hard mask layer structure is 1000-2000 nm.

3. The method for manufacturing an air slot isolation structure according to claim 1, characterized in that: In the step S03, the dry etching adopts reactive ion etching technology, the etching angle of the deep groove structure is 88°-90°; the width of the deep groove structure is 0.5-2.0 μm, and the depth of the deep groove structure is 15.0-25.0 μm.

4. The method for manufacturing an air slot isolation structure according to claim 1, characterized in that: In the step S04, sacrificial oxidation is performed by thermal oxidation followed by rinsing or by dry etching to directly repair the sidewalls.

5. The method for manufacturing an air slot isolation structure according to claim 1, characterized in that: In the step S05, the thickness of the thermal oxidation buffer layer is 100nm-1000nm.

6. The method for manufacturing an air slot isolation structure according to claim 1, characterized in that: In step S06, the gas in the air gap is air, nitrogen or argon.

7. The method for manufacturing an air slot isolation structure according to claim 1, characterized in that: In the step S06, the width of the air gap is 50nm-1000nm.

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