Chip packaging substrate and preparation method thereof

Abstract

The invention provides a chip packaging substrate and a preparation method thereof. The preparation method of the chip packaging substrate comprises the following steps that a plurality of modified parts are formed in an original substrate, the original substrate is provided with a front face and a back face which are opposite to each other, each modified part extends from the front face to the back face, and a first distance is formed between the back face and each modified part; a first wiring layer is prepared on the front face, the first wiring layer comprises a first conductive part, and the first conductive part covers all the modified parts; thinning the original substrate from the back surface to a denatured part, and removing the denatured part to form a through hole; a plurality of conductive columns and a second wiring layer are prepared from the back face, the through holes are filled with the conductive columns, the second wiring layer is formed on the back face and comprises a second conductive part, and the second conductive part is electrically connected with the first conductive part through the conductive columns. According to the invention, the preparation difficulty of the chip packaging substrate can be reduced, and the reliability of the chip packaging substrate can be improved.

Description

Technical Field

[0001] The present application relates to the field of electronic packaging, and in particular to a chip packaging substrate and a preparation method thereof. Background Art

[0002] Through Glass Via (TGV) interconnection technology has the advantages of excellent high-frequency electrical properties, low cost, simple process flow, and strong mechanical stability. Therefore, it is widely used in RF devices, Micro-Electro-Mechanical Systems (MEMS) packaging, optoelectronic system integration and other fields.

[0003] In the related art, there are deficiencies in the method for preparing the chip packaging substrate. Summary of the invention

[0004] The embodiments of the present application provide a chip packaging substrate and a method for preparing the same, aiming to reduce the difficulty of preparing the chip packaging substrate and improve the reliability of the chip packaging substrate.

[0005] An embodiment of the first aspect of the present application provides a chip packaging substrate, the chip packaging substrate comprising: a substrate having a front side and a back side opposite to each other and a through hole extending from the front side to the back side; a first wiring layer comprising a first conductive portion, the first conductive portion comprising a first seed layer and a first routing layer, the first seed layer being arranged on the front side and covering each through hole, and the first routing layer being stacked on the first seed layer; a plurality of conductive columns, the conductive columns comprising an inner wall seed layer arranged in the through hole and connected to the first seed layer, and a conductive core stacked on the inner wall seed layer; a second wiring layer comprising a second conductive portion, the second conductive portion comprising a second seed layer arranged on the back side and connected to the inner wall seed layer, and a second routing layer stacked on the second seed layer and connected to the conductive core.

[0006] According to the aforementioned embodiment of the first aspect of the present application, the aperture of the through hole tends to decrease from the back to the front; or / and, the thickness of the first seed layer and the thickness of the inner wall seed layer are both smaller than the thickness of the seed material on the axis of the through hole.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the first seed layer includes a plurality of first seed portions, and the through hole is covered by the first seed portions; the first routing layer includes a plurality of first routings, and each first routing layer is stacked on each first seed portion.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the second seed layer includes multiple second seed portions, and the inner wall seed layer is connected to the second seed portions; the second routing layer includes multiple second routing layers, and each second routing layer is stacked on each second seed portion.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the inner wall seed layer and the second seed portion are an integrated structure; or / and, the conductive core and the second wiring are an integrated structure.

[0010] An embodiment of the second aspect of the present application provides a method for preparing a chip packaging substrate, which comprises the following steps: forming a plurality of degeneration parts in a substrate original plate, the substrate original plate having a front side and a back side opposite to each other, each degeneration part extending from the front side to the back side, and a first spacing between the back side and the degeneration part; preparing a first wiring layer on the front side, the first wiring layer comprising a first conductive part, the first conductive part covering each degeneration part; thinning the substrate original plate to the degeneration part from the back side, removing the degeneration part to form a through hole; preparing a plurality of conductive pillars and a second wiring layer from the back side, each conductive pillar filling each through hole, the second wiring layer being formed on the back side, the second wiring layer comprising a second conductive part, the second conductive part being electrically connected to the first conductive part via a plurality of conductive pillars.

[0011] According to the aforementioned implementation of the first aspect of the present application, the original substrate is made of glass.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the steps of thinning the substrate original plate from the back side to the denatured portion, and removing the denatured portion to form a through hole include: thinning the substrate original plate from the back side for the first time; and thinning the substrate original plate from the back side to the denatured portion for the second time using a first etchant, and removing the denatured portion to form a through hole.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the first conductive portion includes a first seed layer and a first routing layer that are stacked, the first seed layer covers the degeneration portion, and in the substrate original plate and the first seed layer, the first etchant selectively etches the substrate original plate.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, the thinning rate of the first thinning is greater than the thinning rate of the second thinning.

[0015] According to any of the aforementioned embodiments of the first aspect of the present application, the first etchant is an alkaline etchant or an acidic etchant.

[0016] According to any of the aforementioned embodiments of the first aspect of the present application, a second etchant is used to perform a first thinning of the substrate original plate until a second distance is provided between the back side and each degeneration portion.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the ratio of the etching rate of the second etchant on the original substrate to the etching rate of the first etchant on the original substrate is 5-20.

[0018] According to any of the aforementioned embodiments of the first aspect of the present application, the second etchant is an acidic etchant.

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, a grinding process is used to perform a first thinning of the original substrate until each modified portion is exposed.

[0020] According to any of the aforementioned embodiments of the first aspect of the present application, the step of preparing a first wiring layer on the front side includes: forming a first seed material layer covering the front side on the front side; preparing a patterned first pattern layer on the first seed material layer, the first pattern layer having a plurality of first openings, the first openings exposing the first seed material layer to form a first area, and the degeneration part is covered by the first area; forming a first routing layer on each first area; removing the first pattern layer to expose the first seed material layer to form a plurality of first removal parts; removing the first removal parts to form a first seed layer.

[0021] According to any of the aforementioned embodiments of the first aspect of the present application, the first seed material layer is formed by a deposition process; or / and, the first routing layer is formed by an electroplating process.

[0022] According to any of the aforementioned embodiments of the first aspect of the present application, the step of preparing a plurality of conductive pillars and a second wiring layer from the back side includes: forming an inner wall seed layer arranged in the through hole and a second seed material layer covering the back side from the back side; preparing a patterned second pattern layer on the second seed material layer, the second pattern layer having a plurality of second openings, each second opening exposing the second seed material layer to form a second area, and the through hole is exposed through the second opening; forming a conductive core on the inner wall seed layer and forming a second routing on each second area; removing the second pattern layer to expose the second seed material layer to form a plurality of second removal portions; removing the second removal portions to form a second seed layer.

[0023] According to any of the aforementioned embodiments of the first aspect of the present application, the second seed material layer is formed by a deposition process; or / and, the second routing layer is formed by an electroplating process.

[0024] According to any of the aforementioned embodiments of the first aspect of the present application, before the step of thinning the substrate original plate to the denatured portion from the back side, removing the denatured portion to form a through hole or / and the step of preparing multiple conductive pillars and a second wiring layer from the back side, the preparation method further includes: bonding a protective member to the front side to cover the first wiring layer; after the step of preparing multiple conductive pillars and a second wiring layer from the back side, the preparation method further includes: removing the protective member.

[0025] In the preparation method of the chip packaging substrate of the present application, by first forming a plurality of degeneration parts in the substrate original plate, and then preparing the first wiring layer on the front side of the substrate original plate, a thicker substrate original plate can be selected to improve the mechanical strength of the substrate original plate, thereby reducing the risk of substrate original plate fragmentation during the degeneration part forming process and the first wiring layer forming process, and the process of directly preparing the first wiring layer on the front side of the substrate original plate with a plurality of degeneration parts formed is simple. Therefore, the preparation method of the chip packaging substrate of the present application can not only reduce the difficulty of preparing the chip packaging substrate, but also improve the reliability of the chip packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0027] Figure 1 It is a structural schematic diagram of a chip packaging substrate provided by an embodiment of the first aspect of the present application; Figure 2 It is a structural schematic diagram of another chip packaging substrate provided by the embodiment of the first aspect of the present application; Figure 3 It is a structural schematic diagram of another chip packaging substrate provided by the embodiment of the first aspect of the present application; Figure 4 is a flow chart of a method for preparing a chip packaging substrate provided in an embodiment of the second aspect of the present application; Figure 5 It is a flow chart of thinning the substrate original plate from the back side to the denatured portion, removing the denatured portion to form a through hole, provided by the second aspect embodiment of the present application; Figure 6 is a flow chart of preparing a first wiring layer on the front side provided by an embodiment of the second aspect of the present application; Figure 7 It is a flow chart of preparing a plurality of conductive pillars and a second wiring layer from the back side provided by an embodiment of the second aspect of the present application; Figures 8 to 23 It is a structural schematic diagram of an intermediate product in the preparation process of the chip packaging substrate preparation method provided in the second aspect of the embodiment of the present application; Fig.24 It is a structural schematic diagram of a chip packaging substrate prepared by the method for preparing a chip packaging substrate provided in an embodiment of the second aspect of the present application.

[0028] Description of reference numerals: 1. Original substrate; 1A, substrate; 11, denaturation portion; 11A, through hole; 13, front side; 15, back side; 3. first wiring layer; 301. first conductive part; 303. first insulating part; 305. first insulator; 3a. first connecting line; 30. first seed material layer; 30A. first area; 30B. first removal part; 31. first seed layer; 311. first seed part; 33. first routing layer; 331. first routing; 333. first sub-layer; 335. first insulating layer; 337. first conductive bridge; 4. a first pattern layer; 41. a first opening; 5. Conductive column; 51. Inner wall seed layer; 53. Conductive core; 6, second wiring layer; 601, second conductive part; 603, second insulating part; 605, second insulator; 6a, second connecting line; 60, second seed material layer; 60A, second area; 60B, second removal part; 61, second seed layer; 611, second seed part; 63, second routing layer; 631, second routing; 633, second sub-layer; 635, second insulating layer; 637, second conductive bridge; 7. second pattern layer; 71. second opening; 8. Protective film; 9. Carrier board; 10. Peelable adhesive; D1, first spacing; D2, second spacing. DETAILED DESCRIPTION

[0029] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0030] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0031] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0032] Through Glass Via (TGV) interconnection technology has the advantages of excellent high-frequency electrical properties, low cost, simple process flow, and strong mechanical stability. Therefore, it is widely used in RF devices, Micro-Electro-Mechanical Systems (MEMS) packaging, optoelectronic system integration and other fields.

[0033] In the related art, the preparation method of the chip packaging substrate can be divided into the following two process routes: 1. Blind hole technology: first make a blind hole on the glass substrate, then fill the blind hole and make a metal wiring layer on the front side, grind the back side of the glass substrate so that the metal wiring layer on the front side is exposed from the back side, and then make another metal wiring layer on the back side, so as to achieve the interconnection between the front and back sides. However, grinding will produce a large shear stress, which is easy to cause defects such as the breakage of the glass substrate; in order to reduce the amount of grinding, ultra-thin glass can be used, but the ultra-thin glass itself is not strong enough and is easy to break in the subsequent process, which is not conducive to large-area preparation.

[0034] 2. Through-hole technology: First, make through-holes on the glass substrate, fill the through-holes by double-sided electroplating, and make metal wiring layers on the front and back sides. However, filling through-holes is difficult, and the process and equipment requirements for double-sided electroplating of through-holes are high. In addition, after through-hole electroplating, the metal thickness on the front and back sides of the glass substrate is relatively thick, and the metal layers on the front and back sides need to be ground and removed.

[0035] In order to solve the above technical problems, this application is proposed. In order to better understand this application, Figures 1 to 24 The chip packaging substrate and the preparation method thereof according to the embodiments of the present application are described in detail.

[0036] See also Figures 1 to 3 , Figure 1 It is a structural schematic diagram of a chip packaging substrate provided by an embodiment of the first aspect of the present application; Figure 2 It is a structural schematic diagram of another chip packaging substrate provided by the embodiment of the first aspect of the present application; Figure 3 It is a structural schematic diagram of another chip packaging substrate provided in the embodiment of the first aspect of the present application.

[0037] like Figure 1 As shown, an embodiment of the first aspect of the present application provides a chip packaging substrate. The chip packaging substrate includes a substrate 1A, a first wiring layer 3, a plurality of conductive pillars 5 and a second wiring layer 6, the substrate 1A has a front side 13 and a back side 15 opposite to each other and a through hole 11A extending from the front side 13 to the back side 15, the first wiring layer 3 includes a first conductive part 301, the first conductive part 301 includes a first seed layer 31 and a first routing layer 33, the first seed layer 31 is arranged on the front side 13 and covers each through hole 11A, the first routing layer 33 is stacked on the first seed layer 31, the conductive pillar 5 includes an inner wall seed layer 51 arranged in the through hole 11A and connected to the first seed layer 31, and a conductive core 53 arranged on the inner wall seed layer 51, the second wiring layer 6 includes a second conductive part 601, the second conductive part 601 includes a second seed layer 61 arranged on the back side 15 and connected to the inner wall seed layer 51, and a second routing layer 63 stacked on the second seed layer 61 and connected to the conductive core 53.

[0038] The front surface 13 and the back surface 15 are two surfaces on opposite sides of the substrate 1A, that is, the front surface 13 and the back surface 15 are arranged opposite to each other; the direction from the back surface 15 to the front surface 13 is the thickness direction.

[0039] Optionally, the substrate 1A is made of glass.

[0040] Optionally, the first seed layer 31 , the inner wall seed layer 51 and the second seed layer 61 are all seed material layers, and the seed material layers are conductive.

[0041] Optionally, the material of the seed material layer includes but is not limited to at least one of Ti, Cu, and TiN.

[0042] In some embodiments, the aperture of the through hole 11A decreases along the direction from the back surface 15 to the front surface 13 , that is, the aperture of the through hole 11A at the end close to the back surface 15 is larger than the aperture of the through hole 11A at the end close to the front surface 13 .

[0043] In some embodiments, the thickness of the first seed layer 31 and the thickness of the inner wall seed layer 51 are both smaller than the thickness of the seed material on the axis of the through hole 11A.

[0044] Optionally, the thickness of the seed material on the axis of the through hole 11A is equal to the sum of the thickness of the first seed layer 31 and the thickness of the inner wall seed layer 51 .

[0045] Optionally, the first seed layer 31 includes a plurality of first seed portions 311 , and the through hole 11A is covered by the first seed portions 311 ; the first routing layer 33 includes a plurality of first routings 331 , and each first routing 331 is disposed on each first seed portion 311 .

[0046] Optionally, among the multiple first seed sub-portions 311, each first seed sub-portion 311 covers at least one through hole 11A, that is, each first seed sub-portion 311 is used to cover the through hole 11A; or, among the multiple first seed sub-portions 311, some first seed sub-portions 311 are used to cover the through hole 11A, and each first seed sub-portion 311 among these first seed sub-portions 311 covers one or more through holes 11A, that is, other first seed sub-portions 311 among the multiple first seed sub-portions 311 may not cover the through hole 11A.

[0047] Exemplarily, among the plurality of first seed portions 311 , each first seed portion 311 covers at least one through hole 11A.

[0048] Optionally, the orthographic projection of the first wiring 331 on the substrate 1A is located within the orthographic projection range of the first seed portion 311 on the substrate 1A.

[0049] Optionally, the orthographic projection of the first wiring 331 on the substrate 1A coincides with the orthographic projection of the first seed portion 311 on the substrate 1A.

[0050] Optionally, the first seed portion 311 and the first routing line 331 constitute a first connecting line 3 a , and a plurality of first connecting lines 3 a are arranged at intervals.

[0051] like Figure 1 As shown, in some embodiments, the first trace 331 is a single-layer structure.

[0052] Optionally, the first wiring 331 is a single-layer metal layer.

[0053] Optionally, the first wiring 331 is a single-layer Cu layer.

[0054] In some embodiments, the thickness of the first trace 331 is 0-5 μm.

[0055] For example, the thickness of the first wiring 331 may be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm. Of course, the thickness of the first wiring 331 may also be any combination range of the above values.

[0056] like Figure 2 As shown, in some embodiments, the first trace 331 includes at least two first sub-layers 333, and a first insulating layer 335 is disposed between two adjacent first sub-layers 333. A first conductive bridge 337 connecting two adjacent first sub-layers 333 is disposed in the first insulating layer 335.

[0057] like Figure 1 As shown, in some embodiments, the first wiring layer 3 is the first conductive portion 301 .

[0058] like Figure 3As shown, in some embodiments, the first wiring layer 3 further includes a first insulating portion 303 , and the first insulating portion 303 is disposed in the same layer as the first conductive portion 301 .

[0059] In some embodiments, the first insulating portion 303 includes a plurality of first insulators 305, and two adjacent first connection lines 3a are electrically isolated by the first insulators 305. On the one hand, the first insulators 305 are conducive to improving the breakdown voltage between two adjacent first connection lines 3a, and on the other hand, are conducive to reducing the spacing between two adjacent first connection lines 3a to improve the wiring density of the first wiring layer 3.

[0060] Optionally, the second seed layer 61 includes a plurality of second seed portions 611 , and the inner wall seed layer 51 is connected to the second seed portions 611 ; the second routing layer 63 includes a plurality of second routings 631 , and each second routing 631 is disposed on each second seed portion 611 .

[0061] Optionally, among the multiple second seed sub-portions 611, each second seed sub-portion 611 is connected to at least one inner wall seed layer 51, that is, each second seed sub-portion 611 is used to connect to the inner wall seed layer 51; or, among the multiple second seed sub-portions 611, some second seed sub-portions 611 are used to connect to the inner wall seed layer 51, and each second seed sub-portion 611 among these second seed sub-portions 611 is connected to one or more inner wall seed layers 51, that is, other second seed sub-portions 611 among the multiple second seed sub-portions 611 may not be connected to the inner wall seed layer 51.

[0062] Exemplarily, among the plurality of second seed portions 611 , each second seed portion 611 is connected to at least one inner wall seed layer 51 .

[0063] Optionally, the inner wall seed layer 51 and the second seed portion 611 are an integral structure.

[0064] In some optional embodiments, the inner wall seed layer 51 and the second seed portion 611 are an integrated structure, which means that the whole formed by the inner wall seed layer 51 and the second seed portion 611 has good structural integrity, and there is no splicing transition area between the inner wall seed layer 51 and the second seed portion 611. Therefore, the inner wall seed layer 51 and the second seed portion 611 can be molded at one time through a molding process, thereby reducing the preparation steps of the inner wall seed layer 51 and the second seed portion 611.

[0065] Optionally, the conductive core 53 and the second wiring 631 are an integrated structure.

[0066] In some optional embodiments, the conductive core 53 and the second wiring 631 are an integrated structure, which means that there is no splicing transition area between the conductive core 53 and the second wiring 631 .

[0067] Optionally, the orthographic projection of the second wiring 631 on the substrate 1A is located within the orthographic projection range of the integrated structure formed by the inner wall seed layer 51 and the second seed portion 611 on the substrate 1A.

[0068] Optionally, the orthographic projection of the second wiring 631 on the substrate 1A coincides with the orthographic projection of the integrated structure formed by the inner wall seed layer 51 and the second seed portion 611 on the substrate 1A.

[0069] Optionally, the second seed portion 611 and the second trace 631 constitute a second connection line 6 a , the second connection line 6 a is electrically connected to the first connection line 3 a via at least one conductive column 5 , and a plurality of second connection lines 6 a are arranged at intervals.

[0070] like Figure 1 As shown, in some embodiments, the second trace 631 is a single-layer structure.

[0071] Optionally, the second wiring 631 is a single-layer metal layer.

[0072] Optionally, the second wiring 631 is a single-layer Cu layer.

[0073] Optionally, the thickness of the second wiring 631 is 0-5 μm.

[0074] For example, the thickness of the second wiring 631 may be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm. Of course, the thickness of the second wiring 631 may also be any combination range of the above values.

[0075] like Figure 2 As shown, in some embodiments, the second trace 631 includes at least two second sub-layers 633, and a second insulating layer 635 is disposed between two adjacent second sub-layers 633. A second conductive bridge 637 connecting two adjacent second sub-layers 633 is disposed in the second insulating layer 635.

[0076] In these embodiments, when the second routing 631 is a single-layer structure, the conductive core 53 and the second routing 631 are an integrated structure, which also means that the conductive core 53 and the second routing 631 have good structural integrity as a whole. Therefore, the conductive core 53 and the second routing 631 can be formed at one time through a molding process, thereby reducing the preparation steps of the conductive core 53 and the second routing 631; and when the conductive core 53 and the second routing 631 are formed at one time through a molding process, the inner wall seed layer 51 and the second seed portion 611 are an integrated structure, which can also improve the good structural integrity of the whole formed by the conductive core 53 and the second routing 631.

[0077] In these embodiments, when the second routing 631 includes at least two second sub-layers 633, the conductive core 53 and the second routing 631 are an integrated structure, which also means that the whole formed by the conductive core 53 and one of the second sub-layers 633 in the second routing 631 has good structural integrity. Therefore, the conductive core 53 and one of the second sub-layers 633 in the second routing 631 can be molded at one time through a molding process, thereby reducing the preparation steps of the conductive core 53 and one of the second sub-layers 633 in the second routing 631; and when the conductive core 53 and one of the second sub-layers 633 in the second routing 631 are molded at one time through a molding process, the inner wall seed layer 51 and the second seed portion 611 are an integrated structure, which can also improve the good structural integrity of the whole formed by the conductive core 53 and one of the second sub-layers 633 in the second routing 631.

[0078] like Figure 1 As shown, in some embodiments, the second wiring layer 6 is the second conductive portion 601 .

[0079] like Figure 3 As shown, in some embodiments, the second wiring layer 6 further includes a second insulating portion 603 , and the second insulating portion 603 is disposed in the same layer as the second conductive portion 601 .

[0080] In some embodiments, the second insulating portion 603 includes a plurality of second insulators 605, and two adjacent second connection lines 6a are electrically isolated by the second insulators 605. On the one hand, the second insulators 605 are conducive to improving the breakdown voltage between two adjacent second connection lines 6a, and on the other hand, are conducive to reducing the spacing between two adjacent second connection lines 6a to improve the wiring density of the second wiring layer 6.

[0081] See also Figure 4 , Figure 4 It is a flow chart of a method for preparing a chip packaging substrate provided in an embodiment of the second aspect of the present application.

[0082] like Figure 4 As shown, an embodiment of the second aspect of the present application provides a method for preparing a chip packaging substrate, comprising the following steps: Step S01: Figure 8 As shown, a plurality of degeneration parts 11 are formed in the substrate original plate 1. The substrate original plate 1 has a front side 13 and a back side 15 opposite to each other. Each degeneration part 11 extends from the front side 13 to the back side 15. There is a first distance D1 between the back side 15 and the degeneration part 11.

[0083] Among them, the denatured portion 11 is easier to remove than the non-denatured portion of the substrate original plate 1 .

[0084] The front side 13 and the back side 15 are two surfaces on two opposite sides of the substrate original plate 1 , that is, the front side 13 and the back side 15 are arranged opposite to each other.

[0085] When the multiple degeneration parts 11 are formed, there is an error between the designed depth and the actual depth, which may result in that the depths of the degeneration parts 11 are not necessarily the same. Optionally, the first spacing D1 is the distance between the degeneration part 11 closest to the back surface 15 and the back surface 15.

[0086] Step S02: Fig.13 As shown, a first wiring layer 3 is prepared on the front side 13 . The first wiring layer 3 includes a first conductive portion 301 . The first conductive portion 301 covers each of the modified portions 11 .

[0087] Step S03: Figures 15 to 17 As shown, the substrate original plate 1 is thinned from the back side 15 to the denatured portion 11, and the denatured portion 11 is removed to form a through hole 11A. That is, the through hole 11A extends from the back side 15 to the first conductive portion 301. Since the through hole 11A is covered by the first conductive portion 301, the through hole 11A covered by the first conductive portion 301 forms a blind hole structure.

[0088] The original substrate 1 is used as the substrate 1A of the chip packaging substrate after step S03.

[0089] Optionally, the radial width of the denatured portion 11 is smaller than the diameter of the through hole 11A.

[0090] Optionally, the degeneration portion 11 is cylindrical, and the radial width of the degeneration portion 11 is the diameter.

[0091] Step S04: Fig.23 As shown, a plurality of conductive pillars 5 and a second wiring layer 6 are prepared from the back side 15 , each conductive pillar 5 fills each through hole 11A, and the second wiring layer 6 is formed on the back side 15 . The second wiring layer 6 includes a second conductive portion 601 , and the second conductive portion 601 is electrically connected to the first conductive portion 301 via a plurality of conductive pillars 5 .

[0092] In the preparation method of the chip packaging substrate of the present application, a plurality of degeneration parts 11 are first formed in the substrate original plate 1, and then the first wiring layer 3 is prepared on the front side 13 of the substrate original plate 1. Therefore, a substrate original plate with a larger thickness can be selected to improve the mechanical strength of the substrate original plate, thereby reducing the risk of substrate original plate breakage in the process of forming the degeneration part 11 and the first wiring layer 3. In addition, the process of directly preparing the first wiring layer 3 on the front side 13 of the substrate original plate 1 on which the plurality of degeneration parts 11 are formed is simple. At the same time, the substrate original plate 1 is thinned from the back side 15 to the degeneration part 11, and the degeneration part 11 is removed. In the process of forming the through hole 11A by the denaturation part 11, the problem of reducing the reliability of the chip packaging substrate by damaging the substrate original plate 1 will not be caused. Moreover, although the substrate original plate 1 is penetrated, the through hole 11A forms a blind hole structure due to the existence of the first conductive part 301. Compared with the through hole double-sided deposition process, the preparation of the second wiring layer 6 based on the blind hole structure can control the thickness of the metal layer formed on the back side 15 within the thickness range directly used as the back side wiring. Therefore, the back side wiring and the filling of the through hole 11A can be made simultaneously to reduce the process steps and reduce the cost, and the back side wiring does not need to be ground. Therefore, the preparation method of the chip packaging substrate of the present application can not only reduce the difficulty of preparing the chip packaging substrate, but also improve the reliability of the chip packaging substrate.

[0093] In some embodiments, the substrate original plate 1 is made of glass. The substrate original plate 1 made of glass has better heat resistance and corrosion resistance and is not easy to deform, which is beneficial to improving the stability and reliability of the chip packaging substrate.

[0094] In some embodiments, the denatured portion 11 may be formed by laser induction, but the embodiments of the present application are not limited to the above forming process.

[0095] See also Figure 5 , Figure 5 It is a flow chart provided by the first aspect embodiment of the present application for thinning the original substrate from the back side to the denatured portion and removing the denatured portion to form a through hole.

[0096] like Figure 5 As shown, step S03 includes: S031, such as Fig.15 or Fig.16 As shown, the substrate original plate 1 is thinned for the first time from the back side 15 .

[0097] S032, such as Fig.17As shown, the first etchant is used to perform a second thinning of the substrate original plate 1 from the back side 15 to the denatured portion 11, and the denatured portion 11 is removed to form a through hole 11A. Since the denatured portion 11 is more easily etched than the non-denatured portion of the substrate original plate 1, the aperture of the through hole 11A tends to decrease from the back side 15 to the front side 13 during the process of etching away the denatured portion 11 to form the through hole 11A. That is, the aperture of the through hole 11A at the end close to the back side 15 is larger than the aperture of the through hole 11A at the end close to the front side 13.

[0098] like Fig.13 As shown, optionally, the first conductive portion 301 includes a first seed layer 31 and a first routing layer 33 which are stacked, the first seed layer 31 covers the degeneration portion 11, and in the substrate original plate 1 and the first seed layer 31, the first etchant selectively etches the substrate original plate 1. That is, the first etchant etches the substrate original plate 1 and the degeneration portion 11, but does not etch the first seed layer 31.

[0099] Optionally, the thinning rate of the first thinning is greater than the thinning rate of the second thinning.

[0100] Optionally, in terms of thinning thickness, the etching rate of the first etchant on the substrate original plate 1 is 0.1 μm / min to 1 μm / min. The thickness of the substrate original plate 1 is the thickness of the substrate original plate 1 in the direction from the front surface 13 to the back surface 15 .

[0101] Exemplarily, the etching rate of the first etchant on the substrate original plate 1 can be 0.1 μm / min, 0.2 μm / min, 0.3 μm / min, 0.4 μm / min, 0.5 μm / min, 0.6 μm / min, 0.7 μm / min, 0.8 μm / min, 0.9 μm / min or 1 μm / min. Of course, the etching rate of the first etchant on the substrate original plate 1 can also be any combination range of the above values.

[0102] In some embodiments, the first etchant may be an alkaline etchant. Although the alkaline etchant has a low etching rate on the substrate original plate 1, it has good uniformity and is friendly to the first wiring layer 3, so it will not cause the first wiring layer 3 to be etched.

[0103] Optionally, the alkaline etchant includes a first solvent and an alkaline substance.

[0104] Optionally, the alkaline substance includes but is not limited to sodium hydroxide, potassium hydroxide and the like.

[0105] Optionally, the first solvent is water.

[0106] Optionally, the components of the alkaline etchant and the content of each component can be specifically designed according to the requirements of the etching rate of the first etchant on the substrate original plate 1.

[0107] In some embodiments, the first etchant may also be an acidic etchant.

[0108] Optionally, the acidic etchant includes hydrofluoric acid. The hydrofluoric acid and the main component SiO 2 reaction. Although the etching rate of hydrofluoric acid on the substrate original plate 1 is fast, the etching uniformity is poor, and hydrofluoric acid can etch metals that are not resistant to acid corrosion. Therefore, in order to avoid the first seed layer 31 being etched and causing pores between the first wiring layer 33 and the substrate original plate 1, thereby causing reliability risks, the first seed layer 31 is acid-resistant so that the first etchant selectively etches the substrate original plate 1 in the substrate original plate 1 and the first seed layer 31. At the same time, in order to avoid the fast etching rate of hydrofluoric acid on the substrate original plate 1, which causes the aperture of the through hole 11A to be too large or / and the uniformity of the through hole 11A to be poor, the etching rate of the first etchant on the substrate original plate 1 is controlled to be 0.1μm / min~1μm / min.

[0109] Optionally, the acidic etchant further comprises a second solvent and another acid. The other acid is used to increase the hydrofluoric acid and SiO 2 The solubility of the byproducts after the reaction. When the concentration of hydrofluoric acid is the same, the addition of other acids is beneficial to increasing the etching rate of the acidic etchant on the substrate original plate 1; when the etching rate of the substrate original plate 1 is the same, it is beneficial to reduce the concentration requirement of hydrofluoric acid.

[0110] Alternatively, other acids include but are not limited to sulfuric acid, hydrochloric acid, and the like.

[0111] Optionally, the second solvent is water.

[0112] Optionally, the components of the acidic etchant and the content of each component can be specifically designed according to the requirements of the first etchant on the etching rate of the substrate original plate 1.

[0113] Optionally, the first etchant uses low-concentration hydrofluoric acid to control the etching rate of the first etchant on the substrate original plate 1 to 0.1 μm / min-1 μm / min, which is beneficial to control the porosity of the through hole 11A.

[0114] In these embodiments, step S032 causes little or no damage to the first wiring layer 3 .

[0115] In some embodiments, Fig.15 As shown, the substrate original plate 1 is first thinned using a second etchant until a second distance D2 is provided between the back surface 15 and each of the modified portions 11 .

[0116] The second distance D2 prevents the modified portion 11 and the first seed layer 31 from being etched by the second etchant.

[0117] Optionally, the second distance D2 is the distance between the degeneration section 11 closest to the back surface 15 and the back surface 15 .

[0118] For example, the second distance D2 may be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm. Of course, the second distance D2 may also be any combination range of the above values.

[0119] In some optional embodiments, the second spacing D2 is 10 μm. On the one hand, it can effectively avoid the substrate original plate 1 being thinned to the point where the denatured portion 11 is mistakenly etched due to the molding error of the denatured portion 11 after being etched by the second etchant, and on the other hand, it can ensure the etching time of the substrate original plate 1.

[0120] In some embodiments, the etching rate of the first etchant on the substrate original plate 1 is lower than the etching rate of the second etchant on the substrate original plate 1 so that the thinning rate of the first thinning is higher than the thinning rate of the second thinning. Since the etching rate of the first etchant on the substrate original plate 1 is lower than the etching rate of the second etchant on the substrate original plate 1, the second etchant has a stronger etching performance. The second etchant can etch the denatured portion 11 when it contacts the denatured portion 11, and the second etchant can also etch the first seed layer 31 when it contacts the first seed layer 31. Therefore, the second etchant only etches and thins the substrate original plate 1 until there is a second distance D2 between the back side 15 and each denatured portion 11. By making the substrate original plate 1 retain the thickness of the second distance D2, it is possible to prevent each denatured portion 11 and even the first seed layer 31 from being etched by the second etchant. At the same time, since the denatured portion 11 is easier to be etched relative to the substrate original plate 1, if the second etchant is directly used The etching agent is used to thin the substrate original plate 1 to the degeneration part 11, and the degeneration part 11 is removed to form the through hole 11A. Although the etching rate can be accelerated, the aperture of the formed through hole 11A is large and the uniformity of the through hole 11A is poor, and even the first seed layer 31 is etched, resulting in pores between the first wiring layer 33 and the substrate original plate 1, which leads to reliability risks; if the first etching agent is directly used to thin the substrate original plate 1 to the degeneration part 11, and the degeneration part 11 is removed to form the through hole 11A, although the first seed layer 31 is not etched, the aperture of the through hole 11A is large, and the uniformity of the through hole 11A is poor, the etching rate is too slow, resulting in low preparation efficiency. Therefore, the second etching agent and the first etching agent are used to etch and thin the substrate original plate 1 in steps, which not only has little damage to the first wiring layer 3, but also has high process reliability, and can reduce the difficulty of preparing the chip packaging substrate and improve the preparation rate.

[0121] In some embodiments, the ratio of the etching rate of the second etchant on the substrate original plate 1 to the etching rate of the first etchant on the substrate original plate 1 is 5 to 20. On the one hand, it is beneficial to control the second distance D2 after the second etchant etches the substrate original plate 1, and on the other hand, it can effectively reduce the etching time of the substrate original plate 1.

[0122] Exemplarily, the ratio of the etching rate of the second etchant on the substrate original plate 1 to the etching rate of the first etchant on the substrate original plate 1 can be 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 or 20. Of course, the ratio of the etching rate of the second etchant on the substrate original plate 1 to the etching rate of the first etchant on the substrate original plate 1 can also be any combination range of the above values.

[0123] In some embodiments, the etching rate of the second etchant on the substrate original plate 1 is 1 μm / min to 10 μm / min in terms of thinning thickness.

[0124] Exemplarily, the etching rate of the second etchant on the substrate original plate 1 can be 1 μm / min, 2 μm / min, 3 μm / min, 4 μm / min, 5 μm / min, 6 μm / min, 7 μm / min, 8 μm / min, 9 μm / min or 10 μm / min. Of course, the etching rate of the second etchant on the substrate original plate 1 can also be any combination range of the above values.

[0125] In some embodiments, the second etchant is an acidic etchant.

[0126] Alternatively, the components of the second etchant may be the same as those of the first etchant when the first etchant is an acidic etchant, but the concentration of HF in the first etchant is less than the concentration of HF in the second etchant.

[0127] Optionally, the components of the second etchant and the content of each component can be specifically designed according to the requirements of the second etchant on the etching rate of the substrate original plate 1.

[0128] In some embodiments, Fig.16 As shown, the substrate original plate 1 is thinned for the first time by a grinding process until each of the modified portions 11 is exposed. Since the hole structure and the conductive pillars filling the hole structure are not formed in the substrate original plate 1 before the substrate original plate 1 is thinned for the first time, the grinding and thinning of the substrate original plate 1 will not cause damage to the substrate original plate 1 due to different stresses. Moreover, the process of combining grinding and thinning with etching with the first etchant not only causes less damage to the first wiring layer 3 and has high process reliability, but also reduces the difficulty of preparing the chip packaging substrate and improves the preparation rate.

[0129] like Fig.13As shown, optionally, the first seed layer 31 includes a plurality of first seed portions 311 , and the degeneration portion 11 is covered by the first seed portions 311 ; the first routing layer 33 includes a plurality of first routings 331 , and each first routing 331 is disposed on each first seed portion 311 .

[0130] Optionally, among the multiple first seed sub-portions 311, each first seed sub-portion 311 covers at least one degeneration portion 11, that is, each first seed sub-portion 311 is used to cover the degeneration portion 11; or, among the multiple first seed sub-portions 311, some first seed sub-portions 311 are used to cover the degeneration portion 11, and each first seed sub-portion 311 among these first seed sub-portions 311 covers one or more degeneration portions 11, that is, other first seed sub-portions 311 among the multiple first seed sub-portions 311 may not cover the degeneration portion 11.

[0131] Exemplarily, among the plurality of first seed portions 311 , each first seed portion 311 covers at least one transformed portion 11 .

[0132] Optionally, the first seed portion 311 and the first routing line 331 constitute a first connecting line 3 a , and a plurality of first connecting lines 3 a are arranged at intervals.

[0133] Please continue reading Figure 6 , Figure 6 This is a flow chart of preparing the first wiring layer on the front side provided in the second aspect embodiment of the present application.

[0134] like Figure 6 As shown, in some embodiments, step S02 includes: Step S021: Fig. 9 As shown, a first seed material layer 30 is formed on the front side 13 and covers the front side 13 .

[0135] Optionally, in step S021 , the first seed material layer 30 is formed by a seed material through a deposition process.

[0136] Optionally, the deposition process is a sputtering process.

[0137] Optionally, the seed material may be a metallic material.

[0138] Optionally, the metal material may be one of Ti and Cu, wherein Ti is not acid-resistant but easily etched by an acidic etchant, and Cu is acid-resistant and alkali-resistant but not easily etched by an acidic etchant or an alkaline etchant.

[0139] Optionally, the seed material may also be a non-metallic material with conductivity.

[0140] Optionally, the non-metallic material may be TiN. TiN is acid- and alkali-resistant and is not easily etched by acidic and alkaline etchants.

[0141] Step S022: Fig.10 As shown, a patterned first pattern layer 4 is prepared on the first seed material layer 30 , and the first pattern layer 4 has a plurality of first openings 41 . The first openings 41 expose the first seed material layer 30 to form a first region 30A, and the modified portion 11 is covered by the first region 30A.

[0142] Optionally, the first pattern layer 4 can be formed by a process of coating glue on the first seed material layer 30 and exposing and developing it, wherein the glue in the area where the first opening 41 is located is removed by exposure and development to form the first opening 41; the first pattern layer 4 can also be formed by laminating a dry film on the first seed material layer 30 and performing a laser window opening process, wherein the dry film in the area where the first opening 41 is located is removed by laser window opening to form the first opening 41.

[0143] Optionally, among the multiple first zones 30A, each first zone 30A covers at least one degeneration section 11, that is, each first zone 30A is used to cover the degeneration section 11; or, among the multiple first zones 30A, some first zones 30A are used to cover the degeneration section 11, and each first zone 30A among these first zones 30A covers one or more degeneration sections 11, that is, other first zones 30A among the multiple first zones 30A may not cover the degeneration section 11.

[0144] Exemplarily, among the plurality of first regions 30A, each first region 30A covers at least one denaturation portion 11 .

[0145] Step S023: Fig.11 As shown, a first wiring layer 33 is formed on each first region 30A. Due to the spacing effect of the first pattern layer 4, the first wiring layer 33 includes a plurality of first wirings 331 arranged at intervals, and each first wiring 331 is formed on each first region 30A.

[0146] Optionally, the first wiring layer 33 is a metal layer formed by an electroplating process.

[0147] Step S024: Fig.12 As shown, the first pattern layer 4 is removed to expose the first seed material layer 30 to form a plurality of first removal portions 30B.

[0148] Optionally, the process of removing the first pattern layer 4 is the same as the process of forming the first opening 41. For example, the first pattern layer 4 can be removed by an exposure and development process or a laser irradiation process.

[0149] Step S025: Fig.13As shown, the first removal portion 30B is removed to form the first seed layer 31. That is, in the first seed material layer 30, only the first region 30A is retained to form the first seed layer 31. Since the first opening 41 exposes the first seed material layer 30 to form the first region 30A, and the degeneration portion 11 is covered by the first region 30A, the formed first seed layer 31 covers each degeneration portion 11; and since the first removal portion 30B of the first seed material layer 30 is removed, the formed first seed layer 31 includes a plurality of first seed portions 311 arranged at intervals, that is, the first seed portion 311 is formed by retaining the first region 30A, and the degeneration portion 11 is covered by the first seed portion 311.

[0150] In some embodiments, the first seed layer 31 is easily etched by the second etchant when in contact with the second etchant, thereby causing a cavity to appear between the first wiring layer 33 and the substrate original plate 1 .

[0151] In some embodiments, the orthographic projection of the first trace 331 on the substrate original plate 1 is located within the orthographic projection range of the first seed portion 311 on the substrate original plate 1 .

[0152] In these embodiments, the orthographic projection of the first wiring 331 on the substrate original plate 1 is within the orthographic projection range of the first seed portion 311 on the substrate original plate 1 , which can avoid the occurrence of a void between the first wiring 331 and the substrate original plate 1 .

[0153] Optionally, the orthographic projection of the first trace 331 on the substrate original plate 1 coincides with the orthographic projection of the first seed portion 311 on the substrate original plate 1 .

[0154] In some embodiments, Fig.23 As shown, the conductive column 5 includes an inner wall seed layer 51 arranged in the through hole 11A and connected to the first seed layer 31, and a conductive core 53 arranged on the inner wall seed layer 51; the second wiring layer 6 includes a second seed layer 61 arranged on the back side 15 and connected to the inner wall seed layer 51, and a second routing layer 63 arranged on the second seed layer 61 and connected to the conductive core 53.

[0155] Optionally, the second seed layer 61 includes a plurality of second seed portions 611 , each second seed portion 611 is connected to at least one inner wall seed layer 51 ; the second routing layer 63 includes a plurality of second routings 631 , each second routing 631 is disposed on each second seed portion 611 .

[0156] Optionally, the inner wall seed layer 51 and the second seed portion 611 are an integrated structure, and the conductive core 53 and the second wiring 631 are an integrated structure.

[0157] In these embodiments, the inner wall seed layer 51 and the second seed portion 611 are an integrated structure, which means that the whole formed by the inner wall seed layer 51 and the second seed portion 611 has good structural integrity, and there is no splicing transition area between the inner wall seed layer 51 and the second seed portion 611. Therefore, the inner wall seed layer 51 and the second seed portion 611 can be molded at one time through a molding process, thereby reducing the preparation steps; the conductive core 53 and the second routing 631 are an integrated structure, which means that the whole formed by the conductive core 53 and the second routing 631 has good structural integrity, and there is no splicing transition area between the conductive core 53 and the second routing 631. Therefore, the conductive core 53 and the second routing 631 can be molded at one time through a molding process, thereby reducing the preparation steps; and when the conductive core 53 and the second routing 631 are molded at one time through a molding process, the inner wall seed layer 51 and the second seed portion 611 are an integrated structure, which can also improve the good structural integrity of the whole formed by the conductive core 53 and the second routing 631.

[0158] Optionally, the second seed portion 611 and the second trace 631 constitute a second connection line 6 a , the second connection line 6 a is electrically connected to the first connection line 3 a via at least one conductive column 5 , and a plurality of second connection lines 6 a are arranged at intervals.

[0159] In some embodiments, the thickness of the second wiring 631 is 0-5 μm. The thickness of the second wiring 631 is the thickness of the second wiring 631 from the front surface 13 to the back surface 15 .

[0160] For example, the thickness of the second wiring 631 may be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm. Of course, the thickness of the second wiring 631 may also be any combination range of the above values.

[0161] Optionally, the material of the conductive core 53 and the material of the second wiring 631 are both metal copper. Metal copper has good conductivity, and the process of preparing the conductive core 53 and the second wiring 631 on the back side 15 of the substrate 1A having a plurality of through holes 11A is relatively mature, and the preparation difficulty is relatively low. Moreover, when the surface copper is formed, the thickness of the surface copper can be controlled within the range of 0 to 5 μm, so that the formed surface copper can be directly used as the second wiring 631, thereby avoiding grinding of the surface copper.

[0162] Please continue reading Figure 7 , Figure 7 It is a flow chart of preparing multiple conductive pillars and a second wiring layer from the back side provided by an embodiment of the first aspect of the present application.

[0163] like Figure 7 As shown, in some embodiments, step S04 includes: Step S041: Fig.19As shown, the inner wall seed layer 51 provided in the through hole 11A and the second seed material layer 60 covering the back surface 15 are formed from the back surface 15 .

[0164] Optionally, in step S041 , the inner wall seed layer 51 and the second seed material layer 60 are formed by a seed material through a deposition process.

[0165] Optionally, the deposition process is a sputtering process.

[0166] Optionally, the seed material may be a metallic material.

[0167] Optionally, the metal material may be one of Ti or Cu.

[0168] Optionally, the seed material may also be a non-metallic material with conductivity.

[0169] Optionally, the non-metallic material may be TiN. TiN is acid- and alkali-resistant and is not easily etched by acidic and alkaline etchants.

[0170] In these embodiments, the inner wall seed layer 51 and the second seed material layer 60 are formed at one time through a deposition process, which can reduce the number of preparation steps.

[0171] Step S042: Fig.19 and Fig. 20 As shown, a patterned second pattern layer 7 is prepared on the second seed material layer 60 . The second pattern layer 7 has a plurality of second openings 71 . Each second opening 71 exposes the second seed material layer 60 to form a second region 60A. The through hole 11A is exposed through the second opening 71 .

[0172] Optionally, the second pattern layer 7 can be formed by applying glue on the second seed material layer 60 and exposing and developing it, wherein the glue in the area where the second opening 71 is located is removed by exposure and development to form the second opening 71; the second pattern layer 7 can also be formed by laminating a dry film on the second seed material layer 60 and performing a laser window opening process, wherein the dry film in the area where the second opening 71 is located is removed by laser window opening to form the second opening 71.

[0173] Optionally, among the multiple second openings 71, each second opening 71 exposes the second seed material layer 60 to form the second zone 60A and also exposes the through-hole 11A, that is, each second opening 71 is used to expose the through-hole 11A and to expose the second seed material layer 60 to form the second zone 60A; or, among the multiple second openings 71, each second opening 71 exposes the second seed material layer 60 to form the second zone 60A, and some second openings 71 are also used to expose the through-hole 11A, and each second opening 71 among these second openings 71 exposes one or more through-holes 11A, that is, some second openings 71 among the multiple second openings 71 expose the second seed material layer 60 to form the second zone 60A and also expose the through-hole 11A, while other second openings 71 are only used to expose the second seed material layer 60 to form the second zone 60A. In other words, among the multiple second seed sub-portions 611 formed subsequently, each second seed sub-portion 611 is connected to the inner wall seed layer 51 , or only each second seed sub-portion 611 among some of the second seed sub-portions 611 is connected to the inner wall seed layer 51 .

[0174] Illustratively, among the plurality of second openings 71 , each second opening 71 exposes the second seed material layer 60 to form the second region 60A and also exposes the through hole 11A.

[0175] Optionally, each second region 60A is disposed around each through hole 11A.

[0176] Step S043: Fig. 20 and Fig.21 As shown, a conductive core 53 is formed on the inner wall seed layer 51 and a second wiring layer 63 is formed on each second area 60A. Due to the spacing effect of the second pattern layer 7, the second wiring layer 63 includes a plurality of second wirings 631 spaced apart, and each second wiring 631 is formed on each second area 60A.

[0177] Optionally, the second wiring layer 63 is a metal layer formed by an electroplating process.

[0178] Optionally, the material of the conductive core 53 and the material of the second wiring 631 are both metal copper. In the electroplating process, the thickness of the formed surface copper can be controlled within the range of 0-5 μm, so the formed surface copper can be directly used as the second wiring 631, thereby avoiding grinding of the surface copper.

[0179] In these embodiments, the conductive core 53 and the second wiring 631 are formed at one time through a molding process, that is, the conductive core 53 and the second wiring 631 are an integrated structure, thereby reducing the number of preparation steps.

[0180] Step S044: Fig.21 and Fig. 22As shown, the second pattern layer 7 is removed to expose the second seed material layer 60 to form a plurality of second removed portions 60B.

[0181] Step S045: Fig. 22 and Fig.23 As shown, the second removal portion 60B is removed to form a second seed layer 61. That is, in the second seed material layer 60, only the second region 60A thereof is retained to form the second seed layer 61. Since the second removal portion 60B of the second seed material layer 60 is removed, the formed second seed layer 61 includes a plurality of second seed sub-portions 611 arranged at intervals, that is, the second seed sub-portion 611 is formed by retaining the second region 60A.

[0182] In some embodiments, the orthographic projection of the second wiring 631 on the substrate 1A is located within the orthographic projection range of the integrated structure formed by the inner wall seed layer 51 and the second seed portion 611 on the substrate 1A.

[0183] In these embodiments, the orthographic projection of the second routing line 631 on the substrate 1A is within the orthographic projection range of the integrated structure formed by the inner wall seed layer 51 and the second seed portion 611 on the substrate 1A, which can avoid the appearance of voids between the second routing line 631 and the substrate 1A, thereby affecting the reliability of the chip packaging substrate.

[0184] Optionally, the orthographic projection of the second wiring 631 on the substrate 1A coincides with the orthographic projection of the integrated structure formed by the inner wall seed layer 51 and the second seed portion 611 on the substrate 1A.

[0185] In some optional embodiments, the orthographic projection of the first routing line 331 on the substrate original plate 1 coincides with the orthographic projection of the first seed portion 311 on the substrate original plate 1, and the orthographic projection of the second routing line 631 on the substrate 1A coincides with the orthographic projection of the integrated structure formed by the inner wall seed layer 51 and the second seed portion 611 on the substrate 1A. On the one hand, it is beneficial to increase the wiring density of the first wiring layer 3 and the second wiring layer 6, that is, to increase the density of the first connecting wire 3a and the second connecting wire 6a, thereby facilitating increasing the chip density of the package; on the other hand, it is beneficial to increase the electrical isolation distance between two adjacent wirings in the same wiring layer, that is, to increase the electrical isolation distance between two adjacent first connecting wires 3a and between two adjacent second connecting wires 6a, thereby improving product reliability or / and reducing the risk of breakdown between two adjacent wirings.

[0186] like Figures 14 to 23 As shown, in some embodiments, before step S03 or / and step S04 , the preparation method further includes: bonding the protection member to the front surface 13 to cover the first wiring layer 3 .

[0187] Optionally, in step S03 , when etching thinning is adopted, the protective member is a protective film 8 or a carrier plate 9 .

[0188] Optionally, in step S04 , the protective member is a carrier plate 9 .

[0189] In some optional embodiments, the carrier plate 9 may also provide support for the thinned substrate original plate 1 to improve the strength of the substrate original plate 1 .

[0190] In some optional embodiments, the front surface 13 and the protective member are temporarily bonded via the removable adhesive 10 .

[0191] like Fig.14 As shown, optionally, after step S02 and before step S03 , the preparation method includes: bonding the protection film 8 to the front surface 13 to cover the first wiring layer 3 .

[0192] like Fig.18 As shown, in some embodiments, after step S03 and before step S04 , the preparation method further includes: removing the protective film 8 , and bonding the carrier 9 to the front side 13 to cover the first wiring layer 3 .

[0193] Optionally, after step S04, the preparation method further comprises: removing the protective component to obtain the chip packaging substrate.

[0194] like Figure 8 As shown, in some embodiments, in step S01, the ratio of the thickness of the substrate original plate 1 to the depth of any modified portion 11 is 2.0-3.0. The first distance D1 is the difference between the thickness of the substrate original plate 1 and the depth of the modified portion 11.

[0195] For example, in step S01, the ratio of the thickness of the substrate original plate 1 to the depth of each modified portion 11 can be 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9 or 3.0. Of course, the ratio of the thickness of the substrate original plate 1 to the depth of each modified portion 11 can also be any combination range of the above values.

[0196] Optionally, in step S01, the thickness of the substrate original plate 1 is not less than 250 μm. The substrate original plate 1 with a thickness of not less than 250 μm can provide sufficient mechanical strength, thereby facilitating the improvement of the yield and reliability of the prepared chip packaging substrate.

[0197] For example, in step S01, the thickness of the substrate original plate 1 may be 250 μm, 270 μm, 290 μm, 310 μm, 330 μm, 350 μm, 370 μm, 390 μm, 410 μm, 430 μm, 450 μm, 470 μm, 490 μm or 500 μm, etc. Of course, the thickness of the substrate original plate 1 may also be any combination range of the above values.

[0198] Optionally, the depth of the modified portion 11 is designed according to the thickness of the substrate 1A in the molded chip packaging substrate.

[0199] In these embodiments, the depth of the transformed portion 11 is greater than the thickness of the substrate 1A in the chip packaging substrate.

[0200] by Figure 4 The flowchart shown in Figure 8 is taken as an example, and refer to Figure 8 to Fig.23 A method for preparing a chip packaging substrate provided in an embodiment of the present application is illustrated by way of example. Figures 8 to 23 is a schematic structural diagram of an intermediate product in the preparation process of the chip packaging substrate preparation method provided in the second aspect of the present application, Fig.24 It is a structural schematic diagram of a chip packaging substrate prepared by the method for preparing a chip packaging substrate provided in an embodiment of the second aspect of the present application.

[0201] Step 1: If Figure 8 As shown, a plurality of degeneration parts 11 are formed in the substrate original plate 1. The substrate original plate 1 has a front side 13 and a back side 15 opposite to each other. Each degeneration part 11 extends from the front side 13 to the back side 15. There is a first distance D1 between the back side 15 and the degeneration part 11.

[0202] Step 2: If Fig. 9 As shown, a first seed material layer 30 is formed on the front side 13 and covers the front side 13 .

[0203] Step 3: If Fig.10 As shown, a patterned first pattern layer 4 is prepared on the first seed material layer 30 , and the first pattern layer 4 has a plurality of first openings 41 . The first openings 41 expose the first seed material layer 30 to form a first region 30A, and the modified portion 11 is covered by the first region 30A.

[0204] Step 4: forming a first wiring layer 33 on each first region 30A.

[0205] Step 5: If Fig.12 As shown, the first pattern layer 4 is removed to expose the first seed material layer 30 to form a plurality of first removal portions 30B.

[0206] Step 6: If Fig.13 As shown, the first removed portion 30B is removed to form the first seed layer 31 .

[0207] Step 7: If Fig.14 As shown, the protective film 8 is bonded to the front surface 13 to cover the first wiring layer 3 .

[0208] Step 8: If Fig.15 As shown, the substrate original plate 1 is thinned for the first time using a second etchant until a second distance D2 is provided between the back surface 15 and each of the modified portions 11 .

[0209] Step 9: If Fig.16 As shown, the substrate original plate 1 is thinned for the second time to the transformed portion 11 using a first etchant, and the transformed portion 11 is removed to form a through hole 11A.

[0210] Step 10: Fig.17 and Fig.18 As shown, the protective film 8 is removed, and the carrier 9 is bonded to the front side 13 to cover the first wiring layer 3 .

[0211] Step 11: Fig.19 As shown, the inner wall seed layer 51 provided in the through hole 11A and the second seed material layer 60 covering the back surface 15 are formed from the back surface 15 .

[0212] Step 12: Fig.19 and Fig. 20 As shown, a patterned second pattern layer 7 is prepared on the second seed material layer 60 . The second pattern layer 7 has a plurality of second openings 71 . Each second opening 71 exposes the second seed material layer 60 to form a second region 60A. The through hole 11A is exposed through the second opening 71 .

[0213] Step 13: Fig. 20 and Fig.21 As shown, a conductive core 53 is formed on the inner wall seed layer 51 and a second wiring layer 63 is formed on each second region 60A.

[0214] Step 14: Fig.21 and Fig. 22 As shown, the second pattern layer 7 is removed to expose the second seed material layer 60 to form a plurality of second removed portions 60B.

[0215] Step 15: Fig. 22 and Fig.23 As shown, the second removed portion 60B is removed to form a second seed layer 61 .

[0216] Step 16: Fig.23 and Fig.24 As shown, the chip packaging substrate can be obtained by removing the protective component.

[0217] The third embodiment of the present application further provides a chip assembly, which includes the chip packaging substrate of any of the first embodiments, or a chip packaging substrate prepared by the preparation method of the chip packaging substrate of any of the second embodiments.

[0218] The application can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in the specific embodiment can be modified, and the system architecture does not depart from the basic spirit of the application. Therefore, the current embodiment is regarded as exemplary and non-restrictive in all aspects, and the scope of the application is defined by the attached claims rather than the above description, and all changes falling within the meaning of the claims and the scope of equivalents are thereby included in the scope of the application.

Claims

1. A chip packaging substrate, characterized in that: include: A substrate having a front surface and a back surface opposite to each other and a through hole extending from the front surface to the back surface; A first wiring layer, comprising a first conductive portion, wherein the first conductive portion comprises a first seed layer and a first routing layer, wherein the first seed layer is disposed on the front surface and covers each of the through holes, and the first routing layer is stacked on the first seed layer; a plurality of conductive pillars, each conductive pillar comprising an inner wall seed layer disposed in the through hole and connected to the first seed layer, and a conductive core stacked on the inner wall seed layer; The second wiring layer includes a second conductive part, wherein the second conductive part includes a second seed layer disposed on the back surface and connected to the inner wall seed layer and a second routing layer stacked on the second seed layer and connected to the conductive core.

2. The chip packaging substrate according to claim 1, characterized in that: The aperture of the through hole decreases along the direction from the back side to the front side; or / and the thickness of the first seed layer and the thickness of the inner wall seed layer are both smaller than the thickness of the seed material on the axis of the through hole.

3. The chip packaging substrate according to claim 1, characterized in that: The first seed layer includes a plurality of first seed portions, and the through hole is covered by the first seed portions; the first routing layer includes a plurality of first routings, and each of the first routing layers is stacked on each of the first seed portions.

4. The chip packaging substrate according to claim 1, characterized in that: The second seed layer includes a plurality of second seed portions, and the inner wall seed layer is connected to the second seed portions; the second routing layer includes a plurality of second routings, and each of the second routing layers is stacked on each of the second seed portions.

5. The chip packaging substrate according to claim 4, characterized in that: The inner wall seed layer and the second seed portion are an integral structure; or / and, the conductive core and the second wiring are an integral structure.

6. A method for preparing a chip packaging substrate, characterized in that: The following steps are involved: A plurality of degeneration parts are formed in a substrate original plate, wherein the substrate original plate has a front side and a back side opposite to each other, each of the degeneration parts extends from the front side to the back side, and a first distance is formed between the back side and the degeneration part; Prepare a first wiring layer on the front surface, wherein the first wiring layer includes a first conductive portion, and the first conductive portion covers each of the denatured portions; Thinning the substrate original plate from the back side to the modified portion, and removing the modified portion to form a through hole; A plurality of conductive pillars and a second wiring layer are prepared from the back side, each of the conductive pillars fills each of the through holes, the second wiring layer is formed on the back side, the second wiring layer includes a second conductive portion, and the second conductive portion is electrically connected to the first conductive portion via the plurality of conductive pillars.

7. The method for preparing a chip packaging substrate according to claim 6, characterized in that: The substrate original plate is made of glass.

8. The method for preparing a chip packaging substrate according to claim 6, characterized in that: The steps of thinning the substrate original plate from the back side to the modified portion and removing the modified portion to form a through hole include: Performing a first thinning on the substrate original plate from the back side; The substrate original plate is thinned a second time from the back side to the modified portion using a first etchant, and the modified portion is removed to form the through hole.

9. The method for preparing a chip packaging substrate according to claim 8, characterized in that: The first conductive portion includes a first seed layer and a first routing layer which are stacked, the first seed layer covers each of the modified portions, and in the substrate original plate and the first seed layer, the first etchant selectively etches the substrate original plate.

10. The method for preparing a chip packaging substrate according to claim 8, characterized in that: The thinning rate of the first thinning is greater than the thinning rate of the second thinning.

11. The method for preparing a chip packaging substrate according to claim 10, characterized in that: The first etchant is an alkaline etchant or an acidic etchant.

12. The method for preparing a chip packaging substrate according to any one of claims 8 to 11, characterized in that: The substrate original plate is thinned for the first time using a second etchant until a second distance exists between the back surface and each of the modified parts.

13. The method for preparing a chip packaging substrate according to claim 12, characterized in that: The ratio of the etching rate of the second etchant on the substrate original plate to the etching rate of the first etchant on the substrate original plate is 5-20.

14. The method for preparing a chip packaging substrate according to claim 12, characterized in that: The second etchant is an acidic etchant.

15. The method for preparing a chip packaging substrate according to any one of claims 8 to 11, characterized in that: The substrate original plate is thinned for the first time using a grinding process until each of the modified portions is exposed.

16. The method for preparing a chip packaging substrate according to claim 6, characterized in that: The step of preparing a first wiring layer on the front side comprises: forming a first seed material layer covering the front surface on the front surface; Preparing a patterned first pattern layer on the first seed material layer, wherein the first pattern layer has a plurality of first openings, wherein the first openings expose the first seed material layer to form a first region, and the denatured portion is covered by the first region; forming a first wiring layer on each of the first regions; removing the first pattern layer to expose the first seed material layer to form a plurality of first removal portions; The first removed portion is removed to form a first seed layer.

17. The method for preparing a chip packaging substrate according to claim 16, characterized in that: The first seed material layer is formed by a deposition process; or / and the first wiring layer is formed by an electroplating process.

18. The method for preparing a chip packaging substrate according to claim 6, characterized in that: The step of preparing a plurality of conductive pillars and a second wiring layer from the back side includes: forming an inner wall seed layer disposed in the through hole and a second seed material layer covering the back side from the back side; Preparing a patterned second pattern layer on the second seed material layer, wherein the second pattern layer has a plurality of second openings, each of the second openings exposes the second seed material layer to form a second region, and the through hole is exposed through the second opening; forming a conductive core on the inner wall seed layer and forming a second wiring layer on each of the second regions; removing the second pattern layer to expose the second seed material layer to form a plurality of second removed portions; The second removed portion is removed to form a second seed layer.

19. The method for preparing a chip packaging substrate according to claim 18, characterized in that: The second seed material layer is formed by a deposition process; or / and, the second wiring layer is formed by an electroplating process.

20. The method for preparing a chip packaging substrate according to claim 6, characterized in that: Before the step of thinning the substrate original plate from the back side to the modified portion and removing the modified portion to form a through hole or / and the step of preparing a plurality of conductive pillars and a second wiring layer from the back side, the preparation method further comprises: bonding a protective member to the front side to cover the first wiring layer; After the step of preparing a plurality of conductive pillars and a second wiring layer from the back side, the preparation method further comprises: The protective member is removed.

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