Rail-to-rail amplifier and chip

Abstract

The embodiment of the invention provides a rail-to-rail amplifier and a chip, and relates to the technical field of amplifiers. The rail-to-rail amplifier comprises a first current mirror, a common mode point judgment module and a calibration module. The common mode point judgment module judges whether the input is at a high input common mode point, an intermediate input common mode point or a low input common mode point according to the current provided by the first current mirror. The calibration module provides different calibration currents at different common mode points, so that the offset voltage can be properly adjusted at each common mode point, and more accurate output is obtained.

Description

Technical Field

[0001] The present application relates to the technical field of amplifiers, and in particular to a rail-to-rail amplifier and a chip. Background Art

[0002] Rail-to-rail operational amplifier Figure 1 , a complementary differential pair 101 is usually used to form an input stage, so that the input stage can achieve a higher gain within the full common mode range (the full common mode range means that the common mode input voltage is within the range of 0V to the power supply voltage VDD).

[0003] However, the total offset voltage of a rail-to-rail op amp changes with changes in the common mode input voltage over the full common mode input range. For example, at high input common mode points, the NMOS differential pair ( Figure 1 The offset voltage of NM1 and NM2 in the rail-to-rail op amp affects the output of the rail-to-rail op amp, while the PMOS differential pair ( Figure 1 The offset voltage of PM1 and PM2 in the input common mode has no effect on the output of the rail-to-rail operational amplifier; the influencing factors at low input common mode points are opposite; at the intermediate input common mode point, the offset voltages of the PMOS differential pair and the NMOS differential pair jointly affect the output of the rail-to-rail operational amplifier.

[0004] How to achieve calibration (trim) at different common mode points and stabilize the offset voltage within a certain range within the full common mode range (the full common mode range includes the above-mentioned high input common mode point, middle input common mode point and low input common mode point) is the technical problem to be solved by this application. Summary of the invention

[0005] The purpose of the present application is to provide a rail-to-rail amplifier and chip to achieve calibration at different common mode points and stabilize the offset voltage within a certain range within the full common mode range.

[0006] In a first aspect, an embodiment of the present application provides a rail-to-rail amplifier, comprising an input stage, a load stage, and an output stage; the input stage comprises a first input stage and a second input stage, the first input stage and the second input stage are respectively connected to the load stage; the load stage is connected to the output stage;

[0007] The first input stage is an NMOS transistor pair, and the second input stage is a PMOS transistor pair, or the first input stage is a PMOS transistor pair, and the second input stage is an NMOS transistor pair;

[0008] The first input stage and the second input stage are used to receive a positive input voltage and a negative input voltage, and obtain an output current according to the positive input voltage and the negative input voltage;

[0009] The load stage is used to obtain a voltage signal according to the output current;

[0010] The output stage is used to obtain an output voltage according to the voltage signal;

[0011] The rail-to-rail amplifier also includes a first current mirror, a common mode point judgment module and a calibration module;

[0012] The first current mirror comprises a first transistor and a second transistor, wherein the second transistor is used to replicate the current of the first transistor; the first transistor is connected in series with the first input stage;

[0013] The common mode point judgment module is connected to the second transistor; the common mode point judgment module is used to output at least two first control signals to the calibration module according to the current of the second transistor; the at least two first control signals represent the input state of the rail-to-rail amplifier, and the input state includes a high input common mode point, a middle input common mode point and a low input common mode point;

[0014] The input end of the calibration module is connected to the common mode point judgment module, and the output end of the calibration module is connected to the transistor in the load stage; the calibration module pre-stores the current output values ​​corresponding to different first control signals; the calibration module is used to provide current to the transistor in the load stage according to the at least two first control signals.

[0015] In a second aspect, an embodiment of the present application provides a chip, in which the rail-to-rail amplifier of the first aspect is packaged.

[0016] Compared with the prior art, this application has the following beneficial effects:

[0017] In the rail-to-rail amplifier provided in the embodiment of the present application, the common-mode point judgment module judges whether the input is at a high input common-mode point, a middle input common-mode point or a low input common-mode point, and the calibration module provides different calibration currents at different common-mode points, so that the offset voltage can be properly adjusted at each common-mode point to obtain a more accurate output. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a schematic diagram of a rail-to-rail amplifier in the prior art;

[0020] Figure 2 A schematic diagram of a rail-to-rail amplifier provided in an embodiment of the present application;

[0021] Figure 3 A calibration module provided in an embodiment of the present application includes a schematic diagram of a logic circuit unit and a plurality of current source branches;

[0022] Figure 4 A schematic diagram of a control terminal of a control switch unit provided in an embodiment of the present application being directly connected to a common mode point determination module;

[0023] Figure 5 A schematic diagram of an embodiment of the present application in which each current source branch includes a positive calibration unit and a negative calibration unit;

[0024] Figure 6 A schematic diagram of using a comparator to generate a Vctrl_n signal provided in an embodiment of the present application;

[0025] Figure 7 and Figure 8 A schematic diagram showing the current sources of the four current source branches are 125nA, 250nA, 500nA, and 1000nA;

[0026] Fig. 9 A schematic diagram of generating a Vctrl_n signal without using a comparator is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. The described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described in the drawings here can be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0029] In the description of this application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. "Connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0030] See also Figure 2 The embodiment of the present application provides a rail-to-rail amplifier, including an input stage, a load stage and an output stage; the input stage includes a first input stage and a second input stage. The first input stage and the second input stage are respectively an NMOS tube pair and a PMOS tube pair. Specifically, when the first input stage is an NMOS tube pair, the second input stage is a PMOS tube pair, or when the first input stage is a PMOS tube pair, the second input stage is an NMOS tube pair.

[0031] like Figure 2 , with the following connection relationship: the first input stage and the second input stage are connected to the load stage respectively; the load stage is connected to the output stage. Their functions are as follows: the first input stage and the second input stage are used to receive the positive input voltage INP and the negative input voltage INM (the first input stage can receive the negative input voltage INM, and the second input stage can receive the positive input voltage INP, Figure 2 In the example, the first input stage receives a positive input voltage INP, the second input stage receives a negative input voltage INM), and obtains an output current based on the positive input voltage INP and the negative input voltage INM; the load stage is used to obtain a voltage signal based on the output current; and the output stage is used to obtain an output voltage based on the voltage signal of the load stage.

[0032] like Figure 2 The rail-to-rail amplifier further includes a first current mirror, a common mode point determination module and a calibration module. The first current mirror includes a first transistor and a second transistor. The second transistor is used to replicate the current of the first transistor; the first transistor is connected in series with the first input stage, so the current of the first transistor is the current of the first input stage, and the current of the second transistor is the current of the first input stage.

[0033] The common mode point judgment module is connected to the second transistor, so the common mode point judgment module can obtain the current of the second transistor. The common mode point judgment module is used to output at least two first control signals to the calibration module according to the current of the second transistor. The first control signal can be a digital signal that controls the cutoff and conduction of the MOS tube device. The working principle of the common mode point judgment module can be a principle of an analog-to-digital converter that converts an analog signal into a digital signal. An implementation method will be described below.

[0034] At least two first control signals represent the input state of the rail-to-rail amplifier, and the input state can be divided into multiple high and low states, for example, there are at least three input states, including a high input common mode point, an intermediate input common mode point, and a low input common mode point. Therefore, the first control signal output by the common mode point judgment module can be used to judge which input common mode point the current input is at.

[0035] For example, there are three input states, namely, a high input common mode point, an intermediate input common mode point, and a low input common mode point. The high input common mode point may refer to a voltage above 0.9 times the power supply voltage (e.g., 0.9 times the power supply voltage to 1 times the power supply voltage), the power supply voltage refers to the voltage of the power supply of the rail-to-rail amplifier, the intermediate input common mode refers to an interval of about 0.5 times the power supply voltage (e.g., 0.1 times the power supply voltage to 0.9 times the power supply voltage), and the low input common mode point may refer to a voltage below 0.1 times the power supply voltage (e.g., 0 to 0.1 times the power supply voltage). When the first control signal is a digital signal, there are four combinations of 2-bit digital signals (00, 01, 10, 11), so only 2-bit digital signals are sufficient to represent the three input states.

[0036] The input end of the calibration module is connected to the common mode point judgment module, and the output end of the calibration module is connected to the transistor in the load stage. The calibration module pre-stores the current output values ​​corresponding to different digital signals, and the corresponding relationship information can be set during the test calibration before leaving the factory. The calibration module is used to provide current to the transistor in the load stage according to the two-bit first control signal of the common mode point judgment module. Therefore, the calibration module provides different calibration currents at different common mode points, so that the offset voltage can be properly adjusted at each common mode point to obtain a more accurate output.

[0037] like Figure 3 The calibration module may include a logic circuit unit and a plurality of current source branches, each current source branch includes a current source and a switch unit connected in series, and a control end of the switch unit is connected to an output end of the logic circuit unit. A first end of the switch unit is connected to the current source, a second end of the switch unit is connected to a transistor in a load stage, and the switch unit provides a current of the current source to the transistor in the load stage in a conducting state.

[0038] The input end of the logic circuit unit is connected to the common mode point judgment module. The functions of the logic circuit unit include: according to the first control signal of the common mode point judgment module, obtaining the second control signal of each switch unit through logical operation, providing the second control signal to each switch unit to control each switch unit to be cut off or turned on, thereby realizing different current sources connected to the load-level transistor, that is, providing different currents for calibration.

[0039] The current sources of each current source branch may be the same, so different currents can be provided by selecting different numbers of current sources to be connected to the load stage.

[0040] The current sources of each current source branch may also be different, so different currents can be provided by selecting different current source combinations to connect to the load stage.

[0041] The current sources of each current source branch can be arranged in a regular pattern. For example, there are n current source branches, and the currents of the current sources of the n current source branches are arranged in a pattern of 2^n times the basic current, where n is a natural number. This arrangement can obtain a larger current range and better current accuracy. If the basic current is 125nA, then the four current sources can be 125nA, 250nA, 500nA, and 1000nA, respectively.

[0042] Figure 3 The principle of the embodiment shown is that the first control signal of the common mode point judgment module is converted by the logic circuit unit in the calibration module to obtain the second control signal of the switch unit. The second embodiment is that the first control signal of the common mode point judgment module is not converted by the logic circuit unit, but is directly provided to the switch unit, and the first control signal of the common mode point judgment module can be used as the second control signal of the switch unit.

[0043] Figure 4 An implementation method is shown in which the control end of the control switch unit is directly connected to the common mode point judgment module, and each current source branch includes a current source and a control switch unit connected in series. The control switch unit can be composed of multiple switch devices connected to each other.

[0044] Figure 5 An implementation of a control switch unit is shown, wherein the control switch unit of each current source branch includes a positive calibration unit and a negative calibration unit.

[0045] In each current source branch, the first end of the positive calibration unit is connected to the positive calibration point of the load stage, the positive calibration point is connected to the transistor in the input stage that receives the negative input voltage INM (the voltage at the inverting input terminal of the operational amplifier), the first end of the negative calibration unit is connected to the negative calibration point of the load stage, the negative calibration point is connected to the transistor in the input stage that receives the positive input voltage INP (the voltage at the non-inverting input terminal of the operational amplifier), the second end of the positive calibration unit is connected to the current source, and the control end of the positive calibration unit and the control end of the negative calibration unit are used to receive the first control signal of the common mode point judgment module. Therefore, the current source of each current source branch can provide positive calibration and reverse calibration for the load stage.

[0046] In the case where the first control signal is two bits, the two first control signals can respectively represent the working states of the NMOS transistor pair and the PMOS transistor pair, and the two first control signals are Vctrl_n and Vctrl respectively.

[0047] The level of Vctrl_n represents the working state of the PMOS tube pair, for example, a high level represents working, and a low level represents non-working (or a low level represents working, and a high level represents non-working).

[0048] The level of Vctrl represents the working state of the NMOS tube pair, for example, a high level represents working, and a low level represents not working.

[0049] Reference below Figure 6 Explain the specific principle.

[0050] like Figure 6 , the NMOS tube pair is MOS tube NM1 and MOS tube NM2, and the PMOS tube pair is MOS tube PM1 and MOS tube PM2.

[0051] When the input common mode point is low, all the current on the MOS tube PMS flows through the PMOS tube pair, and there is no current on the MOS tube NMS, that is, only the PMOS tube pair works and the NMOS tube pair does not work. Then the influencing factor of the offset voltage is mainly the PMOS tube pair, and the first control signal level of this state is set to Vctrl_n high level and Vctrl low level.

[0052] When at the middle input common mode point, both the PMOS tube pair and the NMOS tube pair are working, so the factors affecting the offset voltage are mainly the PMOS tube pair and the NMOS tube pair, and the first control signal level of this state is set to Vctrl_n high level and Vctrl high level.

[0053] When at a high input common mode point, the PMOS tube pair is cut off and current flows through the MOS tube NMS, that is, only the NMOS tube pair works and the PMOS tube pair does not work. Then the influencing factor of the offset voltage is mainly the NMOS tube pair. The first control signal level of this state is set to Vctrl_n low level and Vctrl high level.

[0054] When the first control signal is two bits, it can be further set as follows:

[0055] The forward calibration unit includes two branches, namely a first switch branch and a second switch branch, each branch includes two parts, namely a first part and a second part; the first part of the first switch branch can be used to receive Vctrl, the first part of the second switch branch can be used to receive Vctrl_n, the states of the first part and the second part can be one of an on state and an off state, the state of the first part can follow the level change of Vctrl and Vctrl_n, and the state of the second part can be set before leaving the factory;

[0056] The negative calibration unit includes two branches, namely the third switch branch and the fourth switch branch, each branch includes two parts, namely the first part and the second part; the first part of the third switch branch can be used to receive Vctrl, and the first part of the fourth switch branch can be used to receive Vctrl_n. The states of the first part and the second part can be one of the on state and the off state. The state of the first part can follow the level changes of Vctrl and Vctrl_n, and the state of the second part can be set before leaving the factory.

[0057] As mentioned above, the states of the first part and the second part can be either an on state or an off state. The first part can be implemented by a switch device, and the second part can also be implemented by a switch device. Figure 7 and Figure 8 , Figure 7 and Figure 8 The implementation of 4 current sources of 125nA, 250nA, 500nA, and 1000nA is shown. Figure 7 The 500nA and 1000nA current source branches are shown. Figure 8 The 125nA and 250nA current source branches are shown.

[0058] like Figure 7 and Figure 8 In each current source branch, the current source is connected to the positive calibration point VSP through the positive calibration unit, and the current source is connected to the negative calibration point VSN through the negative calibration unit. Each positive calibration unit and negative calibration unit may include two left and right branches, the left branch of the positive calibration unit is the first switch branch, the right branch of the positive calibration unit is the second switch branch, the left branch of the negative calibration unit is the third switch branch, and the right branch of the negative calibration unit is the fourth switch branch. Each branch may include two upper and lower switches, the lower switch is the first part, and the upper switch is the second part.

[0059] The switches of each current source branch are now named as follows: the first switch branch includes a first switch at the top and a second switch at the bottom; the second switch branch includes a third switch at the top and a fourth switch at the bottom; the third switch branch includes a fifth switch at the top and a sixth switch at the bottom; the fourth switch branch includes a seventh switch at the top and an eighth switch at the bottom.

[0060] For all current source branches, the second control signal of the second switch is Vctrl, the second control signal of the fourth switch is Vctrl_n, the second control signal of the sixth switch is Vctrl, and the second control signal of the eighth switch is Vctrl.

[0061] At this time, at the low input common mode point, Vctrl_n controls conduction and Vctrl controls cutoff, then the current obtained by the positive calibration point VSP depends on the four bits TRIM_P<7:4>, and the current obtained by the negative calibration point VSN depends on the four bits TRIM_N<7:4>.

[0062] At the high input common mode point, Vctrl_n controls the cutoff and Vctrl controls the conduction. Then the current obtained at the positive calibration point VSP depends on the four bits TRIM_P<3:0>, and the current obtained at the negative calibration point VSN depends on the four bits TRIM_N<3:0>.

[0063] The above TRIM_P<7:4> and TRIM_N<7:4> are the calibration codes for the PMOS tube pair, and TRIM_P<3:0> and TRIM_N<3:0> are the calibration codes for the NMOS tube pair. TRIM_P and TRIM_N are used to calibrate the positive offset voltage and the negative offset voltage. The trim code can be set during the test calibration before delivery. The trim code is TRIM_P and TRIM_N. The trim code is stored in the memory, and the memory can generate the above TRIM_P and TRIM_N signals.

[0064] Calibration instructions for the mid-input common mode point:

[0065] 1. Assuming that the input common mode point is low, the PMOS tube pair needs to inject current IT1 to calibrate the PMOS tube pair;

[0066] 2. At the middle input common mode point, assuming that the PMOS tube pair and the NMOS tube pair have a positive and a negative offset voltage, the inverse offset voltage itself can be partially compensated by the PMOS tube pair and the NMOS tube pair, so when injecting current IT1 to calibrate the PMOS tube pair, only one current mirror is needed for the PMOS tube pair and the NMOS tube pair, and the PMOS tube pair and the NMOS tube pair can assign calibration values ​​to themselves. Assuming that the offset voltages of the PMOS tube pair and the NMOS tube pair are in phase, for example, both are positive, then inject current at the negative calibration point VSN, and calibrate the offset voltages of the PMOS tube pair and the NMOS tube pair according to the trim code value preset before leaving the factory.

[0067] The offset voltages of the PMOS and NMOS pairs will be in opposite directions at the intermediate input common-mode point, so a current mirror (such as Figure 7 and Figure 8 ), but also because the differential pairs (PMOS transistor pair and NMOS transistor pair) themselves can compensate each other.

[0068] like Figure 6The calibration module can provide current for the positive calibration point VSP and the negative calibration point VSN of the load level according to the TRIM_P, TRIM_N, Vctrl_n and Vctrl signals. The current obtained at the positive calibration point VSP affects the current of the MOS tube PM1, and the current obtained at the negative calibration point VSN affects the current of the MOS tube PM2, thereby affecting the gate-source voltage of the MOS tubes PM1 and PM2, that is, adjusting the offset voltage.

[0069] A way to obtain Vctrl_n and Vctrl in the common mode point judgment module is as follows Figure 6 The common mode point judgment module 102 may include a comparator A1, a first resistor R1, a third transistor M3 and a fourth transistor M4, the third transistor M3 and the fourth transistor M4 constitute a current mirror, the fourth transistor M4 is used to copy the current of the third transistor M3, the third transistor M3 is connected in series with the second transistor M2, the current of the third transistor M3 is the same as that of the second transistor M2, the current of the second transistor M2 is the same as that of the first transistor NMS, and thus the fourth transistor M4 obtains the current of the first transistor NMS.

[0070] The fourth transistor M4 is connected in series with the first resistor R1, the first end of the first resistor R1 is connected to the first potential VSSA, the second end of the first resistor R1 obtains the Vctrl signal, the second end of the first resistor R1 is connected to the control switch unit of the calibration module, and the second end of the first resistor R1 is connected to the first input end of the comparator A1, and the second input end of the comparator A1 receives the reference voltage Vref.

[0071] Comparator A1 is used to output a first level signal when the voltage at the first input terminal is greater than a reference voltage, and output a second level signal when the voltage at the first input terminal is less than the reference voltage, the first level signal and the second level signal are high level and low level respectively; the output end of comparator A1 obtains Vctrl_n, and the output end of comparator A1 is connected to the control switch unit.

[0072] like Figure 6, a common mode point judgment switch S1 can also be set, and the common mode point judgment switch S1 is connected in series with a fifth transistor M5, and the gate of the fifth transistor M5 is connected to the gate of the first transistor NMS. Set the switch S1 to be disconnected at the low input common mode point and turned on at the middle input common mode point and the high input common mode point. Then, when it is at the low input common mode point, the current on the MOS tube PMS flows through the PMOS tube pair, and there is no current on the MOS tube NMS. At this time, Vctrl_n is pulled high; when it is at the middle input common mode point, the common mode point judgment switch S1 is turned on, the PMOS tube pair and the NMOS tube pair work normally, and share the current on the MOS tube PMS. At this time, Vctrl is raised, and Vctrl_n is still high; when it is at the high input common mode point, the common mode point judgment switch S1 is turned on, the PMOS tube pair is cut off, current flows through the MOS tube NMS, Vctrl is high, and Vctrl_n is pulled low.

[0073] Because the potential of Vctrl is determined by the current on the MOS tube NMS, the current on the mirror MOS tube NMS flows through the resistor to generate Vctrl. The larger the current on the MOS tube NMS, the higher the potential of Vctrl. Vctrl_n is pulled high only when the current on the MOS tube PMS flows through the MOS tube NMS, or in other words, the PMOS tube is completely cut off, so Vctrl_n is generated by comparator A1. The reference voltage Vref can be generated by a fixed current flowing through a resistor. When Vctrl exceeds Vref, comparator A1 outputs 0.

[0074] Fig. 9 An implementation method of generating Vctrl and Vctrl_n signals without using a comparator is shown. The rail-to-rail amplifier further includes a second current mirror, which includes a MOS transistor PMS and a seventh transistor M7; the seventh transistor M7 is used to replicate the current of the MOS transistor PMS; the MOS transistor PMS is connected in series with the second input stage, and the second input stage is Fig. 9 The MOS tubes PM1 and PM2 in the first input stage are Fig. 9 MOS tubes NM1 and NM2 in the figure. VBPS and VBNS in the figure are provided by the bias module, which has been omitted in the figure.

[0075] The common mode point judgment module 102 is connected to the second transistor M2 and the seventh transistor M7. The common mode point judgment module 102 may include two three current mirrors: the first current mirror includes the third transistor and the fourth transistor; the second current mirror includes the eighth transistor and the ninth transistor; the third current mirror includes the tenth transistor and the eleventh transistor.

[0076] The third transistor and the fourth transistor generate Vctrl in the same manner as before.

[0077] The second current mirror, the third current mirror and the resistor R2 generate Vctrl_n, which is also converted into a voltage signal through the resistor R2, and this method does not require a comparator. Specifically, the eighth transistor is connected in series with the seventh transistor M7 so that the current is the same, the ninth transistor is used to copy the current of the eighth transistor, the tenth transistor is connected in series with the ninth transistor so that the current is the same, and the eleventh transistor is used to copy the current of the tenth transistor. Therefore, the current of the eleventh transistor is the current of the MOS tube PMS, and the voltage of the resistor R2 can determine whether the MOS tube PMS has current passing through it. That is, the two sets of current mirrors can determine the working status of the NMOS tube pair and the PMOS tube pair.

[0078] Based on the above embodiments, the embodiments of the present application further provide a chip, in which the above rail-to-rail amplifier is packaged.

[0079] The above-described device and system embodiments are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. A person skilled in the art may understand and implement the present embodiment without creative effort.

[0080] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A rail-to-rail amplifier, comprising an input stage, a load stage and an output stage; the input stage comprises a first input stage and a second input stage, the first input stage and the second input stage are respectively connected to the load stage; the load stage is connected to the output stage; The first input stage is an NMOS transistor pair, and the second input stage is a PMOS transistor pair, or the first input stage is a PMOS transistor pair, and the second input stage is an NMOS transistor pair; The first input stage and the second input stage are used to receive a positive input voltage (INP) and a negative input voltage (INM), and obtain an output current according to the positive input voltage (INP) and the negative input voltage (INM); The load stage is used to obtain a voltage signal according to the output current; The output stage is used to obtain an output voltage according to the voltage signal; It is characterized in that The rail-to-rail amplifier also includes a first current mirror, a common mode point judgment module and a calibration module; The first current mirror comprises a first transistor and a second transistor, wherein the second transistor is used to replicate the current of the first transistor; the first transistor is connected in series with the first input stage; The common mode point determination module is connected to the second transistor; The common mode point determination module is used to output at least two first control signals to the calibration module according to the current of the second transistor; the at least two first control signals represent the input state of the rail-to-rail amplifier, and the input state includes a high input common mode point, a middle input common mode point and a low input common mode point; The input end of the calibration module is connected to the common mode point judgment module, and the output end of the calibration module is connected to the transistor in the load stage; the calibration module pre-stores the current output values ​​corresponding to different first control signals; The calibration module is used to provide current to the transistor in the load stage according to the at least two-bit first control signal.

2. The rail-to-rail amplifier according to claim 1, wherein: The calibration module comprises a logic circuit unit and a plurality of current source branches, each of the current source branches comprising a current source and a switch unit connected in series; In each of the current source branches, the first end of the switch unit is connected to the current source, the second end of the switch unit is connected to the transistor in the load stage, and the control end of the switch unit is connected to the output end of the logic circuit unit; The input end of the logic circuit unit is connected to the common mode point determination module, and the logic circuit unit is used to provide a second control signal to the switch unit according to the at least two first control signals to control the switch unit to be cut off or turned on.

3. The rail-to-rail amplifier according to claim 1, wherein: The calibration module includes a plurality of current source branches, each of which is connected to a transistor in the load stage; Each of the current source branches includes a current source and a control switch unit connected in series, and a control end of the control switch unit is connected to the common mode point judgment module.

4. The rail-to-rail amplifier according to claim 3, wherein: The control switch unit of each current source branch includes a positive calibration unit and a negative calibration unit; In each of the current source branches, the first end of the positive calibration unit is connected to the positive calibration point of the load stage, the positive calibration point is connected to the transistor in the input stage that receives the negative input voltage (INM), the first end of the negative calibration unit is connected to the negative calibration point of the load stage, the negative calibration point is connected to the transistor in the input stage that receives the positive input voltage (INP), the second end of the positive calibration unit is connected to the current source, and the control end of the positive calibration unit and the control end of the negative calibration unit are used to receive the at least two first control signals.

5. The rail-to-rail amplifier according to claim 4, characterized in that The at least two first control signals are a first first control signal and a second first control signal; The calibration module includes a memory; The memory is used to generate a calibration digital signal; The calibration digital signal includes a calibration digital signal for each of the current source branches; The calibration digital signal for each current source branch includes a positive calibration digital signal when the NMOS tube pair is working, a negative calibration digital signal when the NMOS tube pair is working, a positive calibration digital signal when the PMOS tube pair is working, and a negative calibration digital signal when the PMOS tube pair is working; The forward calibration unit comprises a first switch branch and a second switch branch; The first switch branch includes a first switch and a second switch connected in series; The second switch branch includes a third switch and a fourth switch connected in series; The control end of the first switch is used to receive the forward calibration digital signal when the NMOS transistor pair is working; The control end of the second switch is used to receive the first-bit first control signal, and when the first-bit first control signal turns on the second switch, it indicates that current flows through the NMOS transistor; The control end of the third switch is used to receive the forward calibration digital signal when the PMOS tube pair is working; The control end of the fourth switch is used to receive the second-bit first control signal, and when the second-bit first control signal turns on the fourth switch, it indicates that current flows through the PMOS tube; The negative calibration unit includes a third switch branch and a fourth switch branch; The third switch branch includes a fifth switch and a sixth switch connected in series; The fourth switch branch includes a seventh switch and an eighth switch connected in series; The control end of the fifth switch is used to receive the negative calibration digital signal when the NMOS transistor pair is working; The control end of the sixth switch is used to receive the first first control signal, and when the first first control signal turns on the sixth switch, it indicates that current flows through the NMOS transistor; The control end of the seventh switch is used to receive the negative calibration digital signal when the PMOS tube pair is working; The control end of the eighth switch is used to receive the second-bit first control signal. When the second-bit first control signal turns on the eighth switch, it indicates that current flows through the PMOS transistor.

6. The rail-to-rail amplifier according to claim 3, wherein: The common mode point determination module includes a comparator, a first resistor, a third transistor and a fourth transistor, the third transistor and the fourth transistor form a current mirror, and the fourth transistor is used to replicate the current of the third transistor; The third transistor is connected in series with the second transistor, the fourth transistor is connected in series with the first resistor, a first end of the first resistor is connected to a first potential, a second end of the first resistor is connected to the control switch unit, and a second end of the first resistor is connected to a first input end of the comparator, and a second input end of the comparator receives a reference voltage; an output end of the comparator is connected to the control switch unit; The comparator is used to output a first level signal when the voltage at the first input terminal is greater than the reference voltage, and output a second level signal when the voltage at the first input terminal is less than the reference voltage; The potential output by the comparator and the potential at the second end of the first resistor are used as the at least two-bit first control signal; The control switch unit is used for cutting off or turning on according to the potential output by the comparator and the potential of the second end of the first resistor.

7. The rail-to-rail amplifier according to claim 6, wherein: The rail-to-rail amplifier further includes a common mode point determination switch; the first current mirror further includes a fifth transistor, and the common mode point determination switch is connected in series with the fifth transistor; The fifth transistor is used to replicate the current of the first transistor when the common mode point determination switch is turned on; The second transistor is used to replicate the current of the first transistor when the common mode point judgment switch is turned on; The common mode point determination switch is used to be cut off at the low input common mode point and to be turned on at the high input common mode point and the middle input common mode point.

8. The rail-to-rail amplifier according to claim 3, wherein: The rail-to-rail amplifier further includes a second current mirror, the second current mirror including a sixth transistor and a seventh transistor; The seventh transistor is used to replicate the current of the sixth transistor; The sixth transistor is connected in series with the second input stage; The common mode point determination module is connected to the second transistor and the seventh transistor; The at least two first control signals include a first first control signal and a second first control signal; The common mode point determination module is used to generate the first-bit first control signal according to the current of the second transistor, and to generate the second-bit first control signal according to the current of the seventh transistor; The first control signal of the first bit indicates the working state of the first input stage; The second-bit first control signal indicates a working state of the second input stage.

9. The rail-to-rail amplifier according to any one of claims 2 to 8, characterized in that There are n current source branches in total, and the current magnitudes of the current sources of the n current source branches are arranged in a 2^n times basic current arrangement, where n is a natural number.

10. A chip, characterized in that: The chip encapsulates the rail-to-rail amplifier according to any one of claims 1 to 9.

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