Low-temperature-drift precise clock generation circuit
By designing a low-temperature drift precise clock generation circuit, using bias current generation unit and oscillator unit, the problem of large area occupied by external crystal oscillator circuits is solved, and an accurate clock with adjustable frequency and adjustable duty cycle is realized, suitable for highly integrated small size and low cost application scenarios.
Patent Information
- Application Number
- CN202411320849.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2025-02-18
AI Technical Summary
In the prior art, the method of generating clock signals through external crystal oscillator circuits occupies a large area and cannot be integrated on the chip.
A low-temperature drift precise clock generation circuit is designed, including a bias current generation unit, a bias current adjustment unit and an oscillator unit. Through the superposition of positive temperature coefficient current and negative temperature coefficient current, a frequency adjustable and duty cycle are generated. Adjustable precision clock.
It realizes the integrated clock signal generation circuit on the chip, reducing costs, and is suitable for highly integrated, small-size and low-cost application scenarios.
Smart Images
Figure CN119483549A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-temperature drift precision clock generating circuit. Background Art
[0002] The clock signal generating circuit has always been one of the core modules of many chips. The clock signal generating circuit is widely used in circuits such as wireless transceiver systems, digital system chips, SOC systems and data converters. The quality of the clock signal affects the performance of the system. For very accurate clock signals, an external crystal oscillator is usually used to generate them, but the crystal oscillator has the disadvantages of occupying a large area, being unable to be integrated into the chip and being high in cost. Compared with the external crystal oscillator circuit, the on-chip clock signal generating circuit can be integrated on the chip, which greatly reduces the cost. The present invention provides an on-chip clock signal, which is a precise clock with adjustable frequency and adjustable duty cycle, suitable for application scenarios with high integration, small size and low cost. Summary of the invention
[0003] In view of the above problems existing in the prior art, the present invention is proposed.
[0004] Therefore, the problem to be solved by the present invention is how to solve the problem that the method of generating a clock signal through an external crystal oscillator circuit occupies a large area and cannot be integrated.
[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: a low temperature drift precision clock generating circuit, comprising: a bias current generating unit, comprising a positive temperature coefficient current generating module, a negative temperature coefficient current generating module, and a current superposition module; the positive temperature coefficient current generating module is used to generate a positive temperature coefficient current, the negative temperature coefficient current generating module is used to generate a negative temperature coefficient current, and the current superposition module is used to superimpose the positive temperature coefficient current and the negative temperature coefficient current; a bias current trimming unit, whose input end is connected to the output end of the bias current generating unit, comprising a current coarse adjustment module, a current fine adjustment module and a thermometer decoder; the current coarse adjustment module and the current fine adjustment module are used to mirror the bias current generated by the bias current generating unit, and the thermometer decoder is used to control the magnitude of the output current of the bias current trimming unit; an oscillator unit, whose input end is connected to the output end of the bias current trimming unit, and the output end is connected to the input end of the buffer module.
[0006] As a preferred solution of the low-temperature drift precision clock generating circuit of the present invention, the positive temperature coefficient current generating module includes a first transistor, a second transistor, a first operational amplifier, a first resistor array, a first triode and a second triode; the gate of the first transistor and the gate of the second transistor are connected and are both connected to the output end of the first operational amplifier, the sources of the two are connected to the power line, and the drains of the two are respectively connected to the emitter of the first triode and the emitter of the second triode; the first resistor array is connected in series between the drain of the second transistor and the emitter of the second triode; the reverse input end of the first operational amplifier is connected to the drain of the first transistor, and the forward input end of the first operational amplifier is connected to the drain of the second transistor; the base and collector of the first triode and the second triode are both grounded.
[0007] As a preferred solution of the low-temperature drift precision clock generating circuit of the present invention, the negative temperature coefficient current generating module includes a third transistor, a second operational amplifier, a second resistor array and a binary decoder; the source of the third transistor is connected to the power line, the drain is grounded, and the gate is connected to the output end of the second operational amplifier; the second resistor array is connected in series between the drain of the third transistor and the ground line; the input end of the binary decoder is connected to an external control signal, and the output end is connected to the control end of the second resistor array; the reverse input end of the second operational amplifier is connected to the reverse input end of the first operational amplifier, and the forward output end is connected to the drain of the third transistor.
[0008] As a preferred solution of the low-temperature drift precision clock generating circuit described in the present invention, wherein: the current superposition module includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; the gates of the fourth transistor and the sixth transistor are both connected to the output end of the first operational amplifier, and the sources are both connected to the power line; the gates of the fifth transistor and the seventh transistor are both connected to the output end of the second operational amplifier, and the sources are both connected to the power line; the drains of the fourth transistor and the fifth transistor are connected to each other, and the drains of the sixth transistor and the seventh transistor are connected to each other.
[0009] As a preferred solution of the low-temperature drift precision clock generating circuit described in the present invention, wherein: the current coarse adjustment module includes an eighth transistor, a first transistor array and a second transistor array, the gate and drain of the eighth transistor are both connected to the gates of each transistor in the first transistor array; the source of each transistor in the second transistor array is correspondingly connected to the drain of each transistor in the first transistor array.
[0010] As a preferred solution of the low-temperature drift precision clock generating circuit described in the present invention, wherein: the current fine-tuning module includes a ninth transistor, a third transistor array and a fourth transistor array; the gate and drain of the ninth transistor are both connected to the gates of each transistor in the third transistor array; the source of each transistor in the fourth transistor array is correspondingly connected to the drain of each transistor in the third transistor array.
[0011] As a preferred solution of the low-temperature drift precision clock generating circuit of the present invention, the input end of the thermometer decoder is connected to an external control signal, and the output end is respectively connected to the gates of each transistor in the second transistor array and the fourth transistor array.
[0012] As a preferred solution of the low-temperature drift precision clock generating circuit of the present invention, wherein: the oscillator unit includes a 138th transistor, a 139th transistor, a 140th transistor, a 141st transistor and a 142nd transistor; the gates of the 138th transistor and the 139th transistor are connected to each other; the drain of the 138th transistor and the gate of the 140th transistor are both connected to the output end of the bias current trimming unit; the drain of the 139th transistor is connected to the drain and gate of the 141st transistor; the gate of the 142nd transistor is connected to the gate of the 141st transistor, the source is connected to the source of the 140th transistor, and the drain is connected to the drain of the 140th transistor.
[0013] As a preferred solution of the low-temperature drift precision clock generating circuit described in the present invention, wherein: the oscillator unit also includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first capacitor and a second capacitor; the output end of the first inverter is connected to one electrode of the first capacitor, and the other electrode of the first capacitor is connected to the drain of the first one hundred and forty transistors; the input end of the second inverter is connected to the drain of the first one hundred and forty transistors, and the output end is connected to the input end of the first inverter; the output end of the third inverter is connected to the input end of the fourth inverter and the input end of the buffer module; the output end of the fourth inverter is connected to the drain of the first one hundred and forty transistors; one electrode of the second capacitor is connected to the drain of the first one hundred and forty transistors, and the other electrode is grounded.
[0014] As a preferred solution of the low-temperature drift precision clock generating circuit of the present invention, the output end of the buffer module is a clock output end.
[0015] The beneficial effects of the present invention are as follows: through the setting of the bias current generating unit, the bias current adjusting unit and the oscillator unit, the clock generating circuit of the present invention can generate a precise clock with adjustable frequency and adjustable duty cycle, which is suitable for highly integrated, small-size and low-cost application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 This is the overall structure diagram of the low temperature drift precision clock generation circuit.
[0018] Figure 2 This is the circuit structure diagram of the bias current generating unit.
[0019] Figure 3 This is the circuit structure diagram of the bias current adjustment unit.
[0020] Figure 4 This is the circuit structure diagram of the oscillator unit.
[0021] Figure 5 Output waveform for the oscillator unit.
[0022] Figure 6 This is the circuit diagram of the parasitic capacitance of the oscillator unit.
[0023] Figure 7 Waveform output plot when parasitic capacitance is considered for the oscillator unit. DETAILED DESCRIPTION
[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.
[0025] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0026] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it an embodiment that is mutually exclusive with other embodiments, either individually or selectively.
[0027] Example 1
[0028] Reference Figure 1 to Figure 7 , which is the first embodiment of the present invention, and provides a low temperature drift precision clock generation circuit, the low temperature drift precision clock generation circuit includes a bias current generation unit 100, a bias current adjustment unit 200 and an oscillator unit 300, such as Figure 1 shown.
[0029] Specifically, the bias current generating unit 100 includes a positive temperature coefficient generating module 101, a negative temperature coefficient current generating module 102, a current superposition module 103 and a binary decoder 104;
[0030] Further, see Figure 2 The positive temperature coefficient generating module 101 includes a first transistor MP1, a second transistor MP2, a first operational amplifier OP1, a first resistor array R P , a first transistor Q1 and a second transistor Q2.
[0031] Reference Figure 3 The negative temperature coefficient current generating module 102 includes a third transistor MP3, a second operational amplifier OP2, a second resistor array R N and a binary decoder 104;
[0032] The current superposition module 103 includes a fourth transistor MP4 , a fifth transistor MP5 , a sixth transistor MP6 and a seventh transistor MP7 .
[0033] The first transistor MP1 , the second transistor MP2 , the third transistor MP3 , the fourth transistor MP4 , the fifth transistor MP5 , the sixth transistor MP6 and the seventh transistor MP7 are all PMOS transistors.
[0034] Specifically, the gate of the first transistor MP1 is connected to the gate of the second transistor MP2, the gate of the fourth transistor MP4, the gate of the sixth transistor MP6 and the output terminal of the first operational amplifier OP1 respectively. The node number of the first transistor MP1, the second transistor MP2, the fourth transistor MP4, the fifth transistor MP6 and the first operational amplifier OP1 is V P ;
[0035] The source of the first transistor MP1 is connected to a power line, and the power node is numbered as VDD;
[0036] The drain of the first transistor MP1 is connected to the emitter of the first triode Q1, the inverting input terminal of the first operational amplifier OP1, and the inverting input terminal of the second operational amplifier OP2. The node number of the first transistor MP1, the first triode Q1, the first operational amplifier OP1, and the second operational amplifier OP2 is V BE1 The gate of the second transistor MP2 is connected to the node V P The source of the second transistor MP2 is connected to the power supply node VDD.
[0037] The drain of the second transistor MP2 is connected to the first resistor array R P The first end of the first operational amplifier OP1 is connected to the positive input end of the first transistor MP2 and the first resistor array R P The node number connected to the first operational amplifier OP1 is V R1 ;
[0038] The gate of the third transistor MP3 is connected to the gate of the fifth transistor MP5, the gate of the seventh transistor MP7 and the output terminal of the second operational amplifier OP2 respectively. The node number of the third transistor MP3, the fifth transistor MP5, the seventh transistor MP7 and the second operational amplifier OP2 is V N ;
[0039] The source of the third transistor MP3 is connected to the power supply node VDD;
[0040] The drain of the third transistor MP3 is respectively connected to the second resistor array R N The first end of the second operational amplifier OP2 is connected to the positive input end of the third transistor MP3 and the second resistor array R N The node number connected to the second operational amplifier OP2 is V R2 ;
[0041] The gate of the fourth transistor MP4 is connected to the node V P , the source is connected to the power supply node VDD, and the drain is connected to the drain of the fifth transistor MP5.
[0042] The gate of the fifth transistor MP5 is connected to the node V N , the source is connected to the power supply node VDD, and the drain is connected to the drain of the fourth transistor MP4.
[0043] The gate of the sixth transistor MP6 is connected to the node V P The source is connected to the power supply node VDD, and the drain is connected to the drain of the seventh transistor MP7.
[0044] The gate of the seventh transistor MP7 is connected to the node V N , the source is connected to the power supply node VDD, and the drain is connected to the drain of the sixth transistor MP6.
[0045] The emitter of the first transistor Q1 is connected to the node V BE1 , the base is grounded, the ground node is numbered as GND, and the collector is connected to node GND.
[0046] The emitter of the second transistor Q2 is connected to the first resistor array R P The second end, the base is connected to the node GND, and the collector is connected to the node GND.
[0047] The first resistor array R P , whose first end is connected to node V R1 , the second end is connected to the emitter of the second transistor Q2.
[0048] The second resistor array R N , whose first end is connected to node V R2 , the second end is connected to the node GND, and the control end is connected to the output end of the binary decoder.
[0049] The first operational amplifier OP1 has its positive input terminal connected to the node V R1 , the negative input terminal is connected to node V BE1 , the output terminal is connected to node V P ;
[0050] The second operational amplifier OP2 has its positive input terminal connected to the node V R2 , the negative input terminal is connected to node V BE1 , the output terminal is connected to node V N .
[0051] Specifically, the bias current trimming unit 200 includes a current coarse adjustment module 201 , a current fine adjustment module 202 and a thermometer decoder 203 .
[0052] Furthermore, the current coarse adjustment module 201 includes an eighth transistor MN8, a first transistor array and a second transistor array.
[0053] The current fine tuning module 202 includes a ninth transistor MN9 , a third transistor array and a fourth transistor array.
[0054] The transistors in the bias current trimming unit 200 are all NMOS transistors, the first transistor array includes the 74th transistor MN74 to the 105th transistor MN105, a total of 32 transistors, and the second transistor array includes the 106th transistor MN106 to the 137th transistor MN137, a total of 32 transistors.
[0055] The third transistor array includes a tenth transistor MN10 to a forty-first transistor MN41, which are 32 transistors in total. The fourth transistor array includes a forty-second transistor MN42 to a seventy-third transistor MN73, which are 32 transistors in total.
[0056] Further, the gate of the eighth transistor MN8 is connected to the drain of the fourth transistor MP4, the drain of the fifth transistor MP5, and the gates of the seventy-fourth transistor MN74 to the one hundred and sixth transistor MN106. The node number of the eighth transistor MN8, the fourth transistor MP4, the fifth transistor MP5, and the seventy-fourth transistor MN74 to the one hundred and sixth transistor MN106 is 1. B1 ;
[0057] The source of the eighth transistor MN8 is connected to the node GND, and the drain is connected to the node I B1 .
[0058] The ninth transistor MN9 has a gate connected to the drain of the sixth transistor MP6, the drain of the seventh transistor MP7, and the gates of the tenth transistor MN10 to the forty-first transistor MN41. The node number of the ninth transistor MN9, the sixth transistor MP6, the seventh transistor MP7, and the tenth transistor MN10 to the forty-first transistor MN41 is 1. B2 .
[0059] The ninth transistor MN9 has a source connected to the node GND and a drain connected to the node I. B2 .
[0060] The tenth transistor MN10 to the forty-first transistor MN41 have their sources connected to the node GND and their gates connected to the node I. B2 , the drains are respectively connected to the sources of the forty-second transistor MN42 to the seventy-third transistor MN73.
[0061] The seventy-fourth transistor MN74 to the one hundred and fifth transistor MN105 have their sources connected to the node GND, and their gates connected to the node I. B1 , the drains are respectively connected to the sources of the one-hundred-and-fifth transistor MN105 to the one-hundred-and-thirty-seventh transistor MN137.
[0062] The sources of the 42nd transistor MN42 to the 73rd transistor MN73 are respectively connected to the drains of the 10th transistor MN10 to the 41st transistor MN41, and the gates are respectively connected to the output control signal S of the thermometer decoder 203. <0> ~S <31> , the drains are respectively connected to the drains of the one-hundred-sixth transistor MN106 to the one-hundred-thirty-seventh transistor MN137.
[0063] The sources of the 106th transistor MN106 to the 137th transistor MN137 are respectively connected to the drains of the 74th transistor MN74 to the 105th transistor MN105, and the gates are respectively connected to the output control signal S of the thermometer decoder 203. <32> ~S <63> , the drains are respectively connected to the drains of the forty-second transistor MN42 to the seventy-third transistor MN73.
[0064] The thermometer decoder 203 has an input terminal connected to an external control signal, and an output terminal connected to the gates of the 42nd transistor MN42 to the 73rd transistor MN73 and the gates of the 106th transistor MN106 to the 137th transistor MN137 respectively.
[0065] Specifically, refer to Figure 4 The oscillator unit 300 includes a 138th transistor MN138, a 139th transistor MN139, a 140th transistor MN140, a 141st transistor MN141, a 142nd transistor MN142, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor C1 and a second capacitor C2.
[0066] Further, the source of the 138th transistor MP138 is connected to the node VDD, and the gate is respectively connected to the drains of the 42nd transistor MN42 to the 73rd transistor MN73, the drains of the 105th transistor MN105 to the 137th transistor MN137, the gate of the 139th transistor MP139, and the gate of the 140th transistor MP140. The node to which the 138th transistor MP138, the 139th transistor MP139, the 140th transistor MP140, the 42nd transistor MN42 to the 73rd transistor MN73, and the 105th transistor MN105 to the 137th transistor MN137 are connected is numbered 1. ROSC .
[0067] The drain of the 138th transistor MP138 is connected to the node I ROSC .
[0068] The one hundred and thirty-ninth transistor MP139 has a source connected to the node VDD and a gate connected to the node I ROSC The drain is connected to the drain and gate of the 141st transistor MN141 and the gate of the 142nd transistor MN142. The node numbered as 1 is connected to the 139th transistor MP139, the 141st transistor MN141 and the 142nd transistor MN142. BN .
[0069] The source of the 140th transistor MP140 is connected to the source of the 142nd transistor MN142 and the output end of the fourth inverter INV4. The node numbered V is where the 140th transistor MP140, the 142nd transistor MN142 and the fourth inverter NV4 are connected. A .
[0070] The gate of the 140th transistor MP140 is connected to the node I ROSC The drain is connected to the drain of the 142nd transistor MN142, the first end of the first capacitor C1, the first end of the second capacitor C2, and the input end of the second inverter INV2. The node numbered V is where the 140th transistor MP140, the 142nd transistor MN142, the first capacitor C1, the second capacitor C2, and the second inverter INV2 are connected. B ;
[0071] The one hundred and forty-first transistor MN141 has a source connected to the node GND and a gate connected to the node I BN , the drain is connected to node I BN .
[0072] The source of the 142nd transistor MN142 is connected to the node V A , the gate connection node I BN , the drain is connected to the node V B .
[0073] The first capacitor C1 has a first end connected to the node V B , and the second end is connected to the output end of the first inverter INV1.
[0074] The second capacitor C2 has a first end connected to the node V B , and the second end is connected to node GND.
[0075] The first inverter INV1 has an input end connected to the output end of the second inverter INV2 and the input end of the third inverter INV3. The node number of the first inverter INV1, the second inverter INV2 and the third inverter INV3 is V C .
[0076] The first inverter INV1 has an output end connected to the second end of the first capacitor C1.
[0077] The second inverter INV2 has its input terminal connected to the node V B , the output terminal is connected to node V C .
[0078] The third inverter INV3 has its input terminal connected to the node V C , the output end is connected to the input end of the fourth inverter INV4;
[0079] The fourth inverter INV4 has an input end connected to the output end of the third inverter INV3 and an output end connected to the node V A .
[0080] Furthermore, an input end of the buffer module 400 is connected to an output end of the third inverter INV3 and an input end of the fourth inverter INV4 , and an output end thereof is a clock output end.
[0081] Based on the above circuit structure, the working principle of the present invention is:
[0082] First, for the bias current generating unit 100, due to the action of the first operational amplifier OP1, the voltage V BE1 =V R1 , positive temperature coefficient current I PTAT It can be expressed as:
[0083]
[0084] Among them, V T is the thermal voltage, which is positively correlated with temperature.
[0085] Due to the action of the second operational amplifier OP2, the voltage V BE1 =V R2 , negative temperature coefficient current I CTAT It can be expressed as:
[0086]
[0087] The binary decoder 203 controls the second resistor array R N The opening and closing of the switch in the middle changes the second resistor array R N The resistance value of the negative temperature coefficient current is changed.
[0088] The fourth transistor MP4 and the sixth transistor MP6 mirror the current of the first transistor MP1 and the second transistor MP2 , ie, the positive temperature coefficient current.
[0089] The fifth transistor MP5 and the seventh transistor MP7 mirror the current of the third transistor MP3, ie, the negative temperature coefficient current.
[0090] The fourth transistor MP4 and the fifth transistor MP5 superimpose the positive temperature coefficient current and the negative temperature coefficient current, and the sixth transistor MP6 and the seventh transistor MP7 also superimpose the positive temperature coefficient current and the negative temperature coefficient current, and the current I B1 and current I B2 They are:
[0091] I B1 =α1I PTAT +α2IPTAT
[0092] I B2 =α3I PTAT +α4I PTAT
[0093] When the coefficients α1, α2, α3 and α4 are appropriate, the current I B1 and current I B2 is a bias current with a near zero temperature coefficient.
[0094] Secondly, for the bias current trimming unit 200, the current flows through the eighth transistor MN8, wherein the 74th transistor MN74 to the 105th transistor MN105 and the eighth transistor MN8 form a current mirror array to replicate the current I B1 .
[0095] The current flows through the ninth transistor MN9, wherein the tenth transistor MN10 to the forty-first transistor MN41 and the ninth transistor MN9 form a current mirror array to replicate the current I B2 .
[0096] Current I B2 Less than current I B1 Therefore, the current mirror array of the ninth transistor MN9, the tenth transistor MN10 to the forty-first transistor MN41 is the current fine adjustment module 202, and the current mirror array of the eighth transistor MN8, the seventy-fourth transistor MN74 to the one hundred and fifth transistor MN105 is the current coarse adjustment module 101.
[0097] The gates of the 42nd transistor MN42 to the 73rd transistor MN73 and the 106th transistor MN106 to the 137th transistor MN137 are controlled by the thermometer decoder 203, which is responsible for turning on and off the entire current mirror array and regulating the output current I ROSC The size of the current I ROSC It can be expressed as:
[0098] I ROSC =(β1+β2+…+β 32 )I B1 +(γ1+γ2+…+γ 32 )I B2
[0099] Next, for the oscillator unit 300 and the buffer module 400, the current I ROSC The 138th transistor MP138, the 139th transistor MP139 and the 140th transistor MP140 form a current mirror, and the 141st transistor MN141 and the 142nd transistor MN142 form a current mirror.
[0100] When the one hundred and forty transistor MP140 and the one hundred and forty-second transistor MN142 operate normally, the current I1 ≈ I1 ≈ I ROSC When V A When V is VDD, V B is GND, V C is VDD, the 140th transistor MP140 works normally, the 142nd transistor MN142 does not work, the current I1 charges the first capacitor C1 and the second capacitor C2, V B Gradually rises, when V B When the rising flip threshold of the second inverter INV2 is reached, the output of the second inverter INV2 flips. A When flipped to GND, V B Flip to VDD, V C Flip to GND, the 140th transistor MP140 does not work, the 142nd transistor MN142 works normally, the current I2 discharges the first capacitor C1 and the second capacitor C2, V B Gradually decreases, when V B When the falling flip threshold of the second inverter INV2 is reached, the output of the second inverter INV2 flips. A When it turns to VDD, V B Flip to GND, V C When it switches to VDD, an oscillation cycle ends.
[0101] V B The output waveform of CLK is as follows Figure 5 As shown, V H 、V L 、V t,r and V t,f are respectively the output high level voltage, the output low level voltage, the input rising flip threshold voltage and the input falling flip threshold voltage of the second inverter INV2. H and T L The clock high level maintenance time and the clock low level maintenance time are respectively, the clock cycle T CLK =T H +T L , T L and T H It can be expressed as:
[0102]
[0103] Due to T L ≈T H , the clock duty cycle is about 50%, and the clock frequency f CLK It can be expressed as:
[0104]
[0105] Since I1≈I1≈I ROSC , clock frequency f CLK It can be expressed as:
[0106]
[0107] like Figure 6 and Figure 7 As shown, considering the parasitic capacitances of the one hundred and forty transistor MP140, the one hundred and forty-second transistor MN142 and the second inverter INV2:
[0108]
[0109] Due to T L ′≈T H ′, the clock duty cycle is about 50%.
[0110] Clock frequency and power supply voltage VDD, first capacitor C1, second capacitor C2, parasitic capacitance, current I ROSC And process related, by adjusting the current I ROSC The value of can change the clock frequency.
[0111] In summary, the on-chip clock signal provided by the present invention is a precise clock with adjustable frequency and adjustable duty cycle, and can be applied to highly integrated, small-size and low-cost application scenarios.
[0112] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.
Claims
1. A low temperature drift precision clock generation circuit, characterized in that: include, A bias current generating unit (100) comprises a positive temperature coefficient current generating module (101), a negative temperature coefficient current generating module (102), and a current superposition module (103); the positive temperature coefficient current generating module (101) is used to generate a positive temperature coefficient current, the negative temperature coefficient current generating module (102) is used to generate a negative temperature coefficient current, and the current superposition module (103) is used to superimpose the positive temperature coefficient current and the negative temperature coefficient current; A bias current trimming unit (200), whose input end is connected to the output end of the bias current generating unit (100), comprises a current coarse adjustment module (201), a current fine adjustment module (202) and a thermometer decoder (203); the current coarse adjustment module (201) and the current fine adjustment module (202) are used to mirror the bias current generated by the bias current generating unit (100), and the thermometer decoder (203) is used to control the magnitude of the output current of the bias current trimming unit (200); An oscillator unit (300) has an input end connected to the output end of the bias current trimming unit (200), and an output end connected to the input end of the buffer module (400).
2. The low temperature drift precision clock generation circuit according to claim 1, characterized in that: The positive temperature coefficient current generating module (101) comprises a first transistor (MP1), a second transistor (MP2), a first operational amplifier (OP1), a first resistor array (R P ), a first triode (Q1) and a second triode (Q2); the gate of the first transistor (MP1) and the gate of the second transistor (MP2) are connected and are both connected to the output end of the first operational amplifier (OP1), the sources of both are connected to the power line, and the drains of both are respectively connected to the emitter of the first triode (Q1) and the emitter of the second triode (Q2); the first resistor array (R P ) is connected in series between the drain of the second transistor (MP2) and the emitter of the second triode (Q2); the inverting input terminal of the first operational amplifier (OP1) is connected to the drain of the first transistor (MP1), and the positive input terminal of the first operational amplifier (OP1) is connected to the drain of the second transistor (MP2); the bases and collectors of the first triode (Q1) and the second triode (Q2) are both grounded.
3. The low temperature drift precision clock generation circuit according to claim 2, characterized in that: The negative temperature coefficient current generating module (102) comprises a third transistor (MP3), a second operational amplifier (OP2), a second resistor array (R N ) and a binary decoder (104); the source of the third transistor (MP3) is connected to the power line, the drain is grounded, and the gate is connected to the output end of the second operational amplifier (OP2); the second resistor array (R N ) is connected in series between the drain of the third transistor (MP3) and the ground line; the input end of the binary decoder (104) is connected to an external control signal, and the output end is connected to the second resistor array (R N ) control terminal; the inverting input terminal of the second operational amplifier (OP2) is connected to the inverting input terminal of the first operational amplifier (OP1), and the forward output terminal is connected to the drain of the third transistor (MP3).
4. The low temperature drift precision clock generation circuit according to claim 3, characterized in that: The current superposition module (103) comprises a fourth transistor (MP4), a fifth transistor (MP5), a sixth transistor (MP6) and a seventh transistor (MP7); the gates of the fourth transistor (MP4) and the sixth transistor (MP6) are both connected to the output end of the first operational amplifier (OP1), and the sources are both connected to a power line; the gates of the fifth transistor (MP5) and the seventh transistor (MP7) are both connected to the output end of the second operational amplifier (OP2), and the sources are both connected to the power line; the drains of the fourth transistor (MP4) and the fifth transistor (MP5) are connected to each other, and the drains of the sixth transistor (MP6) and the seventh transistor (MP7) are connected to each other.
5. The low temperature drift precision clock generation circuit according to claim 4, characterized in that: The current coarse adjustment module (201) comprises an eighth transistor (MN8), a first transistor array and a second transistor array, the gate and drain of the eighth transistor (MN8) are both connected to the gates of each transistor in the first transistor array; the source of each transistor in the second transistor array is correspondingly connected to the drain of each transistor in the first transistor array.
6. The low temperature drift precision clock generation circuit according to claim 5, characterized in that: The current fine adjustment module (202) comprises a ninth transistor (MN9), a second transistor array and a fourth transistor array; the gate and drain of the ninth transistor (MN9) are both connected to the gates of each transistor in the third transistor array; the source of each transistor in the fourth transistor array is correspondingly connected to the drain of each transistor in the third transistor array.
7. The low temperature drift precision clock generation circuit according to claim 6, characterized in that: The input end of the thermometer decoder (203) is connected to an external control signal, and the output end is respectively connected to the gates of each transistor in the second transistor array and the fourth transistor array.
8. The low temperature drift precision clock generation circuit according to claim 7, characterized in that: The oscillator unit (300) comprises a one-hundred-thirty-eighth transistor (MN138), a one-hundred-thirty-nineth transistor (MN139), a one-hundred-fortyth transistor (MN140), a one-hundred-forty-first transistor (MN141) and a one-hundred-forty-second transistor (MN142); the gates of the one-hundred-thirty-eighth transistor (MN138) and the one-hundred-thirty-ninth transistor (MN139) are connected to each other; the drain of the one-hundred-thirty-eighth transistor (MN138) and the gate of the one-hundred-fortyth transistor (MN140) are both connected to the output end of the bias current trimming unit (200); the drain of the one-hundred-thirty-ninth transistor (MN139) is connected to the drain and gate of the one-hundred-forty-first transistor (MN141); the gate of the one-hundred-forty-second transistor (MN142) is connected to the gate of the one-hundred-forty-first transistor (MN141), the source is connected to the source of the one-hundred-fortyth transistor (MN140), and the drain is connected to the drain of the one-hundred-fortyth transistor (MN140).
9. The low temperature drift precision clock generation circuit according to claim 8, characterized in that: The oscillator unit (300) further comprises a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a fourth inverter (INV4), a first capacitor (C1) and a second capacitor (C2); the output end of the first inverter (INV1) is connected to one electrode of the first capacitor (C1), the other electrode of the first capacitor (C1) is connected to the drain of the first one hundred and forty transistors (MN140); the input end of the second inverter (INV2) is connected to the first one hundred and forty transistors (MN140); The drain of the transistor (MN140) is connected, and the output end is connected to the input end of the first inverter (INV1); the output end of the third inverter (INV3) is connected to the input end of the fourth inverter (INV4) and the input end of the buffer module (400); the output end of the fourth inverter (INV4) is connected to the drain of the first one hundred and forty transistors (MN140); one electrode of the second capacitor (C2) is connected to the drain of the first one hundred and forty transistors (MN140), and the other electrode is grounded.
10. The low temperature drift precision clock generation circuit according to claim 9, characterized in that: The output end of the buffer module (400) is a clock output end.