Power-on reset circuit

Abstract

The invention provides a power-on reset circuit, which comprises a voltage stabilization module configured to receive power supply voltages and convert different power supply voltages into stable intermediate voltages; the voltage dividing module comprises a first voltage dividing element and a second voltage dividing element which are connected to the output end of the voltage stabilizing module in series, the first voltage dividing element and the second voltage dividing element divide the intermediate voltage, and a connecting node of the first voltage dividing element and the second voltage dividing element outputs sampling voltage; a bandgap reference circuit configured to output a reference voltage; the comparator is used for receiving and comparing the reference voltage and the sampling voltage and outputting a comparison result; and the pulse generation circuit is used for converting into a pulse power-on reset signal based on the change of the comparison result.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a power-on reset circuit. Background Art

[0002] The traditional power-on reset circuit (POR) relies on the principle of capacitor charging and discharging to trigger the reset signal by generating a current pulse. However, when the power supply is powered on slowly, the capacitor may have released all the current during the power-on process, resulting in the failure to generate the reset signal. In addition, under different power supply voltages, the traditional power-on reset circuit cannot generate the power-on reset signal at the right time, so it cannot be used in wide voltage scenarios. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a power-on reset circuit, which can generate a reset signal at an appropriate time under different power supply voltages and is suitable for wide voltage scenarios.

[0004] The technical solution of the present invention is achieved in this way: The embodiment of the present disclosure provides a power-on reset circuit, including: a voltage stabilizing module, a voltage dividing module, a bandgap reference circuit, a comparator and a pulse generating circuit; the voltage stabilizing module is configured to receive a power supply voltage and convert different power supply voltages into a stable intermediate voltage; the voltage dividing module is configured to divide the intermediate voltage, including a first voltage dividing element and a second voltage dividing element connected in series at the output end of the voltage stabilizing module, the first voltage dividing element and the second voltage dividing element divide the intermediate voltage, and the connection node between the first voltage dividing element and the second voltage dividing element outputs a sampling voltage; the bandgap reference circuit is configured to output a reference voltage; the comparator receives and compares the reference voltage and the sampling voltage, and outputs a comparison result; when the comparison result changes, a pulse power-on reset signal is generated, so that the chip can be automatically reset after power-on.

[0005] Because the voltage stabilizing module can convert different power supply voltages into a stable intermediate voltage, no matter the setting level of the power supply voltage is high (e.g. 5V) or low (e.g. 2V), when the power supply voltage rises to the setting level, the level of the intermediate voltage is fixed (e.g. 2V). The intermediate voltage changes with the power supply voltage, and the rising speed of the intermediate voltage follows the power-on speed of the power supply voltage. When the intermediate voltage reaches a fixed value, the power supply voltage rises to the setting level, so the intermediate voltage can reflect whether the power supply voltage rises to the setting level.

[0006] The sampling voltage obtained by the voltage divider module by dividing the intermediate voltage is a fixed value. Since the sampling voltage is obtained by dividing the intermediate voltage, the size of the sampling voltage can reflect whether the power supply voltage has reached the set level. The comparator compares the reference voltage and the sampling voltage and outputs the comparison result. When the sampling voltage is greater than the reference voltage, it indicates whether the power supply voltage has reached the set level.

[0007] When the comparison result changes, the pulse generating circuit generates a pulse power-on reset signal. The change in the comparison result indicates that the sampling voltage just exceeds the reference voltage, that is, the power supply voltage just rises to the set level, and the pulse power-on reset signal is triggered at this time. The power-on reset signal will not be triggered in advance when the power supply voltage does not reach the set level, nor will it be triggered after a long time after the power supply voltage reaches the set level.

[0008] The power-on reset circuit may also include a capacitor connected between the output node and the ground. The capacitor can delay the power-on time of the sampling voltage. When the power supply voltage starts to be powered on, if the power supply voltage is powered on too fast, the capacitor can slow down the rising speed of the sampling voltage, so that the sampling voltage is less than the reference voltage, and the comparison result is the first state at this time; when the power supply voltage is powered on to a set level, the sampling voltage is equal to or greater than the reference voltage, and the comparison result is a second state different from the first state at this time, and the comparison result changes, so that the pulse generation circuit can generate a pulse power-on reset signal to avoid erroneous triggering of reset caused by the power supply voltage being powered on too fast.

[0009] The power-on reset circuit may also include a calibration module for outputting a calibration signal to adjust the voltage division ratio of the voltage division module to the intermediate voltage, and / or to adjust the magnitude of the intermediate voltage. When normal reset cannot be performed due to process deviation, the calibration module adjusts the voltage division ratio or the magnitude of the intermediate voltage. When the power supply voltage rises to a set level, the magnitude of the sampled voltage is consistent with a preset condition (reference voltage). Through comparison and conversion, a correct power-on reset signal is generated to improve the yield of the chip.

[0010] The operating voltage of the bandgap reference circuit can be the intermediate voltage, because the bandgap reference circuit does not need to work at a higher level power supply voltage, and the area of ​​the bandgap reference circuit can be smaller. At the same time, the operating voltages of the comparator and the bandgap reference circuit can both be the intermediate voltage, and the power-on speeds of the operating voltages of the comparator and the bandgap reference circuit are the same, which can avoid the inconsistency of the power-on speeds of the operating voltages of the comparator and the bandgap reference circuit, causing the comparator to fail to generate a correct comparison result, thereby avoiding the erroneous triggering of reset caused by the power-on speed of the power supply voltage being too fast.

[0011] The comparator may be a hysteresis comparator, and the hysteresis effect of the hysteresis comparator can prevent the comparison result from flipping back and forth due to power supply voltage jitter, thereby avoiding repeated resetting. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a reset signal provided by the present disclosure; Figure 2 A schematic diagram of the structure of the power-on reset circuit provided in the first embodiment of the present disclosure Figure 1 ; Figure 3 The structure of the voltage stabilizing module provided in the first embodiment of the present disclosure is shown in FIG. Figure 1 ; Figure 4 Schematic diagram of the relationship between the intermediate voltage and the power supply voltage provided in the second embodiment of the present disclosure Figure 1 ; Figure 5 Schematic diagram of the relationship between the intermediate voltage and the power supply voltage provided in the third embodiment of the present disclosure Figure 2 ; Figure 6 A schematic diagram of the structure of a bandgap reference circuit provided in Embodiment 1 of the present disclosure; Figure 7 A schematic diagram of the structure of a comparator provided in Embodiment 1 of the present disclosure; Figure 8 A characteristic diagram of a comparator provided in Embodiment 1 of the present disclosure; Fig. 9 A schematic diagram of the structure of a pulse generation module provided in Embodiment 1 of the present disclosure; Fig.10 A schematic diagram of the structure of a pulse generation module provided in Embodiment 4 of the present disclosure; Fig.11 A schematic diagram of the structure of the power-on reset circuit provided in the fifth embodiment of the present disclosure Figure 2 ; Fig.12 A schematic diagram of the structure of the voltage stabilizing module provided in the sixth embodiment of the present disclosure Figure 2 ; Fig.13 A schematic diagram of the structure of the voltage stabilizing module provided in the seventh embodiment of the present disclosure Figure 3 ; Fig.14 A schematic diagram of the structure of the power-on reset circuit provided in the eighth embodiment of the present disclosure Figure 3 ; Fig.15 The change of the sampling voltage provided in the ninth embodiment of the present disclosure is shown in FIG. Figure 1 ; Fig.16 The change of the sampling voltage provided in the eighth embodiment of the present disclosure is shown in FIG. Figure 2 ; Fig.17 A schematic diagram of the structure of the power-on reset circuit provided in the tenth embodiment of the present disclosure Figure 4 ; Fig.18 A schematic diagram of the structure of the power-on reset circuit provided in the eleventh embodiment of the present disclosure Figure 5 ; Fig.19 A schematic diagram of the structure of the power-on reset circuit provided in the twelfth embodiment of the present disclosure Figure 6 ; Fig. 20 A schematic diagram of the structure of the power-on reset circuit provided in the thirteenth embodiment of the present disclosure Figure 7 ; Fig.21 A schematic diagram of the structure of a calibration module provided in Embodiment 12 of the present disclosure; Fig. 22 This is a schematic diagram of the structure of the state machine provided in the twelfth embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0014] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0015] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0017] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0018] Figure 1 is a schematic diagram of an optional power-on reset signal. Figure 1 In FIG. 1 , POR1, POR2, and POR3 respectively illustrate the relationship between the pulse power-on reset signal at different times and the power-on time of the power supply voltage. It should be noted that: Figure 1 The power-on reset signal POR1 occurs when the power supply voltage VDD has not risen sufficiently. Due to the premature reset, the reset operation may fail and the stable startup of the system cannot be guaranteed. On the contrary, the power-on reset signal POR3 is reset too late, which prolongs the user's waiting time and reduces the system response efficiency. In contrast, the power-on reset signal POR2 can output the power-on reset signal when VDD rises to an appropriate level. However, in a wide voltage application scenario, the fluctuation of the power supply voltage VDD makes the triggering condition of the power-on reset signal POR2 complex and uncertain, thereby affecting the effectiveness of the power-on reset signal. Therefore, the purpose of this scheme is to design a power-on reset circuit, so that the power-on reset signal can be generated at the position of POR2 in a wide voltage scenario, without being too early or too late. Among them, the wide voltage scenario means that when the power supply voltage VDD is stable, its voltage value may have more than two kinds, and the voltage difference between different voltage values ​​is usually greater than 1V, or at least one voltage value is more than 150% of another voltage value.

[0019] Figure 2 1 is an optional structural diagram of a power-on reset circuit 100 provided in an embodiment of the present disclosure. The power-on reset circuit 100 can be applied to a chip equipped with a digital logic circuit or the like. The power-on reset circuit 100 is used to generate an internal power-on reset signal when the chip is powered on. The power-on reset signal can determine the initial state of the digital logic circuit or the like in the chip when it is powered on, thereby ensuring that all circuits in the chip that receive the reset signal start to operate from the determined initial state.

[0020] In the embodiments of the present disclosure, reference Figure 2The power-on reset circuit 100 may include a voltage stabilizing module 10, a voltage dividing module 20, a bandgap reference circuit 30, a comparator 40 and a pulse generating circuit 50. The voltage stabilizing module 10 is configured to receive a power supply voltage and convert different power supply voltages into a stable intermediate voltage.

[0021] The voltage dividing module 20 includes a first voltage dividing element 11 and a second voltage dividing element 12 connected in series to the output terminal A of the voltage stabilizing module 10. The first voltage dividing element 11 and the second voltage dividing element 12 are connected in series, the first end of the first voltage dividing element 11 is connected to the output terminal A of the voltage stabilizing module 10, the second end of the first voltage dividing element 11 is connected to the first end of the second voltage dividing element 12, and the second end of the second voltage dividing element 12 is grounded. The first voltage dividing element 11 and the second voltage dividing element 12 divide the intermediate voltage Vsupply. The connection node B of the first voltage dividing element 11 and the second voltage dividing element 12 outputs the sampling voltage Vdivide. In other words, the voltage dividing module 20 generates the sampling voltage Vdivide by dividing the intermediate voltage Vsupply generated by the voltage stabilizing module 10. In this way, regardless of the different voltage values ​​of the power supply voltage VDD, the different power-on speeds, or the fluctuations in the voltage value of the power supply voltage VDD, the sampling voltage Vdivide generated by the voltage dividing module 20 is a fixed and determined value, and the magnitude of the sampling voltage Vdivide can reflect whether the power supply voltage reaches the set level.

[0022] The bandgap reference circuit 30 is configured to output a reference voltage. For example, the bandgap reference circuit 30 can receive a power supply voltage VDD and convert it into a reference voltage V BG Among them, the reference voltage V BG As a reference voltage for comparison, it is used to determine whether the power supply voltage has reached the set level. BG The voltage value is equal to Vsupply1*R2 / (R1+R2), where Vsupply1 is the voltage value of the intermediate voltage when the power supply voltage reaches the set level, R1 is the voltage value of the first voltage divider element 11, and R2 is the voltage value of the second voltage divider element 12. When the power supply voltage reaches the set level, the sampling voltage Vdivide rises to Vsupply1*R2 / (R1+R2). At this time, the sampling voltage Vdivide is equal to the reference voltage V BG equal.

[0023] The comparator 40 receives and compares the reference voltage V BG and the sampling voltage Vdivide, and outputs the comparison result. For example, the voltage of the sampling voltage Vdivide is greater than or equal to the reference voltage V BG , the comparison result output by the comparator 40 is a high level. Otherwise, the voltage of the sampling voltage Vdivide is less than the reference voltage V BG, the comparison result of the comparator 40 is a low level. Because the magnitude of the sampling voltage Vdivide can reflect whether the power supply voltage has reached the set level, the comparison result can reflect whether the power supply voltage has reached the set level.

[0024] The pulse generating circuit 50 is connected to the output terminal of the comparator 40 and receives the comparison result output by the comparator 40. When the comparison result changes, the pulse generating circuit 50 generates a pulse power-on reset signal, thereby generating a power-on reset signal when the power supply voltage reaches a set level. In other words, the power-on reset circuit 100 generates a pulse signal as a power-on reset signal through the pulse generating circuit 50, and the pulse signal can be stably and continuously maintained for a period of time, providing sufficient reset time for the chip, thereby providing a more stable and lasting reset effect, and improving the stability and reliability of the chip operation.

[0025] It can be understood that the voltage stabilizing module 10 in the embodiment of the present disclosure can convert different power supply voltages VDD into a stable intermediate voltage Vsupply. No matter the setting level of the power supply voltage VDD is high (e.g., 5V) or the setting level of the power supply voltage VDD is low (e.g., 2V), when the power supply voltage VDD rises to the setting level, the level of the intermediate voltage Vsupply is fixed (e.g., 2V). The intermediate voltage changes with the power supply voltage, and the rising speed of the intermediate voltage follows the power-on speed of the power supply voltage. When the intermediate voltage reaches a fixed value, the power supply voltage rises to the setting level, so the intermediate voltage can reflect whether the power supply voltage rises to the setting level.

[0026] The sampling voltage obtained by the voltage dividing module 20 by dividing the intermediate voltage is a fixed value. Since the sampling voltage is obtained by dividing the intermediate voltage, the magnitude of the sampling voltage can reflect whether the power supply voltage has reached the set level. The comparator compares the reference voltage and the sampling voltage and outputs the comparison result. When the sampling voltage is greater than the reference voltage, it indicates whether the power supply voltage has reached the set level.

[0027] When the comparison result changes, the pulse generating circuit 50 generates a pulse power-on reset signal. The change in the comparison result indicates that the sampling voltage just exceeds the reference voltage, that is, the power supply voltage just rises to the set level, and the power-on reset signal generating the pulse is just triggered at this time. The power-on reset signal will not be triggered in advance when the power supply voltage does not reach the set level, nor will it be triggered after a long time after the power supply voltage reaches the set level.

[0028] In some embodiments, the voltage regulator module may be a low-dropout regulator (LDO). Figure 3is a schematic diagram of the structure of an optional low-voltage dropout linear regulator provided in an embodiment of the present disclosure. It should be noted that the voltage stabilizing module may also be other types of low-voltage dropout linear regulators, which are not limited here. Figure 3 Taking the low voltage dropout linear regulator shown in as an example, the working principle of the voltage regulator module is explained: In the embodiments of the present disclosure, reference Figure 3 , the voltage stabilizing module 10 may include a reference voltage source V REF , sampling resistor ( Figure 3 Medium R 11 and R 12 ), error amplifier EA, power transistor M 11 , resistor R L and capacitor C 11 Among them, the reference voltage source V REF Can provide a stable reference voltage Vref, the inverting input terminal of the error amplifier EA is connected to the reference voltage source V REF The output of the error amplifier EA is connected to the power transistor M 11 The control terminal of the power transistor M 11 The first end is connected to the power supply voltage VDD, the sampling resistor R 11 and R 12 In series with the power transistor M 11 Between the second end (that is, output terminal A) and ground, R 11 and R 12 The middle node connected is at the non-inverting input terminal + of the error amplifier EA. The sampling resistor R 11 and R 12 It is used to monitor the intermediate voltage Vsupply of the output terminal A, and to convert the intermediate voltage Vsupply of the output into the feedback voltage V FB The resistor R is fed back to the non-inverting input terminal + of the error amplifier EA to form a closed-loop control. L and capacitor C 11 It is used to enhance the stability of the low voltage drop linear regulator. In some embodiments, the low voltage drop linear regulator may not be provided with a resistor R L and capacitor C 11 The error amplifier EA converts the feedback voltage V FB Compare with the reference voltage Vref to generate an error signal V EA , error signal V EA Reflects the feedback voltage V FB The difference between the reference voltage Vref and the power transistor M 11 According to the error signal V EA The size of the regulator adjusts the current inside it, thereby controlling the intermediate voltage Vsupply output by the output terminal A.

[0029] In the embodiments of the present disclosure, reference Figure 3 When the input power supply voltage VDD increases or decreases, the low voltage drop linear regulator included in the voltage regulator module will adjust its power transistor M 11 The on-resistance of the output is used to maintain the stability of the output intermediate voltage Vsupply. For example, when the power supply voltage VDD increases, the error signal V EA When the power supply voltage VDD decreases, the current of the power transistor M11 decreases, causing the output intermediate voltage Vsupply to decrease. On the contrary, when the power supply voltage VDD decreases, the error signal V EA The current of the power transistor M11 increases, resulting in an increase in the output intermediate voltage Vsupply. In other words, the voltage value of the power supply voltage VDD fluctuates, and the voltage stabilizing module can also convert the power supply voltage VDD into a stable intermediate voltage Vsupply.

[0030] In the embodiments of the present disclosure, reference Figure 3 The voltage stabilizing module is configured to convert different power supply voltages VDD into a stable intermediate voltage Vsupply. When the setting voltage of the power supply voltage VDD is different, the stable intermediate voltage Vsupply can be output.

[0031] Figure 4 and Figure 5 Schematic diagram of the relationship between the intermediate voltage and the power supply voltage provided by the embodiment of the present disclosure. Figure 2 The voltage regulator module 10 receives Figure 4 and Figure 5 When the power supply voltage VDD1 corresponding to the middle line L1 is, the voltage variation of the intermediate voltage Vsupply output by the voltage stabilizing module 10 is as follows: Figure 4 and Figure 5 When the voltage regulator module 10 receives Figure 4 When the power supply voltage VDD2 corresponds to the line L3 shown in FIG. 1 , the voltage variation of the intermediate voltage Vsupply output by the voltage stabilizing module 10 is as follows: Figure 4 When the voltage regulator module 10 receives Figure 5 When the power supply voltage VDD3 corresponding to L5 is shown, the voltage change of the intermediate voltage Vsupply output by the voltage stabilizing module 10 is as follows: Figure 5 Line L6. Figure 4 Take line L1 in the figure as an example. At the start time, the voltage value corresponding to the power supply voltage is 0. After a period of time, the power supply voltage stabilizes at VDD1 (for example, 5V). The time between the power supply voltage changing from 0V to VDD1 is the power-on time, and the slope of line L1 between the power supply voltage changing from 0V to VDD1 represents the power-on speed.

[0032] Figure 4 and Figure 5The voltage value of the power supply voltage VDD1 corresponding to the line L1 shown is greater than Figure 4 The power supply voltage VDD2 of L2 and Figure 5 The power supply voltage VDD3 of L5 in the embodiment. The power supply voltage VDD1 may be 5V, and the power supply voltage VDD2 and the power supply voltage VDD3 may be 2V. Figure 4 and Figure 5 The power-on speed of L1 corresponding to the power supply voltage VDD1 is shown, and Figure 5 The power-on speed of the power supply voltage VDD3 corresponding to line L5 in the figure is greater than Figure 4 The power-on speed of the power supply voltage VDD2 of line L2 in FIG. And, Figure 4 and Figure 5 The lines L2, Figure 4 The line L4, Figure 5 The intermediate voltage Vsupply of the line L6 shown in the figure maintains the same voltage value after stabilization. That is to say, when the voltage value and the power-on speed of the power supply voltage VDD are different, the voltage stabilization module 10 can convert the power supply voltage VDD into a stable intermediate voltage Vsupply.

[0033] Figure 6 FIG. 1 is a schematic diagram of a structure of an optional bandgap reference circuit provided in an embodiment of the present disclosure. It should be noted that the bandgap reference circuit may also have other structures, which are not limited here. Figure 6 Taking the bandgap reference circuit shown in as an example, the working principle of the bandgap reference circuit is explained: In the embodiments of the present disclosure, reference Figure 6 , the high gain amplifier OPA ensures that the currents flowing through R23 and R24 are equal. The emitter area ratio of the two transistors Q1 and Q2 in the bandgap reference circuit 30 is 1:N. Due to the difference in emitter area, there is a voltage difference between the base-emitter voltages (VBE1 and VBE2) of the two transistors Q1 and Q2. The current IPTAT passing through resistors R21 and R22 is generated based on the voltage difference between the transistors Q1 and Q2. The current IPTAT has a positive temperature coefficient, and the current IPTAT is injected into the resistor R22 to generate a voltage with a positive temperature coefficient. This voltage with a positive temperature coefficient is added to the base-emitter voltage VBE1 of the transistor Q1. VBE1 has a negative temperature coefficient, so the temperature coefficients of the two items can be offset by adjusting the ratio of resistors R22 to R21 to generate a stable reference voltage V BG .

[0034] In some embodiments, the comparator may be a hysteresis comparator. The hysteresis comparator has a hysteresis characteristic, which can effectively prevent false triggering problems caused by signal noise or voltage fluctuations. Figure 7is a schematic diagram of the structure of an optional hysteresis comparator provided in an embodiment of the present disclosure. The comparator may also have other structures, which are not limited here. Figure 7 Taking the hysteresis comparator shown in FIG. 1 as an example, the working principle of the comparator is explained as follows: In the embodiments of the present disclosure, reference Figure 7 The hysteresis effect produced by the hysteresis comparator is achieved by setting the gate width-to-length ratio of transistors M23 and M25, M24 and M26, and using the current mirror principle. Transistors M23 and M25 can adjust the high threshold of the hysteresis comparator, and transistors M24 and M26 can adjust the low threshold of the hysteresis comparator. Transistor M27 forms a current mirror with transistors M23 and M25. Transistor M29 forms a current mirror with transistors M24 and M26. Transistor M28 forms a current mirror with transistor M210. Transistor M211 provides bias current Ibias to transistors M23, M24, M25 and M26 based on the control of bias signal Vb. Transistors M21 and M22 are used to receive sampling voltage Vdivide and reference voltage VBG, respectively.

[0035] For example, when the sampling voltage Vdivide is much lower than the reference voltage V BG , and the logic value of the comparison result is 1, transistors M24 and M26 are in the off state, and the bias current Ibias flows through transistors M25 and M23. When the sampling voltage Vdivide gradually increases to the reference voltage V BG When the potential of the comparison result is switched from 1 to 0, the bias current Ibias flows through the transistors M24 and M26 until the sampling voltage Vdivide is equal to the lower threshold voltage.

[0036] Figure 8 is a schematic diagram of a comparison result of an optional hysteresis comparator provided in an embodiment of the present disclosure. It should be noted that the hysteresis comparator compares the voltage V TH Two comparison limit voltages are divided around, namely the comparison voltage high limit (upper threshold V H ) and compare voltage lower limit (lower threshold V L ). Comparison voltage V TH Can be the reference voltage V BG , reference voltage V BG Then the corresponding upper threshold V H and lower threshold V L .

[0037] In the embodiments of the present disclosure, reference Figure 7 and Figure 8 , when the sampling voltage Vdivide reaches the upper limit V H When the sampling voltage Vdivide drops to the upper limit VH When the sampling voltage Vdivide drops to the lower threshold V L When the sampling voltage Vdivide increases again and reaches the lower threshold V L When the sampling voltage Vdivide rises to the upper threshold V H The comparison result of the output is high level. In this way, the input voltage must be higher than V H To make the output signal flip from low to high, the input voltage must be lower than V L Instead of V H That is to say, the comparator 40 can keep the output state unchanged within an input voltage range until the sampling voltage Vdivide exceeds this range, thereby generating a pulse signal with hysteresis characteristics. Thus, it is prevented that the input voltage fluctuates around VH, causing the level of the output result to flip back and forth.

[0038] Fig. 9 is a schematic diagram of the structure of an optional pulse generating circuit 50 provided in an embodiment of the present disclosure, with reference to Fig. 9 The pulse generating circuit 50 includes a first trigger 51, a second trigger 52, a delay resistor R delay , delay capacitor C delay And XOR gate XOR. Wherein, the input end of the first trigger 51 is connected to the output end of the comparator 40, and the output end of the first trigger 51 is connected to the first input end of the XOR gate XOR. Delay resistor R delay The first end of the delay resistor R delay The second end of the delay capacitor C delay The first end of the delay capacitor C delay The second end of the second trigger 52 is connected to the delay resistor R delay The output end of the second trigger 52 is connected to the second input end of the XOR gate XOR. The output end of the XOR gate XOR outputs a power-on reset signal. The first trigger 51 and the second trigger 52 can be Schmitt triggers.

[0039] In the embodiments of the present disclosure, reference Fig. 9 The first trigger 51 and the second trigger 52 are used to receive the comparison result output by the comparator 40 and convert it into a stable logic level signal, thereby preventing the jitter caused by the ripple on the intermediate voltage Vsupply. delay and the delay capacitor C delayThe RC delay circuit is used to delay the comparison result output by the comparator 40 to generate an appropriate signal change time. The XOR gate receives the output signal of the first trigger 51 and the second trigger 52. When the two states are different (for example, one is high level and the other is low level), the XOR gate outputs a pulse signal as a power-on reset signal. Therefore, the pulse signal can be kept stable and continuously for a period of time, providing sufficient reset time for the chip and improving the stability and reliability of the chip operation.

[0040] Fig.10 is a schematic diagram of an optional pulse generating circuit 50 provided in an embodiment of the present disclosure, with reference to Fig.10 The pulse generating circuit 50 includes an inverter INV, an XOR gate XOR, a delay resistor R delay , delay capacitor C delay and a third trigger 53. The first end of the inverter INV is connected to the first input end of the comparator 40 and the XOR gate XOR respectively. The second end of the inverter INV is connected to the delay resistor R delay The first end of the delay resistor R delay The second end of the delay capacitor C delay The first end of the delay capacitor C delay The second end of the third trigger 53 is connected to the delay resistor R delay The second end of the third trigger 53 is connected to the second output end of the XOR gate XOR. The third trigger 53 can be a Schmitt trigger.

[0041] In the embodiments of the present disclosure, reference Fig.10 , the inverter INV performs a logical inversion on the comparison result output by the comparator 40, and inputs it to an input terminal of the XOR gate XOR and an RC delay circuit. The RC delay circuit performs a time delay on the signal output by the inverter to generate a slightly delayed signal. The third trigger 53 receives the delayed signal and outputs it to the other input terminal of the XOR gate XOR. The XOR gate XOR compares the signal directly output by the inverter INV with the delayed signal output by the third trigger 53. When the two states are different (for example, one is a high level and the other is a low level), the XOR gate XOR outputs a pulse signal as a power-on reset signal. Thus, the pulse signal can be stably and continuously maintained for a period of time, providing sufficient reset time for the chip, and improving the stability and reliability of the chip operation.

[0042] Fig.11 Schematic diagram of an optional power-on reset circuit 100 provided in an embodiment of the present disclosure.

[0043] In some embodiments of the present disclosure, reference Fig.11The voltage stabilizing module 10 includes at least one unidirectional conduction unit 110, a first resistor R4 and a transistor M1. The transistor M1 may be a PMOS tube. The first end of the first resistor R4 receives the power supply voltage VDD, and the second end of the first resistor R4 is grounded through at least one unidirectional conduction unit 110. The transistor M1 includes a first end, a second end and a control end, the first end receives the power supply voltage VDD, the second end outputs the intermediate voltage Vsupply, and the control end is connected to the second end of the first resistor R4.

[0044] In the embodiments of the present disclosure, reference Fig.11 , the first resistor R4 is connected in series between the power supply voltage VDD and the ground, and is used to divide the voltage and generate a control voltage (the gate voltage of the transistor M1). The unidirectional conduction unit 110 is connected in series with the first resistor R4 and is grounded to ensure that the current can only flow in one direction. The unidirectional conduction unit 110 has a stable voltage drop, which helps to stabilize the control voltage. The first end of the transistor M1 receives the power supply voltage VDD. The control end of the transistor M1 is connected to the second end of the first resistor R4 to receive the control voltage. The voltage stabilizing module 10 adjusts the conduction degree of the transistor M1, and the second end of the transistor M1 can stably output the intermediate voltage Vsupply. Among them, the voltage value of the intermediate voltage Vsupply is equal to the voltage drop of the unidirectional conduction unit 110 minus V GD , V GD is the voltage difference between the gate and drain of transistor M1. GD The voltage is controlled by the current of transistor M1, and the current of transistor M1 is related to the voltage value of VDD, the resistance value of R4, and the resistance value of R3. When VDD is powered on, transistor M1 is turned on, the current of transistor M1 is fixed, and the voltage drop of the unidirectional conduction unit 110 is fixed, so the voltage value of the intermediate voltage Vsupply is fixed.

[0045] That is to say, the voltage stabilizing module 10 uses the voltage drop of the unidirectional conduction unit 110, the resistance value of R4, and the resistance value of R3 to control the current of the transistor M1, and then the drain of the transistor M1 outputs a stable intermediate voltage Vsupply. The voltage rise time of the intermediate voltage Vsupply is closely related to the voltage rise time of the power supply voltage VDD, that is, when the power supply voltage VDD rises, the intermediate voltage Vsupply also rises proportionally. For example, when the power supply voltage VDD is 5V, the intermediate voltage Vsupply is 2V, and both rise from 0V to their respective set levels at the same time at T1. When the power supply voltage VDD is 2V, the intermediate voltage Vsupply is still 2V, and both also complete the voltage rise at T2. Therefore, compared with the traditional low voltage difference linear regulator, the embodiment of the present disclosure reduces the area of ​​the voltage stabilizing module 10 and reduces the power consumption of the voltage stabilizing module 10.

[0046] exist Fig.11In the figure, the first voltage dividing element includes a second resistor R1, the second voltage dividing element includes a third resistor R2, the voltage dividing module 20 includes a second resistor R1 and a third resistor R2 connected in series, the intermediate voltage can be divided by the second resistor R1 and the third resistor R2, and the connection node B between the second resistor R1 and the third resistor outputs the sampling voltage.

[0047] Fig.12 1 is a schematic diagram of the structure of an optional unidirectional conduction unit 110 provided in an embodiment of the present disclosure, and at least one unidirectional conduction unit 110 includes a plurality of diodes D1 to Dn connected in series. The cathode of each diode is connected to the anode of the next diode, and the plurality of diodes D1 to Dn are connected in series. For example, the cathode of diode D1 is connected to the anode of the next diode D2. Each diode has a fixed voltage drop, and the overall voltage drop of the unidirectional conduction unit 110 is adjusted by adjusting the number of diodes. In this way, the voltage stabilizing module 10 uses the voltage drop of the plurality of diodes D1 to Dn to control the voltage difference between the gate and the drain of the transistor M1, so that the drain of the transistor M1 outputs a stable intermediate voltage Vsupply. Thus, the area of ​​the voltage stabilizing module 10 is reduced, and the power consumption of the voltage stabilizing module 10 is reduced.

[0048] Fig.13 It is a structural schematic diagram of another optional unidirectional conduction unit 110 provided in an embodiment of the present disclosure, and at least one unidirectional conduction unit 110 includes multiple transistors M31 to M3n. After the transistors are connected in the form of diodes, multiple transistors M31 to M3n are connected in series. For example, when the base (or gate) and the collector (or drain) of the transistor are short-circuited, it is equivalent to a diode with unidirectional conductivity and a fixed voltage drop. The emitter (or source) of the first transistor M31 is connected to the power supply voltage VDD, and then the base (or gate) and the collector (or drain) of the first transistor M31 are short-circuited, and the short-circuited endpoints are connected to the emitter (or source) of the second transistor M32. Similarly, the base (or gate) and the collector (or drain) of the subsequent transistors M32 to M3n are short-circuited and connected in series. In this way, the voltage stabilizing module 10 uses the voltage drops of the multiple transistors M31 to M3n to control the voltage difference between the gate and the drain of the transistor M1, so that the drain of the transistor M1 outputs a stable intermediate voltage Vsupply. Thus, the area of ​​the voltage stabilizing module 10 is reduced, and the power consumption of the voltage stabilizing module 10 is reduced.

[0049] Fig.14 It is a schematic structural diagram of another optional power-on reset circuit 100 provided in an embodiment of the present disclosure.

[0050] In some embodiments of the present disclosure, reference Fig.14The power-on reset circuit 100 may further include a capacitor C1. The capacitor C1 is connected between the connection node B and the ground, and is used to delay the power-on time of the sampling voltage.

[0051] To illustrate the effect of capacitor C1, refer to Fig.15 and Fig.16 . Fig.15 and Fig.16 is a schematic diagram of the optional sampling voltage change provided by the embodiment of the present disclosure. It should be noted that: Fig.15 The sampling voltage Vdivide shown in L8 is powered on faster than the reference voltage V shown in L7. BG The power-on speed is slow, the sampling voltage Vdivide and the reference voltage V BG Input comparator will produce voltage overshoot process; when the reference voltage V BG When the sampling voltage Vdivide is greater than the reference voltage V BG When the comparison result output by the comparator is valid, it will trigger the pulse production circuit to generate a power-on reset signal; thus, a correct comparison result will be generated. Fig.16 The power-on time of the sample voltage Vdivide shown in L9 is shorter than that of the reference voltage V BG The power-on speed is fast, and the sampling voltage Vdivide is always greater than the reference voltage V BG When the voltage exceeds the limit, there is no voltage overrun process, and thus, the correct comparison result will not be generated, and the comparison result will not change, so the power-on reset signal cannot be triggered.

[0052] Therefore, when the power supply voltage VDD is powered on too fast, the sampling voltage Vdivide may show Fig.16 The voltage shown by L9 in the figure will not generate a correct comparison result. When the capacitor C1 is connected between the node A and the ground, the voltage change of the sampling voltage Vdivide can be slowed down by charging and discharging the capacitor C1. Fig.16 In the manner shown by L10, the power-on time of the sampling voltage Vdivide is delayed. In this way, when the power-on speed of the power supply voltage VDD is too fast, the capacitor C1 can slow down the rising speed of the sampling voltage Vdivide, thereby avoiding the false triggering reset caused by the power-on speed of the power supply voltage VDD being too fast.

[0053] Fig.17It is a structural schematic diagram of an optional power-on reset circuit 100 provided in an embodiment of the present disclosure, the power supply end of the comparator 40 is connected to the output end of the voltage regulator module 10, the operating voltage of the comparator 40 is the intermediate voltage Vsupply, the power supply end of the bandgap reference circuit 30 is connected to the power supply voltage VDD, and the operating voltage of the bandgap reference circuit 30 is the power supply voltage VDD. Fig.18 1 is a schematic diagram of an optional power-on reset circuit 100 provided in an embodiment of the present disclosure. Fig.18 , the power supply end of the comparator 40 and the power supply end of the bandgap reference circuit 30 are both connected to the output end of the voltage stabilizing module 10, the operating voltage of the comparator 40 is the intermediate voltage Vsupply, and the operating voltage of the bandgap reference circuit 30 is the intermediate voltage Vsupply. In this way, the operating voltages of the comparator 40 and the bandgap reference circuit 30 can both be the intermediate voltage Vsupply. The power-on speeds of the operating voltages of the comparator 40 and the bandgap reference circuit 30 are the same, which can avoid the inconsistency of the power-on speeds of the operating voltages of the comparator 40 and the bandgap reference circuit 30, causing the comparator 40 to fail to generate a correct comparison result. Thus, the erroneous triggering reset caused by the power-on speed of the power supply voltage VDD being too fast is avoided. At the same time, the bandgap reference circuit 30 does not need to work under a power supply voltage VDD with a higher level, and the area of ​​the bandgap reference circuit can be smaller.

[0054] Fig.19 It is a schematic structural diagram of an optional power-on reset circuit provided in an embodiment of the present disclosure.

[0055] In some embodiments of the present disclosure, reference Fig.19 The power-on reset circuit 100 may further include a calibration module 60, the calibration module 60 is connected to the voltage divider module 20, the first voltage divider element includes a second resistor R1. The second voltage divider element includes a third resistor R2. The calibration module 60 stores calibration data internally, and the calibration module 60 is used to output a first calibration signal based on the stored calibration data to adjust the voltage divider ratio of the intermediate voltage by the voltage divider module 20 so that Vsupply1=V BG *(R1+R2) / R2, where Vsupply1 is the voltage value of the intermediate voltage when the power supply voltage reaches the set level, V BG In this embodiment, the calibration data may reflect the target resistance values ​​of the second resistor R1 and the third resistor R2. For example, the calibration data may be a control signal for adjusting the resistance values ​​of the second resistor R1 and the third resistor R2.

[0056] In the embodiments of the present disclosure, reference Fig.19 , the voltage value of the sampling voltage Vdivide is equal to Vsupply*R2 / (R1+R2). The comparator 40 compares the reference voltage V BGand the sampling voltage Vdivide to determine whether to trigger the discharge reset signal. BG If the sampling voltage Vdivide exceeds the reference voltage V BG For example, the voltage divider module 20 increases the resistance of the second resistor R1 to increase the sampling voltage Vdivide, and the sampling voltage Vdivide can exceed the reference voltage V at an appropriate time. BG , and then, the comparator 40 will output the correct comparison result. BG The sampling voltage Vdivide exceeds the reference voltage V BG , the sampling voltage Vdivide can be reduced by increasing the resistance of the third resistor R2, so that the sampling voltage Vdivide exceeds the reference voltage V later. BG , and then, the comparator 40 will output a correct comparison result.

[0057] In order to make the comparator 40 output a correct comparison result, the first calibration signal output by the calibration module 60 is used to adjust the resistance value of the second resistor R1 and / or the third resistor R2 so that Vsupply1= V BG *(R1+R2) / R2, where Vsupply1 is the voltage value of the intermediate voltage when the power supply voltage reaches the set level. Thus, when the power supply voltage reaches the set level, the sampling voltage Vdivide can rise to the reference voltage V BG , the comparator 40 will output a correct comparison result.

[0058] In the embodiments of the present disclosure, reference Fig.19 The second resistor R1 is an adjustable resistor and may include R1 trim0 To R1 trimn For example, resistor R1 trim0 The reference resistor, resistor R1 trim1 To R1 trimn For adjusting resistance. Resistor R1 trim1 To R1 trimn Both with reference resistor R1 trim0 The first switches S11 to S1n are respectively connected to the corresponding resistors R1 trim1 To R1 trimn The first switches S11 to S1n are used to control the resistor R1 trim1 To R1 trimn The connection and disconnection control the resistance value of the second resistor R1.

[0059] In the embodiments of the present disclosure, reference Fig.19 The third resistor R2 is an adjustable resistor and may include R2 trim0 To R2 trimnFor example, R2 trim0 is the reference resistor, resistor R2 trim1 To R2 trimn For adjusting resistance. Resistor R2 trim1 To R2 trimn Both with reference resistor R2 trim0 The second switches S21 to S2n are respectively connected to the corresponding resistors R2 trim1 To R2 trimn The second switches S21 to S2n are used to control the resistor R2 trim1 To R2 trimn The connection and disconnection of the third resistor R2 are controlled.

[0060] In the embodiments of the present disclosure, reference Fig.19 , the second resistor R1 and / or the third resistor R2 are adjustable resistors, and the resistance of the second resistor R1 and / or the third resistor R2 is adjusted based on the first calibration signal. For example, each bit of the first calibration signal can be used to control one of the first switches S11 to S1n, and the resistance of the second resistor R1 can be adjusted by controlling the opening or closing of the first switch. Alternatively, each bit of the first calibration signal can be used to control one of the second switches S21 to S2n, and the resistance of the third resistor R2 can be adjusted by controlling the opening or closing of the second switch. In this solution, the calibration data is a control signal of the first switch S11 to S1n and / or the second switch S21 to S2n, which is used to control the opening or closing of the first switch S11 to S1n and / or the second switch S21 to S2n, so that the calibration module 60 can adjust the voltage division ratio of the sampling voltage Vdivide and the intermediate voltage Vsupply by adjusting the resistance of the second resistor R1 and / or the third resistor R2, so that the sampling voltage Vdivide can be consistent with the preset conditions and generate a correct power-on reset signal.

[0061] Fig. 20 It is a schematic diagram of the structure of an optional power-on reset circuit provided in an embodiment of the present disclosure.

[0062] In some embodiments of the present disclosure, reference Fig. 20, the power-on reset circuit 100 may further include a calibration module 60. The calibration module 60 is used to output a second calibration signal, and the calibration module 60 is connected to the voltage stabilizing module 10, and the voltage stabilizing module 10 includes at least a fourth resistor R3. The calibration module 60 is based on the internally stored calibration data, and the output second calibration signal is used to adjust the voltage value of Vsupply1 so that the voltage value of the reference voltage VBG is equal to Vsupply1*R2 / (R1+R2), wherein Vsupply1 is the voltage value of the intermediate voltage when the power supply voltage reaches the set level. Thus, when the power supply voltage reaches the set level, the sampling voltage Vdivide can rise to the reference voltage VBG, and the comparator 40 will output a correct comparison result. In this embodiment, the calibration data may reflect the target resistance value of the fourth resistor R3, for example, the calibration data may be a control signal for adjusting the resistance value of the fourth resistor R3.

[0063] In some embodiments, reference Fig. 20 The voltage stabilizing module 10 at least includes a fourth resistor R3, and the voltage value of Vsupply1 can be adjusted by adjusting the resistance value of the fourth resistor R3. The fourth resistor R3 is an adjustable resistor, which can include R3 trim0 To R3 trimn For example, resistor R3 trim0 The reference resistor is R3. trim1 To R3 trimn For adjusting resistance. Resistor R3 trim1 To R3 trimn Both with reference resistor R3 trim0 The third switches S31 to S3n are respectively connected to the corresponding resistors R3 trim1 To R3 trimn The third switches S31 to S3n are used to control the resistor R3 trim1 To R3 trimn The connection and disconnection of the fourth resistor R3 are controlled.

[0064] In the embodiments of the present disclosure, reference Fig. 20 , the power-on reset circuit 100 may further include a calibration module 60. The resistance of the fourth resistor R3 is adjusted based on the second calibration signal. Each bit of the second calibration signal can be used to control one of the third switches S31 to S3n to adjust the resistance of the fourth resistor R3. In this solution, the calibration data is a control signal of the third switches S31 to S3n, which is used to control the opening or closing of the third switches S31 to S3n, so that the calibration module 60 can adjust the size of the intermediate voltage Vsupply by adjusting the resistance of the fourth resistor R3, so that the sampling voltage Vdivide can be consistent with the preset condition and generate a correct power-on reset signal.

[0065] Fig.21is a schematic diagram of the structure of an optional calibration module 60 provided in an embodiment of the present disclosure, where the calibration module 60 is used to provide a suitable first calibration signal and / or second calibration signal.

[0066] In some embodiments of the present disclosure, reference Fig.21 The calibration module 60 includes an electronic fuse 61, a control module 62, a shift register 63 and a check module 64. The shift register 63 is configured to receive input data and burn data from the outside. The check module 64 connects the shift register 63 and the electronic fuse 61, and is used to select one of the shift register 63 and the electronic fuse 61 for output, and output the calibration data to the voltage divider module and / or the voltage regulator module. Among them, the intermediate voltage Vsupply can power various parts in the calibration module 60. The steps of the calibration module 60 obtaining the calibration data and outputting the first calibration signal and the second calibration signal are as follows: Before the chip leaves the factory: The check module 64 selects the shift register 63 as the output, and the shift register 63 sequentially outputs calibration data (such as calibration code) for debugging to the check module 64. In some embodiments, the calibration data may be a control signal for controlling the first switches S11 to S1n, the second switches S21 to S2n, and / or the third switches S31 to S3n; The check module 64 outputs calibration data in sequence, and the calibration data is output to the voltage divider module and / or the voltage stabilization module to adjust the resistance values ​​of the second resistor R1, the third resistor R2 and / or the fourth resistor R3; At each calibration data, the power-on reset circuit 100 performs a power-on test to test whether the power-on reset signal is triggered when the power supply voltage just reaches the set level; If yes, the calibration data is the target calibration data, which is used as the burning data to be written into the electronic fuse 61. The first control information and the calibration data can be input into the shift register 63 through the host computer; After the control module 62 identifies the first control information, it burns the calibration data into the electronic fuse 61 .

[0067] After the chip leaves the factory: The check module 64 selects the electronic fuse 61 as the output, and the electronic fuse 61 outputs the programming data to the check module 64; The check module 64 outputs the burning data as the target calibration data. In some embodiments, the burning data may include a first calibration signal and / or a second calibration signal, which are control signals for controlling the first switches S11 to S1n, the second switches S21 to S2n and / or the third switches S31 to S3n to adjust the resistance values ​​of the second resistor R1, the third resistor R2 and / or the fourth resistor R3, so that the power-on reset signal is triggered when the power supply voltage just reaches the set level.

[0068] The following is a detailed description of the various components and working principles of the calibration module 60.

[0069] In the embodiments of the present disclosure, reference Fig.21 , the control module 62 is connected to the shift register 63 and the electronic fuse 61 respectively, and is configured to write the burning data into the electronic fuse 61. The power-on reset circuit 100 can use the control module 62 to burn the burning data in the shift register 63 to the electronic fuse 61, that is, the control module 62 configures the electronic fuse 61. For example, the control module 62 can receive the burning data from the shift register 63, and the burning data may include the first calibration signal and the second calibration signal in the above embodiment. The burning data may come from a host computer outside the chip. The electronic fuse 61 may include a plurality of electronic fuses, each of which may store one data bit of data. The control module 62 may burn all the data bits of the burning data into the electronic fuse corresponding to the electronic fuse 61 for storage.

[0070] In the embodiments of the present disclosure, reference Fig.21 The shift register 63 can be used to transmit and temporarily store external first control information and programming data. The first control information and programming data can be used to configure the electronic fuse 61.

[0071] In the embodiments of the present disclosure, reference Fig.21 The control module 62 may also include a state machine. The state machine may be a Moore state machine or a Mealy state machine. For example, Fig. 22 As shown, the state of the state machine may include a writing state, a reading state and a serial control state. The writing state is a state in which the state machine controls the electronic fuse 61 to be written, the reading state is a state in which the state machine controls the electronic fuse 61 to be read, and the serial control state is a state in which the state machine controls the shift register 63 to perform serial input / output.

[0072] In the embodiments of the present disclosure, reference Fig.21 , the state machine in the control module 62 is connected to the shift register 63 and the electronic fuse 61 respectively. The state machine in the control module 62 is configured to burn data. For example, the state machine in the control module 62 can call the first control information and the burning data received by the shift register 63, or the shift register 63 can send the temporarily stored first control information and the burning data to the state machine in the control module 62. The first control information can be a control instruction for controlling the state of the state machine in the control module 62. The first control information can be encoded in a sequential encoding (Sequential), Gray encoding (Gray) or a one hot encoding (One hot).

[0073] The state machine in the control module 62 can write the programming data into the electronic fuse 61 based on the first control information. Fig.21 The state machine in the control module 62 can directly obtain the control instruction (first control information) of the shift register 63, generate a corresponding waveform, and control the electronic fuse 61 to perform a burning operation.

[0074] In the embodiments of the present disclosure, reference Fig.21 In chip testing, if the intermediate voltage Vsupply does not reach the normal operating voltage, it may cause the reset failure of the logic digital circuit and other circuits. At this time, the reset failure problem can be solved by calibrating the resistors and other components in the voltage divider module 20 or the resistors and other components in the voltage regulator module that control the intermediate voltage Vsupply.

[0075] In this way, the calibration module 60 outputs a calibration signal to adjust the voltage division ratio between the sampling voltage and the intermediate voltage, and / or to adjust the magnitude of the intermediate voltage. When a normal reset cannot be performed due to process deviation, the calibration module 60 can adjust the magnitude of the sampling voltage when the power supply voltage rises to a set level by adjusting the voltage division ratio or the magnitude of the intermediate voltage, so that the sampling voltage can be consistent with the preset conditions, and a correct power-on reset signal is generated through comparison and conversion, thereby improving the yield of the chip.

[0076] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0077] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A power-on reset circuit, characterized in that: include: A voltage stabilization module, configured to receive a power supply voltage and convert different power supply voltages into a stable intermediate voltage; A voltage dividing module, comprising a first voltage dividing element and a second voltage dividing element connected in series at an output end of the voltage stabilizing module, wherein the first voltage dividing element and the second voltage dividing element divide the intermediate voltage, and a connection node between the first voltage dividing element and the second voltage dividing element outputs a sampling voltage; a bandgap reference circuit configured to output a reference voltage; A comparator receives and compares the reference voltage and the sampled voltage, and outputs a comparison result; The pulse generating circuit generates a pulse power-on reset signal when the comparison result changes.

2. The power-on reset circuit according to claim 1, characterized in that: Also includes: Capacitor; the capacitor is connected between the connection node and ground.

3. The power-on reset circuit according to claim 1, characterized in that: The voltage stabilizing module comprises: at least one unidirectional conducting unit, a first resistor and a transistor; wherein, A first end of the first resistor receives the power supply voltage, and a second end of the first resistor is grounded through the at least one unidirectional conductive unit; The transistor includes a first terminal, a second terminal and a control terminal, the first terminal receives the power supply voltage, the second terminal outputs the intermediate voltage, and the control terminal is connected to the second terminal of the first resistor.

4. The power-on reset circuit according to claim 3, characterized in that: The at least one unidirectional conductive unit includes a plurality of diodes connected in series; or, the at least one unidirectional conductive unit includes a plurality of transistors, and after the transistors are connected in the form of diodes, the plurality of transistors are connected in series.

5. The power-on reset circuit according to claim 1, characterized in that: The voltage stabilizing module is a low voltage drop linear regulator.

6. The power-on reset circuit according to claim 1, characterized in that: Also includes: a calibration module, connected to the voltage dividing module, and configured to output a first calibration signal based on internally stored calibration data, so as to adjust a voltage dividing ratio of the intermediate voltage by the voltage dividing module; The first voltage-dividing element includes a second resistor, and the second voltage-dividing element includes a third resistor; the second resistor and / or the third resistor is an adjustable resistor, and the resistance value of the adjustable resistor is adjusted based on the first calibration signal.

7. The power-on reset circuit according to claim 1, characterized in that: Also includes: A calibration module, connected to the voltage stabilization module, configured to output a second calibration signal based on internally stored calibration data to adjust the magnitude of the intermediate voltage; The voltage stabilizing module at least includes a fourth resistor, the fourth resistor is an adjustable resistor, and the resistance of the adjustable resistor is adjusted based on the second calibration signal.

8. The power-on reset circuit according to claim 6 or 7, characterized in that: The adjustable resistor comprises: Reference resistor; A plurality of first switches and a plurality of regulating resistors, wherein the first switches are connected in series with the corresponding regulating resistors and then connected in parallel with the reference resistor; or the first switches are connected in parallel with the corresponding regulating resistors and then connected in series with the reference resistor.

9. The power-on reset circuit according to claim 6 or 7, characterized in that: The calibration module includes: an electronic fuse, a control module, a shift register and a check module; wherein, The shift register is configured to receive input data and programming data from the outside; The control module is connected to the shift register and the electronic fuse respectively, and is configured to write the programming data into the electronic fuse; The check module is connected to the shift register and the electronic fuse respectively, and is configured to select to transmit the input data received by the shift register or the programming data in the electronic fuse to the adjustable resistor based on whether the chip is powered on.

10. The power-on reset circuit according to claim 1, characterized in that: The operating voltage of the comparator is the intermediate voltage; and / or the operating voltage of the bandgap reference circuit is the intermediate voltage or the power supply voltage.

11. The power-on reset circuit according to claim 1, characterized in that: The comparator is a hysteresis comparator.

12. The power-on reset circuit according to claim 1, characterized in that: The pulse generating circuit comprises: a first trigger, a second trigger, a delay resistor, a delay capacitor and an XOR gate; wherein, The input end of the first trigger is connected to the output end of the comparator, and the output end of the first trigger is connected to the first input end of the XOR gate; The input end of the second trigger is connected to the output end of the comparator, and the output end of the second trigger is connected to the second input end of the XOR gate; The first end of the delay resistor is connected to the output end of the comparator, and the second end of the delay resistor is grounded; A first end of the delay capacitor is connected to the output end of the comparator, and a second end of the delay capacitor is grounded; The output end of the XOR gate outputs the power-on reset signal.

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