Power-down reset level conversion circuit

Abstract

The invention discloses a power-down reset level conversion circuit, which belongs to the technical field of level conversion circuits and comprises PMOS (P-channel Metal Oxide Semiconductor) transistors P1-P8, NMOS (N-channel Metal Oxide Semiconductor) transistors N1-N5, a resistor R1, an input end IN and an output end OUT, after a digital power supply DVDD is powered down, a net1 line and a net2 line are in low levels, a net3 line is originally in a high-resistance state, due to weak pull-up of a PMOS tube P7 and a resistor R1, charges of the net3 line can be gradually charged to the high level, and finally an OUT outputs the low level; the NMOS tube N4 is in a turn-off state at the moment, and the net3 line has no path, so that power consumption is avoided; during normal work, when an IN inputs a high level and a net2 line is at a high level, the PMOS tube P6 is turned off, and the PMOS tube P7 and the resistor R1 have no discharge path, so that no power consumption exists; when the IN input is at a low level, the NMOS tube N4 is also in a turn-off state at the moment, and the PMOS tube P7 and the resistor R1 have no discharge path, so that the power consumption is avoided; therefore, a conventional weak pull-down circuit is prevented from consuming certain power consumption during working.

Description

Technical Field

[0001] The invention belongs to the technical field of level conversion circuits, and in particular relates to a level conversion circuit for power-off reset. Background Art

[0002] Existing level conversion circuits can only perform conventional high-low level conversion, or state latching (can only latch the state before power failure). For some applications that need to be reset after power failure, such as the SPDT switch switching of the SPMI bus, the on-off state of each switch also needs to be specified when the digital power fails. Therefore, a level conversion circuit with power-off reset is required to give a specified state. The conventional pull-up technology is used for reset, which requires a large resistor and generates a certain amount of power consumption. Summary of the invention

[0003] The purpose of the present invention is to provide a power-off reset level conversion circuit. When the digital power supply DVDD is powered off, P7 and R1 can make the OUT output be 0 level, and the circuit power consumption is low, so as to solve the problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions: a power-off reset level conversion circuit, the level conversion circuit comprising PMOS tubes P1-P8, NMOS tubes N1-N5, a resistor R1, an input terminal IN and an output terminal OUT;

[0005] Among them, the input terminal IN is connected to the gates of the PMOS tube P1 and the NMOS tube N1; the drains of the PMOS tube P1 and the NMOS tube N1 are connected, and are also connected to the gates of the PMOS tube P2, the NMOS tube N2, the PMOS tube P4 and the NMOS tube N3; the drains of the PMOS tube P2 and the NMOS tube N2 are connected, and are also connected to the gates of the PMOS tube P6 and the NMOS tube N4; the sources and substrates of the PMOS tubes P1 and P2 are connected to the digital power supply DVDD;

[0006] The drains of the PMOS tube P4 and the NMOS tube N3 are connected to the gate of the PMOS tube P5; the drains of the PMOS tube P6 and the NMOS tube N4 are connected to the gates of the PMOS tube P3, the PMOS tube P8 and the NMOS tube N5; the drain of the PMOS tube P3 is connected to the source of the PMOS tube P4; the drain of the PMOS tube P5 and the source of the PMOS tube P6 are connected to one end of the resistor R1; the other end of the resistor R1 is connected to the gate and drain of the PMOS tube P7, and the drain of the PMOS tube P8 and the drain of the NMOS tube N5 are connected to the output terminal OUT.

[0007] Preferably, in the level conversion circuit, the sources and substrates of the PMOS tubes P3, P5, P7, and P8 are all connected to the analog power supply AVDD; and the substrates of the PMOS tubes P4 and P6 are all connected to the analog power supply AVDD.

[0008] Preferably, in the level conversion circuit, sources and substrates of the NMOS transistors N1, N2, N3, N4, and N5 are all connected to GND.

[0009] Compared with the prior art, the present invention has the following beneficial effects:

[0010] The power-off reset level conversion circuit of the present invention can make the output end OUT output 0 level when the digital power DVDD is powered off, and no power is consumed; after the digital power DVDD is powered off, the net1 line and the net2 line are low level, and the net3 line is originally in a high impedance state. Due to the weak pull-up of the PMOS tube P7 and the resistor R1, the charge of the net3 line will gradually be charged to a high level, and finally OUT outputs a low level; and the NMOS tube N4 is in a turned-off state at this time, the net3 line has no path, and no power is consumed; in addition, during normal operation, when the IN input is high level and the net2 line is high level, the PMOS tube P6 is turned off, the PMOS tube P7 and the resistor R1 have no discharge path, and no power is consumed; and when the IN input is low level, the NMOS tube N4 is also in a turned-off state at this time, and the PMOS tube P7 and the resistor R1 have no discharge path, so no power is consumed; this avoids the conventional weak pull-down circuit from consuming a certain amount of power when working. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The circuit structure diagram of a level conversion circuit for power-off reset of the present invention is shown in FIG. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] like Figure 1 As shown in the figure, this power-off reset level conversion circuit, in which P1~P8 are PMOS tubes, N1~N5 are NMOS tubes; R1 is a resistor.

[0014] The input terminal IN is connected to the gates of the PMOS tube P1 and the NMOS tube N1, the drains of the PMOS tube P1 and the NMOS tube N1 are connected together, and are connected to the gates of the PMOS tube P2, the NMOS tube N2, the PMOS tube P4, and the NMOS tube N3; the drains of the PMOS tube P2 and the NMOS tube N2 are connected together, and are connected to the gates of the PMOS tube P6 and the NMOS tube N4; the source and substrate of the PMOS tubes P1 and P2 are connected to the digital power supply DVDD; the source and substrate of the NMOS tubes N1 and N2 are connected to GND;

[0015] The drains of PMOS tube P4 and NMOS tube N3 are connected to the gate of PMOS tube P5; the drains of PMOS tube P6 and NMOS tube N4 are connected to the gates of PMOS tube P3, PMOS tube P8, and NMOS tube N5; the sources and substrates of NMOS tubes N3, N4, and N5 are connected to GND; the drain of PMOS tube P3 is connected to the source of PMOS tube P4, and the source and substrate of PMOS tube P3 and the substrate of PMOS tube P4 are connected to the analog power supply AVDD. The drain of the PMOS tube P5 and the source of the PMOS tube P6 are connected to one end of the resistor R1; the source and substrate of the PMOS tube P5 and the substrate of the PMOS tube P6 are connected to the analog power supply AVDD; the other end of the resistor R1 is connected to the gate and drain of the PMOS tube P7, and the source and substrate of the PMOS tube P7 are connected to the analog power supply AVDD; the source and substrate of the PMOS tube P8 are connected to the analog power supply AVDD, and the drain of the PMOS tube P8 and the drain of the NMOS tube N5 are connected to the output terminal OUT.

[0016] The present invention discloses a level conversion circuit with power-off reset. When the digital power supply DVDD is powered off, the PMOS tube P7 and the resistor R1 can make the output terminal OUT output 0 level without consuming power. After the digital power supply DVDD is powered off, the net1 line and the net2 line are low level, and the net3 line is originally in a high impedance state. Due to the weak pull-up of the PMOS tube P7 and the resistor R1, the charge of the net3 line will gradually be charged to a high level, and finally the output terminal OUT outputs a low level; and the NMOS tube N4 tube is in a turned-off state at this time, the net3 line has no path, and no power consumption is consumed; in addition, during normal operation, when the input terminal IN inputs a high level and the net2 line is a high level, the PMOS tube P6 is turned off, the PMOS tube P7 and the resistor R1 have no discharge path, and no power consumption will occur; and when the input terminal IN inputs a low level, the NMOS tube N4 is also in a turned-off state at this time, and the PMOS tube P7 and the resistor R1 have no discharge path, so no power consumption will occur; this avoids the conventional weak pull-down circuit from consuming a certain amount of power when working.

[0017] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0018] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A level conversion circuit for power-off reset, characterized in that: The level conversion circuit includes PMOS tubes P1-P8, NMOS tubes N1-N5, a resistor R1, an input terminal IN and an output terminal OUT; Among them, the input terminal IN is connected to the gates of the PMOS tube P1 and the NMOS tube N1; the drains of the PMOS tube P1 and the NMOS tube N1 are connected, and are also connected to the gates of the PMOS tube P2, the NMOS tube N2, the PMOS tube P4 and the NMOS tube N3; the drains of the PMOS tube P2 and the NMOS tube N2 are connected, and are also connected to the gates of the PMOS tube P6 and the NMOS tube N4; the sources and substrates of the PMOS tubes P1 and P2 are connected to the digital power supply DVDD; The drains of the PMOS tube P4 and the NMOS tube N3 are connected to the gate of the PMOS tube P5; the drains of the PMOS tube P6 and the NMOS tube N4 are connected to the gates of the PMOS tube P3, the PMOS tube P8 and the NMOS tube N5; the drain of the PMOS tube P3 is connected to the source of the PMOS tube P4; the drain of the PMOS tube P5 and the source of the PMOS tube P6 are connected to one end of the resistor R1; the other end of the resistor R1 is connected to the gate and drain of the PMOS tube P7, and the drain of the PMOS tube P8 and the drain of the NMOS tube N5 are connected to the output terminal OUT.

2. A level conversion circuit for power-off reset according to claim 1, characterized in that: In the level conversion circuit, the sources and substrates of the PMOS tubes P3, P5, P7, and P8 are all connected to the analog power supply AVDD; the substrates of the PMOS tubes P4 and P6 are all connected to the analog power supply AVDD.

3. The level conversion circuit for power-off reset according to claim 1, characterized in that: In the level conversion circuit, the sources and substrates of the NMOS tubes N1, N2, N3, N4, and N5 are all connected to GND.

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