Method and device for testing delayed startup stability of variable frequency transmitter

Abstract

The invention discloses a frequency conversion transmitter delayed startup stability test method and device, and the method comprises the steps: generating a complex baseband dot frequency test signal e when a frequency conversion transmitter is powered off and restarted, and carrying out the preprocessing of the signal e, so as to obtain a radio frequency test signal h; collecting the signal h by taking the reference clock b as a trigger to obtain a phase value i of the signal h at the trigger moment; the frequency conversion transmitter is powered off and restarted according to preset restarting times, and the phase value i of the signal h at the triggering moment is obtained repeatedly; screening to obtain a maximum value and a minimum value of the phase value i, and calculating a phase difference value s between the maximum value and the minimum value; and when the phase difference value s is within the preset phase difference value range, judging that the delayed startup of the main signal link of the frequency conversion transmitter is stable. Compared with the prior art, the method and the device for testing the delayed startup stability of the frequency conversion transmitter have the advantages that the testing process is remarkably simplified, and the equipment requirement and the testing cost are reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a method and device for testing the stability of delayed startup of a variable frequency transmitter. Background Art

[0002] In the phased array system, the frequency conversion transmitter undertakes the important task of converting the baseband digital signal into a radio frequency signal and transmitting it. This conversion process involves digital and analog frequency conversion processing of the signal, aiming to generate the required high-frequency band signal. In this process, the power-on stability of the signal link delay is a key indicator to measure the performance of the frequency conversion transmitter, which is directly related to whether the phased array system can achieve the correction-free function. If the delay can be kept stable every time it is turned on, the system can save the complex transmission channel correction steps, which can not only greatly reduce the complexity of the system's software and hardware, but also significantly shorten the system startup deployment time, improve the response speed, and enhance the system's anti-interference performance. However, due to the significant differences in frequency and nature between the input and output signals of the frequency conversion transmitter, this poses a great challenge to the test of link delay. Therefore, how to accurately test the link delay stability of the frequency conversion transmitter at startup has become an urgent problem to be solved.

[0003] In order to solve this problem, the existing solutions are mainly the following two methods: 1. Use two identical frequency conversion transmitters, inject the same signal and observe the delay relationship of the output signals from the two modules. This method is more intuitive, but the disadvantage is that at least two identical modules are required, and the synchronous read and write timing needs to be designed when the same signal is injected, which increases the test cost and complexity. 2. Use a frequency conversion transmitter to generate a known excitation signal and connect it to a receiver with a symmetrical frequency conversion structure. By observing the delay relationship between the receiver output signal and the signal generated by the transmitter, it is determined whether the power-on link delay of the frequency conversion transmitter is stable. This method also requires the use of other complex software and hardware systems, which increases the complexity, uncertainty and cost of the test.

[0004] Therefore, the industry urgently needs to find a simple, efficient, low-cost method that does not rely on special external equipment to test the startup stability of the main signal link delay of the frequency conversion transmitter. This will help meet the test requirements of the correction-free phased array system in rapid deployment scenarios and anti-interference scenarios, especially the test requirements of batch frequency conversion transmitters, and is of great significance for improving the overall performance and reliability of the phased array system. Summary of the invention

[0005] In order to solve the technical problems existing in the background technology, the present invention proposes a method and device for testing the stability of delayed startup of a variable frequency transmitter.

[0006] The present invention provides a method for testing the stability of delayed startup of a variable frequency transmitter, comprising the following steps:

[0007] S1. When the frequency conversion transmitter is powered off and restarted, a complex baseband frequency test signal e is generated, and the complex baseband frequency test signal e is preprocessed to obtain a corresponding radio frequency test signal h;

[0008] S2, obtaining a reference clock b, and using the rising edge of the reference clock b as a trigger to collect a radio frequency test signal h, so as to obtain a phase value i of the radio frequency test signal h at the triggering moment;

[0009] S3, power off and restart the frequency conversion transmitter according to a preset restart number, and repeat step S1 and step S2 to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband point frequency test signal e generated in each power-off and restart stage at the triggering time;

[0010] S4, screening the phase values ​​i collected at the triggering moment in each power-off restart phase to obtain the maximum and minimum values ​​of the phase value i, and calculating the phase difference s between the maximum and minimum values ​​of the phase value i;

[0011] S5. When the phase difference value s is within the preset phase difference value range, it is determined that the delayed startup of the main signal link of the frequency conversion transmitter is stable.

[0012] Preferably, the preprocessing specifically includes:

[0013] Performing interpolation and digital up-conversion processing on the complex baseband point frequency test signal e to obtain an intermediate frequency digital test signal f;

[0014] Performing clock domain conversion and interface adaptation conversion on the intermediate frequency digital test signal f to obtain an intermediate frequency digital test signal k;

[0015] Performing digital-to-analog conversion on the intermediate frequency digital test signal k to obtain an intermediate frequency analog test signal g;

[0016] The intermediate frequency analog test signal g is analog up-converted, filtered and amplified to obtain a radio frequency test signal h.

[0017] Preferably, in step S2, the reference clock b is generated by the frequency source of the variable frequency transmitter, and the frequency source of the variable frequency transmitter also generates a radio frequency local oscillator clock a, and the radio frequency local oscillator clock a is homologous to the reference clock b; the frequency synthesizer of the variable frequency transmitter generates a low-frequency clock c and a system operating clock d whose initial rising edge is aligned with the rising edge of the reference clock b.

[0018] Preferably, the preset phase difference range is specifically:

[0019]

[0020] Where K is a constant less than 1; f e is the frequency of the complex baseband frequency test signal e; f nco The frequency of the digital local oscillator used for digital up-conversion; f dac is the conversion clock frequency of the DAC.

[0021] Preferably, the relationship between the frequency of the digital local oscillator used in the digital up-conversion processing, the frequency of the complex baseband frequency test signal e, and the frequency of the low-frequency clock c is as follows:

[0022] f e +f nco =M×f c ;

[0023] Where M is any positive integer; f nco is the frequency of the digital local oscillator; f e is the frequency of the complex baseband frequency test signal e; f c is the frequency of the low-frequency clock c.

[0024] Preferably, the relationship between the frequency of the RF local oscillator clock a and the frequency of the low-frequency clock c is as follows:

[0025] f a =N×f c ;

[0026] Where N is any positive integer; f a is the frequency of the RF local oscillator clock a; f c is the frequency of the low-frequency clock c;

[0027] The relationship between the frequency of the reference clock b, the frequency of the low-frequency clock c, and the frequency of the system working clock d is as follows:

[0028] f c =P×f b ;

[0029] f d =R×f c ;

[0030] Where P and R are any positive integers; f b is the frequency of the reference clock b; f c is the frequency of the low-frequency clock c; f d is the frequency of the system working clock d.

[0031] Preferably, it also includes:

[0032] After the frequency conversion transmitter is turned on, the frequency conversion transmitter generates a phase clear signal j synchronized with the low-frequency clock c, and the phase clear signal j is used to synchronously reset the direct frequency synthesis unit for generating the complex baseband point frequency test signal e and the digital up-conversion unit for interpolating and digitally up-converting the complex baseband point frequency test signal e.

[0033] The present invention provides a device for testing the stability of delayed startup of a variable frequency transmitter, comprising:

[0034] The waveform generation and preprocessing module is used to generate a complex baseband frequency test signal e when the frequency conversion transmitter is powered off and restarted, and preprocess the complex baseband frequency test signal e to obtain a corresponding radio frequency test signal h;

[0035] The first processing module is used to obtain a reference clock b, and collect a radio frequency test signal h with the rising edge of the reference clock b as a trigger to obtain a phase value i of the radio frequency test signal h at the triggering moment;

[0036] The second processing module is used to power off and restart the frequency conversion transmitter according to a preset restart number, and repeatedly process it through the waveform generation and preprocessing module and the first processing module to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband point frequency test signal e generated in each power-off and restart stage at the triggering time;

[0037] The third processing module is used to screen the phase values ​​i collected at the triggering moment in each power-off restart phase to obtain the maximum and minimum values ​​of the phase value i at the triggering moment, and calculate the phase difference s between the maximum and minimum values ​​of the phase value i;

[0038] The output module is used to determine that the delayed startup of the main signal link of the frequency conversion transmitter is stable when the phase difference value s is within the preset phase difference value range.

[0039] Preferably, the waveform generation and preprocessing module specifically includes:

[0040] A direct frequency synthesis unit, used to generate a complex baseband frequency test signal e;

[0041] A digital up-conversion unit, used for performing interpolation and digital up-conversion processing on the complex baseband point frequency test signal e to obtain an intermediate frequency digital test signal f;

[0042] A clock domain conversion unit, used for performing clock domain conversion and interface adaptation conversion on the intermediate frequency digital test signal f to obtain an intermediate frequency digital test signal k;

[0043] A digital-to-analog conversion unit, used for performing digital-to-analog conversion on an intermediate frequency digital test signal k to obtain an intermediate frequency analog test signal g;

[0044] The radio frequency channel unit is used to perform analog up-conversion, filtering and amplification on the intermediate frequency analog test signal g to obtain a radio frequency test signal h.

[0045] Preferably, the waveform generation and preprocessing module also includes: a phase clearing unit, which is used to generate a phase clearing signal j synchronized with the low-frequency clock c after the frequency conversion transmitter is turned on, and synchronously reset the direct frequency synthesis unit and the digital up-conversion unit through the phase clearing signal j.

[0046] In the present invention, the proposed method and device for testing the stability of delayed startup of a variable frequency transmitter generate a complex baseband frequency test signal e when the variable frequency transmitter is powered off and restarted, and pre-process the complex baseband frequency test signal e to obtain a corresponding radio frequency test signal h; obtain a reference clock b, and use the rising edge of the reference clock b as a trigger to collect the radio frequency test signal h to obtain a phase value i of the radio frequency test signal h at the triggering moment; the variable frequency transmitter is powered off and restarted according to a preset number of restarts, and steps S1 and S2 are repeated to obtain the phase value i of the radio frequency test signal h at the triggering moment corresponding to the complex baseband frequency test signal e generated in each power-off and restart stage; the phase value i collected at the triggering moment in each power-off and restart stage is screened to obtain the maximum and minimum values ​​of the phase value i, and the phase difference s between the maximum and minimum values ​​of the phase value i is calculated; when the phase difference s is within the preset phase difference range, it is determined that the delayed startup of the main signal link of the variable frequency transmitter is stable. By controlling the frequency relationship between the clock, local oscillator and digitally controlled oscillator, and using synchronization technology, the test problem of the startup stability of the main signal link delay of the variable frequency transmitter is converted into a test problem of the RF signal phase, so as to accurately and efficiently test whether the link delay of a single variable frequency transmitter remains stable between multiple startups. Compared with the prior art, the present invention only requires common instruments and cables, without the need for external complex software and hardware systems, which significantly simplifies the test process and reduces equipment requirements and testing costs. The present invention has significant significance in the application of correction-free phased arrays that need to be quickly deployed and avoid interference during the correction process, improves test efficiency, and provides strong support for batch frequency conversion transmitter testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of the working process of a variable frequency transmitter delayed start-up stability testing method proposed by the present invention;

[0048] Figure 2 A schematic diagram of the device architecture of a variable frequency transmitter delayed start-up stability testing device proposed by the present invention;

[0049] Figure 3 This is a schematic diagram of the waveform generation and preprocessing module structure of a variable frequency transmitter delayed start-up stability test device proposed by the present invention;

[0050] Figure 4 The present invention provides a schematic structural diagram of a digital up-conversion unit of a frequency conversion transmitter delayed startup stability testing device. DETAILED DESCRIPTION

[0051] Reference Figure 1-4 The present invention provides a method for testing the stability of delayed startup of a variable frequency transmitter, comprising the following steps:

[0052] S1. When the frequency conversion transmitter is powered off and restarted, a complex baseband frequency test signal e is generated, and the complex baseband frequency test signal e is preprocessed to obtain a corresponding radio frequency test signal h.

[0053] In this embodiment, the preprocessing specifically includes: interpolating and digitally up-converting the complex baseband frequency test signal e to obtain an intermediate frequency digital test signal f; performing clock domain conversion and interface adaptation conversion on the intermediate frequency digital test signal f to obtain an intermediate frequency digital test signal k; performing digital-to-analog conversion on the intermediate frequency digital test signal k to obtain an intermediate frequency analog test signal g; performing analog up-conversion, filtering and amplification on the intermediate frequency analog test signal g to obtain a radio frequency test signal h.

[0054] S2. Obtain a reference clock b, and use the rising edge of the reference clock b as a trigger to collect a radio frequency test signal h, so as to obtain a phase value i of the radio frequency test signal h at the triggering moment.

[0055] In this embodiment, in step S2, the reference clock b is generated by the frequency source of the frequency conversion transmitter, and the frequency source of the frequency conversion transmitter also generates a radio frequency local oscillator clock a, and the radio frequency local oscillator clock a is of the same source as the reference clock b; the frequency synthesizer of the frequency conversion transmitter generates a low-frequency clock c and a system operating clock d whose initial rising edge is aligned with the rising edge of the reference clock b.

[0056] In this embodiment, the relationship between the frequency of the digital local oscillator used in the digital up-conversion process, the frequency of the complex baseband frequency test signal e, and the frequency of the low-frequency clock c is as follows:

[0057] f e +f nco =M×f c ;

[0058] Where M is any positive integer; f nco is the frequency of the digital local oscillator; f e is the frequency of the complex baseband frequency test signal e; f c is the frequency of the low-frequency clock c.

[0059] In this embodiment, the relationship between the frequency of the RF local oscillator clock a and the frequency of the low-frequency clock c is as follows:

[0060] f a =N×f c ;

[0061] Where N is any positive integer; f a is the frequency of the RF local oscillator clock a; f c is the frequency of the low-frequency clock c;

[0062] The relationship between the frequency of the reference clock b, the frequency of the low-frequency clock c, and the frequency of the system working clock d is as follows:

[0063] f c =P×f b ;

[0064] f d =R×f c ;

[0065] Where P and R are any positive integers; f b is the frequency of the reference clock b; f c is the frequency of the low-frequency clock c; f d is the frequency of the system working clock d.

[0066] In this embodiment, the RF local oscillator clock frequency a is f a The reference clock frequency f is 1 GHz. b The frequency f of the low-frequency clock c is 10MHz. c The frequency of the system operating clock d is 10MHz. d It is 200MHz, so N=100, P=1, R=20.

[0067] Exemplarily, the sampling rate of the complex baseband frequency test signal e may not be equal to the sampling rate of the intermediate frequency digital test signal f, and in this case the interpolation multiple I is not equal to 1.

[0068] In this embodiment, the frequency f of the complex baseband frequency test signal e is e The sampling rate is 50MSPS (using a 1 / 4 duty cycle signal to achieve a 50MSPS signal sampling rate at a system operating clock d of 200MHz), and the frequency of the digital local oscillator used in the digital up-conversion is f nco The frequency of the intermediate frequency digital test signal f is 170 MHz, the sampling rate is 200 MSPS.

[0069] In this embodiment, the conversion frequency of the digital-to-analog converter is equal to the sampling rate of the intermediate frequency digital test signal f, the clock domain conversion is to switch the intermediate frequency digital test signal f from the system working clock domain to the DAC conversion clock domain, and the interface adaptation is to convert the intermediate frequency digital test signal f into the data format required by the DAC.

[0070] In the embodiment of the present invention, the DAC conversion frequency is 200MSPS.

[0071] In this embodiment, a 170 MHz intermediate frequency digital test signal f is subjected to analog up-conversion, band-pass filtering and amplification using a local oscillator with a frequency of 1 GHz to obtain a 1170 MHz RF test signal h.

[0072] In this embodiment, the reference clock b and the RF test signal h are connected to a high-speed oscilloscope, and the rising edge of the reference clock b is used as a trigger to collect the RF test signal h, and the phase value i of the RF test signal h at the triggering moment is recorded;

[0073] Exemplarily, a high-speed oscilloscope with dual channels, an analog bandwidth of 3 GHz, and a maximum sampling rate of 10 GS / s can be selected. The reference clock b and the RF test signal h can be connected to the two channels of the oscilloscope respectively. The reference clock b is used as the acquisition trigger signal to acquire the RF test signal h. The phase of the RF test signal h can be automatically calculated using the oscilloscope, or its phase can be determined by observing the waveform.

[0074] S3, power off and restart the frequency conversion transmitter according to the preset restart times, and repeat steps S1 and S2 to obtain the phase value i of the RF test signal h corresponding to the complex baseband point frequency test signal e generated in each power-off and restart stage at the triggering moment.

[0075] S4. Screen the phase values ​​i collected at the triggering moment in each power-off restart phase to obtain the maximum and minimum values ​​of the phase value i, and calculate the phase difference s between the maximum and minimum values ​​of the phase value i.

[0076] S5. When the phase difference value s is within the preset phase difference value range, it is determined that the delayed startup of the main signal link of the frequency conversion transmitter is stable.

[0077] In this embodiment, the preset phase difference range is specifically:

[0078]

[0079] Where K is a constant less than 1; f e is the frequency of the complex baseband frequency test signal e; f nco The frequency of the digital local oscillator used for digital up-conversion; f dac is the conversion clock frequency of the DAC.

[0080] In this embodiment, it also includes:

[0081] After the frequency conversion transmitter is turned on, the frequency conversion transmitter generates a phase clear signal j synchronized with the low-frequency clock c, and the phase clear signal j is used to synchronously reset the direct frequency synthesis unit for generating the complex baseband point frequency test signal e and the digital up-conversion unit for interpolating and digitally up-converting the complex baseband point frequency test signal e.

[0082] Specifically, each time the frequency conversion transmitter is turned on, a phase clear signal j synchronized with the low-frequency clock c is generated. The timing between the phase clear signal j and the system working clock d must meet the setup and hold time requirements to synchronously reset the direct frequency synthesis unit and the digital up-conversion unit.

[0083] It is worth noting that the purpose of doing so is to align the initial phase of the generated intermediate frequency digital test signal f with the rising edge of the low frequency clock c, and then with the rising edge of the reference clock b. In addition, when the digital up-conversion unit is synchronously reset, the interpolation filter unit and the digital control oscillator inside the reset module are specifically reset.

[0084] For example, after the variable frequency transmitter is powered on, a low-frequency clock c can be used to generate a pulse signal with a width of one low-frequency clock c cycle as a phase clear signal j, and through timing constraints, the timing between the phase clear signal j and the system working clock d must meet the setup and hold time requirements.

[0085] Specifically, during the process of multiple power-off and restart of the frequency conversion transmitter, if the change of the phase value i observed on the oscilloscope is less than Then it is determined that the link delay of the variable frequency transmitter is stable every time it is turned on, otherwise it is unstable, where K is a constant less than 1, f e is the frequency of the complex baseband frequency test signal e, f nco is the frequency of the digital local oscillator used for digital up-conversion, f dac is the conversion clock frequency of the DAC.

[0086] In the embodiment of the present invention, K is set to 0.5, so during the process of multiple power-off and restart of the frequency conversion transmitter, if the change of the phase value i observed on the oscilloscope is less than It is considered that the change of the link delay of the variable frequency transmitter each time it is turned on is less than one DAC conversion clock cycle, and it can be determined that the link delay is stable when it is turned on, otherwise it is unstable.

[0087] Reference Figure 1-4 The present invention provides a variable frequency transmitter delayed start-up stability testing device, comprising:

[0088] The waveform generation and preprocessing module is used to generate a complex baseband frequency test signal e when the frequency conversion transmitter is powered off and restarted, and preprocess the complex baseband frequency test signal e to obtain a corresponding radio frequency test signal h.

[0089] The first processing module is used to obtain a reference clock b, and collect a radio frequency test signal h with the rising edge of the reference clock b as a trigger to obtain a phase value i of the radio frequency test signal h at the triggering moment.

[0090] The second processing module is used to power off and restart the frequency conversion transmitter according to a preset number of restart times, and repeatedly process it through the waveform generation and preprocessing module and the first processing module to obtain the phase value i of the RF test signal h at the triggering moment corresponding to the complex baseband point frequency test signal e generated in each power-off and restart stage.

[0091] The third processing module is used to screen the phase values ​​i collected at the triggering moment in each power-off restart phase to obtain the maximum and minimum values ​​of the phase value i at the triggering moment, and calculate the phase difference s between the maximum and minimum values ​​of the phase value i;

[0092] The output module is used to determine that the delayed startup of the main signal link of the frequency conversion transmitter is stable when the phase difference value s is within the preset phase difference value range.

[0093] In this embodiment, if Figure 3 As shown, the waveform generation and preprocessing module specifically includes:

[0094] A direct frequency synthesis unit, used to generate a complex baseband frequency test signal e;

[0095] The digital up-conversion unit is used to perform interpolation and digital up-conversion processing on the complex baseband point frequency test signal e to obtain an intermediate frequency digital test signal f.

[0096] The clock domain conversion unit is used to perform clock domain conversion and interface adaptation conversion on the intermediate frequency digital test signal f to obtain the intermediate frequency digital test signal k.

[0097] The digital-to-analog conversion unit is used to perform digital-to-analog conversion on the intermediate frequency digital test signal k to obtain an intermediate frequency analog test signal g.

[0098] The radio frequency channel unit is used to perform analog up-conversion, filtering and amplification on the intermediate frequency analog test signal g to obtain a radio frequency test signal h.

[0099] In the embodiment of the present invention, Figure 4 As shown, the digital up-conversion unit includes: an interpolation filter unit, a numerically controlled oscillator (NCO), a multiplier and a subtractor;

[0100] The interpolation filter unit is used to digitally interpolate and low-pass filter the real and imaginary parts of the complex baseband frequency test signal e, respectively, output signals m and n to the multiplier, and use the phase clear signal j to reset the interpolation filter unit;

[0101] A digital controlled oscillator is used to output the real part o and the imaginary part p of the digital local oscillator to the multiplier respectively, and the digital controlled oscillator is reset using a phase clearing signal j;

[0102] A multiplier, for respectively multiplying signals m and o to output a signal q, and multiplying signals n and p to output a signal r;

[0103] The subtractor is used for subtracting the signal r from the signal q, and outputting an intermediate frequency digital test signal f.

[0104] In this embodiment, the waveform generation and preprocessing module also includes: a phase clearing unit, which is used to generate a phase clearing signal j synchronized with the low-frequency clock c after the frequency conversion transmitter is turned on, and synchronously reset the direct frequency synthesis unit and the digital up-conversion unit through the phase clearing signal j.

[0105] In this embodiment, the waveform generation and preprocessing module also includes:

[0106] A frequency source is used to output a homologous RF local oscillator clock a and a reference clock b, wherein the RF local oscillator clock a is sent to the RF channel, and the reference clock b is sent to the frequency synthesizer and the high-speed oscilloscope respectively;

[0107] The frequency synthesizer is used to output a low-frequency clock c and a system working clock d whose initial rising edge is aligned with the rising edge of a reference clock b, wherein the low-frequency clock c is sent to a phase clearing unit, and the system working clock d is sent to a direct frequency synthesis unit, a digital up-conversion unit and a clock domain conversion unit.

[0108] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for testing the stability of delayed startup of a variable frequency transmitter, characterized in that: The following steps are involved: S1. When the frequency conversion transmitter is powered off and restarted, a complex baseband frequency test signal e is generated, and the complex baseband frequency test signal e is preprocessed to obtain a corresponding radio frequency test signal h; S2, obtaining a reference clock b, and using the rising edge of the reference clock b as a trigger to collect a radio frequency test signal h, so as to obtain a phase value i of the radio frequency test signal h at the triggering moment; S3, power off and restart the frequency conversion transmitter according to a preset restart number, and repeat step S1 and step S2 to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband point frequency test signal e generated in each power-off and restart stage at the triggering time; S4, screening the phase values ​​i collected at the triggering moment in each power-off restart phase to obtain the maximum and minimum values ​​of the phase value i, and calculating the phase difference s between the maximum and minimum values ​​of the phase value i; S5. When the phase difference value s is within the preset phase difference value range, it is determined that the delayed startup of the main signal link of the frequency conversion transmitter is stable.

2. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 1, characterized in that: The pre-processing specifically includes: Performing interpolation and digital up-conversion processing on the complex baseband point frequency test signal e to obtain an intermediate frequency digital test signal f; Performing clock domain conversion and interface adaptation conversion on the intermediate frequency digital test signal f to obtain an intermediate frequency digital test signal k; Performing digital-to-analog conversion on the intermediate frequency digital test signal k to obtain an intermediate frequency analog test signal g; The intermediate frequency analog test signal g is analog up-converted, filtered and amplified to obtain a radio frequency test signal h.

3. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 2, characterized in that: In step S2, the reference clock b is generated by the frequency source of the variable frequency transmitter, and the frequency source of the variable frequency transmitter also generates a radio frequency local oscillator clock a, which is the same source as the reference clock b; the frequency synthesizer of the variable frequency transmitter generates a low-frequency clock c and a system working clock d whose initial rising edge is aligned with the rising edge of the reference clock b.

4. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 1, characterized in that: The preset phase difference range is specifically: Where K is a constant less than 1; f e is the frequency of the complex baseband frequency test signal e; f nco The frequency of the digital local oscillator used for digital up-conversion; f dac is the conversion clock frequency of the DAC.

5. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 2 or 3, characterized in that: The relationship between the frequency of the digital local oscillator used in the digital up-conversion process, the frequency of the complex baseband frequency test signal e, and the frequency of the low-frequency clock c is as follows: f e +f nco =M×f c ; Where M is any positive integer; f nco is the frequency of the digital local oscillator; f e is the frequency of the complex baseband frequency test signal e; f c is the frequency of the low-frequency clock c.

6. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 3, characterized in that: The relationship between the frequency of the RF local oscillator clock a and the frequency of the low-frequency clock c is as follows: f a =N×f c ; Where N is any positive integer; f a is the frequency of the RF local oscillator clock a; f c is the frequency of the low-frequency clock c; The relationship between the frequency of the reference clock b, the frequency of the low-frequency clock c, and the frequency of the system working clock d is as follows: f c =P×f b ; f d =R×f c ; Where P and R are any positive integers; f b is the frequency of the reference clock b; f c is the frequency of the low-frequency clock c; f d is the frequency of the system working clock d.

7. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 2, characterized in that: Also includes: After the frequency conversion transmitter is turned on, the frequency conversion transmitter generates a phase clear signal j synchronized with the low-frequency clock c, and the phase clear signal j is used to synchronously reset the direct frequency synthesis unit for generating the complex baseband point frequency test signal e and the digital up-conversion unit for interpolating and digitally up-converting the complex baseband point frequency test signal e.

8. A variable frequency transmitter delayed start-up stability test device, characterized in that: include: The waveform generation and preprocessing module is used to generate a complex baseband frequency test signal e when the frequency conversion transmitter is powered off and restarted, and preprocess the complex baseband frequency test signal e to obtain a corresponding radio frequency test signal h; The first processing module is used to obtain a reference clock b, and collect a radio frequency test signal h with the rising edge of the reference clock b as a trigger to obtain a phase value i of the radio frequency test signal h at the triggering moment; The second processing module is used to power off and restart the frequency conversion transmitter according to a preset restart number, and repeatedly process it through the waveform generation and preprocessing module and the first processing module to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband point frequency test signal e generated in each power-off and restart stage at the triggering time; The third processing module is used to screen the phase values ​​i collected at the triggering moment in each power-off restart phase to obtain the maximum and minimum values ​​of the phase value i at the triggering moment, and calculate the phase difference s between the maximum and minimum values ​​of the phase value i; The output module is used to determine that the delayed startup of the main signal link of the frequency conversion transmitter is stable when the phase difference value s is within the preset phase difference value range.

9. The device for testing the stability of delayed startup of a frequency conversion transmitter according to claim 8, characterized in that: The waveform generation and preprocessing module specifically includes: A direct frequency synthesis unit, used to generate a complex baseband frequency test signal e; A digital up-conversion unit, used for performing interpolation and digital up-conversion processing on the complex baseband point frequency test signal e to obtain an intermediate frequency digital test signal f; A clock domain conversion unit, used for performing clock domain conversion and interface adaptation conversion on the intermediate frequency digital test signal f to obtain an intermediate frequency digital test signal k; A digital-to-analog conversion unit, used for performing digital-to-analog conversion on an intermediate frequency digital test signal k to obtain an intermediate frequency analog test signal g; The radio frequency channel unit is used to perform analog up-conversion, filtering and amplification on the intermediate frequency analog test signal g to obtain a radio frequency test signal h.

10. The variable frequency transmitter delayed start-up stability testing device according to claim 9, characterized in that: The waveform generation and preprocessing module also includes: The phase clearing unit is used for generating a phase clearing signal j synchronized with the low-frequency clock c after the frequency conversion transmitter is turned on, and synchronously resetting the direct frequency synthesis unit and the digital up-conversion unit through the phase clearing signal j.

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