A testing method and device for the stability of delayed startup of a variable-frequency transmitter

Abstract

The present invention discloses a method and device for testing the stability of delayed startup of a variable-frequency transmitter, including: when the variable-frequency transmitter is powered off and restarted, generating a complex baseband point-frequency test signal e, and preprocessing the signal e to obtain a radio-frequency test signal h; triggering with a reference clock b, collecting the signal h to obtain the phase value i of the signal h at the triggering moment; powering off and restarting the variable-frequency transmitter according to a preset number of restart times, and repeatedly obtaining the phase value i of the signal h at the triggering moment; screening to obtain the maximum and minimum values of the phase value i, and calculating the phase difference s between the maximum and minimum values; when the phase difference s is within a preset phase difference range, it is determined that the main signal link of the variable-frequency transmitter has stable delayed startup. Compared with the prior art, the method and device for testing the stability of delayed startup of the variable-frequency transmitter in this application significantly simplify the test process, reduce the equipment requirements and test costs.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and particularly to a method and device for testing the stability of delayed startup of a frequency conversion transmitter. Background Art

[0002] In a phased array system, a frequency conversion transmitter undertakes the important task of converting a baseband digital signal into a radio frequency signal and transmitting it. This conversion process involves digital and analog frequency conversion processing of signals, aiming to generate the required high-frequency signals. During this process, the startup stability of the signal link delay is a key indicator for measuring the performance of the frequency conversion transmitter, which directly relates to whether the phased array system can achieve the function of avoiding calibration. If the delay can be kept stable every time the machine is started, then the system can omit the complex transmission channel calibration steps, which can not only greatly reduce the software and hardware complexity of the system, but also significantly shorten the system startup deployment time, improve the response speed, and enhance the anti-interference performance of the system. However, due to the significant differences in frequency and nature between the input and output signals of the frequency conversion transmitter, this poses a great challenge to the test of the link delay. Therefore, how to accurately test the stability of the link delay of the frequency conversion transmitter during startup has become an urgent problem to be solved.

[0003] To solve this problem, the existing solutions mainly include the following two methods: 1. Use two identical frequency conversion transmitters, input the same signal and observe the delay relationship of the output signals from the two modules. This method is relatively intuitive, but the disadvantage is that at least two identical modules are required, and when inputting the same signal, it is necessary to design synchronous read and write timing sequences, increasing the test cost and complexity. 2. Use a frequency conversion transmitter to generate a known excitation signal and connect it to a receiver with a symmetric frequency conversion structure. By observing the delay relationship between the output signal of the receiver and the signal generated by the transmitter, it is determined whether the startup link delay of the frequency conversion transmitter is stable. This method also requires the assistance of other complex software and hardware systems, increasing the complexity, uncertainty and cost of the test.

[0004] Therefore, the industry urgently needs to find a simple, efficient, low-cost method that does not rely on special external devices to test the startup stability of the main signal link delay of the frequency conversion transmitter. This will help to meet the test requirements of the phased array system without calibration in fast deployment scenarios and anti-interference scenarios, especially the test requirements of batch frequency conversion transmitters, which is of great significance for improving the overall performance and reliability of the phased array system. Summary of the Invention

[0005] To solve the technical problems in the background art, the present invention proposes a method and device for testing the stability of delayed startup of a frequency conversion transmitter.

[0006] A method for testing the stability of delayed startup of a variable-frequency transmitter proposed by the present invention includes the following steps:

[0007] S1. When the variable-frequency transmitter is powered off and restarted, a complex baseband point-frequency test signal e is generated, and the complex baseband point-frequency test signal e is preprocessed to obtain a corresponding radio-frequency test signal h;

[0008] S2. A reference clock b is obtained, and the radio-frequency test signal h is collected triggered by the rising edge of the reference clock b to obtain the phase value i of the radio-frequency test signal h at the trigger moment;

[0009] S3. The variable-frequency transmitter is powered off and restarted according to a preset number of restart times, and steps S1 and S2 are repeated to obtain the phase value i of the radio-frequency test signal h corresponding to the complex baseband point-frequency test signal e generated in each power-off restart stage at the trigger moment;

[0010] S4. The phase values i collected at the trigger moment in each power-off restart stage are screened to obtain the maximum value and the minimum value of the phase values i collected at the trigger moment in each power-off restart stage, and the phase difference s between the maximum value and the minimum value of the phase values i is calculated;

[0011] S5. When the phase difference s is within a preset phase difference range, it is determined that the main signal link of the variable-frequency transmitter has stable delayed startup;

[0012] The specific preset phase difference range is:

[0013]

[0014] where K is a constant less than 1; f e is the frequency of the complex baseband point-frequency test signal e; f nco is the frequency of the digital local oscillator used for digital upconversion; f dac is the conversion clock frequency of the DAC.

[0015] Preferably, the preprocessing specifically includes:

[0016] Performing interpolation and digital upconversion processing on the complex baseband point-frequency test signal e to obtain an intermediate-frequency digital test signal f;

[0017] Performing clock domain conversion and interface adaptation conversion on the intermediate-frequency digital test signal f to obtain an intermediate-frequency digital test signal k;

[0018] Performing digital-to-analog conversion on the intermediate-frequency digital test signal k to obtain an intermediate-frequency analog test signal g;

[0019] Performing analog upconversion, filtering and amplification on the intermediate-frequency analog test signal g to obtain a radio-frequency test signal h.

[0020] Preferably, in step S2, the reference clock b is generated by the frequency source of the frequency conversion transmitter. The frequency source of the frequency conversion transmitter also generates a radio frequency local oscillator clock a, and the radio frequency local oscillator clock a is homologous to the reference clock b; the frequency synthesizer of the frequency conversion transmitter generates a low-frequency clock c and a system working clock d whose initial rising edges are aligned with the rising edge of the reference clock b.

[0021] Preferably, the relationship among the frequency of the digital local oscillator used in the digital up-conversion process, the frequency of the complex baseband point-frequency test signal e, and the frequency of the low-frequency clock c is as follows:

[0022] f e +f nco =M×f c ;

[0023] Where M is any positive integer; f nco is the frequency of the digital local oscillator; f e is the frequency of the complex baseband point-frequency test signal e; f c is the frequency of the low-frequency clock c.

[0024] Preferably, the relationship between the frequency of the radio frequency local oscillator clock a and the frequency of the low-frequency clock c is as follows:

[0025] f a =N×f c ;

[0026] Where N is any positive integer; f a is the frequency of the radio frequency local oscillator clock a; f c is the frequency of the low-frequency clock c;

[0027] The relationship among the frequency of the reference clock b, the frequency of the low-frequency clock c, and the frequency of the system working clock d is as follows:

[0028] f c =P×f b ;

[0029] f d =R×f c ;

[0030] Where P and R are any positive integers; f b is the frequency of the reference clock b; f c is the frequency of the low-frequency clock c; f d is the frequency of the system working clock d.

[0031] Preferably, it further includes:

[0032] After the frequency conversion transmitter is powered on, the frequency conversion transmitter generates a phase reset signal j synchronized with the low-frequency clock c, and synchronously resets the direct frequency synthesis unit for generating the complex baseband point frequency test signal e and the digital up-conversion unit for interpolating and digitally up-converting the complex baseband point frequency test signal e through the phase reset signal j.

[0033] A delay start-up stability test device for a frequency conversion transmitter proposed by the present invention includes:

[0034] A waveform generation and preprocessing module, configured to generate a complex baseband point frequency test signal e when the frequency conversion transmitter is powered off and restarted, and preprocess the complex baseband point frequency test signal e to obtain a corresponding radio frequency test signal h;

[0035] A first processing module, configured to obtain a reference clock b, trigger at the rising edge of the reference clock b, and collect the radio frequency test signal h to obtain the phase value i of the radio frequency test signal h at the trigger moment;

[0036] A second processing module, configured to power off and restart the frequency conversion transmitter according to a preset number of restart times, and repeat the processing through the waveform generation and preprocessing module and the first processing module to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband point frequency test signal e generated in each power-off restart stage at the trigger moment;

[0037] A third processing module, configured to screen the phase values i collected at the trigger moment in each power-off restart stage to obtain the maximum value and the minimum value of the phase values i collected at the trigger moment in each power-off restart stage, and calculate the phase difference s between the maximum value and the minimum value of the phase values i;

[0038] An output module, configured to determine that the delay start-up of the main signal link of the frequency conversion transmitter is stable when the phase difference s is within a preset phase difference range;

[0039] The specific preset phase difference range is:

[0040]

[0041] where K is a constant less than 1; f e is the frequency of the complex baseband point frequency test signal e; f nco is the frequency of the digital local oscillator used for digital up-conversion; f dac is the conversion clock frequency of the DAC.

[0042] Preferably, the waveform generation and preprocessing module specifically includes:

[0043] A direct frequency synthesis unit, configured to generate a complex baseband point frequency test signal e;

[0044] A digital up-conversion unit is used to perform interpolation and digital up-conversion processing on the complex baseband point-frequency test signal e to obtain an intermediate-frequency digital test signal f;

[0045] A clock domain conversion unit is used to perform clock domain conversion and interface adaptation conversion on the intermediate-frequency digital test signal f to obtain an intermediate-frequency digital test signal k;

[0046] A digital-to-analog conversion unit is used to perform digital-to-analog conversion on the intermediate-frequency digital test signal k to obtain an intermediate-frequency analog test signal g;

[0047] A radio frequency channel unit is used to perform analog up-conversion, filtering, and amplification on the intermediate-frequency analog test signal g to obtain a radio frequency test signal h.

[0048] Preferably, the waveform generation and preprocessing module further includes: a phase zeroing unit, which is used to generate a phase zeroing signal j synchronized with the low-frequency clock c after the frequency conversion transmitter is powered on, and synchronously reset the direct frequency synthesis unit and the digital up-conversion unit through the phase zeroing signal j.

[0049] In the present invention, the proposed method and device for testing the delay-on stability of a frequency conversion transmitter generate a complex baseband point-frequency test signal e when the frequency conversion transmitter is powered off and restarted, and perform preprocessing on the complex baseband point-frequency test signal e to obtain a corresponding radio frequency test signal h; obtain a reference clock b, trigger at the rising edge of the reference clock b, and collect the radio frequency test signal h to obtain the phase value i of the radio frequency test signal h at the trigger moment; power off and restart the frequency conversion transmitter according to a preset number of restart times, and repeat step S1 and step S2 to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband point-frequency test signal e generated in each power-off and restart stage at the trigger moment; screen the phase values i collected at the trigger moment in each power-off and restart stage to obtain the maximum value and the minimum value of the phase values i collected at the trigger moment in each power-off and restart stage, and calculate the phase difference s between the maximum value and the minimum value of the phase values i; when the phase difference s is within a preset phase difference range, it is determined that the delay-on stability of the main signal link of the frequency conversion transmitter is stable. By controlling the frequency relationship of the clock, local oscillator, and numerically controlled oscillator, and applying synchronization technology, the problem of testing the delay-on stability of the main signal link of the frequency conversion transmitter is transformed into the problem of testing the phase of the radio frequency signal, so as to accurately and efficiently test whether the link delay between multiple power-on of a single frequency conversion transmitter remains stable. Compared with the prior art, the present invention only requires common instruments and cables, without the need to rely on external complex software and hardware systems, significantly simplifies the test process, reduces the equipment requirements and test costs. The present invention has significant significance in application scenarios of calibration-free phased arrays that require rapid deployment and need to avoid being easily interfered during the calibration process, improves the test efficiency, and provides strong support for batch testing of frequency conversion transmitters. Description of the Drawings

[0050] Figure 1 Schematic diagram of the working process of a method for testing the stability of delayed startup of a variable-frequency transmitter proposed by the present invention;

[0051] Figure 2 Schematic diagram of the device architecture of a device for testing the stability of delayed startup of a variable-frequency transmitter proposed by the present invention;

[0052] Figure 3 Schematic diagram of the waveform generation and preprocessing module structure of a device for testing the stability of delayed startup of a variable-frequency transmitter proposed by the present invention;

[0053] Figure 4 Schematic diagram of the digital up-conversion unit structure of a device for testing the stability of delayed startup of a variable-frequency transmitter proposed by the present invention. Specific implementation manner

[0054] Referring to Figures 1-4 , a method for testing the stability of delayed startup of a variable-frequency transmitter proposed by the present invention includes the following steps:

[0055] S1. When the variable-frequency transmitter is powered off and restarted, a complex baseband point-frequency test signal e is generated, and the complex baseband point-frequency test signal e is preprocessed to obtain a corresponding radio frequency test signal h.

[0056] In this embodiment, the preprocessing specifically includes: performing interpolation and digital up-conversion processing on the complex baseband point-frequency test signal e to obtain an intermediate-frequency digital test signal f; performing clock domain conversion and interface adaptation conversion on the intermediate-frequency digital test signal f to obtain an intermediate-frequency digital test signal k; performing digital-to-analog conversion on the intermediate-frequency digital test signal k to obtain an intermediate-frequency analog test signal g; performing analog up-conversion, filtering, and amplification on the intermediate-frequency analog test signal g to obtain a radio frequency test signal h.

[0057] S2. Obtain a reference clock b, trigger with the rising edge of the reference clock b, and collect the radio frequency test signal h to obtain the phase value i of the radio frequency test signal h at the trigger moment.

[0058] In this embodiment, in step S2, the reference clock b is generated by the frequency source of the variable-frequency transmitter. The frequency source of the variable-frequency transmitter also generates a radio frequency local oscillator clock a, and the radio frequency local oscillator clock a is homologous with the reference clock b; the frequency synthesizer of the variable-frequency transmitter generates a low-frequency clock c and a system working clock d whose initial rising edge is aligned with the rising edge of the reference clock b.

[0059] In this embodiment, the relationship among the frequency of the digital local oscillator used in the digital up-conversion processing, the frequency of the complex baseband point-frequency test signal e, and the frequency of the low-frequency clock c is as follows:

[0060] f e +fnco = M × f c ;

[0061] Where, M is an arbitrary positive integer; f nco is the frequency of the digital local oscillator; f e is the frequency of the complex baseband point-frequency test signal e; f c is the frequency of the low-frequency clock c.

[0062] In this embodiment, the relationship between the frequency of the radio frequency local oscillator clock a and the frequency of the low-frequency clock c is as follows:

[0063] f a = N × f c ;

[0064] Where, N is an arbitrary positive integer; f a is the frequency of the radio frequency local oscillator clock a; f c is the frequency of the low-frequency clock c;

[0065] The relationship between the frequency of the reference clock b, the frequency of the low-frequency clock c, and the frequency of the system working clock d is as follows:

[0066] f c = P × f b ;

[0067] f d = R × f c ;

[0068] Where, P and R are arbitrary positive integers; f b is the frequency of the reference clock b; f c is the frequency of the low-frequency clock c; f d is the frequency of the system working clock d.

[0069] In this embodiment, the frequency f of the radio frequency local oscillator clock a a is 1 GHz, the frequency f of the reference clock b b is 10 MHz, the frequency f of the low-frequency clock c c is 10 MHz, the frequency f of the system working clock d d is 200 MHz. Thus, N = 100, P = 1, R = 20.

[0070] Exemplarily, the sampling rate of the complex baseband point-frequency test signal e may not be equal to the sampling rate of the intermediate frequency digital test signal f. At this time, the interpolation multiple I is not equal to 1.

[0071] In this embodiment, the frequency f of the complex baseband point-frequency test signal e eis 20 MHz, the sampling rate is 50 MSPS (a signal sampling rate of 50 MSPS is achieved using a 1 / 4 duty cycle signal under a system operating clock d of 200 MHz), and the frequency f of the digital local oscillator used for digital upconversion nco is 150 MHz, the frequency of the low-frequency clock c is 10 MHz, the interpolation multiple I = 4, and M = 17. Thus, the frequency of the intermediate-frequency digital test signal f is 170 MHz, and the sampling rate is 200 MSPS.

[0072] In this embodiment, the conversion frequency of the digital-to-analog converter is equal to the sampling rate of the intermediate-frequency digital test signal f. The clock domain conversion is to switch the intermediate-frequency digital test signal f from the system operating clock domain to the DAC conversion clock domain, and the interface adaptation is to convert the intermediate-frequency digital test signal f into the data format required by the DAC.

[0073] In the embodiment of the present invention, the DAC conversion frequency is 200 MSPS.

[0074] In this embodiment, after analog upconversion, bandpass filtering, and amplification of the intermediate-frequency digital test signal f with a frequency of 170 MHz using a local oscillator with a frequency of 1 GHz, a radio frequency test signal h with a frequency of 1170 MHz is obtained.

[0075] In this embodiment, the reference clock b and the radio frequency test signal h are connected to a high-speed oscilloscope. Triggered by the rising edge of the reference clock b, the radio frequency test signal h is collected, and the phase value i of the radio frequency test signal h at the trigger moment is recorded;

[0076] Exemplarily, a high-speed oscilloscope with two channels, an analog bandwidth of 3 GHz, and a maximum sampling rate of 10 GS / s can be selected. The reference clock b and the radio frequency test signal h are respectively connected to the two channels of the oscilloscope. The reference clock b is used as the acquisition trigger signal to collect the radio frequency test signal h. The oscilloscope can automatically calculate the phase of the radio frequency test signal h, or the phase can be determined by observing the waveform.

[0077] S3. Power off and restart the frequency conversion transmitter according to the preset number of restart times, and repeat steps S1 and S2 to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband dot frequency test signal e generated in each power-off and restart stage at the trigger moment.

[0078] S4. Screen the phase values i collected at the trigger moment in each power-off and restart stage to obtain the maximum and minimum values of the phase values i collected at the trigger moment in each power-off and restart stage, and calculate the phase difference s between the maximum and minimum values of the phase values i.

[0079] S5. When the phase difference s is within the preset phase difference range, it is determined that the main signal link of the frequency conversion transmitter delays to start up stably.

[0080] In this embodiment, the preset phase difference range is specifically:

[0081]

[0082] where K is a constant less than 1; f e is the frequency of the complex baseband point frequency test signal e; f nco is the frequency of the digital local oscillator used for digital upconversion; f dac is the conversion clock frequency of the DAC.

[0083] In this embodiment, it further includes:

[0084] After the frequency conversion transmitter is powered on, the frequency conversion transmitter generates a phase clear signal j synchronized with the low-frequency clock c, and synchronously resets the direct frequency synthesis unit for generating the complex baseband point frequency test signal e and the digital upconversion unit for interpolating and digitally upconverting the complex baseband point frequency test signal e through the phase clear signal j.

[0085] Specifically, every time the frequency conversion transmitter is powered on, a phase clear signal j synchronized with the low-frequency clock c is generated, and the phase clear signal j and the system working clock d need to meet the setup and hold time requirements in terms of timing to synchronously reset the direct frequency synthesis unit and the digital upconversion unit.

[0086] It should be noted that the purpose of doing this is to align the initial phase of the generated intermediate frequency digital test signal f with the rising edge of the low-frequency clock c, and further with the rising edge of the reference clock b. In addition, when synchronously resetting the digital upconversion unit, specifically, the interpolation filtering unit and the numerically controlled oscillator inside the module are reset.

[0087] Exemplarily, after the frequency conversion transmitter is powered on, a pulse signal with a width of 1 low-frequency clock c period can be generated using the low-frequency clock c as the phase clear signal j, and the phase clear signal j and the system working clock d need to meet the setup and hold time requirements in terms of timing through timing constraints.

[0088] Specifically, during multiple power-off and restart processes of the frequency conversion transmitter, if the change in the phase value i observed on the oscilloscope is less than then it is determined that the link delay of the frequency conversion transmitter is stable every time it is powered on, otherwise it is unstable. In the formula, K is a constant less than 1, f e is the frequency of the complex baseband point frequency test signal e, f nco is the frequency of the digital local oscillator used for digital upconversion, f dac is the conversion clock frequency of the DAC.

[0089] K is taken as 0.5. Therefore, during multiple power-off and restart processes of the frequency conversion transmitter, if the change in the phase value i observed on the oscilloscope is less than If it is considered that the change of the variable-frequency transmitter link delay at each power-on is less than one DAC conversion clock cycle, it can be determined that the link delay is stable at power-on; otherwise, it is unstable.

[0090] Refer to Figures 1-4 , a variable-frequency transmitter delay power-on stability test device proposed by the present invention includes:

[0091] A waveform generation and preprocessing module, which is used to generate a complex baseband point-frequency test signal e when the variable-frequency transmitter is powered off and restarted, and preprocess the complex baseband point-frequency test signal e to obtain a corresponding radio frequency test signal h.

[0092] A first processing module, which is used to obtain a reference clock b, trigger on the rising edge of the reference clock b, and collect the radio frequency test signal h to obtain the phase value i of the radio frequency test signal h at the trigger moment.

[0093] A second processing module, which is used to power off and restart the variable-frequency transmitter according to a preset number of restarts, and repeat the processing through the waveform generation and preprocessing module and the first processing module to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband point-frequency test signal e generated in each power-off and restart stage at the trigger moment.

[0094] A third processing module, which is used to screen the phase values i collected at the trigger moment in each power-off and restart stage to obtain the maximum value and the minimum value of the phase values i collected at the trigger moment in each power-off and restart stage, and calculate the phase difference s between the maximum value and the minimum value of the phase values i;

[0095] An output module, which is used to determine that the main signal link delay of the variable-frequency transmitter is stable at power-on when the phase difference s is within a preset phase difference range;

[0096] The specific preset phase difference range is:

[0097]

[0098] where K is a constant less than 1; f e is the frequency of the complex baseband point-frequency test signal e; f nco is the frequency of the digital local oscillator used for digital upconversion; f dac is the conversion clock frequency of the DAC.

[0099] In this embodiment, as Figure 3 shown, the waveform generation and preprocessing module specifically includes:

[0100] A direct frequency synthesis unit, which is used to generate a complex baseband point-frequency test signal e;

[0101] A digital up-conversion unit is used to perform interpolation and digital up-conversion processing on the complex baseband point-frequency test signal e to obtain an intermediate-frequency digital test signal f.

[0102] A clock domain conversion unit is used to perform clock domain conversion and interface adaptation conversion on the intermediate-frequency digital test signal f to obtain an intermediate-frequency digital test signal k.

[0103] A digital-to-analog conversion unit is used to perform digital-to-analog conversion on the intermediate-frequency digital test signal k to obtain an intermediate-frequency analog test signal g.

[0104] A radio frequency channel unit is used to perform analog up-conversion, filtering, and amplification on the intermediate-frequency analog test signal g to obtain a radio frequency test signal h.

[0105] In an embodiment of the present invention, as Figure 4 shown, the digital up-conversion unit includes: an interpolation filter unit, a numerically controlled oscillator (NCO), a multiplier, and a subtractor;

[0106] Among them, the interpolation filter unit is used to perform digital interpolation and low-pass filtering on the real part and the imaginary part of the complex baseband point-frequency test signal e respectively, output signals m and n to the multiplier respectively, and reset the interpolation filter unit using the phase clear signal j;

[0107] The numerically controlled oscillator is used to output the real part o and the imaginary part p of the digital local oscillator to the multiplier respectively, and reset the numerically controlled oscillator using the phase clear signal j;

[0108] The multiplier is used to multiply signals m and o respectively to output signal q, and multiply n and p to output signal r;

[0109] The subtractor is used to subtract signal r from signal q and output the intermediate-frequency digital test signal f.

[0110] In this embodiment, the waveform generation and preprocessing module further includes: a phase clear unit, which is used to generate a phase clear signal j synchronized with the low-frequency clock c after the frequency conversion transmitter is powered on, and synchronously reset the direct frequency synthesis unit and the digital up-conversion unit through the phase clear signal j.

[0111] In this embodiment, the waveform generation and preprocessing module further includes:

[0112] A frequency source is used to output a radio frequency local oscillator clock a and a reference clock b of the same source, where the radio frequency local oscillator clock a is sent to the radio frequency channel, and the reference clock b is sent to the frequency synthesizer and the high-speed oscilloscope respectively;

[0113] A frequency synthesizer is used to output a low-frequency clock c whose initial rising edge is aligned with the rising edge of a reference clock b and a system operating clock d. The low-frequency clock c is sent to a phase clear unit, and the system operating clock d is sent to a direct frequency synthesis unit, a digital up-conversion unit, and a clock domain conversion unit.

[0114] As described above, only the preferred specific embodiments of the present invention are provided, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, making equivalent substitutions or changes, shall be covered by the protection scope of the present invention.

Claims

1. A method for testing the stability of delayed startup of a frequency conversion transmitter, characterized in that: The following steps are involved: S1. When the frequency conversion transmitter is powered off and restarted, a complex baseband frequency test signal e is generated and preprocessed to obtain a corresponding radio frequency test signal h. S2. Obtain a reference clock b, and use the rising edge of the reference clock b as a trigger to collect a radio frequency test signal h to obtain a phase value i of the radio frequency test signal h at the triggering moment; S3, powering off and restarting the frequency conversion transmitter according to a preset restart number, and repeating steps S1 and S2 to obtain the phase value i of the radio frequency test signal h corresponding to the complex baseband point frequency test signal e generated in each power-off and restart stage at the triggering moment; S4. Filter the phase values i collected at the triggering moment in each power-off and restart phase to obtain the maximum and minimum values of the phase values i collected at the triggering moment in each power-off and restart phase, and calculate the phase difference s between the maximum and minimum values of the phase values i; S5. When the phase difference value s is within the preset phase difference value range, it is determined that the delayed startup of the main signal link of the frequency conversion transmitter is stable; The preset phase difference range is specifically: ; Wherein, K is a constant less than 1; is the frequency of the complex baseband frequency test signal e; The frequency of the digital local oscillator used for digital up-conversion; is the conversion clock frequency of the DAC.

2. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 1, characterized in that: The pretreatment specifically includes: Performing interpolation and digital up-conversion processing on the complex baseband point frequency test signal e to obtain an intermediate frequency digital test signal f; Performing clock domain conversion and interface adaptation conversion on the intermediate frequency digital test signal f to obtain an intermediate frequency digital test signal k; Performing digital-to-analog conversion on the intermediate frequency digital test signal k to obtain an intermediate frequency analog test signal g; The intermediate frequency analog test signal g is analog up-converted, filtered, and amplified to obtain a radio frequency test signal h.

3. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 2, characterized in that: In step S2, the reference clock b is generated by the frequency source of the frequency conversion transmitter, and the frequency source of the frequency conversion transmitter also generates the radio frequency local oscillator clock a, which is the same source as the reference clock b; the frequency synthesizer of the frequency conversion transmitter generates a low-frequency clock c and a system working clock d whose initial rising edge is aligned with the rising edge of the reference clock b.

4. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 2 or 3, characterized in that: The relationship between the frequency of the digital local oscillator used in the digital up-conversion process, the frequency of the complex baseband frequency test signal e, and the frequency of the low-frequency clock c is as follows: ; Where M is any positive integer; is the frequency of the low-frequency clock c.

5. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 3, characterized in that: The relationship between the frequency of the RF local oscillator clock a and the frequency of the low-frequency clock c is as follows: ; Wherein, N is any positive integer; is the frequency of the RF local oscillator clock a; is the frequency of the low-frequency clock c; The relationship between the frequency of the reference clock b, the frequency of the low-frequency clock c, and the frequency of the system working clock d is as follows: Wherein, P and R are any positive integers; is the frequency of reference clock b; The frequency of the system working clock d.

6. The method for testing the stability of delayed startup of a frequency conversion transmitter according to claim 2, characterized in that: Also includes: After the frequency conversion transmitter is turned on, the frequency conversion transmitter generates a phase clear signal j synchronized with the low-frequency clock c. The phase clear signal j is used to synchronously reset a direct frequency synthesis unit for generating a complex baseband point frequency test signal e and a digital up-conversion unit for performing interpolation and digital up-conversion processing on the complex baseband point frequency test signal e.

7. A device for testing the stability of delayed startup of a frequency conversion transmitter, characterized in that: include: The waveform generation and preprocessing module is used to generate a complex baseband frequency test signal e when the frequency conversion transmitter is powered off and restarted, and preprocess the complex baseband frequency test signal e to obtain a corresponding radio frequency test signal h; The first processing module is configured to obtain a reference clock b, and use the rising edge of the reference clock b as a trigger to collect a radio frequency test signal h to obtain a phase value i of the radio frequency test signal h at the triggering moment; A second processing module is configured to power off and restart the frequency conversion transmitter according to a preset number of restart times, and repeatedly process the waveform generation and preprocessing module and the first processing module to obtain a phase value i at a triggering moment of a radio frequency test signal h corresponding to a complex baseband point frequency test signal e generated in each power-off and restart stage; a third processing module, configured to filter the phase values i collected at the triggering moment in each power-off and restart phase to obtain the maximum and minimum values of the phase values i collected at the triggering moment in each power-off and restart phase, and calculate the phase difference s between the maximum and minimum values of the phase values i; The output module is used to determine that the delayed startup of the main signal link of the frequency conversion transmitter is stable when the phase difference value s is within a preset phase difference value range; The preset phase difference range is specifically: ; Wherein, K is a constant less than 1; is the frequency of the complex baseband frequency test signal e; The frequency of the digital local oscillator used for digital up-conversion; is the conversion clock frequency of the DAC.

8. The device for testing the stability of delayed startup of a frequency conversion transmitter according to claim 7, characterized in that: The waveform generation and preprocessing module specifically includes: Direct frequency synthesis unit, used to generate complex baseband frequency test signal e; A digital up-conversion unit is used to perform interpolation and digital up-conversion processing on the complex baseband point frequency test signal e to obtain an intermediate frequency digital test signal f; A clock domain conversion unit, configured to perform clock domain conversion and interface adaptation conversion on the intermediate frequency digital test signal f to obtain an intermediate frequency digital test signal k; A digital-to-analog conversion unit, configured to perform digital-to-analog conversion on an intermediate frequency digital test signal k to obtain an intermediate frequency analog test signal g; The radio frequency channel unit is used to perform analog up-conversion, filtering and amplification on the intermediate frequency analog test signal g to obtain a radio frequency test signal h.

9. The device for testing the stability of delayed startup of a frequency conversion transmitter according to claim 8, characterized in that: The waveform generation and preprocessing module also includes: The phase clearing unit is used to generate a phase clearing signal j synchronized with the low-frequency clock c after the frequency conversion transmitter is turned on, and synchronously reset the direct frequency synthesis unit and the digital up-conversion unit through the phase clearing signal j.

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