Constant modulus modulation signal timing synchronization method based on feedforward link

Abstract

The invention relates to a constant modulus modulation signal timing synchronization method based on a feed-forward link, which comprises the following steps of: roughly estimating a timing error, and estimating an optimal integer sampling point by utilizing the constant modulus characteristic of a digital modulation signal; precise estimation of the timing error: searching within a range of + / -0.5 sampling points of the optimal integer sampling points on the basis of the rough estimation of the timing error to obtain the position of the optimal decimal sampling point; finalDelay delay is carried out on an input signal, so that a first sampling point of the delayed signal is an optimal sampling point. According to the method, the timing error is estimated for the digital modulation signal with the constant modulus characteristic, modulus square data is used, the method is not sensitive to frequency offset and phase offset errors, and the timing error can be estimated and removed under the condition that the frequency offset and the phase offset exist. The method is a method based on a feed-forward link, has no feedback loop, is based on statistical characteristics in rough estimation, is adjustable in precise estimation step, is high in operation speed and high in precision, and is convenient for engineering realization.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a constant modulus modulation signal timing synchronization method based on a feedforward link. Background Art

[0002] In communication systems, the clock asynchrony between the receiver and transmitter is a common problem, which will cause phase errors in the signal during transmission, thus affecting the correct reception and demodulation of the signal. In order to solve this problem, the receiver needs to maintain a certain degree of synchronization with the transmitter to ensure that the sampling time is consistent with the optimal sampling time of the signal, thereby avoiding phase errors and phase rotation in the frequency domain. This synchronization is crucial to ensure the stability and reliability of the communication system.

[0003] In the existing technology, common methods for timing synchronization include the Gardner algorithm, which is a feedback link. It cannot estimate the timing error of the signal through a rough estimation and a fine estimation method for a digital modulation signal with a constant mode characteristic, and then compensate for the timing error. In addition, its operation speed is slow and difficult to implement. Summary of the invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a constant modulus modulation signal timing synchronization method based on a feedforward link, which estimates the timing error of the signal by a rough estimation and a fine estimation method for a digital modulation signal with a constant modulus characteristic, and then compensates for the timing error. The method has no feedback loop, fast operation speed and is easy to implement in engineering.

[0005] The above-mentioned object of the present invention is achieved through the following technical solutions:

[0006] A constant modulus modulation signal timing synchronization method based on a feedforward link comprises the following steps:

[0007] Step 1: Roughly estimate the timing error by using the constant mode characteristic of the digital modulation signal to estimate the optimal integer sampling point;

[0008] Step 2, precise estimation of the timing error, based on the rough estimation of the timing error, searching within the range of ±0.5 sampling points of the best integer sampling point to obtain the best decimal sampling point position;

[0009] Step 3: Delay the input signal by finalDelay so that the first sampling point of the delayed signal is the optimal sampling point.

[0010] As a further technical solution of the present invention: the step 1 specifically comprises the following steps:

[0011] Step 1a, normalize the power of the input signal so that the modulus value is close to 1, calculate the modulus square data of the signal, and perform power normalization processing on the input data;

[0012] Step 1b, estimating the best integer sampling point position;

[0013] Assuming that the number of sampling points in a symbol time interval is nsmp, if the sampling rate is fs and the symbol rate is fb, then the following formula is obtained:

[0014]

[0015] For digital signal demodulation, the sampling rate is generally processed before demodulation to make the oversampling multiple nsmp an integer. Later, a sampling point is taken in each symbol time interval to judge the symbol. This sampling point is the best sampling point. If there is a timing error and the judgment position is inaccurate, the EVM (error vector amplitude) of the demodulated data will become larger or even the judgment will be wrong. This step is to use the method of minimum constant modulus error to obtain the best sampling point position for nsmp sampling points in a symbol interval;

[0016] In the previous step, the power-normalized modulus square data has been obtained, and its reference value is 1. If the optimal sampling point position is pts, 0≤pts≤nsmp-1, the data of each symbol is taken to calculate the error. The specific formula is as follows:

[0017] The number of symbols is:

[0018]

[0019] The location of the sampling point for each symbol is:

[0020] pts,pts+nsmp,pts+2·nsmp,…,pts+(Nsym-1)·nsmp

[0021] The sum of squared errors is:

[0022]

[0023] Recording data:

[0024] errVec[pts] = err pts

[0025] When 0≤pts≤nsmp-1, all points' err pts After the calculation is completed, the minimum error is searched to obtain the optimal integer sampling point position:

[0026]

[0027] As a further technical solution of the present invention: in step 1a;

[0028] The average power of the input signal is:

[0029]

[0030] The square of the input signal is:

[0031]

[0032] Where N is the number of sampling points of the input signal, I i , Q i is the IQ data of the i-th sampling point, i=0, 1, ..., N-1, and the input data power is normalized using the following formula:

[0033]

[0034] As a further technical solution of the present invention: the step 2 specifically comprises the following steps:

[0035] Step 2a, estimating the optimal decimal sampling point position;

[0036] For the error array errVec, the minimum value is at index1. Now it is necessary to perform a delay process of -0.5 to 0.5 on errVec to obtain the minimum error position with a smaller granularity.

[0037] Starting from a delay of -0.5, calculate the minimum error after each delay step by step;

[0038] If the current fractional delay value is delay, where -0.5≤delay≤0.5, delay=-0.5+cnt·step, cnt=0,1,...,Count-1,

[0039] The specific process of delay processing is as follows:

[0040] (e) Perform FFT of nsmp points on the array errVec;

[0041] yfft=FFT{errVec}

[0042] (f) Calculate the linear phase with delay delay;

[0043]

[0044] Where n = 0, 1, ..., nsmp-1

[0045] (g) Loading linear phase;

[0046] yfft′[n]=yfft[n]·e j·phase [n]

[0047] (h) Perform IFFT of the nsmp point and take the real part as output;

[0048] errVec delay =real(IFFT{yfft′})

[0049] Take the minimum error after delay and record it in the array:

[0050] srch Vec[cnt]=errVec delay [index1]

[0051] When the minimum error after Count delays is calculated, search for the minimum value of srch Vec to get the optimal fractional delay position:

[0052]

[0053] Step 2b, calculate the final timing error timingErr and the delay value finalDelay that needs to be processed;

[0054] timingErr=index1-(-0.5+index2·step)

[0055] finalDelay=nsmp-timingErr.

[0056] As a further technical solution of the present invention: it also includes a method for verifying and processing the timing error, which specifically includes the following steps:

[0057] Step S1, error signal generation, first generate an ideal digital baseband signal according to the configuration parameters, then add Gaussian white noise, and then add timing error;

[0058] Step S2, error analysis and calculation, roughly estimate the timing error, output the data after compensating the positive timing error, then accurately estimate the timing error, output the data after compensating the final timing error, and finally calculate the EVM under the three types of data and draw the eye diagram for analysis.

[0059] In summary, the present invention includes at least one of the following beneficial technical effects:

[0060] The present invention discloses a timing synchronization method for constant modulus modulation signal based on a feedforward link. The method estimates the timing error for a digital modulated signal with constant modulus characteristics, uses modulus square data, is insensitive to frequency deviation and phase deviation errors, and can estimate the timing error and remove the timing error in the presence of frequency deviation and phase deviation. The method is a method based on a feedforward link, has no feedback loop, has a rough estimate based on statistical characteristics, and has an adjustable step for fine estimate, has a fast operation speed, high accuracy, and is easy to implement in engineering. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 This is the timing error rough estimation and precise estimation process of the present invention.

[0062] Figure 2 This is the timing error verification process flow of the present invention.

[0063] Figure 3 This is the constellation diagram of the QPSK signal under three types of data of the present invention.

[0064] Figure 4 This is the eye diagram of the QPSK signal under three types of data of the present invention.

[0065] Figure 5 This is the constellation diagram of the 8PSK signal under three types of data of the present invention.

[0066] Figure 6 This is the eye diagram of the 8PSK signal under three types of data of the present invention. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application; obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments, and all other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application without making creative work are within the scope of protection of the present application.

[0068] Embodiment 1:

[0069] Reference Figure 1 The present invention discloses a timing synchronization method of a constant modulus modulation signal based on a feedforward link, comprising the following steps:

[0070] Step 1: Roughly estimate the timing error by using the constant mode characteristic of the digital modulation signal to estimate the optimal integer sampling point;

[0071] Step 2: accurately estimate the timing error. On the basis of the rough estimation of the timing error, search within the range of ±0.5 sampling points of the best integer sampling point to obtain the best decimal sampling point position.

[0072] Step 3: Delay the input signal by finalDelay so that the first sampling point of the delayed signal is the best sampling point. The above has used the rough estimation and fine estimation of the timing error to obtain a timing error with high accuracy. It is necessary to delay the input signal accordingly so that the first sampling point of the delayed signal is the best sampling point. The delay process is similar to the process in the timing error fine estimation, except that the former is for real data and the latter is for complex data, which will not be repeated here.

[0073] This paper estimates the timing error of constant modulus digital modulation signals and calculates the optimal sampling time for the input baseband digital signal with integer oversampling multiples. The overall process is divided into two steps: coarse timing error estimation and precise timing error estimation. The coarse timing error estimation uses the constant modulus characteristics of the digital modulation signal to estimate the optimal integer sampling point; the precise timing error estimation searches within the range of ±0.5 sampling points of the optimal integer sampling point based on the coarse estimation to obtain the optimal decimal sampling point position.

[0074] The following are IQ values ​​of constellation points of BPSK, QPSK, and 8PSK. Although the present invention uses MPSK as an example to illustrate the principle, the present method is applicable to all digital modulation types with constant mode characteristics.

[0075]

[0076] Step 1 specifically includes the following steps:

[0077] Step 1a, normalize the power of the input signal so that the modulus value is close to 1, calculate the modulus square data of the signal, and perform power normalization processing on the input data;

[0078] In said step 1a;

[0079] The average power of the input signal is:

[0080]

[0081] The square of the input signal is:

[0082]

[0083] Where N is the number of sampling points of the input signal, I i , Q i is the IQ data of the i-th sampling point, i = 0, 1, ..., N-1, and the input data power is normalized using the following formula:

[0084]

[0085] Step 1b, estimating the best integer sampling point position;

[0086] Assuming that the number of sampling points in a symbol time interval is nsmp, if the sampling rate is fs and the symbol rate is fb, then the following formula is obtained:

[0087]

[0088] For digital signal demodulation, the sampling rate is generally processed before demodulation to make the oversampling multiple nsmp an integer. Later, a sampling point is taken in each symbol time interval to judge the symbol. This sampling point is the best sampling point. If there is a timing error and the judgment position is inaccurate, the EVM (error vector amplitude) of the demodulated data will become larger or even the judgment will be wrong. This step is to use the method of minimum constant modulus error to obtain the best sampling point position for nsmp sampling points in a symbol interval;

[0089] In the previous step, the power-normalized modulus square data has been obtained, and its reference value is 1. If the optimal sampling point position is pts, 0≤pts≤nsmp-1, the data of each symbol is taken to calculate the error. The specific formula is as follows:

[0090] The number of symbols is:

[0091]

[0092] The location of the sampling point for each symbol is:

[0093] pts, pts+nsmp, pts+2·nsmp,..., pts+(Nsym-1)·nsmp

[0094] The sum of squared errors is:

[0095]

[0096] Recording data:

[0097] errVec[pts] = err pts

[0098] When 0≤pts≤nsmp-1, all points' err pts After the calculation is completed, the minimum error is searched to obtain the optimal integer sampling point position:

[0099]

[0100] After the timing error is roughly estimated, only the best integer sampling point position is obtained. When the receiver samples the received data, its sampling time is often not the best decision position of the symbol. Therefore, in order to improve the accuracy of the timing error estimation and thus reduce the EVM, it is necessary to estimate the fractional timing error.

[0101] After rough estimation, the best integer sampling point position index1 has been obtained. If fractional moments are taken into account, the best fractional sampling point position is estimated within the sampling moment range of [index1-0.5, index1+0.5].

[0102] Step 2 specifically includes the following steps:

[0103] Step 2a, estimating the optimal decimal sampling point position;

[0104] For the error array errVec, the minimum value is at index1. Now it is necessary to perform a delay process of -0.5 to 0.5 on errVec to obtain the minimum error position with a smaller granularity.

[0105] Starting from a delay of -0.5, calculate the minimum error after each delay step by step;

[0106] If the current fractional delay value is delay, where -0.5≤delay≤0.5, delay=-0.5+cnt·step, cnt=0,1,...,Count-1,

[0107] The specific process of delay processing is as follows:

[0108] (i) Perform FFT of nsmp points on the array errVec;

[0109] yfft=FFT{errVec}

[0110] (j) Calculate the linear phase with delay delay;

[0111]

[0112] Where n = 0, 1, ..., nsmp-1

[0113] (k) Loading linear phase;

[0114] yfft′[n]=yfft[n]·e j·phase [n]

[0115] (I) perform IFFT of nsmp points and take the real part output;

[0116] errVec delay =real(IFFT{yfft′})

[0117] Take the minimum error after delay and record it in the array:

[0118] srch Vec[cnt]=errVec delay [index1]

[0119] When the minimum error after Count delays is calculated, search for the minimum value of srch Vec to get the optimal fractional delay position:

[0120]

[0121] Step 2b, calculate the final timing error timingErr and the delay value finalDelay that needs to be processed;

[0122] timingErr=index1-(-0.5+index2·step)

[0123] finalDelay=nsmp-timingErr.

[0124] The present invention also includes a method for verifying and processing a timing error, which specifically includes the following steps:

[0125] Step S1, error signal generation, first generate an ideal digital baseband signal according to the configuration parameters, then add Gaussian white noise, and then add timing error;

[0126] Step S2, error analysis and calculation, roughly estimate the timing error, output the data after compensating the positive timing error, then accurately estimate the timing error, output the data after compensating the final timing error, and finally calculate the EVM under the three types of data and draw the eye diagram for analysis.

[0127] The present invention uses QPSK and 8PSK signals to simulate and verify the above estimation method. The specific processing flow is as follows: Figure 2 As shown. First, configure the simulation environment, generate a baseband modulation signal with noise and timing error according to the modulation type, oversampling multiple, signal-to-noise ratio, timing error, etc., use the estimation method described above to estimate the timing error, and compare the EVM and eye diagram of the following three types of data: (1) data when the original signal is noisy and has no timing error; (2) data after compensating for integer timing errors; (3) data after compensating for the final timing error. The specific configuration parameters are shown in the following table:

[0128] Modulation type QPSK 8PSK Oversampling multiple 8 8 Shaping filter Raised cosine, factor: 0.35 Raised cosine, factor: 0.35 Signal-to-Noise Ratio 40dB 40dB Loading Timing Error Delay 0.3 sampling points Delay 1.47 samples

[0129] The final timing error estimate and EVM calculation results are shown in the following table:

[0130] Modulation type QPSK 8PSK Final timing error estimate 0.31 1.465 EVM of Data 1 0.977％ 0.955％ EVM of Data 2 5.11％ 7.872％ EVM of Data 3 0.987％ 0.958％

[0131] Constellation diagram and eye diagram Figure 3 , Figure 4 , Figure 5 , Figure 6 shown.

[0132] From the simulation results, it can be seen that this method can estimate the timing error of the signal. Compared with the data after integer point timing error compensation, the EVM is smaller. It can also be seen from the eye diagram that the timing position is more accurate.

[0133] This method estimates the timing error for digital modulation signals with constant mode characteristics. It uses modulus square data and is insensitive to frequency offset and phase offset errors. It can estimate the timing error and remove the timing error in the presence of frequency offset and phase offset. This method is based on a feedforward link and has no feedback loop. The rough estimate is based on statistical characteristics, and the fine estimate step is adjustable. It has fast operation speed, high accuracy, and is easy to implement in engineering.

[0134] The embodiments of this specific implementation method are all preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Therefore, any equivalent changes made based on the structure, shape, and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A constant modulus modulation signal timing synchronization method based on a feedforward link, characterized in that: The following steps are involved: Step 1: Roughly estimate the timing error by using the constant mode characteristic of the digital modulation signal to estimate the optimal integer sampling point; Step 2: precise estimation of the timing error, based on the rough estimation of the timing error, searching within the range of ±0.5 sampling points of the best integer sampling point to obtain the best decimal sampling point position; Step 3: Delay the input signal by finalDelay so that the first sampling point of the delayed signal is the optimal sampling point.

2. A method for timing synchronization of constant modulus modulation signals based on a feedforward link according to claim 1, characterized in that: The step 1 specifically includes the following steps: Step 1a: normalize the power of the input signal so that the modulus value is close to 1, and calculate the modulus square data of the signal to normalize the power of the input data; Step 1b, estimate the optimal integer sampling point position; Assuming that the number of sampling points in a symbol time interval is nsmp, if the sampling rate is fs and the symbol rate is fb, then the following formula is obtained: For digital signal demodulation, the sampling rate is generally processed before demodulation to make the oversampling multiple nsmp an integer. Later, a sampling point is taken within each symbol time interval to judge the symbol. This sampling point is the optimal sampling point. If there is a timing error and the judgment position is inaccurate, the EVM (error vector magnitude) of the demodulated data will increase or even make an incorrect judgment. This step is to use the constant modulus error minimum method to obtain the optimal sampling point position for the nsmp sampling points within a symbol interval; In the previous step, the power-normalized modulus square data has been obtained, and its reference value is 1. If the optimal sampling point is pts, 0≤pts≤nsmp-1, the data of each symbol is taken to calculate the error. The specific formula is as follows: The number of symbols is: The sampling point position of each symbol is: pts,pts+nsmp,pts+2·nsmp,…,pts+(Nsym-1)·nsmp The sum of squared errors is: Recording data: errVec[pts]=err pts When 0≤pts≤nsmp-1, all points' err pts After the calculation is completed, the minimum error is searched to obtain the optimal integer sampling point position:

3. The method for timing synchronization of a constant modulus modulation signal based on a feedforward link according to claim 2, characterized in that: In said step 1a; The average power of the input signal is: The square of the input signal is: Where N is the number of sampling points of the input signal, I i , Q i is the IQ data of the i-th sampling point, i = 0, 1, ..., N-1, and the input data power is normalized using the following formula:

4. The method for timing synchronization of a constant modulus modulation signal based on a feedforward link according to claim 2, wherein: The step 2 specifically includes the following steps: Step 2a, estimating the optimal decimal sampling point position; For the error array errVec, the minimum value is at index1. Now it is necessary to perform a delay process on errVec from -0.5 to 0.5 to obtain the minimum error position with a smaller granularity. Starting from a delay of -0.5, calculate the minimum error value after each delay step by step; If the current fractional delay value is delay, where -0.5≤delay≤0.5, delay=-0.5+cnt·step, cnt=0,1,…,Count-1, The specific process of delay processing is as follows: (a) Perform FFT of nsmp points on the array errVec; yfft=FFT{errVec} (b) Calculate the linear phase with a delay of delay; Where n = 0, 1, ..., nsmp-1 (c) Loading linear phase; yfft'[n]=yfft[n]·e j·phase[n] (d) Perform IFFT of the nsmp point and take the real part as output; errVec delay =resl(IFFT{yfft'}) Get the minimum error after the delay and record it in the array: srch Vec[cnt]=errVec delay [index1] After the minimum error after Count delays is calculated, search for the minimum value of srch Vec to obtain the optimal fractional delay position: Step 2b: Calculate the final timing error timingErr and the delay value finalDelay that needs to be processed; timingErr=index1-(-0.5+index2·step) finalDelay=nsmp-timingErr.

5. A method for timing synchronization of a constant modulus modulation signal based on a feedforward link according to any one of claims 1 to 4, characterized in that: The method for verifying and processing the timing error is also included, which specifically includes the following steps: Step S1: Error signal generation: first generate an ideal digital baseband signal according to the configuration parameters, then add Gaussian white noise, and then add timing error; Step S2: Error analysis and calculation: roughly estimate the timing error and output the data after compensating for the positive timing error. Then, accurately estimate the timing error and output the data after compensating for the final timing error. Finally, calculate the EVM under the three types of data and draw the eye diagram for analysis.

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