PCB plated hole process control method and system

Abstract

The present invention discloses a hole plating process control method and system for a PCB board, and defines a hole plating process scheme based on the hole to be processed of the PCB board, the corresponding relative position and the thickness of the PCB board, thereby ensuring the control accuracy of the hole plating process scheme. Further, based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, a plurality of sub-process nodes are divided, and the hole plating process effect coefficient of the PCB board is defined according to the plurality of sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board; the hole plating process level of the PCB board is defined according to the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization event corresponding to the optimization logic matching, the hole plating process quality of the hole to be processed is controlled, thereby ensuring the accuracy of the hole plating process level of the PCB board, and achieving further quality assurance of the hole plating process quality of the PCB board.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB boards, and in particular to a method and system for controlling a hole plating process of a PCB board. Background Art

[0002] With the development of science and technology, PCB boards are gradually applied to people's lives and are core components of electronic devices. PCB boards are provided with multiple holes to be processed. For the multiple holes to be processed, the multiple holes to be processed need to be electroplated. In the prior art, different types of PCB boards are electroplated along a preset hole plating process scheme, and multiple interactions of the holes to be processed of the PCB board, the corresponding relative positions and the thickness of the PCB board cannot be realized, which affects the control accuracy of the hole plating process scheme. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a method and system for controlling a hole plating process of a PCB board, which collect images of the PCB board in multiple directions; define a three-dimensional model of the PCB board based on multiple images and the model of the PCB board; define holes to be processed on the PCB board according to the traversal of the three-dimensional model of the PCB board; define a hole plating process scheme based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, introduce the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, perform multiple interactions on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, and ensure the control accuracy of the hole plating process scheme.

[0004] Furthermore, based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, a plurality of sub-process nodes are divided, and the hole plating process effect coefficient of the PCB board is defined according to the plurality of sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board; the hole plating process effect coefficient of each hole to be processed is marked, and the hole plating process level of the PCB board is defined according to the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board; based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization events corresponding to the optimization logic matching, the hole plating process quality of the hole to be processed is controlled, and the overall consideration of the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board is compatible, so as to ensure the accuracy of the hole plating process level of the PCB board, and introduce the optimization events, so as to realize the further quality assurance of the hole plating process quality of the PCB board.

[0005] The embodiment of the present invention provides a method for controlling a hole plating process of a PCB board, which is applied to a hole plating process control scenario of a PCB board;

[0006] The method for controlling a hole plating process of a PCB board comprises:

[0007] Collect images of PCB boards in multiple directions;

[0008] Defining a three-dimensional model of the PCB board based on the multiple images and the model of the PCB board;

[0009] Defining the holes to be processed on the PCB board according to the traversal of the three-dimensional model of the PCB board;

[0010] Define the hole plating process plan based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board;

[0011] Based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, multiple sub-process nodes are divided, and the hole plating process effect coefficient of the PCB board is defined according to the multiple sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board;

[0012] Mark the hole plating process effect coefficient of each hole to be processed, define the hole plating process level of the PCB board according to multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and match the corresponding optimization events based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic.

[0013] Optionally, collecting images of the PCB board in multiple directions includes:

[0014] Collect the movement trajectory of the PCB board;

[0015] Define multiple corresponding camera positions based on the moving trajectory, the corresponding environment and the PCB board;

[0016] Multiple camera positions are located in different azimuth dimensions, and trigger corresponding cameras to dynamically shoot the PCB board;

[0017] Based on the dynamic shooting of the PCB by each camera, images of the PCB board in multiple directions are collected. At this time, the images of the PCB board in multiple directions are sorted, and the corresponding shooting time and shooting orientation dimensions are marked. The presentation completeness of the PCB is defined according to the traversal of multiple shooting orientation dimensions.

[0018] Optionally, defining a three-dimensional model of the PCB board based on the multiple images and the model of the PCB board includes:

[0019] Freeze multiple images;

[0020] A circumferential panoramic image is formed based on the integration of multiple images and PCB boards;

[0021] Defining corresponding abnormal areas according to image detection of the circumferential panoramic image, and marking the position and orientation of the abnormal areas;

[0022] Trigger the positioning review of the PCB board based on the position and orientation of the abnormal area until there is no abnormal area in the circumferential panoramic image;

[0023] A three-dimensional model of the PCB board is defined according to the circumferential panoramic image and the three-dimensional logic of the PCB board.

[0024] Optionally, the step of defining the to-be-processed holes of the PCB board according to the traversal of the three-dimensional model of the PCB board includes:

[0025] Freeze the three-dimensional model of the PCB board;

[0026] Match the corresponding traversal mode according to the three-dimensional model of the PCB board and the moving direction of the PCB board;

[0027] Associating the traversal mode with the three-dimensional model of the PCB board;

[0028] The holes to be processed of the PCB board are defined according to the traversal mode and the three-dimensional model of the PCB board, and corresponding hole position information is marked on the holes to be processed of the PCB board.

[0029] Optionally, the hole plating process scheme is defined based on the to-be-processed holes of the PCB board, the corresponding relative positions, and the thickness of the PCB board, including:

[0030] Freeze the holes to be processed on each PCB board;

[0031] Define the corresponding detection direction based on the PCB board shape;

[0032] According to the detection direction and the holes to be processed of each PCB board, corresponding relative positions are defined;

[0033] Associate the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board;

[0034] The hole plating process plan is defined based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board.

[0035] Optionally, the method of dividing a plurality of sub-process nodes based on the hole-plating process scheme, the hole-plating environment of the PCB board, and the application scenario of the PCB board, and defining the hole-plating process effect coefficient of the PCB board according to the plurality of sub-process nodes, the corresponding hole-plating parameters, and the posture of the PCB board includes:

[0036] Fixed-grid hole plating process plan;

[0037] Output multiple sub-processes based on the analysis of the hole plating process plan;

[0038] Associate multiple sub-processes, the via-plating environment of the PCB board, and the application scenarios of the PCB board;

[0039] Multiple sub-process nodes are divided according to multiple sub-processes, the plating environment of the PCB board and the application scenarios of the PCB board.

[0040] Optionally, the dividing of a plurality of sub-process nodes based on the hole plating process scheme, the hole plating environment of the PCB board, and the application scenario of the PCB board, and defining the hole plating process effect coefficient of the PCB board according to the plurality of sub-process nodes, the corresponding hole plating parameters, and the posture of the PCB board, further includes:

[0041] Monitor the PCB board in real time and collect the posture of the PCB board;

[0042] A plurality of sub-process nodes, corresponding hole-plating parameters, and a posture of the PCB board are associated, and a hole-plating process effect coefficient of the PCB board is defined based on the plurality of sub-process nodes, the corresponding hole-plating parameters, and the posture of the PCB board.

[0043] Optionally, the hole plating process effect coefficients of each hole to be processed are marked, and the hole plating process level of the PCB board is defined according to multiple hole plating process effect coefficients, the surface coefficient of the PCB board, and the thickness of the PCB board. The optimization event corresponding to the hole plating process level of the PCB board, the hole plating parameter set of the PCB board, and the optimization logic matching includes:

[0044] Collect each hole to be processed and the corresponding hole plating process effect coefficient, and mark the hole plating process effect coefficient of each hole to be processed;

[0045] Collecting the surface coefficient of the PCB board based on the surface detection of the PCB board;

[0046] Correlate multiple hole plating process effect coefficients, PCB surface coefficients and PCB thickness;

[0047] The hole plating process grade of the PCB board is defined based on multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board.

[0048] Optionally, the marking of the hole plating process effect coefficients of each hole to be processed, defining the hole plating process level of the PCB board according to the multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and matching the corresponding optimization events based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic, further includes:

[0049] Multiple interactions are performed on the PCB board's hole plating process level, the PCB board's hole plating parameter set, and the optimization logic;

[0050] The optimization events corresponding to the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic matching are determined.

[0051] In addition, an embodiment of the present invention further provides a hole plating process control system for a PCB board, and the hole plating process control system for the PCB board comprises:

[0052] An image module is used to collect images of the PCB board in multiple directions;

[0053] A three-dimensional model module, used for defining a three-dimensional model of a PCB board based on a plurality of images and a model of the PCB board;

[0054] A traversal module, used for defining the holes to be processed on the PCB board according to the traversal of the three-dimensional model of the PCB board;

[0055] The hole plating module is used to define the hole plating process plan based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board;

[0056] The hole plating process effect coefficient module is used to divide multiple sub-process nodes based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, and define the hole plating process effect coefficient of the PCB board according to the multiple sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board;

[0057] The optimization module is used to mark the hole plating process effect coefficient of each hole to be processed, define the hole plating process level of the PCB board according to multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and match the corresponding optimization events based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic.

[0058] In an embodiment of the present invention, through the method in the embodiment of the present invention, images of the PCB board in multiple directions are collected; a three-dimensional model of the PCB board is defined based on the multiple images and the model of the PCB board; holes to be processed on the PCB board are defined according to the traversal of the three-dimensional model of the PCB board; a plating process scheme is defined based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board are introduced, and multiple interactions are performed on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, thereby ensuring the control accuracy of the plating process scheme.

[0059] Furthermore, based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, a plurality of sub-process nodes are divided, and the hole plating process effect coefficient of the PCB board is defined according to the plurality of sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board; the hole plating process effect coefficient of each hole to be processed is marked, and the hole plating process level of the PCB board is defined according to the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board; based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization events corresponding to the optimization logic matching, the hole plating process quality of the hole to be processed is controlled, and the overall consideration of the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board is compatible, so as to ensure the accuracy of the hole plating process level of the PCB board, and introduce the optimization events, so as to realize the further quality assurance of the hole plating process quality of the PCB board. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0061] Figure 1 1 is a flow chart of a method for controlling a hole plating process of a PCB board in an embodiment of the present invention;

[0062] Figure 2 1 is a flow chart of S11 in the method for controlling a hole plating process of a PCB board in an embodiment of the present invention;

[0063] Figure 3 1 is a schematic flow chart of S12 in the method for controlling a hole plating process of a PCB board in an embodiment of the present invention;

[0064] Figure 4 1 is a schematic flow chart of S13 in the hole plating process control method of a PCB board in an embodiment of the present invention;

[0065] Figure 5 1 is a schematic flow chart of S14 in the method for controlling a hole plating process of a PCB board in an embodiment of the present invention;

[0066] Figure 6 1 is a schematic flow chart of S15 in the method for controlling a hole plating process of a PCB board in an embodiment of the present invention;

[0067] Figure 7 1 is a schematic flow chart of S16 in the hole plating process control method of a PCB board in an embodiment of the present invention;

[0068] Figure 8 Schematic diagram of the structure of the hole plating process control system of the PCB board in the embodiment of the present invention;

[0069] Fig. 9 The figure is a hardware diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] See also Figures 1 to 9 A hole plating process control method for a PCB board is applied to the hole plating process control scenario of a PCB board; the hole plating process control method for a PCB board includes:

[0072] Step S11: collecting images of the PCB board in multiple directions;

[0073] Step S12: defining a three-dimensional model of the PCB board based on the multiple images and the model of the PCB board;

[0074] Step S13: defining the holes to be processed on the PCB board according to the traversal of the three-dimensional model of the PCB board;

[0075] Step S14: defining a hole plating process scheme based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board;

[0076] Step S15: dividing a plurality of sub-process nodes based on the hole-plating process scheme, the hole-plating environment of the PCB board, and the application scenario of the PCB board, and defining the hole-plating process effect coefficient of the PCB board according to the plurality of sub-process nodes, the corresponding hole-plating parameters, and the posture of the PCB board;

[0077] Step S16: Mark the hole plating process effect coefficient of each hole to be processed, define the hole plating process level of the PCB board according to multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and match the corresponding optimization events based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic.

[0078] In an embodiment of the present invention, through the method in the embodiment of the present invention, images of the PCB board in multiple directions are collected; a three-dimensional model of the PCB board is defined based on the multiple images and the model of the PCB board; holes to be processed on the PCB board are defined according to the traversal of the three-dimensional model of the PCB board; a plating process scheme is defined based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board are introduced, and multiple interactions are performed on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, thereby ensuring the control accuracy of the plating process scheme.

[0079] Furthermore, based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, a plurality of sub-process nodes are divided, and the hole plating process effect coefficient of the PCB board is defined according to the plurality of sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board; the hole plating process effect coefficient of each hole to be processed is marked, and the hole plating process level of the PCB board is defined according to the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board; based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization events corresponding to the optimization logic matching, the hole plating process quality of the hole to be processed is controlled, and the overall consideration of the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board is compatible, so as to ensure the accuracy of the hole plating process level of the PCB board, and introduce the optimization events, so as to realize the further quality assurance of the hole plating process quality of the PCB board.

[0080] refer to Figure 2 , in step S11, collecting images of the PCB board in multiple directions;

[0081] In the specific implementation process of the present invention, the specific steps may be:

[0082] S111: Collect the moving trajectory of the PCB board;

[0083] S112: defining a plurality of corresponding camera positions based on the moving trajectory, the corresponding environment and the PCB board;

[0084] S113: The plurality of camera positions are respectively located at different azimuth dimensions, and the corresponding cameras are triggered to dynamically shoot the PCB board;

[0085] S114: Based on the dynamic shooting of the PCB by each camera, the images of the PCB board in multiple directions are collected. At this time, the images of the PCB board in multiple directions are sorted, and the corresponding shooting time and shooting direction dimensions are marked. The presentation completeness of the PCB is defined according to the traversal of multiple shooting direction dimensions.

[0086] In an embodiment of the present application, the movement trajectory of the PCB board is collected, the movement trajectory of the PCB board is introduced, and the movement trajectory of the PCB board is further controlled to facilitate subsequent processing of the movement trajectory of the PCB board.

[0087] Furthermore, multiple corresponding camera positions are defined based on the movement trajectory, the corresponding environment and the PCB board; the multiple camera positions are respectively in different azimuth dimensions, and the corresponding cameras are triggered to dynamically shoot the PCB board, so as to realize multi-dimensional shooting of the PCB board and ensure the imaging of the PCB board in multiple azimuth dimensions.

[0088] Therefore, based on the dynamic shooting of the PCB by each camera, images of the PCB board in multiple directions are collected. At this time, the images of the PCB board in multiple directions are sorted, and the corresponding shooting time and shooting azimuth dimensions are marked. The presentation completeness of the PCB is defined according to the traversal of multiple shooting azimuth dimensions, thereby ensuring the accuracy of the presentation completeness of the PCB, so as to make full use of the images of the PCB board in multiple directions.

[0089] refer to Figure 3 In step S12, a three-dimensional model of the PCB board is defined based on the multiple images and the model of the PCB board;

[0090] In the specific implementation process of the present invention, the specific steps may be:

[0091] S121: freeze multiple images;

[0092] S122: forming a circumferential panoramic image based on the integration of the multiple images and the PCB board;

[0093] S123: defining a corresponding abnormal area according to the image detection of the circumferential panoramic image, and marking the position and orientation of the abnormal area;

[0094] S124: triggering a positioning review of the PCB board based on the position and orientation of the abnormal area until no abnormal area exists in the circumferential panoramic image;

[0095] S125: defining a three-dimensional model of the PCB board according to the circumferential panoramic image and the three-dimensional logic of the PCB board.

[0096] In an embodiment of the present application, multiple images are frozen and controlled. At the same time, a circumferential panoramic image is formed based on the integration of multiple images and PCB boards. The integration of multiple images and PCB boards is introduced to achieve the integration of multiple images and PCB boards, thereby ensuring the accuracy of the circumferential panoramic image.

[0097] Therefore, the corresponding abnormal area is defined according to the image detection of the circumferential panoramic image, and the position and orientation of the abnormal area are marked; the positioning review of the PCB board is triggered based on the position and orientation of the abnormal area until there is no abnormal area in the circumferential panoramic image, thereby realizing real-time detection of the abnormal area and ensuring the subsequent processing of the circumferential panoramic image.

[0098] Furthermore, the stereoscopic model of the PCB board is defined according to the stereoscopic logic of the circumferential panoramic image and the PCB board, the stereoscopic logic of the circumferential panoramic image and the PCB board is introduced, the overall consideration of the stereoscopic logic of the circumferential panoramic image and the PCB board is compatible, the multi-dimensional control of the stereoscopic logic of the circumferential panoramic image and the PCB board is realized, and the accuracy of the stereoscopic model of the PCB board is ensured.

[0099] refer to Figure 4 In step S13, the holes to be processed of the PCB board are defined according to the traversal of the three-dimensional model of the PCB board;

[0100] In the specific implementation process of the present invention, the specific steps may be:

[0101] S131: freeze the three-dimensional model of the PCB board;

[0102] S132: matching a corresponding traversal mode according to the three-dimensional model of the PCB board and the moving direction of the PCB board;

[0103] S133: Associating the traversal mode with the three-dimensional model of the PCB board;

[0104] S134: defining the holes to be processed of the PCB board according to the traversal mode and the three-dimensional model of the PCB board, and marking corresponding hole position information of the holes to be processed of the PCB board.

[0105] In the embodiment of the present application, the three-dimensional model of the PCB board is frozen, the three-dimensional model of the PCB board is introduced, and the three-dimensional model of the PCB board is further processed to achieve subsequent processing of the three-dimensional model of the PCB board.

[0106] Therefore, the corresponding traversal mode is matched according to the three-dimensional model of the PCB board and the moving direction of the PCB board; the traversal mode and the three-dimensional model of the PCB board are associated; the holes to be processed of the PCB board are defined according to the traversal mode and the three-dimensional model of the PCB board, and the hole position information corresponding to the holes to be processed of the PCB board are marked, which is compatible with the overall consideration of the traversal mode and the three-dimensional model of the PCB board, realizes the multi-dimensional control of the traversal mode and the three-dimensional model of the PCB board, ensures the accuracy of the holes to be processed of the PCB board, and facilitates further processing of the holes to be processed of the PCB board.

[0107] refer to Figure 5, S14: defining a hole plating process plan based on the to-be-processed holes of the PCB board, the corresponding relative positions and the thickness of the PCB board;

[0108] In the specific implementation process of the present invention, the specific steps may be:

[0109] S141: freeze the holes to be processed on each PCB board;

[0110] S142: defining a corresponding detection direction based on the shape of the PCB board;

[0111] S143: defining corresponding relative positions according to the detection direction and the holes to be processed of each PCB board;

[0112] S144: Associating the to-be-processed holes of the PCB board, the corresponding relative positions, and the thickness of the PCB board;

[0113] S145: defining a hole plating process plan based on the to-be-processed holes of the PCB board, the corresponding relative positions, and the thickness of the PCB board.

[0114] In an embodiment of the present application, images of a PCB board in multiple directions are collected; a three-dimensional model of the PCB board is defined based on the multiple images and the model of the PCB board; holes to be processed on the PCB board are defined according to the traversal of the three-dimensional model of the PCB board; a hole plating process scheme is defined based on the holes to be processed on the PCB board, the corresponding relative positions, and the thickness of the PCB board, the holes to be processed on the PCB board, the corresponding relative positions, and the thickness of the PCB board are introduced, and multiple interactions are performed on the holes to be processed on the PCB board, the corresponding relative positions, and the thickness of the PCB board, thereby ensuring the control accuracy of the hole plating process scheme.

[0115] At this time, the holes to be processed on each PCB board are frozen and controlled. At the same time, the corresponding detection direction is defined based on the shape of the PCB board and the corresponding detection direction is introduced.

[0116] Therefore, according to the detection direction and the corresponding relative position of the holes to be processed of each PCB board, the detection direction and the holes to be processed of each PCB board are introduced, and multiple interactions are performed on the detection direction and the holes to be processed of each PCB board to ensure the accuracy of the corresponding relative position.

[0117] Furthermore, the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board are associated; the hole plating process scheme is defined based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, and the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board are introduced, and the overall consideration of the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board is compatible, and the multi-dimensional control of the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board is realized, and the accuracy of the hole plating process scheme is ensured.

[0118] At this time, the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board are introduced, and multiple interactions are performed on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board to ensure the control accuracy of the hole plating process plan.

[0119] refer to Figure 6 , S15: dividing a plurality of sub-process nodes based on the hole plating process scheme, the hole plating environment of the PCB board, and the application scenario of the PCB board, and defining the hole plating process effect coefficient of the PCB board according to the plurality of sub-process nodes, the corresponding hole plating parameters, and the posture of the PCB board;

[0120] In the specific implementation process of the present invention, the specific steps may be:

[0121] S151: Fixed-grid hole plating process plan;

[0122] S152: Outputting a plurality of sub-processes according to the analysis of the hole plating process plan;

[0123] S153: Associating multiple sub-processes, the hole-plating environment of the PCB board, and the application scenario of the PCB board;

[0124] S154: Divide a plurality of sub-process nodes according to a plurality of sub-processes, a hole-plating environment of the PCB board, and an application scenario of the PCB board;

[0125] S155: monitor the PCB board in real time and collect the posture of the PCB board;

[0126] S156: Associating a plurality of sub-process nodes, corresponding hole-plating parameters, and a posture of the PCB board, and defining a hole-plating process effect coefficient of the PCB board based on the plurality of sub-process nodes, corresponding hole-plating parameters, and the posture of the PCB board.

[0127] In an embodiment of the present application, the hole plating process scheme is frozen and the hole plating process scheme is further controlled. At the same time, multiple sub-processes are output based on the analysis of the hole plating process scheme and the multiple sub-processes are further controlled.

[0128] At this time, multiple sub-processes, the hole-plating environment of the PCB board, and the application scenarios of the PCB board are associated; multiple sub-process nodes are divided according to the multiple sub-processes, the hole-plating environment of the PCB board, and the application scenarios of the PCB board, and multiple sub-processes, the hole-plating environment of the PCB board, and the application scenarios of the PCB board are introduced, and the multiple sub-processes, the hole-plating environment of the PCB board, and the application scenarios of the PCB board are controlled in multiple dimensions to ensure the accuracy of multiple sub-process nodes.

[0129] Therefore, the PCB board is monitored in real time, and the posture of the PCB board is collected; multiple sub-process nodes, corresponding hole-plating parameters and the posture of the PCB board are associated, and the hole-plating process effect coefficient of the PCB board is defined based on the multiple sub-process nodes, corresponding hole-plating parameters and the posture of the PCB board. Multiple sub-process nodes, corresponding hole-plating parameters and the posture of the PCB board are introduced, and the overall consideration of multiple sub-process nodes, corresponding hole-plating parameters and the posture of the PCB board is compatible, and multi-dimensional control of multiple sub-process nodes, corresponding hole-plating parameters and the posture of the PCB board is realized, thereby ensuring the accuracy of the hole-plating process effect coefficient of the PCB board.

[0130] refer to Figure 7 , S16: marking the hole plating process effect coefficient of each hole to be processed, defining the hole plating process level of the PCB board according to the multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and matching the corresponding optimization event based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic;

[0131] In the specific implementation process of the present invention, the specific steps may be:

[0132] S161: Collecting each hole to be processed and the corresponding hole plating process effect coefficient, and marking the hole plating process effect coefficient of each hole to be processed;

[0133] S162: collecting surface coefficients of the PCB board based on surface detection of the PCB board;

[0134] S163: Correlate multiple hole plating process effect coefficients, surface coefficients of the PCB board, and thickness of the PCB board;

[0135] S164: defining a hole plating process level of the PCB board based on a plurality of hole plating process effect coefficients, a surface coefficient of the PCB board, and a thickness of the PCB board;

[0136] S165: Multiple interactions between the PCB board’s hole plating process level, the PCB board’s hole plating parameter set, and the optimization logic;

[0137] S166: Optimizing events corresponding to the hole plating process level of the PCB board, the hole plating parameter set of the PCB board, and the optimization logic matching.

[0138] In the specific implementation process of the present invention, a plurality of sub-process nodes are divided based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, and the hole plating process effect coefficient of the PCB board is defined according to the plurality of sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board; the hole plating process effect coefficient of each hole to be processed is marked, and the hole plating process level of the PCB board is defined according to the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board; based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization event corresponding to the optimization logic matching, the hole plating process quality of the hole to be processed is controlled, and the overall consideration of the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board is compatible, so as to ensure the accuracy of the hole plating process level of the PCB board, and introduce the optimization event, so as to achieve further quality assurance of the hole plating process quality of the PCB board.

[0139] At this time, the hole plating process effect coefficients of each hole to be processed and the corresponding hole plating process effect coefficients are collected, and the hole plating process effect coefficients of each hole to be processed are marked. The hole plating process effect coefficients of each hole to be processed are introduced to control the hole plating process effect coefficients of each hole to be processed as a whole.

[0140] Furthermore, the surface coefficient of the PCB board is collected based on the surface detection of the PCB board; multiple hole-plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board are associated; the hole-plating process level of the PCB board is defined based on the multiple hole-plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and multiple hole-plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board are introduced, and the overall consideration of multiple hole-plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board is compatible, thereby realizing the precise control of the hole-plating process level of the PCB board.

[0141] Therefore, multiple interactions are performed on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board, and the optimization logic; based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board, and the optimization logic matching corresponding optimization events, multiple interactions of the hole plating process level of the PCB board, the hole plating parameter set of the PCB board, and the optimization logic are realized, thereby ensuring the accuracy of the optimization events.

[0142] At this time, based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization events corresponding to the optimization logic matching, the hole plating process quality of the processed holes is controlled, and it is compatible with the overall consideration of multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, ensuring the accuracy of the hole plating process level of the PCB board, and introducing optimization events to achieve further quality assurance of the hole plating process quality of the PCB board.

[0143] In an embodiment of the present invention, through the method in the embodiment of the present invention, images of the PCB board in multiple directions are collected; a three-dimensional model of the PCB board is defined based on the multiple images and the model of the PCB board; holes to be processed on the PCB board are defined according to the traversal of the three-dimensional model of the PCB board; a plating process scheme is defined based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board are introduced, and multiple interactions are performed on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, thereby ensuring the control accuracy of the plating process scheme.

[0144] Furthermore, based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, a plurality of sub-process nodes are divided, and the hole plating process effect coefficient of the PCB board is defined according to the plurality of sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board; the hole plating process effect coefficient of each hole to be processed is marked, and the hole plating process level of the PCB board is defined according to the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board; based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization events corresponding to the optimization logic matching, the hole plating process quality of the hole to be processed is controlled, and the overall consideration of the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board is compatible, so as to ensure the accuracy of the hole plating process level of the PCB board, and introduce the optimization events, so as to realize the further quality assurance of the hole plating process quality of the PCB board.

[0145] See also Figure 8 , Figure 8 The figure is a schematic diagram of the structure of a hole plating process control system of a PCB board in an embodiment of the present invention.

[0146] like Figure 8 As shown, a hole plating process control system for a PCB board, the hole plating process control system for the PCB board comprises:

[0147] An image module 21 is used to collect images of the PCB board in multiple directions;

[0148] A three-dimensional model module 22, used to define a three-dimensional model of the PCB board based on multiple images and the model of the PCB board;

[0149] A traversal module 23, used to define the holes to be processed of the PCB board according to the traversal of the three-dimensional model of the PCB board;

[0150] The hole plating module 24 is used to define the hole plating process scheme based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board;

[0151] The hole plating process effect coefficient module 25 is used to divide a plurality of sub-process nodes based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, and define the hole plating process effect coefficient of the PCB board according to the plurality of sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board;

[0152] The optimization module 26 is used to mark the hole plating process effect coefficient of each hole to be processed, define the hole plating process level of the PCB board according to multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and match the corresponding optimization events based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic.

[0153] See also Fig. 9 , refer to the following Fig. 9 The electronic device 40 according to this embodiment of the present invention will be described. Fig. 9 The electronic device 40 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0154] like Fig. 9 As shown, the electronic device 40 is in the form of a general computing device. The components of the electronic device 40 may include but are not limited to: at least one processing unit 41, at least one storage unit 42, and a bus 43 connecting different system components (including the storage unit 42 and the processing unit 41).

[0155] The storage unit stores program codes, which can be executed by the processing unit 41, so that the processing unit 41 executes the steps according to various exemplary embodiments of the present invention described in the above “Embodiment Method” section of this specification.

[0156] The storage unit 42 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 421 and / or a cache memory unit 422 , and may further include a read-only memory unit (ROM) 423 .

[0157] The storage unit 42 may also include a program / utility 424 having a set (at least one) of program modules 425, such program modules 425 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0158] Bus 43 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0159] The electronic device 40 may also communicate with one or more external devices (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device 40, and / or any device that enables the electronic device 40 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 44. Furthermore, the electronic device 40 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 45. Fig. 9 As shown, the network adapter 45 communicates with other modules of the electronic device 40 via the bus 43. It should be understood that although Fig. 9 Not shown, other hardware and / or software modules may be used in conjunction with the electronic device 40, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup planning systems.

[0160] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0161] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, and the storage medium can include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc. In addition, it stores computer program instructions, and when the computer program instructions are executed by a computer, the computer executes the above method.

[0162] In addition, the above is a detailed introduction to the hole plating process control method and system for the PCB board provided by the embodiment of the present invention. In this article, specific examples are used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for controlling a hole plating process of a PCB board, characterized in that: Applied to the hole plating process control scenario of PCB board; The method for controlling a hole plating process of a PCB board comprises: Collect images of PCB boards in multiple directions; Defining a three-dimensional model of the PCB board based on the multiple images and the model of the PCB board; Defining the holes to be processed on the PCB board according to the traversal of the three-dimensional model of the PCB board; Define the hole plating process plan based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board; Based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, multiple sub-process nodes are divided, and the hole plating process effect coefficient of the PCB board is defined according to the multiple sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board; Mark the hole plating process effect coefficient of each hole to be processed, define the hole plating process level of the PCB board according to multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and match the corresponding optimization events based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic.

2. The method for controlling the hole plating process of a PCB board according to claim 1, characterized in that: The collecting of images of the PCB board in multiple directions includes: Collect the movement trajectory of the PCB board; Define multiple corresponding camera positions based on the moving trajectory, the corresponding environment and the PCB board; Multiple camera positions are located in different azimuth dimensions, and trigger corresponding cameras to dynamically shoot the PCB board; Based on the dynamic shooting of the PCB by each camera, images of the PCB board in multiple directions are collected. At this time, the images of the PCB board in multiple directions are sorted, and the corresponding shooting time and shooting orientation dimensions are marked. The presentation completeness of the PCB is defined according to the traversal of multiple shooting orientation dimensions.

3. The method for controlling the hole plating process of a PCB board according to claim 1, characterized in that: Defining a three-dimensional model of the PCB board based on the multiple images and the model of the PCB board includes: Freeze multiple images; A circumferential panoramic image is formed based on the integration of multiple images and PCB boards; Defining corresponding abnormal areas according to image detection of the circumferential panoramic image, and marking the position and orientation of the abnormal areas; Trigger the positioning review of the PCB board based on the position and orientation of the abnormal area until there is no abnormal area in the circumferential panoramic image; A three-dimensional model of the PCB board is defined according to the circumferential panoramic image and the three-dimensional logic of the PCB board.

4. The method for controlling the hole plating process of a PCB board according to claim 3, characterized in that: The method of defining the holes to be processed on the PCB board according to the traversal of the three-dimensional model of the PCB board includes: Freeze the three-dimensional model of the PCB board; Match the corresponding traversal mode according to the three-dimensional model of the PCB board and the moving direction of the PCB board; Associating the traversal mode with the three-dimensional model of the PCB board; The holes to be processed of the PCB board are defined according to the traversal mode and the three-dimensional model of the PCB board, and corresponding hole position information is marked on the holes to be processed of the PCB board.

5. The method for controlling the hole plating process of a PCB board according to claim 4, characterized in that: The hole plating process scheme is defined based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board, including: Freeze the holes to be processed on each PCB board; Define the corresponding detection direction based on the PCB board shape; According to the detection direction and the holes to be processed of each PCB board, corresponding relative positions are defined; Associate the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board; The hole plating process plan is defined based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board.

6. The method for controlling the hole plating process of a PCB board according to claim 5, characterized in that: The method divides a plurality of sub-process nodes based on the hole-plating process scheme, the hole-plating environment of the PCB board, and the application scenario of the PCB board, and defines the hole-plating process effect coefficient of the PCB board according to the plurality of sub-process nodes, the corresponding hole-plating parameters, and the posture of the PCB board, including: Fixed-grid hole plating process plan; Output multiple sub-processes based on the analysis of the hole plating process plan; Associate multiple sub-processes, the via-plating environment of the PCB board, and the application scenarios of the PCB board; Multiple sub-process nodes are divided according to multiple sub-processes, the plating environment of the PCB board and the application scenarios of the PCB board.

7. The method for controlling the hole plating process of a PCB board according to claim 6, characterized in that: The method further includes dividing a plurality of sub-process nodes based on the hole-plating process scheme, the hole-plating environment of the PCB board, and the application scenario of the PCB board, and defining the hole-plating process effect coefficient of the PCB board according to the plurality of sub-process nodes, the corresponding hole-plating parameters, and the posture of the PCB board. Monitor the PCB board in real time and collect the posture of the PCB board; A plurality of sub-process nodes, corresponding hole-plating parameters, and a posture of the PCB board are associated, and a hole-plating process effect coefficient of the PCB board is defined based on the plurality of sub-process nodes, the corresponding hole-plating parameters, and the posture of the PCB board.

8. The method for controlling the hole plating process of a PCB board according to claim 7, characterized in that: The hole plating process effect coefficients of the holes to be processed are marked, and the hole plating process level of the PCB board is defined according to the multiple hole plating process effect coefficients, the surface coefficient of the PCB board, and the thickness of the PCB board. The optimization events corresponding to the hole plating process level of the PCB board, the hole plating parameter set of the PCB board, and the optimization logic matching include: Collect each hole to be processed and the corresponding hole plating process effect coefficient, and mark the hole plating process effect coefficient of each hole to be processed; Collecting the surface coefficient of the PCB board based on the surface detection of the PCB board; Correlate multiple hole plating process effect coefficients, PCB surface coefficients and PCB thickness; The hole plating process grade of the PCB board is defined based on multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board.

9. The method for controlling the hole plating process of a PCB board according to claim 8, characterized in that: The method further includes marking the hole plating process effect coefficient of each hole to be processed, defining the hole plating process level of the PCB board according to the plurality of hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and matching the corresponding optimization events based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic: Multiple interactions are performed on the PCB board's hole plating process level, the PCB board's hole plating parameter set, and the optimization logic; The optimization events corresponding to the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic matching are determined.

10. A PCB plated hole process control system, characterized in that: The hole plating process control system of the PCB board is applied to the hole plating process control method of the PCB board as claimed in any one of claims 1 to 9, and the hole plating process control system of the PCB board comprises: An image module is used to collect images of the PCB board in multiple directions; A three-dimensional model module, used for defining a three-dimensional model of a PCB board based on a plurality of images and a model of the PCB board; A traversal module, used for defining the holes to be processed on the PCB board according to the traversal of the three-dimensional model of the PCB board; The hole plating module is used to define the hole plating process plan based on the holes to be processed on the PCB board, the corresponding relative positions and the thickness of the PCB board; The hole plating process effect coefficient module is used to divide multiple sub-process nodes based on the hole plating process scheme, the hole plating environment of the PCB board and the application scenario of the PCB board, and define the hole plating process effect coefficient of the PCB board according to the multiple sub-process nodes, the corresponding hole plating parameters and the posture of the PCB board; The optimization module is used to mark the hole plating process effect coefficient of each hole to be processed, define the hole plating process level of the PCB board according to multiple hole plating process effect coefficients, the surface coefficient of the PCB board and the thickness of the PCB board, and match the corresponding optimization events based on the hole plating process level of the PCB board, the hole plating parameter set of the PCB board and the optimization logic.

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