Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, and electronic equipment, the semiconductor device comprises multiple layers of storage structures stacked along a first direction and at least one common source line structure, each layer of storage structure comprises multiple storage transistors arranged in multiple columns along a second direction, the first direction is vertical to the second direction, and the common source line structure is arranged between the multiple storage transistors. Each storage transistor comprises a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer, the common source line structure penetrates through the multiple layers of storage structures in the first direction, and the storage transistors in the same column in the same layer of storage structures are correspondingly connected to the same common source line structure; the adjacent storage transistors in the first direction in different layers of storage structures are correspondingly connected to the same common source line structure, so that the number of stacked layers of storage units in the semiconductor device can be increased to improve the storage density, the preparation process of the semiconductor device is simplified, the production cycle of a product is shortened, and the production cost is reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. Background Art

[0002] With the miniaturization of technology nodes, semiconductor devices with 1T0C (1Transistor-0Capacitor) as the basic storage unit, such as DRAM (Dynamic Random Access Memory), have the advantages of small footprint and high space utilization due to the lack of capacitors. It has become a cutting-edge semiconductor storage technology with great development potential.

[0003] However, as the number of stacked layers of memory cells in semiconductor devices increases, the manufacturing process of semiconductor devices using 1T0C as a basic memory cell will become increasingly complex, which is not conducive to reducing production costs. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, as well as an electronic device, so as to improve storage density while simplifying the preparation process of the semiconductor device, which is conducive to shortening the production cycle of the product and reducing production costs.

[0005] An embodiment of the present application provides a semiconductor device, which includes: a multi-layer storage structure stacked along a first direction, each layer of the storage structure includes a plurality of storage transistors, the plurality of storage transistors are arranged in a plurality of columns along a second direction, the first direction is perpendicular to the second direction, the storage transistors include a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer; at least one common source line structure, the common source line structure runs through the multi-layer storage structure along the first direction, and the storage transistors in the same column in the same layer of the storage structure are correspondingly connected to the same common source line structure, and the storage transistors adjacent to each other along the first direction in different layers of the storage structure are correspondingly connected to the same common source line structure.

[0006] Each layer of storage structure further includes at least one bit line, and opposite ends of the channel layer of storage transistors in the same column in the same layer of storage structure are respectively connected to the same bit line and the same common source line structure.

[0007] Among them, the channel layer is parallel to the second direction, the bit line is perpendicular to the first direction and the second direction, and the bit line and common source line structure corresponding to the same column of storage transistors in the same layer of storage structure are respectively located on the opposite sides of the same column of storage transistors in the same layer of storage structure along the second direction.

[0008] Among them, the widths of each bit line adjacent to each other along the first direction in different layers of storage structures gradually decrease along the first direction to form a step structure; the semiconductor device also includes multiple bit line contacts, and the multiple bit line contacts are electrically connected to the corresponding bit lines at the positions of the step structure.

[0009] The plurality of storage transistors are arranged in a plurality of rows along a third direction, and the third direction is perpendicular to the first direction and the second direction.

[0010] Among them, an adjacent even-numbered column storage transistor and an odd-numbered column storage transistor in the same layer of storage structure form a transistor group and are correspondingly connected to the same common source line structure.

[0011] The two columns of storage transistors in the same transistor group are correspondingly connected to different bit lines.

[0012] The storage transistor includes: a gate insulating layer, a channel layer including a first end, a channel portion and a second end connected in sequence along a second direction, a gate insulating layer and a gate layer are arranged in sequence around the channel portion, and the gate insulating layer electrically isolates the gate layer from the channel portion.

[0013] The end surface area of ​​the channel portion connected to the first end is smaller than the end surface area of ​​the first end connected to the channel portion, and the end surface area of ​​the channel portion connected to the second end is smaller than the end surface area of ​​the second end connected to the channel portion.

[0014] Wherein, gate layers of storage transistors adjacent to each other along a first direction in different layers of storage structures are connected together.

[0015] The semiconductor device further includes an isolation structure, which penetrates the multi-layer storage structure along a first direction and is located between adjacent storage transistors in the same column of the same storage structure, and electrically isolates adjacent storage transistors in the same column of the same storage structure.

[0016] The present application also provides a method for manufacturing a semiconductor device, including: forming a multi-layer storage structure stacked along a first direction, each layer of the storage structure includes a plurality of storage transistors, the plurality of storage transistors are arranged in multiple columns along a second direction, the first direction is perpendicular to the second direction, the storage transistor includes a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer; forming at least one common source line structure, the common source line structure runs through the multi-layer storage structure along the first direction, and the storage transistors in the same column of the storage structure in the same layer are correspondingly connected to the same common source line structure, and the storage transistors adjacent to each other along the first direction in different layers of the storage structure are correspondingly connected to the same common source line structure.

[0017] Among them, forming a multi-layer storage structure stacked along a first direction includes: forming a stacking structure, the stacking structure includes multiple insulating layers and multiple semiconductor layers alternately stacked along the first direction, the semiconductor layer includes at least one bit line, and multiple channel layers arranged in multiple columns along the second direction, the channel layers in the same column of the same semiconductor layer are correspondingly connected to the same bit line, the adjacent channel layers in the same column of the same semiconductor layer are spaced, and the insulating layer fills the spaced area between the adjacent channel layers; removing the insulating layer adjacent to the channel layer to obtain a gap exposing the surface of the channel layer; through the gap, forming a gate insulating layer and a gate layer covering the gate insulating layer on the exposed surface of the channel layer, to obtain a storage transistor including the channel layer, the gate insulating layer and the gate layer.

[0018] Wherein, removing the insulating layer adjacent to the channel layer on all sides to obtain a gap exposing the surface of the channel layer on all sides, including: etching the insulating layer adjacent to the two opposite sides of the channel layer in the first direction to form a first gate hole at least partially penetrating the stacking structure along a third direction, and etching the insulating layer adjacent to the two opposite sides of the channel layer in the third direction to form a second gate hole at least partially penetrating the stacking structure along the first direction, wherein the third direction is perpendicular to the first direction and the second direction, and the first gate hole and the second gate hole are connected; removing the insulating layer covering the surface of the channel layer on all sides through the first gate hole and the second gate hole until the surface of the channel layer on all sides is exposed to the first gate hole and the second gate hole, thereby obtaining a gap including the first gate hole and the second gate hole.

[0019] Among them, a gate insulating layer and a gate layer covering the gate insulating layer are formed on the exposed surfaces of the channel layer through the gap, so as to obtain a storage transistor including the channel layer, the gate insulating layer and the gate layer, including: a gate insulating layer and a gate layer covering the gate insulating layer are formed on the inner wall surfaces of the first gate hole and the second gate hole, so as to obtain a storage transistor including the channel layer, the gate insulating layer and the gate layer.

[0020] Among them, forming at least one common source line structure includes: forming at least one first groove penetrating the stack structure along the first direction, one end of the same column of channel layers in the same layer of storage structure along the second direction is correspondingly exposed on the inner wall surface of the same first groove, and one end of the adjacent channel layers along the first direction in different layers of storage structure are correspondingly exposed on the inner wall surface of the same first groove along the second direction; filling conductive material in the first groove to form a common source line structure.

[0021] The method further includes: forming a second trench penetrating the stacked structure along the first direction, the second trench separating adjacent storage transistors in the same column in the same layer of storage structure; and filling the second trench with insulating material to form an isolation structure.

[0022] The method also includes: etching the stacked structure so that the width of each bit line adjacent to each other along the first direction in different layers of storage structures gradually decreases along the first direction to form a step structure; forming multiple bit line contacts, and the multiple bit line contacts are electrically connected to the corresponding bit lines at the position of the step structure.

[0023] The present application also provides an electronic device, which includes any of the semiconductor devices described above.

[0024] The beneficial effects of the present application are as follows: the semiconductor device and its manufacturing method, as well as the electronic device provided by the present application, are stacked in a first direction with multiple layers of storage structures, each layer of the storage structure includes multiple storage transistors arranged in multiple columns along a second direction, the first direction is perpendicular to the second direction, the storage transistor includes a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer, and the storage transistors in the same column of the same layer of the storage structure are connected to the same common source line structure, and the storage transistors adjacent to each other along the first direction in different layers of the storage structure are connected to the same common source line structure, and the common source line structure runs through each layer of the storage structure along the first direction, so that the storage transistor can be a junctionless field effect transistor, that is, there can be no fixed source and drain in a conventional field effect transistor, and there is no need to form a PN junction doping between the source and the drain of the storage transistor, so that the manufacturing process of the storage transistor does not need to perform ion implantation, photolithography, ashing and cleaning processes to form a PN junction doping between the source and the drain, which can simplify the process flow, speed up the production cycle of the product, and save production costs. In addition, the gate layer in the storage transistor is arranged around the channel layer, which can improve the control of the gate over the channel in the storage transistor, so that the channel can be fully depleted more effectively in the off state, the off-state leakage current can be reduced, and the gate control effect can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of the three-dimensional structure of a semiconductor device provided in an embodiment of the present application;

[0026] Figure 2 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present application;

[0027] Figure 3 is a schematic diagram of a side view structure of a semiconductor device provided in an embodiment of the present application;

[0028] Figure 4 is a schematic diagram of the main structure of a semiconductor device provided in an embodiment of the present application;

[0029] Figure 5 is along Figure 2 A schematic diagram of the longitudinal section structure taken along the line P-P' in FIG.

[0030] Figure 6 is along Figure 4 A schematic diagram of a cross-sectional structure taken along the line R-R';

[0031] Figure 7 is a schematic diagram of a cross-sectional structure of a storage transistor provided in an embodiment of the present application at a first viewing angle;

[0032] Figure 8 is a schematic diagram of a cross-sectional structure of a storage transistor provided in an embodiment of the present application at a second viewing angle;

[0033] Fig. 9 is a schematic diagram of a cross-sectional structure of a storage transistor provided in an embodiment of the present application at a third viewing angle;

[0034] Fig.10 is along Figure 2 Another schematic diagram of the longitudinal section structure taken along the line P-P' in FIG.

[0035] Fig.11 is along Figure 4 Another cross-sectional structural schematic diagram taken along the line R-R' in FIG.

[0036] Fig.12 is another schematic cross-sectional structure diagram of a storage transistor provided by an embodiment of the present application at a first viewing angle;

[0037] Fig.13 is another schematic cross-sectional structure diagram of a storage transistor provided by an embodiment of the present application at a second viewing angle;

[0038] Fig.14 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor device provided in an embodiment of the present application;

[0039] Fig.15 is a schematic cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present application;

[0040] Fig.16 is a schematic flow chart of a method for manufacturing a semiconductor device provided in this embodiment of the present application;

[0041] Fig.17 is a schematic diagram of the longitudinal section structure after step S111 provided in an embodiment of the present application is completed;

[0042] Fig.18 is along Fig.17 A schematic diagram of a cross-sectional structure taken along the line S-S' in FIG.

[0043] Fig.19 is a schematic diagram of the longitudinal section structure after step S112 provided in an embodiment of the present application is completed;

[0044] Fig. 20 is along Fig.19A schematic diagram of a cross-sectional structure taken along the line S-S' in FIG.

[0045] Fig.21 is another schematic diagram of a longitudinal cross-sectional structure after step S112 provided in an embodiment of the present application is completed;

[0046] Fig. 22 is along Fig.21 A schematic diagram of a cross-sectional structure taken along the line S-S' in FIG.

[0047] Fig.23 is a schematic diagram of the longitudinal section structure after step S113 provided in an embodiment of the present application is completed;

[0048] Fig.24 is along Fig.23 A schematic diagram of a cross-sectional structure taken along the line S-S' in FIG.

[0049] Fig.25 is a schematic diagram of the cross-sectional structure after step S14 is completed provided in an embodiment of the present application;

[0050] Fig.26 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0052] In the description of the present application, it should be understood that the orientation or positional relationship indicated in the description of the direction and positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0053] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0054] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0055] In the embodiments of the present application, the technical concept "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower structure or upper structure, or may have a range smaller than the lower structure or upper structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure.

[0056] For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may include multiple layers, and / or may have one or more layers thereon, above, and / or below.

[0057] In the embodiments of the present application, the technical concept "vertical" refers to approximately vertical, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes the angle of greater than 85° and less than 95°. In addition, "parallel" refers to approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes the angle of greater than -5° and less than 5°.

[0058] The technical concept of "A and B are arranged in the same layer" in the embodiment of the present application means that A and B are formed simultaneously through the same patterning process. The technical concept of "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0059] The technical concept of the embodiment of the present application that "A and B are an integrated structure" may refer to the absence of obvious boundary interfaces such as obvious faults or gaps in the microstructure. Generally, a film layer patterned to form a connection on a film layer is an integrated structure. For example, A and B use the same material to form a film layer and simultaneously form a structure with a connection relationship through the same patterning process.

[0060] When describing the structure of a component, when a layer or a region is referred to as being "on" or "above" another layer or another region, it may mean being directly above the other layer or another region, or having other layers or regions between it and the other layer or another region. Also, if the component is turned over, the layer or the region will be "under" or "below" the other layer or another region. In addition, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0061] In addition, the directional terms mentioned in the embodiments of the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the embodiments of the present application, rather than to limit the embodiments of the present application. In each of the accompanying drawings, units with similar structures are represented by the same figure numbers. For clarity, the various parts in the drawings are not drawn to scale. In addition, certain related parts may not be shown in the drawings.

[0062] The following is a detailed description with reference to specific embodiments. It should be noted that the embodiments of the present application can be presented in various forms, some examples of which will be described below.

[0063] See also Figures 1 to 6 , Figure 1 is a schematic diagram of the three-dimensional structure of a semiconductor device provided in an embodiment of the present application, Figure 2 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present application, Figure 3 is a schematic diagram of a side view structure of a semiconductor device provided in an embodiment of the present application, Figure 4 is a schematic diagram of the main structure of a semiconductor device provided in an embodiment of the present application, Figure 5 is along Figure 2 A schematic diagram of the longitudinal section structure taken along the line P-P' in FIG. Figure 6 is along Figure 4 Schematic diagram of the cross-sectional structure taken along the line R-R' in FIG. Figures 1 to 6 As shown, the semiconductor device 1000 includes a multi-layer memory structure 100 (eg, a first layer memory structure 100A, a second layer memory structure 100B, and a third layer memory structure 100C) stacked along a first direction Z (eg, from bottom to top) and at least one common source line structure 20.

[0064] Each layer of the storage structure 100 may include a plurality of storage transistors 11, and the plurality of storage transistors 11 may be arranged in a plurality of columns along the second direction X (for example, from left to right) to form a plurality of columns of storage transistors 10. The plurality of columns of storage transistors 10 may be arranged at intervals along the second direction X, and the plurality of storage transistors 11 in each column of storage transistors 10 may be arranged at intervals along the third direction Y, wherein the second direction X and the third direction Y may be perpendicular to the first direction Z, and the second direction X may be perpendicular to the third direction Y, so that the plurality of storage transistors 11 extend divergently along a plane perpendicular to the first direction Z in the first direction Z to form a regular storage transistor array, such as a storage transistor array with a square surface or a rectangular surface, which not only facilitates the stacking distribution of the storage transistors 11 in the first direction X, the second direction Y and the third direction Z, but also keeps the semiconductor device 1000 regular.

[0065] In this embodiment, the semiconductor device 1000 can be a semiconductor device with 1T0C (1Transistor-0Capacitor) as a basic storage unit, such as DRAM (Dynamic Random Access Memory), that is, a single storage transistor 11 can be the smallest storage unit in the semiconductor device 1000, which is beneficial for controlling the volume of the semiconductor device 1000 while ensuring the storage density.

[0066] In the above-mentioned semiconductor device 1000, the multi-layer storage structure 100 is stacked and distributed along the first direction Z, so that multiple storage transistors 11 can be distributed in different layers of storage structures 100 stacked along the first direction Z, so that the number of stacking layers of the storage structure 100 can be increased as needed to improve the storage capacity and increase the storage density of the semiconductor device 100.

[0067] and, Figure 1 Only a few layers of stacked storage structures 100 and a few storage transistors 11 arranged in multiple columns are shown. It should be understood that the semiconductor device 1000 may include any number of layers of storage structures 100 and any number of storage transistors 11, and the storage transistors 11 may be extended and stacked arbitrarily along the first direction Z, the second direction X and the third direction Y.

[0068] Specifically, Figures 7 to 9 As shown, the storage transistor 11 may include a channel layer 111 and a gate layer 113 disposed around the channel layer 111, wherein the channel layer 111 may be perpendicular to the first direction Z, that is, the lateral surface of the channel layer 111 (eg, Figure 7 An upper surface or a lower surface of the middle channel layer 111 may be perpendicular to the first direction Z.

[0069] Furthermore, it should be noted that, in this embodiment, the gate layer 113 of the storage transistor 11 is disposed around the channel layer 111, so that the gate layer 113 of the storage transistor 11 can be connected from multiple directions (for example, Fig. 9 The gate layer 113 in the storage transistor 11 surrounds the channel layer 111 in four directions (up, down, left, and right) of the middle channel layer 111, which is beneficial to improving the control ability of the gate layer 113 in the storage transistor 11 over the channel layer 111, thereby achieving a higher current density and lower leakage current in the channel layer 111, thereby improving the performance of the above-mentioned semiconductor device 1000.

[0070] In some embodiments, Figures 7 to 9 As shown, the storage transistor 11 may be a field effect transistor in which a gate is arranged around a channel, that is, the gate layer 113 of the storage transistor 11 can be connected from four sides (for example, Fig. 9 The top, bottom, left and right sides of the channel layer 111 surround the channel layer 111, so that compared with a planar field effect transistor and a field effect transistor in which the gate surrounds the channel from three sides, the gate layer 113 in the storage transistor 11 can better control the channel layer 111, so that the channel layer 111 can be more effectively fully depleted in the off state, the off-state leakage current of the storage transistor 11 can be reduced, and the gate control effect can be improved.

[0071] In some embodiments, Figures 7 to 9 As shown, the memory transistor 11 may further include a gate insulating layer 112, and the gate insulating layer 112 is used to electrically isolate the gate layer 113 of the memory transistor 11 from the channel layer 111. Specifically, the gate insulating layer 112 may be located between the gate layer 113 and the channel layer 111, and its material may include a high dielectric constant insulating material such as silicon oxide or TEOS (tetraethoxysilane) to ensure insulation between the gate layer 113 and the channel layer 111.

[0072] Specifically, the gate layer 113 may be made of a conductive material such as metal (eg, tungsten or copper).

[0073] In some embodiments, Figures 7 to 9As shown, the channel layer 111 of the memory transistor 11 may include a first end 1111, a channel portion 1112, and a second end 1113 sequentially connected along the second direction X. Among them, one of the first end 1111 and the second end 1113 can be used as a drain (Drain) in the memory transistor 11, the other of the first end 1111 and the second end 1113 can be used as a source (Source) in the memory transistor 11, and the channel portion 1112 can be used as a channel (Channel) in the memory transistor 11. In addition, when the memory transistor 11 is working, the current direction in the channel (i.e., the channel portion 1112) is from the drain to the source.

[0074] Specifically, Figures 7 to 9 As shown, the gate insulation layer 112 and the gate layer 113 of the above-mentioned storage transistor 11 can be arranged in sequence around the channel portion 1112 in a direction away from the channel portion 1112, and may not cover the first end 1111 and the second end 1113 of the channel layer 111, thereby ensuring that the first end 1111 and the second end 1113 can both be exposed from both ends of the gate insulation layer 112 and the gate metal layer 113 to achieve good coupling with other structures (i.e., the bit line 30 and the common ground connection layer 20, respectively).

[0075] Specifically, the storage transistor 11 in this embodiment may be a junctionless field effect transistor, that is, it may not have a fixed source and drain as in a conventional field effect transistor. Figures 7 to 9 As shown, the doping type and concentration of the source and the drain (i.e., the first end 1111 and the second end 1113 of the channel layer 111) in the above-mentioned storage transistor 11 can be consistent with the doping type and concentration of the channel portion 1112 of the channel layer 111, so that there is no need to form PN junction doping between the source and the drain of the storage transistor 11. Therefore, in the manufacturing process of the storage transistor 11, there is no need to perform ion implantation, photolithography, ashing and cleaning processes to form PN junction doping between the source and the drain, which can simplify the preparation process flow of the above-mentioned semiconductor device 1000, speed up the production cycle of the product, and save production costs.

[0076] In some examples, such as Figures 7 to 9 As shown, the first end 1111, the channel portion 1112 and the second end 1113 of the channel layer 111 in the storage transistor 11 may be made of the same material, for example, they may all be N-type semiconductor materials (eg, N-type polysilicon).

[0077] In some examples, the cross-sectional shape of the channel layer 111 of the storage transistor 11 perpendicular to the second direction X may be a geometric shape such as a circle, a square, a rectangle, a hexagon or an octagon. Fig. 9As shown, the cross-sectional shape of the channel layer 111 of the storage transistor 11 perpendicular to the second direction X may be a rectangle.

[0078] In some examples, the thickness of the channel layer 111 of the storage transistor 11 may be less than 50 nm, wherein the thickness of the channel layer 111 refers to the distance between the upper and lower surfaces of the channel layer 111 in the first direction Z. In addition, in a specific implementation, the full depletion of the leakage current may be achieved by controlling the thickness of the channel layer 111. Exemplarily, the thickness of the channel layer 111 may be 40 nm, 30 nm, 20 nm, or 10 nm, etc., as long as it can be achieved in terms of process and the normal flow of current in the channel layer 111 is guaranteed.

[0079] In some specific embodiments, Figures 10 to 13 As shown, in the above-mentioned storage transistor 11, the end surface area of ​​the channel portion 1112 connected to the first end 1111 can be smaller than the end surface area of ​​the first end 1111 connected to the channel portion 1112, and the end surface area of ​​the channel portion 1112 connected to the second end 1113 can be smaller than the end surface area of ​​the second end 1113 connected to the channel portion 1112.

[0080] Moreover, in a specific implementation, for each storage transistor 11, the gate insulation layer 112 of the storage transistor 11 can be obtained by oxidizing the surface of the channel portion 1112 of the storage transistor 11, which will cause the cross-sectional area of ​​the channel portion 1112 in the storage transistor 11 perpendicular to the second direction X to be smaller than the cross-sectional area of ​​the first end 1111 perpendicular to the second direction X and the cross-sectional area of ​​the second end 1113 perpendicular to the second direction X.

[0081] In this embodiment, if Figures 1 to 6 as well as Figure 10 to Figure 11 As shown, the semiconductor device 1000 may further include an insulating layer 101, which is used to electrically isolate first ends 1111 of storage transistors 11 adjacent to each other along a first direction Z in different layers of storage structures 100, and to electrically isolate second ends 1113 of storage transistors 11 adjacent to each other along a first direction Z in different layers of storage structures 100.

[0082] In some examples, the material of the insulating layer 101 may be the same as or different from the material of the gate insulating layer 112 in the storage transistor 11. For example, the material of the insulating layer 101 may be an insulating material such as silicon oxide or TEOS (tetraethoxysilane). For example, the insulating layer 101 and the gate insulating layer 112 in the storage transistor 11 may be made of the same insulating material, and the two may be connected as one.

[0083] Furthermore, it can be understood that the number of layers of the storage structure 100 in the semiconductor device 1000 determines the number of layers of the storage units (i.e., storage transistors 11) stacked in the first direction Z. For example, the number of layers of the storage structure 100 can be (2×a) layers, where a is a positive integer, such as 16 or 32, and the more layers of the storage structure 100, the higher the integration of the corresponding semiconductor device 1000. Furthermore, in specific implementation, if necessary, the number of stacked layers of the storage structure 100 in the semiconductor device 1000 can be increased to improve the storage capacity of the semiconductor device 1000 to meet the storage capacity requirements.

[0084] In some embodiments, Figure 6 As shown, the multiple storage transistors 11 included in each layer of the storage structure 100 can be arranged in multiple rows along the third direction Y. In other words, the multiple storage transistors 11 included in each layer of the storage structure 100 can be arranged in rows and columns with the third direction Y and the second direction X being the column direction and the row direction respectively. In addition, in specific implementation, the total number of rows and / or the total number of columns of the storage transistors 11 in each layer of the storage structure 100 can be increased as needed to improve the storage capacity and storage density of the semiconductor device 1000.

[0085] In this embodiment, if Figure 5 As shown, the common source line structure 20 may penetrate all the storage structures 100 along the first direction Z, for example, vertically penetrate each layer of the storage structure 100 in the multi-layer storage structure 100A from top to bottom. Figure 6 As shown, in the same layer of storage structure 100, each storage transistor 11 (for example, storage transistor 11B1, storage transistor 11B2 and storage transistor 11B3) in the same column of storage transistors 10 can be connected to the same common source line structure 20. Figure 5 As shown, the memory transistors 11 (eg, the memory transistor 11A1 and the memory transistor 11A2 ) adjacent to each other along the first direction Z in the memory structures 100 at different layers may be connected to the same common source line structure 20 .

[0086] Specifically, Figure 6 As shown, in the same layer of storage structure 100, one end (i.e., the first end 1111 or the second end 1113) of the channel layer 111 of each storage transistor 11 in the same column of storage transistors 10 in the second direction X can be connected to the same common source line structure 20, for example, can be connected vertically to the same common source line structure 20. Figure 5As shown, one end of the channel layer 111 of the storage transistor 11 adjacent along the first direction Z in different layers of storage structures 100 in the second direction X (i.e., the first end 1111 or the second end 1113) can be correspondingly connected to the same common source line structure 20, for example, can be correspondingly vertically connected to the same common source line structure 20.

[0087] Furthermore, for each storage transistor 11 , the end of the channel layer 111 in the storage transistor 11 correspondingly connected to the common source line structure 20 can be considered as the source of the storage transistor 11 .

[0088] Furthermore, in a specific implementation, one end (eg, the top end) of each common source line structure 20 may be grounded, so as to realize grounding of each storage transistor 11 in the semiconductor device 1000 .

[0089] In some examples, the material of the common source line structure 20 may be the same as or different from the material of the channel layer 111 . For example, the material of the common source line structure 20 may be a conductive material such as polysilicon or metal.

[0090] In some embodiments, Figure 6 As shown, in the same layer of storage structure 100, each storage transistor 11 in two adjacent columns of storage transistors 10 (for example, a first column of storage transistors 10A and a second column of storage transistors 10B) can be connected to the same common source line structure 20 accordingly, and, in the two adjacent columns of storage transistors 10, the second end 1113 of the channel layer 111 of each storage transistor 11 in one column of storage transistors 10 (for example, the first column of storage transistors 10A) can be connected to the same common source line structure 20 accordingly with the first end 1111 of the channel layer 111 of each storage transistor 11 in the other column of storage transistors 10 (for example, the second column of storage transistors 10B).

[0091] In some specific embodiments, Figure 6 As shown, in the same layer of storage structure 100, an adjacent even-numbered column storage transistor 10 and an odd-numbered column storage transistor 10 can constitute a transistor group, for example, the first column storage transistor 10A and the second column storage transistor 10B can constitute a transistor group. In addition, in each layer of storage structure 100, two columns of storage transistors 10 in the same transistor group can be connected to the same common source line structure 20, and the common source line structure 20 can be located between the two columns of storage transistors 10 in the transistor group connected thereto.

[0092] In some examples, in the same layer of storage structure 100, the (2×i-1)th column storage transistor 10 and the (2×i)th column storage transistor 10 can together constitute a transistor group, and the (2×i)th column storage transistor 10 and the (2×i+1)th column storage transistor 10 can belong to different transistor groups. Wherein, i is a positive integer, and the column numbers of the columns of storage transistors 10 in the same layer of storage structure 100 are arranged along the second direction X (that is, Figure 6 The serial numbers of the common source line structures 20 in the semiconductor device 1000 are 1, 2, 3, ..., m in sequence, and the serial numbers of the common source line structures 20 in the semiconductor device 1000 are arranged along the second direction X (ie, Figure 6 In the direction from left to right in the figure, it can be 1, 2, 3, ..., n respectively, where m and n are both positive integers, m represents the total number of columns of storage transistors 11 included in each layer of the storage structure 100, and n represents the total number of common source line structures 20 included in the above-mentioned semiconductor device 1000.

[0093] Specifically, in the same layer of storage structure 100, the (2×i-1)th column storage transistor 10 and the (2×i)th column storage transistor 10 can be connected to the (2×i-1)th common source line structure 20 respectively, and the (2×i-1)th common source line structure 20 can be located between the (2×i-1)th column storage transistor 10 and the (2×i)th column storage transistor 10, and can separate the (2×i-1)th column storage transistor 10 from the (2×i)th column storage transistor 10.

[0094] In the same layer of storage structure 100, the (2×i)th column storage transistor 10 and the (2×i+1)th column storage transistor 10 can be connected to different common source line structures 20 respectively. For example, they can be connected to the (2×i-1)th common source line structure 20 and the (2×i)th common source line structure 20 respectively, and the (2×i-1)th common source line structure 20 and the (2×i)th common source line structure 20 can be respectively located on two pairs of sides (i.e., left and right sides) of the two adjacent columns of storage transistors 10 in the second direction X, the (2×i)th column storage transistor 10 and the (2×i+1)th column storage transistor 10.

[0095] In different layers of storage structures 100, each column of storage transistors 10 in the same column position (i.e., the same column number) can be correspondingly connected to the same common source line structure 20. Taking the jth column as an example, the jth column of storage transistors 10 in each layer of storage structures 100 can be correspondingly connected to the same common source line structure 20, where j is a positive integer.

[0096] In this embodiment, if Figure 5As shown, the memory transistors 11 adjacent to each other along the first direction Z in the memory structures 100 at different layers may be stacked along the first direction Z. Furthermore, the semiconductor device 1000 may have a plurality of memory strings 50, and each memory string 50 may be composed of a plurality of memory transistors 11 stacked along the first direction Z at the same position in the semiconductor device 1000 and belonging to memory structures 100 at different layers.

[0097] For example, Figure 5 As shown, the memory string 50A may be composed of the memory transistor 11A1 , the memory transistor 11A2 , and the memory transistor 11A3 which are stacked along the first direction Z in the semiconductor device 1000 and belong to different layers of the memory structure 100 .

[0098] Specifically, for each storage string 50, the number of storage transistors 11 included in the storage string 50 can be equal to the number of layers of the storage structure 100 included in the above-mentioned semiconductor device 1000, and the multiple storage transistors 11 included in the storage string 50 can correspond one by one to the multi-layer storage structure 100 included in the above-mentioned semiconductor device 1000.

[0099] In this embodiment, if Figure 5 As shown, the gate layers 121 of the storage transistors 11 (for example, the storage transistor 11A1 and the storage transistor 11A2) adjacent along the first direction Z in different layers of the storage structure 100 can be electrically connected, thereby realizing the series connection of the gate layers 113 of all the storage transistors 11 in the same storage string 50.

[0100] In some embodiments, Figure 5 As shown, the gate layers 113 of the storage transistors 11 (for example, the storage transistor 11A1 and the storage transistor 11A2) adjacent to each other along the first direction Z in different layers of the storage structure 100 can be connected together, for example, can be connected as a whole, thereby eliminating the need to separately provide related structures for electrically connecting the gate layers 113 of the storage transistors 11 adjacent to each other vertically in different layers of the storage structure 100, which is beneficial for simplifying the process technology of the above-mentioned semiconductor device and reducing manufacturing costs.

[0101] In some specific embodiments, Figure 5As shown, in two adjacent storage transistors 11 stacked along the first direction Z (for example, storage transistor 11A1 and storage transistor 11A2), the upper surface of the storage transistor 11 located below and the lower surface of the storage transistor 11 located above can be fitted together, for example, can be completely overlapped, so as to achieve a fitting connection between the gate layers 113 of the two, and to achieve that the gate layers 113 of all storage transistors 11 stacked along the first direction Z at one position in the multi-layer storage structure 100 are connected together, so that only the gate layer 113 of the topmost storage transistor 11 needs to be contacted, and there is no need to make a word line (Word Line, WL) connected to the gate layer 113 of the storage transistor 11, so that the current on-off control of all storage transistors 11 can be achieved.

[0102] In some examples, such as Figure 7 and Fig. 9 As shown, in the above-mentioned storage transistor 11, the surfaces of the gate layer 113 on two opposite sides in the first direction Z can be planes, so that the stacking of multiple storage transistors 11 along the first direction Z is more stable and the stacking of the multi-layer storage structure 100 is more regular.

[0103] In some embodiments, Figures 1 to 6 As shown, the semiconductor device 1000 may further include an isolation structure 40, and the isolation structure 40 runs through all the storage structures 100 along the first direction Z, for example, it may vertically run through each layer of the storage structure 100 in the multi-layer storage structure 100 from top to bottom. In addition, the isolation structure 40 may be located between adjacent storage transistors 11 in the same column of the same layer of storage structure 100, and electrically isolate adjacent storage transistors 11 in the same column of the same layer of storage structure 100, so as to independently control different storage transistors 11 in the same column of the same layer of storage structure 100.

[0104] Specifically, each storage transistor 11 in the above-mentioned semiconductor device 1000 can be provided with an isolation structure 40 on both relative sides along the third direction Y, so that any two adjacent storage transistors 11 in the third direction Y can be isolated by the isolation structure 40, and the outermost storage transistor 11 can be covered and protected.

[0105] In some examples, the isolation structure 40 may also be in contact with two opposite side surfaces of the gate layer 113 of the storage transistor 11 along the third direction Y.

[0106] In some examples, the material of the isolation structure 40 may be the same as or different from the material of the insulating layer 101. Exemplarily, the isolation structure 40 may be made of a low dielectric constant (Low K) material, for example, a material with a dielectric constant lower than 3.9, thereby facilitating the reduction of parasitic capacitance between the storage transistors 11 and ensuring its stability.

[0107] In the above embodiment, if Figures 1 to 6 As shown, each layer of the storage structure 100 may also include at least one bit line 30 (for example, a bit line 30A and a bit line 30B), and the bit lines 30 adjacent to each other along the first direction Z in different layers of the storage structure 100 may be electrically isolated by the insulating layer 101. Specifically, in the same layer of the storage structure 100, the opposite ends of the channel layer 111 of each storage transistor 10 in the same column along the second direction X may be respectively connected to the same bit line 30 and the same common source line structure 20. Moreover, for each storage transistor 11, the end of the channel layer 111 in the storage transistor 11 corresponding to the common source line structure 20 may be considered as the source of the storage transistor 11, and the end of the channel layer 111 in the storage transistor 11 corresponding to the bit line 30 may be considered as the drain of the storage transistor 11.

[0108] Specifically, the number of bit lines 30 included in each layer of the storage structure 100 may be multiple, and the multiple bit lines included in each layer of the storage structure 100 may be arranged in parallel and at intervals along the second direction X, for example, they may be arranged in parallel and at equal intervals along the second direction X. Moreover, in each layer of the storage structure 100, any two adjacent bit lines 30 may correspond to two adjacent columns of storage transistors 10, and the two adjacent columns of storage transistors 10 may be respectively connected to the two adjacent bit lines 30.

[0109] In some specific embodiments, Figure 5 and Figure 6 As shown, the channel layer 111 in the storage transistor 11 may be parallel to the second direction X and perpendicular to the first direction Z, that is, the lateral surface (e.g., the upper surface or the lower surface) of the channel layer 111 may be parallel to the second direction X and perpendicular to the first direction Z. The bit line 30 may be perpendicular to the first direction Z and the second direction Z, that is, the extension direction (i.e., the length direction) of the bit line 30 may be perpendicular to the first direction Z and the second direction Z.

[0110] Specifically, the extension direction of the bit line 30 may be consistent with the extension direction of each column of the storage transistors 10. The bit line 30 is connected to the sources of the multiple storage transistors 11 in the same column, and the common source line structure 20 is connected to the drains of the multiple storage transistors 11 in the same column and in the same vertical direction Z. Through the cooperation of the bit line 30 and the common source line structure 20, data storage and reading of any storage transistor 11 in any column of the storage transistors 10 can be achieved.

[0111] Specifically, for each layer of storage structure 100, the bit line 30 and the common source line structure 20 correspondingly connected to the same column of storage transistors 10 in the layer of storage structure 100 can be respectively located on the opposite sides of the same column of storage transistors 10 in the layer of storage structure 100 along the second direction X. For example, the bit line 30 and the common source line structure 20 correspondingly connected to the k-th column of storage transistors 10 in the layer of storage structure 100 can be respectively located on the opposite sides of the k-th column of storage transistors 10 in the layer of storage structure 100 along the second direction X, where k is a positive integer.

[0112] Specifically, in the above embodiment in which an even-numbered column storage transistor 10 and an odd-numbered column storage transistor 10 adjacent to each other in the same layer of storage structure 100 constitute a transistor group, in each layer of storage structure 100, two columns of storage transistors 10 in the same transistor group can be connected to different bit lines 30, for example, can be connected to two bit lines 30 respectively, and the two bit lines 30 can be located on opposite sides of the transistor group connected thereto along the second direction X, so that the storage transistors 11 in adjacent columns in the same layer of storage structure 100 can share a common source line structure 20, that is, a groove can be patterned between two adjacent columns of storage transistors 10, and after the groove is filled with a conductive material, a common source line structure 20 that simultaneously connects the drains of all storage transistors 11 on both sides of the vertical plane where the groove is located can be formed, which not only saves materials and further simplifies the manufacturing process, but also can control a larger number of storage transistors 11.

[0113] In some examples, the material of the bit line 30 may be the same as or different from the material of the common source line structure 20 and the channel layer 111. For example, the material of the bit line 30 may be polysilicon, as long as it is conductive to achieve coupling with the source of the storage transistor 11. For example, the bit line 30 and the channel layer 111 in the storage transistor 11 may be made of the same conductive material, and the two may be connected as one.

[0114] In some examples, the material of the bit line 30 and the material of the channel layer 111 can be the same, and the bit line 30 and the channel layer 111 in the same layer of the storage structure 100 can be provided by the same semiconductor layer 102, that is, the two can be parts of the same semiconductor layer 102. Among them, the semiconductor layer 102 can be made of N-type polysilicon or P-type polysilicon, for example, it can be made of N-type polysilicon. Exemplarily, the length of the bit line 30 can be the same as the length of the semiconductor layer 102 along the third direction X, and the thickness of the bit line 30 can also be equal to the thickness of the semiconductor layer 102.

[0115] It should be noted that in this embodiment, there is no concept of a word line (WL) connected to the gate of a conventional transistor. Instead, a common source line structure 20 is used to connect the sources of each storage transistor 11 in multiple columns of storage transistors 10 in the same vertical direction Z. It can be understood that the common source line structure 20 in this embodiment can be in a sheet or layered form, so that the sources of all storage transistors 11 located on at least one side thereof can be well coupled thereto. Combined with the connection between the bit line (BL) and the drain of the storage transistor 11, any storage transistor 11 can be accurately located for data storage and reading.

[0116] Furthermore, in the prior art, if the connection between the peripheral circuit and the source / drain of the storage transistor is to be achieved, it is necessary to form a through hole on the semiconductor layer and then make a contact (Contact, CT) to achieve subsequent control. The process of opening the through hole is relatively complicated. Moreover, if the source / drain connection of all storage transistors is to be achieved, all storage transistors need to be etched to form a large number of through holes, which is a huge workload and has great process difficulty. If it is necessary to make a contact for each one to achieve subsequent control, it is also a large and complicated task, and the material cost and process cost are both high.

[0117] In the present embodiment, the design of the common source line structure 20 eliminates the need to open a through hole on the storage transistor 11. It is only necessary to etch a groove at a preset position of the storage structure 100 and then fill it with conductive material to form the common source line structure 20, so as to connect a large number of storage transistors 11. Subsequently, it is only necessary to make contact with each common source line structure 20 to achieve control of all storage transistors 11 coupled to the common source line structure 20. This not only greatly reduces the material cost and process cost, but is also easier to implement in terms of process, which can greatly shorten the product cycle.

[0118] Specifically, in the above embodiment where each layer of the memory structure 100 further includes a bit line 30, as shown in FIG. Fig.14 As shown, the widths of the bit lines 30 adjacent to each other in the first direction Z in different layers of the storage structure 100 may gradually decrease along the first direction Z (eg, from bottom to top) to form a first step structure.

[0119] Specifically, the semiconductor device 1000 may further include a plurality of bit line contacts 60 , and the plurality of bit line contacts 60 may be electrically connected to corresponding bit lines 30 at positions of the first stepped structure, respectively.

[0120] Specifically, the semiconductor device 1000 may further include a dielectric layer 500 , the dielectric layer 500 may cover the first stepped structure, and the word line contact 60 may pass through the dielectric layer 500 on the first stepped structure to be electrically connected to the corresponding bit line 30 .

[0121] Furthermore, in a specific implementation, a first transfer layer 600 may be provided on the bit line 30, and the plurality of bit line contacts 60 may be respectively connected to the first transfer layer 600 on the corresponding bit line 30 at the position of the first step structure (e.g., vertically connected) to achieve electrical connection with the corresponding bit line 30. Furthermore, the first transfer layer 600 can reduce the contact resistance between the bit line contact 60 and the corresponding bit line 30.

[0122] Specifically, the dielectric layer 500 may also cover the topmost storage structure 100 and the common source line structure 20 of the semiconductor device 1000. In addition, the semiconductor device 1000 may further include a plurality of word line contacts 70 and a common source line contact 80. Each word line contact 70 may pass through the dielectric layer 500 on the topmost storage structure 100 to be electrically connected (e.g., vertically connected) to the gate layer 113 of the corresponding storage transistor 11 in the topmost storage structure 100. Each common source line contact 80 may pass through the dielectric layer 500 on the common source line structure 20 to be electrically connected (e.g., vertically connected) to the corresponding common source line structure 20.

[0123] Furthermore, in a specific implementation, a second transfer layer 800 may be provided on the common source line structure 20, and the common source line contact 80 may be connected (for example, vertically connected) to the second transfer layer 800 on the corresponding common source line structure 20 to achieve electrical connection with the corresponding common source line structure 20. Furthermore, the second transfer layer 800 can reduce the contact resistance between the common source line contact 80 and the corresponding common source line structure 20.

[0124] In some examples, the dielectric layer 500 and the insulating layer 101 may be made of the same conductive material, and the two may be connected as one.

[0125] In some examples, the bit line contact 60 and the common source line contact 80 may be made of a conductive material such as metal.

[0126] In some examples, the material of the word line contact 70 may be the same as the material of the gate layer 113 in the storage transistor 11. For example, the material of the word line contact 70 may be a conductive material such as tungsten or copper.

[0127] In some examples, the material of the first transfer layer 600 and the second transfer layer 800 may be a conductive material such as titanium silicide.

[0128] Furthermore, it should be noted that the bit line contact 60, word line contact 70 and common source line contact 80 can be electrically connected to a peripheral circuit (eg, a peripheral circuit chip) to establish a coupling relationship between the semiconductor device 1000 and the peripheral circuit to facilitate subsequent related control.

[0129] In some alternative embodiments, the widths of the bit lines 30 adjacent to each other along the first direction Z in the different layers of the memory structure 100 may not gradually decrease along the first direction Z, for example, they may remain unchanged along the first direction Z. Fig.15 As shown, each layer of the storage structure 100 may further include at least one bit line connection line 90. Furthermore, in the same layer of the storage structure 100, each bit line connection line 90 may be connected to a bit line 30, each bit line 30 may be connected to one or two bit line connection lines 90, and for each bit line 30, a bit line connection line 90 correspondingly connected to the bit line 30 may be located on one side of at least one column of storage transistors 10 correspondingly connected to the bit line 30 along the third direction Y, or two bit line connection lines 90 correspondingly connected to the bit line 30 may be located on opposite sides of at least one column of storage transistors 10 correspondingly connected to the bit line 30 along the third direction Y, respectively.

[0130] Specifically, the lengths of the bit line connection lines 90 adjacent to each other in the first direction Z in different layers of the storage structure 100 may gradually decrease along the first direction Z (eg, from bottom to top) to form a second step structure.

[0131] Correspondingly, the plurality of bit line contacts 60 may be electrically connected to the corresponding bit line connection lines 90 at the positions of the second step structures, respectively, so as to be electrically connected to the corresponding bit lines 30 .

[0132] In some examples, the material of the bit line connection line 90 can be the same as the material of the bit line 30, for example, both can be polysilicon (e.g., N-type polysilicon), and the two can be connected as one and can be provided by the same semiconductor layer 102, thereby reducing the use of other materials and simplifying the process while ensuring that the bit line connection line 90 and the bit line 30 are effectively connected.

[0133] Furthermore, it should be noted that the memory array architecture formed by the memory transistor 11 in this embodiment can promote 4F 2 1T0C DRAM has a higher integrated storage density, and when the pitch size is relatively large, the same storage capacity can be achieved by increasing the number of stacked layers. This not only reduces the production cost, but also greatly reduces the technical challenges brought about by the miniaturization of the technology stage.

[0134] In the above embodiment, if Figure 5 As shown, the semiconductor device 1000 may further include a substrate 200, and the multi-layer storage structure 100 may be stacked on one side of the substrate 200 in a direction away from the substrate 200 (ie, the first direction Z). The substrate 200 is used to support the device structure thereon.

[0135] Specifically, the substrate 200 refers to an underlying material structure on which subsequent material layers can be added or stacked, which can be a thinned substrate 200 thinned by grinding, wet / dry etching, chemical mechanical polishing (CMP) or any combination thereof. Such a substrate 200 itself can be patterned, or the material disposed on top of the substrate 200 can be patterned, or can remain unpatterned to form a specific functional structure.

[0136] In addition, the substrate 200 may include a variety of semiconductor materials, such as silicon (e.g., single crystal silicon), silicon germanium (SiGe), silicon on insulator (SOI), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), germanium on insulator (GOI), and silicon carbide (SIC), etc. Alternatively, the substrate 200 may be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0137] In some examples, the substrate 200 may be made of semiconductor material, insulating material, conductive material, or any combination thereof.

[0138] The substrate 200 may be a single-layer structure, for example, a single-layer structure made of the above-mentioned silicon, germanium, gallium arsenide, etc. The substrate 200 may also be a multi-layer structure, for example, a laminate of silicon and silicon germanium, a laminate of silicon and silicon carbide, a layered substrate 200 of silicon on insulator or silicon germanium on insulator, etc.

[0139] In some specific embodiments, the substrate 200 may be made of silicon on insulator, so that no PN junction needs to be generated in the transistor, thereby eliminating the latching effect, improving the ability of the semiconductor device 1000 to withstand negative pressure, and eliminating the need to introduce additional manufacturing processes, thereby simplifying the process flow of the semiconductor device 1000.

[0140] In some examples, one or more peripheral devices may be formed on and / or in substrate 200. Among other things, the peripheral devices may include any suitable digital, analog, and / or mixed-signal peripheral circuits for facilitating the operation of semiconductor device 1000. For example, the peripheral devices may include one or more of a data buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor).

[0141] In some specific embodiments, Figure 5As shown, the semiconductor device 1000 may further include an oxide layer 300 . The oxide layer 300 is disposed between the substrate 200 and the multi-layer storage structure 100 . The oxide layer 300 is used to protect the substrate 200 , and the material of the oxide layer 300 may be silicon oxide.

[0142] Specifically, Figure 5 As shown, the semiconductor device 1000 may further include a buffer layer 400 , which may be disposed between the oxide layer 300 and the multi-layer storage structure 100 . The buffer layer 400 is used to improve the quality of epitaxial growth on the substrate 200 , and its material may be silicon nitride.

[0143] As can be seen from the above, the semiconductor device provided by the embodiment of the present application is stacked with multiple layers of storage structures along a first direction, and each layer of the storage structure includes a plurality of storage transistors arranged in multiple columns along a second direction, the first direction is perpendicular to the second direction, and the storage transistor includes a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer, and the storage transistors in the same column of the same layer of the storage structure are correspondingly connected to the same common source line structure, and the storage transistors adjacent to each other along the first direction in different layers of the storage structure are correspondingly connected to the same common source line structure, and the common source line structure runs through each layer of the storage structure along the first direction, so that the storage transistor can be a junctionless field effect transistor, that is, there can be no fixed source and drain in a conventional field effect transistor, and there is no need to form a PN junction doping between the source and the drain of the storage transistor, so that the manufacturing process of the storage transistor does not need to perform ion implantation, photolithography, ashing and cleaning processes to form a PN junction doping between the source and the drain, which can simplify the process flow, speed up the production cycle of the product, and save production costs. In addition, the gate layer in the storage transistor is arranged around the channel layer, which can improve the control of the gate over the channel in the storage transistor, so that the channel can be fully depleted more effectively in the off state, the off-state leakage current can be reduced, and the gate control effect can be improved.

[0144] See also Fig.16 , Fig.16 The schematic diagram of the manufacturing method of the semiconductor device provided in the embodiment of the present application is also provided in Figures 1 to 15 as well as Figures 17 to 25 , Figures 1 to 15 as well as Figures 17 to 25 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present application. The specific process of the method for manufacturing the semiconductor device provided by the embodiment can be as follows:

[0145] Step S11: forming a multi-layer storage structure 100 stacked along a first direction Z, wherein each layer of the storage structure 100 includes a plurality of storage transistors 11, and the plurality of storage transistors 11 are arranged in a plurality of columns along a second direction X, wherein the first direction Z is perpendicular to the second direction X, and the storage transistors 11 include a channel layer 111 perpendicular to the first direction Z and a gate layer 113 (such as Figures 1 to 6 shown).

[0146] Step S12: forming at least one common source line structure 20, wherein the common source line structure 20 penetrates the multi-layer storage structure 100 along the first direction Z, and the storage transistors 10 in the same column of the same layer of the storage structure 100 are correspondingly connected to the same common source line structure 20, and the storage transistors 11 adjacent to each other along the first direction Z in different layers of the storage structure 100 are correspondingly connected to the same common source line structure 20 (e.g. Figures 1 to 6 shown).

[0147] In some embodiments, the above step S11 may include:

[0148] Step S111: forming a stacked structure 1000A, the stacked structure 1000A comprising a plurality of insulating layers 101 and a plurality of semiconductor layers 102 alternately stacked along a first direction Z, the semiconductor layer 102 comprising at least one bit line 30, and a plurality of channel layers 111 arranged in a plurality of columns along a second direction X, the channel layers 110 in the same column of the same semiconductor layer 102 correspondingly connected to the same bit line 30, the adjacent channel layers 111 in the same column of the same semiconductor layer 102 are arranged at intervals, and the insulating layer 101 fills the interval area between the adjacent channel layers 111 (such as Fig.17 and Fig.18 shown).

[0149] Specifically, Fig.17 As shown, a stacked structure 1000A may be formed on a substrate 200. The substrate 200 is used to support a device structure thereon and may include semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). The stacked structure 1000A may include multiple layers of insulating layers 101 and semiconductor layers 102 alternately stacked in a first direction Z perpendicular to the substrate 200.

[0150] In the stacked structure 1000A, the semiconductor layer 102 may be formed between two adjacent insulating layers 101. The material of the semiconductor layer 102 may be, but not limited to, a semiconductor material such as N-type polysilicon, and the material of the insulating layer 101 may be, but not limited to, an insulating material such as silicon oxide. In a specific embodiment, the stacked structure 1000A may be a stacked structure of an N-type polysilicon layer / silicon oxide layer.

[0151] Furthermore, in a specific implementation, forming a semiconductor layer 102 between two adjacent insulating layers 101 may include: a thin film deposition method such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc. may be used to sequentially form a first insulating layer 101 and a whole-surface semiconductor layer on one side of the substrate 200; then, the whole-surface semiconductor layer may be patterned, for example, an anisotropic etching process (such as an ion etching process, a reactive ion etching process, or other dry etching process) may be used to etch the whole-surface semiconductor layer from top to bottom in a first direction Z perpendicular to the substrate 200. A semiconductor layer on the surface is formed with multiple openings to obtain a patterned semiconductor layer 102 (that is, the semiconductor layer 102 in the above-mentioned stacked structure 1000A); then, a thin film deposition method such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc. can be used to form a second insulating layer 101 on the side of the first insulating layer 101 away from the substrate 200. The second insulating layer 101 covers the patterned semiconductor layer 102 and fills the openings on the patterned semiconductor layer 102, thereby completing the formation of a semiconductor layer 102 between two adjacent insulating layers 101.

[0152] Specifically, after stacking and depositing multiple layers of semiconductor layers 102 and insulating layers 101 to form a preliminary stacking structure 1000A, further processing is required to form a semiconductor device 1000, and in the process of forming multiple storage transistors 11 arranged in multiple columns in each layer of the storage structure 100, specific functional areas can be divided on the semiconductor layer 102 by patterning processes and the like. The bit line 30 in this embodiment is pre-designed and reserved in the semiconductor layer 102, such as being designed to be reserved on one side of the semiconductor layer 102 without being damaged by etching, and can be specifically reserved on one side of a column of storage transistors 10, so that there is no need to separately form a structure for connecting the drains of each storage transistor 11 in a column of storage transistors 10, thereby simplifying the production process.

[0153] Exemplarily, the material of the semiconductor layer 102 is not limited, and may be a material containing silicon or a metal oxide, etc. Taking metal oxide as an example, the semiconductor layer 102 may be an Indium Gallium Zinc Oxide (IGZO) layer, but is not limited thereto.

[0154] It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mgx Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO and other materials, the specific selection can be made according to the actual situation.

[0155] Exemplarily, the material of the insulating layer 101 may be an insulating material, such as but not limited to silicon oxide, and may also be TEOS (tetraethoxysilane).

[0156] In addition, after each insulating layer 101 and semiconductor layer 102 is deposited, an annealing process (e.g., rapid thermal annealing, oxidation densification, etc.) and / or a planarization process (e.g., chemical mechanical planarization) may be performed to harden and / or planarize each layer in the stack structure 1000A so that the subsequent deposition stack remains flat.

[0157] In some specific embodiments, Fig.17As shown, before forming the stacked structure 1000A on the substrate 200, the method for manufacturing the semiconductor device may further include: forming an oxide layer 300 on the substrate 200; and forming a buffer layer 400 on the side of the oxide layer 300 facing away from the substrate 200. Accordingly, the stacked structure 1000A may be formed on the side of the buffer layer 400 facing away from the oxide layer 300. Specifically, the oxide layer 300 is used to protect the substrate 200, and its material may be silicon oxide. The buffer layer 400 is used to improve the quality of epitaxial growth on the substrate 200, and its material may be silicon nitride.

[0158] Step S112: removing the insulating layer 101 adjacent to the periphery of the channel layer 111 to obtain a gap 103 (such as Fig.19 and Fig. 20 shown).

[0159] Specifically, Fig.19 and Fig. 20 As shown, surfaces of each channel layer 111 on two opposite sides in the first direction Z may be exposed in the gap 103 , and surfaces of each channel layer 111 on two opposite sides in the third direction Y may be exposed in the gap 103 .

[0160] Specifically, Fig.19 and Fig. 20 As shown, each channel layer 111 may include a first end portion 1111, a channel portion 1112, and a second end portion 1113 sequentially connected along the second direction X. Moreover, the entire surface of the channel portion 1112 of each channel layer 111 may be exposed in the above-mentioned gap 103, at least a portion of the surface of the first end portion 1111 of each channel layer 111 may be exposed in the above-mentioned gap 103, and at least a portion of the surface of the second end portion 1113 of each channel layer 111 may be exposed in the above-mentioned gap 103, so as to ensure that the gate layer 113 formed subsequently can completely cover the channel portion 1112 of the channel layer 111.

[0161] In some specific embodiments, Fig.19 and Fig. 20As shown, the gap 103 may include a first gate hole 103A and a second gate hole 103B that are connected, the first gate hole 103A is used to expose the surface of the channel layer 111 on two opposite sides in the first direction Z, and the second gate hole 103B is used to expose the surface of the channel layer 111 on two opposite sides in the third direction X. Accordingly, the above step S112 may include: etching the insulating layer 101 adjacent to the opposite sides of each channel layer 111 in the first direction Z respectively to form the first gate hole 103A that at least partially penetrates the stack structure 1000A along the third direction Y, and etching the insulating layer 101 adjacent to the opposite sides of each channel layer 111 in the third direction Y respectively to form the second gate hole 103B that at least partially penetrates the stack structure 1000A along the first direction Z.

[0162] Specifically, Fig.21 and Fig. 22 As shown, after forming the first gate hole 103A and the second gate hole 103B, the surrounding surfaces of the channel layer 111 may not be completely exposed in the first gate hole 103A and the second gate hole 103B. For example, the surfaces of the channel layer 111 on two opposite sides in the first direction Z are exposed in the first gate hole 103A, but the surfaces of the channel layer 111 on two opposite sides in the third direction Y are not exposed in the second gate hole 103B. Therefore, in order to ensure that the surrounding surfaces of the channel layer 111 can be fully exposed to the above-mentioned first gate hole 103A and the second gate hole 103B, after forming the above-mentioned first gate hole 103A and the second gate hole 103B, the manufacturing method of the above-mentioned semiconductor device may also include: removing the insulating layer 101 covering the surrounding surfaces of the channel layer 111 through the first gate hole 103A and the second gate hole 103B until the surrounding surfaces of the channel layer 111 are exposed to the first gate hole 103A and the second gate hole 103B, thereby ensuring that the gap 103 including the first gate hole 103A and the second gate hole 103B can expose the surrounding surfaces of the channel layer 111.

[0163] Step S113: forming a gate insulating layer 112 and a gate layer 113 covering the gate insulating layer 112 on the exposed peripheral surfaces of the channel layer 111 through the gap 103, thereby obtaining a storage transistor 11 (eg, Fig.23 and Fig.24 shown).

[0164] Specifically, in the above embodiment where the gap 103 includes the first gate hole 103A and the second gate hole 103B, as shown in FIG. Fig.23 and Fig.24As shown, the above step S113 may include: sequentially forming a gate insulating layer 112 and a gate layer 113 covering the gate insulating layer 112 on the inner wall surfaces of the first gate hole 103A and the second gate hole 103B to obtain a storage transistor 11 including a channel layer 111, a gate insulating layer 112 and a gate layer 113.

[0165] Specifically, the gate insulating layer 112 may be formed by oxidizing the exposed peripheral surfaces of the channel layer 111, or may be formed by thin film deposition methods such as atomic layer deposition (ALD) and physical vapor deposition (PVD).

[0166] Moreover, in a specific implementation, the manufacturing method of the above-mentioned semiconductor device may further include: filling a dielectric material (e.g., silicon oxide) in the first gate hole 103A and the second gate hole 103B formed with a gate insulation layer 112 and a gate layer 113, forming an insulating filling layer 104 to fill the remaining space in the first gate hole 103A and the second gate hole 103B, thereby achieving coverage and protection of the gate layer 113 in the first gate hole 103A and the second gate hole 103B.

[0167] In some specific embodiments, when executing the above-mentioned step S112 and the above-mentioned step S113, the following steps can be specifically performed: etching downward from the top of the stacked structure 1000A to form a second gate hole 103B that penetrates all semiconductor layers 102 and all insulating layers 101, and then continuing to perform specific etching in the second gate hole 103B to etch the insulating layers 101 on the upper and lower layers of each channel layer 111 to form a first gate hole 103A, and setting a mask layer for other structures (such as the insulating layer 101 on the side) in advance to prevent them from being removed or damaged, etching until the remaining design thickness of the insulating layer 101 surrounds and wraps around the channel layer 111, and the remaining insulating layer 101 here is the gate insulating layer 112, or the insulating layers 101 on the upper and lower layers of the channel layer 111 are completely removed, and then insulating material is re-deposited around the channel layer 111 to form the gate insulating layer 112.

[0168] Specifically, after obtaining the gate insulating layer 112, a gate layer 113 surrounding the remaining insulating layer 101 can be formed by depositing a conductive metal or by an ISSG (In-Situ Steam Generation) process. In this process, it is also necessary to remove (e.g., wet removal) excess gate metal and perform grinding (e.g., chemical mechanical polishing) to ensure that the gate layer 113 is flat and smooth.

[0169] In some examples, the selectivity of the etching process used to form the channel layer 111 can be adjusted so that the channel layer 111 is formed to have a smooth surface or include multiple faceted surfaces. In this way, the channel layer 111 can be formed to have different contour shapes, such as circular, square, rectangular, hexagonal, octagonal, etc.

[0170] Furthermore, it should be noted that, in the process of forming the gate layer 113 outside the gate insulating layer 112, since the stacked structure 1000A has a large number of layers, if the gap 103 (i.e., the first gate hole 103A and the second gate hole 103B) is filled with gate metal, a deeper metal layer will be formed. From a process point of view, the subsequent etching of the gate metal layer 113 is difficult, and it is difficult to etch a suitable groove in the gate metal to make the storage transistor 11. Therefore, in this embodiment, after the gate insulating layer 112 and the gate layer 113 covering the gate insulating layer 112 are sequentially formed on the inner wall surfaces of the first gate hole 103A and the second gate hole 103B, it can be ensured that there is still residual space in at least one of the first gate hole 103A and the second gate hole 103B formed with the gate insulating layer 112 and the gate layer 113, so as to reduce the process difficulty.

[0171] In some embodiments, Figure 5 and Figure 6 As shown, after the above S11, the manufacturing method of the semiconductor device may further include:

[0172] Step S13 : forming a second trench penetrating the stacked structure 1000A along the first direction Z, wherein the second trench separates adjacent storage transistors 11 in the same column of the storage structure 100 in the same layer.

[0173] Step S14 : filling the second trench with insulating material to form an isolation structure 40 .

[0174] Specifically, after forming the storage transistor 11, that is, after forming the multi-layer storage structure 100 stacked along the first direction Z, the stacked structure 1000A can continue to be patterned, such as by etching, to form a plurality of second trenches vertically penetrating all the storage structures 100 to the surface of the substrate 200 (or the cache layer 400) between two adjacent storage transistors 11 in the same column in the same layer of the storage structure 100, and then fill each second trench with isolation material to form an isolation structure 40 that vertically separates two adjacent storage transistors 11 in the third direction Y.

[0175] The material of the isolation layer 40 (ie, isolation material) may be the same as or different from the material of the insulating layer 101. For example, the isolation layer 40 may be made of a low dielectric constant (Low K) material.

[0176] Specifically, Fig.25As shown, in the above-mentioned embodiment in which the above-mentioned gap 103 includes the first gate hole 103A and the second gate hole 103B, the above-mentioned step S13 may specifically include: retaining part of the insulating filling layer 104 on the outer wall of two adjacent storage transistors 11 in the third direction Y, patterning a second groove between the two relative parts of the insulating filling layer 104 and vertically penetrating all the storage structures 100 to the surface of the substrate 200 (or the cache layer 400), and then filling each second groove with isolation material to form an isolation structure 40 of two adjacent storage transistors 11 vertically spaced in the third direction Y.

[0177] Furthermore, during specific implementation, the above steps S13 and S14 may be executed before the above step S12, or after the above step S12, or may be executed in parallel with the above step S12.

[0178] In some embodiments, Figure 5 and Figure 6 As shown, the above step S12 may include:

[0179] Step S121: at least one first groove is formed along the first direction Z and passes through the stack structure 1000A, wherein one end of each channel layer 111 in the same column of the same layer storage structure 100 along the second direction X is correspondingly exposed on the inner wall surface of the same first groove, and one end of the channel layers 111 adjacent to each other along the first direction Z in different layers of storage structures 100 along the second direction X is correspondingly exposed on the inner wall surface of the same first groove.

[0180] Step S122 : filling the first trench with a conductive material to form a common source line structure 20 .

[0181] Specifically, after forming the storage transistor 11, that is, after forming the multi-layer storage structure 100 stacked along the first direction Z, the stacked structure 1000A may continue to be patterned, such as by etching, to form a plurality of first trenches vertically penetrating all the storage structures 100 to the surface of the substrate 200 (or the cache layer 400) between two adjacent columns of storage transistors 10 in the same layer of storage structure 100, and then fill each first trench with a conductive material to form a common source line structure 20 that separates two adjacent columns of storage transistors 10 in the second direction X. The conductive material may be a conductive material such as a semiconductor material and / or a metal material.

[0182] In some embodiments, Fig.14 As shown, the manufacturing method of the semiconductor device may further include:

[0183] Step S15: etching the stacked structure 1000A so that the widths of the bit lines 30 adjacent to each other along the first direction Z in the storage structures 100 at different layers gradually decrease along the first direction Z to form a first step structure.

[0184] Step S16: forming a plurality of bit line contacts 60 , wherein the plurality of bit line contacts 60 are electrically connected to corresponding bit lines 30 at positions of the first stepped structure.

[0185] Specifically, after forming the first step structure, the upper surfaces of the bit lines 30 may be exposed at the step surfaces of the first step structure. Furthermore, before forming the bit line contacts 60, the method for manufacturing the semiconductor device may further include: forming first transfer layers 600 on the bit lines 30 exposed at the step surfaces of the first step structure. Next, the bit line contacts 60 may be formed on the first transfer layers 600.

[0186] Furthermore, in a specific implementation, the first transfer layer 600 can be deposited on the bit line 30 by a deposition method (such as atomic layer deposition), and is deposited on the bit line 30 in a high-temperature liquid state, and then contacts the bit line contact 60 to achieve coupling.

[0187] In some embodiments, Fig.14 As shown, the manufacturing method of the semiconductor device may further include:

[0188] Step S17 : forming a plurality of common source line contacts 80 , wherein the plurality of common source line contacts 80 are electrically connected to the common source line structures 20 respectively and correspondingly.

[0189] Specifically, before forming the common source line contact 80 , the method for manufacturing the semiconductor device may further include: forming a second transfer layer 800 on each common source line junction 20 . Next, a common source line contact 80 may be formed on the second transfer layer 800 .

[0190] Furthermore, in a specific implementation, the second transfer layer 800 can be deposited on the common source line structure 20 by a deposition method (such as atomic layer deposition), and is deposited on the common source line structure 20 in a high-temperature liquid state, and then contacts the common source line 80 to achieve coupling.

[0191] In some embodiments, Fig.14 As shown, the manufacturing method of the semiconductor device may further include:

[0192] Step S18 : forming a plurality of word line contacts 70 , wherein the plurality of word line contacts 70 are electrically connected to the gate layer 113 of the storage transistor 11 in the topmost storage structure 100 .

[0193] Furthermore, it can be understood that the bit line contact 60, the common source line contact 80 and the word line contact 70 in this embodiment can be used to couple with peripheral circuits to establish a coupling relationship between the semiconductor device 1000 and the peripheral circuits to facilitate subsequent related control.

[0194] It should be noted that the specific structure of the semiconductor device 1000 in this embodiment can refer to the specific implementation in the above-mentioned embodiment of the semiconductor device 1000, so it will not be repeated here.

[0195] As can be seen from the above, the manufacturing method of the semiconductor device provided in the embodiment of the present application forms a multi-layer storage structure stacked along a first direction, each layer of the storage structure includes a plurality of storage transistors, and the plurality of storage transistors are arranged in multiple columns along a second direction, the first direction is perpendicular to the second direction, and the storage transistor includes a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer, and forms at least one common source line structure, the common source line structure runs through the multi-layer storage structure along the first direction, and the storage transistors in the same column of the same layer of the storage structure are correspondingly connected to the same common source line structure, and the storage transistors adjacent to each other along the first direction in different layers of the storage structure are correspondingly connected to the same common source line structure, so that the storage transistor can be a junctionless field effect transistor, that is, there can be no fixed source and drain in a conventional field effect transistor, and there is no need to form a PN junction doping between the source and the drain of the storage transistor, so that the production of the storage transistor does not need to perform ion implantation, photolithography, ashing and cleaning processes to form a PN junction doping between the source and the drain, which can simplify the process flow, speed up the production cycle of the product, and save production costs. In addition, the gate layer in the storage transistor is arranged around the channel layer, which can improve the control of the gate over the channel, so that the channel can be fully depleted more effectively in the off state, the off-state leakage current can be reduced, and the gate control effect can be improved.

[0196] See also Fig.26 , Fig.26 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application. Fig.26 As shown, the electronic device 2000 may include the semiconductor device 1000 of any of the above embodiments, or include the semiconductor device 1000 manufactured by the method for manufacturing the semiconductor device of any of the above embodiments.

[0197] Specifically, the semiconductor device 1000 may include a multi-layer storage structure stacked along a first direction and at least one common source line structure. Each layer of the storage structure includes a plurality of storage transistors, which are arranged in multiple columns along a second direction, the first direction is perpendicular to the second direction, and the storage transistor includes a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer. The common source line structure runs through each layer of the storage structure in the multi-layer storage structure along the first direction, and the storage transistors in the same column in the same layer of the storage structure are correspondingly connected to the same common source line structure, and the storage transistors adjacent to each other along the first direction in different layers of the storage structure are correspondingly connected to the same common source line structure.

[0198] In some examples, the electronic device 2000 may be a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The data storage device may include a memory in a computer, etc., which is not specifically limited here.

[0199] In some embodiments, the electronic device 2000 may include a housing and a circuit board disposed in the housing, and the semiconductor device 1000 may be integrated on the circuit board. In addition, during specific implementation, the electronic device 2000 may also include other necessary elements or components, which are not limited in the embodiments of the present application.

[0200] In some specific embodiments, an external control device such as a controller or an actuator coupled to the semiconductor device 1000 may also be integrated on the circuit board. For example, the electronic device further includes a controller integrated on the circuit board. The controller is coupled to the semiconductor device 1000, and the controller can control the read and write operations of the semiconductor device 1000.

[0201] For example, the controller may be configured to control the read and write operations of the storage transistors in the semiconductor device 1000 through the bit line and common source line structure in the semiconductor device 1000. The controller may specifically manage the data stored in the semiconductor device 1000 and communicate with the host.

[0202] In some examples, the controller is designed to operate in an embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. The controller can be configured to control operations of the semiconductor device 1000, such as read, erase, and program operations. The controller can also be configured to manage various functions related to data stored or to be stored in the semiconductor device 1000, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.

[0203] In some examples, the controller is also configured to process error correction codes (ECC) on data read from or written to the semiconductor device 1000. The controller may also perform any other suitable functions, such as formatting the semiconductor device 1000. The controller may communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0204] The controller and one or more semiconductor devices 1000 can be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the semiconductor device 1000 system can be implemented and packaged into different types of terminal electronic products.

[0205] In one example, the controller and the single semiconductor device 1000 may be integrated into a semiconductor device card. The semiconductor device card may include a PC card (PCMCIA, Personal Computer Semiconductor Device Card International Association), a CF card, a Smart Media (SM) card, a semiconductor device stick, a multimedia card (MMC, RS MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The semiconductor device card may also include a semiconductor device card connector that electrically couples the semiconductor device card with a host.

[0206] The above description of practical applications of the semiconductor device 1000 is merely exemplary and should not be construed as limiting the present application. Those skilled in the art may adaptably apply the semiconductor device 1000 to different types of electronic devices according to actual needs.

[0207] It should be noted that the electronic device provided in the embodiment of the present application, since it is equipped with the semiconductor device provided in the embodiment of the present application, can achieve the beneficial effects that can be achieved by any semiconductor device provided in the embodiment of the present application. Please refer to the previous embodiments for details, which will not be repeated here.

[0208] In the description of this specification, the description with reference to the terms "Example 1", "Example 2", etc. means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0209] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: A multi-layer storage structure stacked along a first direction, each layer of the storage structure comprising a plurality of storage transistors, the plurality of storage transistors being arranged in a plurality of columns along a second direction, the first direction being perpendicular to the second direction, the storage transistor comprising a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer; At least one common source line structure, the common source line structure passes through the multi-layer storage structure along the first direction, and the storage transistors in the same column in the same layer of storage structure are correspondingly connected to the same common source line structure, and the storage transistors adjacent along the first direction in different layers of storage structures are correspondingly connected to the same common source line structure.

2. The semiconductor device according to claim 1, wherein: Each layer of the storage structure further includes at least one bit line, and opposite ends of the channel layer of the storage transistors in the same column in the same layer of the storage structure are respectively connected to the same bit line and the same common source line structure.

3. The semiconductor device according to claim 2, characterized in that The channel layer is parallel to the second direction, the bit line is perpendicular to the first direction and the second direction, and the bit line and the common source line structure corresponding to the storage transistors in the same column in the same layer of storage structure are respectively located on opposite sides of the storage transistors in the same column in the same layer of storage structure along the second direction.

4. The semiconductor device according to claim 3, characterized in that The widths of the bit lines adjacent to each other along the first direction in different layers of storage structures gradually decrease along the first direction to form a step structure; The semiconductor device further includes a plurality of bit line contacts, each of which is electrically connected to the corresponding bit line at a position of the step structure.

5. The semiconductor device according to claim 1, wherein: The plurality of storage transistors are arranged in a plurality of rows along a third direction, and the third direction is perpendicular to the first direction and the second direction.

6. The semiconductor device according to claim 1, wherein: An adjacent even-numbered column of storage transistors and an adjacent odd-numbered column of storage transistors in the same layer of storage structure form a transistor group and are correspondingly connected to the same common source line structure.

7. The semiconductor device according to claim 6, characterized in that The two columns of storage transistors in the same transistor group are correspondingly connected to different bit lines.

8. The semiconductor device according to claim 1, wherein: The storage transistor comprises: The gate insulating layer comprises a first end, a channel portion and a second end connected in sequence along the second direction, the gate insulating layer and the gate layer are sequentially arranged around the channel portion, and the gate insulating layer electrically isolates the gate layer from the channel portion.

9. The semiconductor device according to claim 8, characterized in that An end surface area of ​​the channel portion connected to the first end is smaller than an end surface area of ​​the first end connected to the channel portion, and an end surface area of ​​the channel portion connected to the second end is smaller than an end surface area of ​​the second end connected to the channel portion.

10. The semiconductor device according to claim 1, wherein: The gate layers of the storage transistors adjacent to each other along the first direction in different layers of storage structures are connected together.

11. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: An isolation structure, wherein the isolation structure penetrates the multi-layer storage structure along the first direction and is located between adjacent storage transistors in the same column in the same layer of the storage structure, and electrically isolates adjacent storage transistors in the same column in the same layer of the storage structure.

12. A method for manufacturing a semiconductor device, characterized in that: include: Forming a multi-layer storage structure stacked along a first direction, each layer of the storage structure comprising a plurality of storage transistors, the plurality of storage transistors being arranged in a plurality of columns along a second direction, the first direction being perpendicular to the second direction, the storage transistor comprising a channel layer perpendicular to the first direction and a gate layer arranged around the channel layer; At least one common source line structure is formed, and the common source line structure runs through the multi-layer storage structure along the first direction, and the storage transistors in the same column in the same layer of storage structure are correspondingly connected to the same common source line structure, and the storage transistors adjacent to each other along the first direction in different layers of storage structure are correspondingly connected to the same common source line structure.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The forming of a multi-layer storage structure stacked along a first direction comprises: Forming a stacked structure, the stacked structure comprising a plurality of insulating layers and a plurality of semiconductor layers alternately stacked along the first direction, the semiconductor layers comprising at least one bit line, and a plurality of channel layers arranged in a plurality of columns along the second direction, the channel layers in the same column of the same semiconductor layer being correspondingly connected to the same bit line, the adjacent channel layers in the same column of the same semiconductor layer being spaced apart, and the insulating layer filling the spaced region between the adjacent channel layers; Removing the insulating layer adjacent to the periphery of the channel layer to obtain a gap exposing the periphery of the channel layer; A gate insulating layer and a gate layer covering the gate insulating layer are formed on the exposed peripheral surfaces of the channel layer through the gap, so as to obtain a storage transistor including the channel layer, the gate insulating layer and the gate layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The step of removing the insulating layer adjacent to the periphery of the channel layer to obtain a gap exposing the periphery of the surface of the channel layer comprises: Etching the insulating layer adjacent to two opposite sides of the channel layer in the first direction to form a first gate hole at least partially penetrating the stack structure along a third direction, and etching the insulating layer adjacent to two opposite sides of the channel layer in the third direction to form a second gate hole at least partially penetrating the stack structure along the first direction, wherein the third direction is perpendicular to the first direction and the second direction, and the first gate hole is connected to the second gate hole; The insulating layer covering the peripheral surface of the channel layer is removed through the first gate hole and the second gate hole until the peripheral surface of the channel layer is exposed to the first gate hole and the second gate hole, thereby obtaining a gap including the first gate hole and the second gate hole.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The gate insulating layer and the gate layer covering the gate insulating layer are formed on the exposed peripheral surfaces of the channel layer through the gap to obtain a storage transistor including the channel layer, the gate insulating layer and the gate layer, including: A gate insulating layer and a gate layer covering the gate insulating layer are formed on inner wall surfaces of the first gate hole and the second gate hole to obtain a storage transistor including the channel layer, the gate insulating layer and the gate layer.

16. The method for manufacturing a semiconductor device according to claim 13, wherein: The forming of at least one common source line structure comprises: At least one first groove is formed to penetrate the stack structure along the first direction, one end of the channel layer in the same column of the same layer of storage structure along the second direction is correspondingly exposed on the inner sidewall surface of the same first groove, and one end of the channel layer adjacent to each other along the first direction in different layers of storage structure along the second direction is correspondingly exposed on the inner sidewall surface of the same first groove; A conductive material is filled in the first trench to form a common source line structure.

17. The method for manufacturing a semiconductor device according to claim 13, wherein: The method further comprises: forming a second trench penetrating the stacked structure along the first direction, wherein the second trench separates adjacent storage transistors in the same column of the same layer of storage structure; An insulating material is filled in the second trench to form an isolation structure.

18. The method for manufacturing a semiconductor device according to claim 13, wherein: The method further comprises: Etching the stacked structure so that the widths of the bit lines adjacent to each other along the first direction in different layers of storage structures gradually decrease along the first direction to form a step structure; A plurality of bit line contacts are formed, and the plurality of bit line contacts are electrically connected to the corresponding bit lines at positions of the step structures.

19. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 11.

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