A SONOS flash memory device, a manufacturing method, a chip, and an electronic device

Abstract

The present disclosure relates to the field of semiconductor technologies, and specifically discloses a SONOS flash memory device, a preparation method, a chip, and an electronic device. The preparation method includes: preparing a tunneling oxide layer on a silicon substrate; preparing a bottom silicon nitride layer on the tunneling oxide layer; performing an ion bombardment treatment on the bottom silicon nitride layer; performing a plasma passivation treatment on the bottom silicon nitride layer after the ion bombardment treatment; preparing a blocking oxide layer above the bottom silicon nitride layer; and preparing a polysilicon gate on the blocking oxide layer. This technical solution can improve the storage window and reliability of the SONOS flash memory device simultaneously, and is mainly used for preparing the SONOS flash memory device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and particularly to a SONOS flash memory device, a preparation method, a chip, and an electronic device. Background Art

[0002] In recent years, NVM (Non-volatile Memory) with large capacity and high reliability has become one of the hotspots in the consumer electronics market. As a charge trapping memory, the SONOS (Silicon Oxide Nitride Oxide Silicon) flash memory device has become one of the most valuable NVMs due to its advantages such as simple process, low operating voltage, and the ability to scale down the structure proportionally with the process. However, when the process node of the SONOS flash memory device is scaled down to below 2x nm, the SONOS flash memory device has serious problems such as insufficient storage window and decreased reliability.

[0003] [[ID=ll]]To improve the storage window of the SONOS flash memory device, the existing conventional methods mainly include the following:

[0004] The first method is to increase the thickness of the trap layer of the SONOS flash memory device. By increasing the thickness of the trap layer, the number of traps is increased to improve the storage window. However, this method has the disadvantages of large operating voltage and slow programming / erasing speed.

[0005] The second method is to change the composition ratio of the trap layer of the SONOS flash memory device to prepare a silicon-rich trap layer. The silicon-rich silicon nitride trap layer is rich in shallow-level traps, which is beneficial to storing a large amount of charge. However, the shallow-level traps will cause a serious decline in the retention characteristics of the device and affect the device reliability.

[0006] The third method is to use a high-k material as the trap layer. The high-k material has abundant traps and can improve the storage window of the SONOS flash memory device. However, the incompatibility between the high-k material and the traditional material, the interface reaction problem during the annealing process, and the existence of oxygen vacancies will lead to a decline in the performance and reliability of the SONOS flash memory device.

[0007] Therefore, there is an urgent need for a preparation process that can simultaneously improve the storage window and reliability of the SONOS flash memory device. Summary of the Invention

[0008] To solve the problems in the related art, embodiments of the present disclosure provide a SONOS flash memory device, a preparation method, a chip, and an electronic device.

[0009] In a first aspect, embodiments of the present disclosure provide a preparation method for a SONOS flash memory device, including:

[0010] Prepare a tunneling oxide layer on a silicon substrate;

[0011] Prepare a bottom silicon nitride layer on the tunneling oxide layer;

[0012] Perform ion bombardment treatment on the bottom silicon nitride layer;

[0013] Perform plasma passivation treatment on the bottom silicon nitride layer after ion bombardment treatment;

[0014] Prepare a blocking oxide layer above the bottom silicon nitride layer;

[0015] Prepare a polysilicon gate on the blocking oxide layer.

[0016] In a possible implementation manner, the performing ion bombardment treatment on the bottom silicon nitride layer includes:

[0017] Perform ion bombardment treatment on the bottom silicon nitride layer using inert ions.

[0018] In a possible implementation manner, the inert ions include argon ions.

[0019] In a possible implementation manner, when performing ion bombardment treatment on the bottom silicon nitride layer using argon ions, the radio frequency power includes 180W - 220W, the DC power includes 4.5W - 5.5W, the reaction temperature includes 335°C - 415°C, and the treatment duration includes 4.5s - 5.5s.

[0020] In a possible implementation manner, the performing plasma passivation treatment on the bottom silicon nitride layer after ion bombardment treatment includes:

[0021] Perform NH3 plasma passivation treatment on the bottom silicon nitride layer after ion bombardment treatment. [[ID=3 / 6]]

[0022] In a possible implementation manner, the performing NH3 plasma passivation treatment on the bottom silicon nitride layer after ion bombardment treatment includes:

[0023] Perform NH3 plasma passivation treatment on the bottom silicon nitride layer after ion bombardment treatment using high - density plasma chemical vapor deposition, where the radio frequency power during passivation treatment includes 800W - 1000W, the reaction temperature includes 335°C - 415°C, and the treatment duration includes 50s - 70s.

[0024] In a possible implementation manner, the preparation method further includes:

[0025] Prepare a top silicon nitride layer on the bottom silicon nitride layer;

[0026] Preparing a blocking oxide layer above the bottom silicon nitride layer includes:

[0027] Preparing a blocking oxide layer on the top silicon nitride layer.

[0028] In a possible implementation, preparing the bottom silicon nitride layer on the tunneling oxide layer includes:

[0029] Using low-pressure chemical vapor deposition process to prepare a bottom silicon nitride layer with a thickness of 30 - 40 Å on the tunneling oxide layer, where the reaction temperature includes 550 - 750 °C, the reaction duration includes 20 - 30 s, the reaction gas sources are ammonia and dichlorosilane, and the ratio of ammonia to dichlorosilane in the reaction gas sources is 10:1.

[0030] In a possible implementation, preparing the top silicon nitride layer on the bottom silicon nitride layer includes:

[0031] Using low-pressure chemical vapor deposition process to prepare a top silicon nitride layer with a thickness of 40 Å - 50 Å on the bottom silicon nitride layer, where the reaction temperature includes 550 °C - 750 °C, the reaction duration includes 35 s - 45 s, the reaction gas sources are ammonia and dichlorosilane, and the ratio of ammonia to dichlorosilane in the reaction gas sources is 10:1.

[0032] In a possible implementation, preparing the tunneling oxide layer on the silicon substrate includes:

[0033] Using in-situ steam generation process to prepare a tunneling oxide layer with a thickness of 30 - 40 Å on the silicon substrate, where the process temperature of the in-situ steam generation process includes 950 °C - 1150 °C, and the process duration includes 20 - 40 s.

[0034] In a possible implementation, preparing the blocking oxide layer above the bottom silicon nitride layer includes:

[0035] Using high-temperature thermal oxidation process to prepare a blocking oxide layer with a thickness of 50 - 60 Å above the bottom silicon nitride layer, where the process temperature of the high-temperature thermal oxidation process includes 700 °C - 850 °C, and the process duration includes 25 min - 45 min.

[0036] In a possible implementation, preparing the polysilicon gate on the blocking oxide layer includes:

[0037] Using low-pressure chemical vapor deposition process to prepare a polysilicon gate with a thickness of 600 Å - 800 Å on the blocking oxide layer, where the process temperature of the low-pressure chemical vapor deposition process includes 600 °C - 800 °C, and the process duration includes 50 min - 70 min.

[0038] In a second aspect, embodiments of the present disclosure provide a SONOS flash memory device, which is prepared by the preparation method of the SONOS flash memory device according to any one of the first aspect. The SONOS flash memory device includes, from bottom to top,

[0039] a silicon substrate, a tunneling oxide layer, a bottom silicon nitride layer, a blocking oxide layer, and a polysilicon gate.

[0040] In a possible implementation, the SONOS flash memory device further includes:

[0041] a top silicon nitride layer, which is located between the bottom silicon nitride layer and the blocking oxide layer.

[0042] In a third aspect, embodiments of the present disclosure provide a chip, including the SONOS flash memory device according to any one of the above aspects.

[0043] In a fourth aspect, embodiments of the present disclosure provide an electronic device, including the SONOS flash memory device according to any one of the above aspects.

[0044] According to the technical solution provided by the embodiments of the present disclosure, the silicon substrate, the tunneling oxide layer, the bottom silicon nitride trap layer, the blocking oxide layer, and the polysilicon gate can be prepared successively from bottom to top. Among them, the bottom silicon nitride layer is successively subjected to ion bombardment treatment and plasma passivation treatment. The ion bombardment treatment can significantly increase the number of traps in the bottom silicon nitride trap layer, improve the number of charges that the SONOS flash memory device can capture, and thus expand the storage window of the SONOS flash memory device; while the plasma passivation treatment can saturate the dangling bonds with shallow energy levels in the bottom silicon nitride trap layer, reduce the trap density at the interface, significantly reduce the number of shallow energy level traps in the silicon nitride layer, and greatly improve the reliability of the SONOS flash memory device. In this way, the storage window and reliability of the SONOS flash memory device are improved simultaneously.

[0045] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In combination with the drawings, through the following detailed description of non-limiting embodiments, other features, objects, and advantages of the present disclosure will become more obvious. In the drawings:

[0047] Figure 1 A flowchart showing a preparation method of a SONOS flash memory device provided by an embodiment of the present disclosure is shown.

[0048] Figure 2 A comparison diagram showing the number of trap energy levels in silicon nitride layers prepared by three methods provided by an embodiment of the present disclosure is shown.

[0049] Figure 3 Shows a comparison diagram of the storage windows of SONOS flash devices prepared by three methods provided by embodiments of the present disclosure.

[0050] Figure 4 Shows a schematic structural diagram of a SONOS flash device provided by an embodiment of the present disclosure.

[0051] Figure 5 Shows a schematic structural diagram of another SONOS flash device provided by an embodiment of the present disclosure. Detailed implementation manners

[0052] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for clarity, parts unrelated to the description of the exemplary embodiments are omitted in the drawings.

[0053] In the present disclosure, it should be understood that terms such as "including" or "having" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0054] In addition, it should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0055] Figure 1 Shows a flowchart of a method for manufacturing a SONOS flash device provided by an embodiment of the present disclosure. As Figure 1 shown, the manufacturing method includes the following steps S101 - S106:

[0056] In step S101, a tunneling oxide layer is formed on a silicon substrate;

[0057] In step S102, a bottom silicon nitride layer is formed on the tunneling oxide layer;

[0058] In step S103, the bottom silicon nitride layer is subjected to ion bombardment treatment;

[0059] In step S104, the bottom silicon nitride layer after ion bombardment treatment is subjected to plasma passivation treatment;

[0060] In step S105, a blocking oxide layer is formed above the bottom silicon nitride layer;

[0061] In step S106, a polysilicon gate is formed on the blocking oxide layer.

[0062] In a possible implementation, the silicon substrate is the foundation of the SONOS flash memory device. Other layers of the SONOS flash memory device are built on top of the silicon substrate, which is usually a single crystal silicon. As the starting point of the device, other layers will be grown and fabricated layer by layer on the silicon substrate.

[0063] In a possible implementation, a tunnel oxide layer is fabricated on top of the silicon substrate. The tunnel oxide layer is very thin and allows charges to be injected from the silicon substrate into the silicon nitride layer through the tunneling effect.

[0064] In a possible implementation, a bottom silicon nitride layer can be fabricated on the tunnel oxide layer. This bottom silicon nitride layer is mainly used for storing charges. The bottom silicon nitride layer is rich in traps at various energy levels and can store electrons and holes. These traps can retain charges for a long time, thereby achieving non-volatile storage.

[0065] In a possible implementation, in order to achieve the effect of simultaneously improving the storage window and reliability of the SONOS flash memory device, this implementation can perform ion bombardment treatment and plasma passivation treatment on the bottom silicon nitride layer successively. Among them, the ion bombardment treatment can significantly increase the number of traps in the silicon nitride trap layer and improve the number of charges that the memory can capture, thereby expanding the storage window of the SONOS flash memory device. Although the ion bombardment can improve the storage window of the SONOS flash memory device, the increase in shallow energy level traps will accelerate the leakage of the device in the vertical direction, seriously affecting the reliability of the SONOS flash memory device. The plasma passivation treatment can saturate the dangling bonds at the shallow energy levels in the trap layer, reduce the trap density at the interface, and significantly reduce the number of shallow energy level traps in the silicon nitride layer, greatly improving the reliability of the device.

[0066] Exemplarily, Figure 2 shows a comparison diagram of the number of trap energy levels in the silicon nitride layer prepared by three methods provided by the embodiments of the present disclosure. As Figure 2 shown in the three curves, curve 1 is the curve of the trap energy levels and their numbers in the silicon nitride layer without ion bombardment and plasma passivation treatment in the prior art, curve 2 is the curve of the trap energy levels and their numbers in the silicon nitride layer after ion bombardment but without plasma passivation treatment, and curve 3 is the curve of the trap energy levels and their numbers in the silicon nitride layer after ion bombardment and plasma passivation treatment. From Figure 2It can be seen that the number of shallow-level traps, medium-level traps, and deep-level traps in the silicon nitride layer without ion bombardment and plasma passivation treatment shown by Curve 1 is the smallest. For the silicon nitride layer that has undergone ion bombardment but not plasma passivation treatment shown by Curve 2, compared with Curve 1, the number of shallow-level traps and medium-level traps has increased significantly. This proves that ion bombardment treatment can significantly increase the number of traps in the silicon nitride trap layer, improve the amount of charge that the memory can capture, and thus expand the storage window of the SONOS flash device. However, the increase in shallow-level traps is too much, which will accelerate the leakage current of the device in the vertical direction and seriously affect the reliability of the SONOS flash device. For the silicon nitride layer that has undergone ion bombardment and plasma passivation treatment shown by Curve 3, compared with Curve 1, the number of shallow-level traps has increased less, and the number of medium-level traps has increased significantly; compared with Curve 2, the number of shallow-level traps has decreased significantly, the number of medium-level traps has decreased slightly, and the number of deep-level traps has hardly changed. This proves that plasma passivation treatment can significantly reduce the number of shallow-level traps in the silicon nitride layer and has little effect on the number of medium-level traps and deep-level traps, which greatly improves the reliability of the SONOS flash device.

[0067] Figure 3 Fig. shows a comparison diagram of the storage windows of SONOS flash devices prepared by three methods provided in the embodiments of the present disclosure. Figure 3 Among them, Curve a1 and a2 are the threshold voltage curves of the SONOS flash device without ion bombardment and plasma passivation treatment of the silicon nitride layer in the programmed state and the erased state, respectively; Curve b1 and b2 are the threshold voltage curves of the SONOS flash device with ion bombardment but without plasma passivation treatment of the silicon nitride layer in the programmed state and the erased state, respectively; Curve c1 and c2 are the threshold voltage curves of the SONOS flash device with ion bombardment and plasma passivation treatment of the silicon nitride layer in the programmed state and the erased state, respectively. The storage window refers to the difference in threshold voltage between the (Programmed State) and the erased state (Erased State). As can be seen from Figure 3 shown, when the silicon nitride layer in the SONOS flash device is not subjected to ion bombardment and plasma passivation treatment, the initial storage window of the SONOS flash device is about 3V. After ion bombardment of the silicon nitride layer in the SONOS flash device, the storage window of the SONOS flash device becomes 5.3V. After ion bombardment and plasma passivation treatment of the silicon nitride layer in the SONOS flash device, the storage window of the SONOS flash device becomes 4.7V, which is increased by 76.7% and 56.7% respectively compared with the initial storage window. Although plasma passivation treatment will cause the storage window to decrease by 0.6V, the reliability of the SONOS flash device is better, and the threshold voltage change is only 0.8V after 100,000 cycles.

[0068] In a possible implementation, a blocking oxide layer can be prepared above the bottom silicon nitride layer. Its function is to prevent charge leakage from the silicon nitride layer to the control gate, ensuring that the charge stored in the silicon nitride layer can be stably retained.

[0069] In a possible implementation, a polysilicon gate can be prepared on the blocking oxide layer. The polysilicon gate is located at the uppermost layer and serves as the control gate. During programming and erasing operations, the injection and removal of charge are controlled by changing the voltage of the control gate.

[0070] In this implementation, the silicon substrate, tunneling oxide layer, bottom silicon nitride trap layer, blocking oxide layer, and polysilicon gate can be prepared in sequence from bottom to top. Among them, the bottom silicon nitride layer is successively subjected to ion bombardment treatment and plasma passivation treatment. Ion bombardment treatment can significantly increase the number of traps in the bottom silicon nitride trap layer, improving the amount of charge that the SONOS flash memory device can capture, thereby expanding the storage window of the SONOS flash memory device; while plasma passivation treatment can saturate the dangling bonds with shallow energy levels in the bottom silicon nitride trap layer, reducing the trap density at the interface, significantly reducing the number of shallow energy level traps in the silicon nitride layer, and greatly improving the reliability of the SONOS flash memory device. In this way, the storage window and reliability of the SONOS flash memory device are simultaneously improved.

[0071] In a possible implementation, the ion bombardment treatment of the bottom silicon nitride layer includes:

[0072] Using inert ions to perform ion bombardment treatment on the bottom silicon nitride layer.

[0073] In this implementation, inert ions generally refer to those ions with chemically inactive properties and are not prone to react with other elements or compounds, such as helium ions, argon ions, etc. Preferably, the inert ions in this implementation can be argon ions.

[0074] In a possible implementation, when using argon ions to perform ion bombardment treatment on the bottom silicon nitride layer, the radio frequency power includes 180W - 220W, for example, it can be 180W, 190W, 200W, 210W, 220W; the direct current power includes 4.5W - 5.5W, for example, it can be 4.5W, 5W, 5.5W; the reaction temperature includes 335°C - 415°C, for example, it can be 335°C, 345°C, 355°C, 365°C, 375°C, 385°C, 395°C, 405°C, 415°C; the treatment duration includes 4.5s - 5.5s, for example, it can be 4.5s, 5s, 5.5s.

[0075] In this embodiment, the radio frequency power mainly affects the energy of argon ions. When the radio frequency power is within the range of 180W - 220W, it ensures that the argon ion bombardment has sufficient energy to generate traps. During the ion bombardment process, the DC power mainly affects the acceleration and direction of ions. When the DC power is within the low power range of 4.5W - 5.5W, it can reduce the energy of argon ions and minimize the damage to the silicon nitride layer structure. The reaction temperature refers to the temperature during ion bombardment, which significantly affects the ion bombardment effect on the silicon nitride layer and the internal stress of the material. The temperature range of 335°C - 415°C enables the surface atoms of the silicon nitride layer to have good mobility when subjected to ion bombardment, facilitating the release of stress. The processing duration refers to the duration of ion bombardment. A relatively short processing duration can ensure that excessive processing does not occur during argon ion bombardment, thus preventing damage to the overall structure of the bottom silicon nitride layer. By controlling the time between 4.5s - 5.5s, a stable modification effect can be obtained.

[0076] For example, during ion bombardment processing, the radio frequency power is 200W, the DC power is 5W, the reaction temperature is 375°C, and the processing duration is 5s; or, the radio frequency power is 180W, the DC power is 5.5W, the reaction temperature is 335°C, and the processing duration is 5.5s; or, the radio frequency power is 220W, the DC power is 4.5W, the reaction temperature is 415°C, and the processing duration includes 4.5s, and so on.

[0077] In a possible embodiment, the plasma passivation treatment of the bottom silicon nitride layer after ion bombardment treatment includes:

[0078] Performing NH3 plasma passivation treatment on the bottom silicon nitride layer after ion bombardment treatment.

[0079] In this embodiment, NH3 plasma passivation treatment is a method of modifying the surface of a material using ammonia (NH3) in a plasma state. In this embodiment, NH3 plasma passivation treatment is used for the bottom silicon nitride layer after ion bombardment treatment, which can saturate the dangling bonds with shallow energy levels in the bottom silicon nitride trap layer, reduce the trap density at the interface, significantly reduce the number of shallow energy level traps in the silicon nitride layer, and greatly improve the reliability of SONOS flash memory devices.

[0080] In a possible embodiment, the NH3 plasma passivation treatment of the bottom silicon nitride layer after ion bombardment treatment includes:

[0081] The bottom silicon nitride layer after ion bombardment treatment is passivated by NH3 plasma using high-density plasma chemical vapor deposition. Among them, the radio frequency power during passivation treatment includes 800W - 1000W, for example, it can be 800W, 900W, 1000W; the reaction temperature includes 335°C - 415°C, for example, it can be 335°C, 345°C, 355°C, 365°C, 375°C, 385°C, 395°C, 405°C, 415°C; the treatment duration includes 50s - 70s, for example, it can be 50s, 60s, 70s.

[0082] In this embodiment, high-density plasma chemical vapor deposition (HDPCVD) is a variant of chemical vapor deposition (CVD) technology. High-density plasma is generated in the gas through excitation sources such as high-frequency radio frequency (such as 800 - 1000W). The reaction temperature is the temperature during passivation treatment; the treatment duration refers to the duration of NH3 plasma passivation treatment. The radio frequency power is set to 800W - 1000W, ensuring high density and good reaction activity of the plasma. High power can effectively excite ammonia (NH3) molecules to generate high-energy nitrogen and hydrogen radicals, and these radicals can quickly react with the dangling bonds in the silicon nitride layer to form a passivation layer; the relatively high temperature range of 335°C - 415°C ensures good reaction rate and film quality. The higher temperature can also improve the activity of reactants, which is beneficial for ammonia molecules to effectively penetrate to the surface of the silicon nitride layer and promote the formation of the passivation layer; the treatment duration of 50s - 70s can ensure the full passivation of shallow-level traps while avoiding the problem of mid-level traps being passivated due to too long treatment time.

[0083] For example, the radio frequency power during passivation treatment is 900W, the reaction temperature is 375°C, and the time is 60s; or, the radio frequency power is 800W, the reaction temperature is 335°C, and the treatment duration is 70s; or, the radio frequency power is 1000W, the reaction temperature is 415°C, and the treatment duration is 50s; and so on.

[0084] In a possible embodiment, the preparation method further includes:

[0085] A top silicon nitride layer is prepared on the bottom silicon nitride layer;

[0086] The preparation of the blocking oxide layer above the bottom silicon nitride layer includes:

[0087] A blocking oxide layer is prepared on the top silicon nitride layer.

[0088] In this embodiment, in order to further improve the reliability of the SONOS flash memory device, a top silicon nitride layer can also be prepared on the bottom silicon nitride layer, and then a blocking oxide layer is prepared on this top silicon nitride layer.

[0089] In a possible implementation, preparing the bottom silicon nitride layer on the tunneling oxide layer includes:

[0090] Using low-pressure chemical vapor deposition process to prepare a bottom silicon nitride layer with a thickness of 30 Å - 40 Å on the tunneling oxide layer. For example, the thickness can be 30 Å, 35 Å, or 40 Å. Among them, the reaction temperature includes 550°C - 750°C, such as 550°C, 650°C, or 750°C; the reaction duration includes 20 s - 30 s, such as 20 s, 25 s, or 30 s. The reaction gas sources are ammonia and dichlorosilane, and the ratio of ammonia to dichlorosilane in the reaction gas sources is 10:1.

[0091] In this implementation, the low-pressure chemical vapor deposition process (Low-pressure CVD, LPCVD) refers to a thermal process in which reaction gas sources are deposited in a reactor under a state lower than atmospheric pressure. An overly thin bottom silicon nitride layer will cause the trap centroid position to be too low and the device reliability to decline. An overly thick bottom silicon nitride layer will cause the trap centroid position to be too high and the device programming and erasing speed to become slow, resulting in a decline in device performance. A bottom silicon nitride layer with a thickness of 30 Å - 40 Å is more appropriate, taking into account both device reliability and performance. The above-mentioned relevant parameters of the reaction temperature, reaction duration, and reaction gas sources can ensure the formation of a high-quality bottom silicon nitride film within an appropriate time.

[0092] For example, when using the low-pressure chemical vapor deposition process to prepare this bottom silicon nitride layer, the reaction temperature is 650°C, the reaction duration is 20 s, and the thickness of the prepared bottom silicon nitride layer is 30 Å; or the reaction temperature is 650°C, the reaction duration is 30 s, and the thickness of the prepared bottom silicon nitride layer is 40 Å; or the reaction temperature is 550°C, the reaction duration is 30 s, and the thickness of the prepared bottom silicon nitride layer is 33 Å; or the reaction temperature is 750°C, the reaction duration is 25 s, and the thickness of the prepared bottom silicon nitride layer is 40 Å; and so on.

[0093] In a possible implementation, preparing the top silicon nitride layer on the bottom silicon nitride layer includes:

[0094] Using low-pressure chemical vapor deposition process to prepare a top silicon nitride layer with a thickness of 40 Å - 50 Å on the bottom silicon nitride layer. The thickness can be, for example, 40 Å, 45 Å, or 50 Å. Among them, the reaction temperature includes 550°C - 750°C, such as 550°C, 650°C, or 750°C; the reaction duration includes 35 s - 45 s, such as 35 s, 40 s, or 45 s. The reaction gas sources are ammonia and dichlorosilane, and the ratio of ammonia to dichlorosilane in the reaction gas sources is 10:1.

[0095] In this embodiment, the thickness of the top silicon nitride layer is related to the thickness of the bottom silicon nitride layer. As the thickness of the silicon nitride layer increases, the durability of the device will be improved, and it can better withstand multiple programming and erasing cycles. However, an overly thick silicon nitride layer may cause an increase in mechanical stress, thus affecting the long-term reliability of the device. Therefore, the sum of the thicknesses of the top silicon nitride layer and the bottom silicon nitride layer can be set to include 75 Å - 85 Å. For example, the sum of the thicknesses can be 75 Å, 79 Å, 80 Å, 81 Å, and 85 Å. Preferably, the sum of the thicknesses of the top silicon nitride layer and the bottom silicon nitride layer can be 80 Å. This thickness can also ensure a lower leakage current, improve the data retention time, and ensure moderate writing and erasing efficiency. Similarly, the relevant parameters of the above reaction temperature, reaction duration, and reaction gas source can ensure the formation of a high-quality top silicon nitride film within an appropriate time.

[0096] Exemplarily, when preparing the top silicon nitride layer by low-pressure chemical vapor deposition process, the reaction temperature is 650 °C, the reaction duration is 30 s, and the thickness of the prepared bottom silicon nitride layer is 40 Å; or, the reaction temperature is 650 °C, the reaction duration is 40 s, and the thickness of the prepared bottom silicon nitride layer is 50 Å; or, the reaction temperature is 550 °C, the reaction duration is 40 s, and the thickness of the prepared bottom silicon nitride layer is 43 Å; or, the reaction temperature is 750 °C, the reaction duration is 35 s, and the thickness of the prepared bottom silicon nitride layer is 45 Å; and so on.

[0097] In a possible embodiment, preparing a tunneling oxide layer on the silicon substrate includes:

[0098] Using an in-situ steam generation process to prepare a tunneling oxide layer with a thickness of 30 Å - 40 Å on the silicon substrate. The thickness can be, for example, 30 Å, 35 Å, 40 Å. Among them, the process temperature of the in-situ steam generation process includes 950 °C - 1150 °C, such as 950 °C, 1050 °C, 1150 °C, and the process duration includes 20 s - 40 s, such as 20 s, 30 s, 40 s.

[0099] In this embodiment, the in-situ steam generation (ISSG) process is a process for growing an oxide layer through a high-temperature water vapor atmosphere. Its growth rate of the oxide layer is relatively fast. The in-situ steam generation process can improve the chemical uniformity and physical properties of the oxide layer, can more effectively promote the formation of Si - O bonds, reduce interface defects, and improve the dielectric properties and stability of the film.

[0100] In this embodiment, a tunneling oxide layer with a thickness of 30 Å - 40 Å can effectively enhance the tunneling effect, meet the requirements of non-volatile memories, help improve the data programming and erasing efficiency, reduce the demand for electric field strength, and lower power consumption; a temperature range of 950 °C - 1150 °C can promote the effective generation of water vapor and chemical reactions, enhancing the formation rate and quality of the oxide layer; a process duration of 20 s - 40 s can ensure the formation of the oxide layer within an effective time, avoiding excessive film thickness or increased stress caused by too long time.

[0101] For example, when preparing the tunneling oxide layer using the in-situ water vapor generation process, the process temperature is 1150 °C, the process duration is 40 s, and the thickness of the prepared tunneling oxide layer is 40 Å; or, with a process temperature of 1000 °C and a process duration of 30 s, the thickness of the prepared tunneling oxide layer is 35 Å; or, with a process temperature of 950 °C and a process duration of 20 s, the thickness of the prepared tunneling oxide layer is 30 Å.

[0102] In a possible embodiment, preparing the blocking oxide layer above the bottom silicon nitride layer includes:

[0103] Using a high-temperature thermal oxidation process to prepare a blocking oxide layer with a thickness of 50 Å - 60 Å above the bottom silicon nitride layer. The thickness can be, for example, 50 Å, 55 Å, 60 Å. Among them, the process temperature of the high-temperature thermal oxidation process is 700 °C - 850 °C, such as 700 °C, 750 °C, 800 °C, 850 °C, and the process duration includes 25 min - 45 min, such as 25 min, 30 min, 35 min, 40 min, 45 min.

[0104] In this embodiment, the high-temperature thermal oxidation process refers to a process of forming an oxide film through chemical reactions in a high-temperature environment with an oxidant. This high-temperature thermal oxidation process can utilize heat energy to promote the penetration of the oxidant, improving the quality and stability of the SiO2 film. This process helps improve the electrical insulation performance of the oxide layer, reduce leakage current, enhance the blocking effectiveness, and thus improve the overall reliability of the device. Selecting a thickness of 50 Å - 60 Å can ensure that the blocking oxide layer has good insulation and the effect of blocking back-gate injection, while preventing the performance of the device from being affected due to excessive thickness; a temperature range of 700 °C - 850 °C can promote the activity of the oxidation reaction, accelerate the growth of the oxide layer, and a higher temperature helps improve the denseness of the oxide layer, reduce defects, and enhance the dielectric properties of the film layer; a process duration of 25 min - 45 min helps control the growth rate of the oxide layer, ensuring a uniform and dense oxide layer within the specified time.

[0105] Exemplarily, when preparing the barrier oxide layer using a high-temperature thermal oxidation process, the process temperature is 700 °C, the process duration is 30 min, and the thickness of the prepared barrier oxide layer is 50 Å; or, with a process temperature of 850 °C and a process duration of 30 min, the thickness of the prepared barrier oxide layer is 60 Å; or, with a process temperature of 800 °C and a process duration of 25 min, the thickness of the prepared barrier oxide layer is 52 Å; or, with a process temperature of 800 °C and a process duration of 45 min, the thickness of the prepared barrier oxide layer is 60 Å.

[0106] In a possible implementation manner, preparing the polysilicon gate on the barrier oxide layer includes:

[0107] Using a low-pressure chemical vapor deposition process to prepare a polysilicon gate with a thickness of 600 Å - 800 Å on the barrier oxide layer. The thickness is, for example, 600 Å, 700 Å, 800 Å. Among them, the process temperature of the low-pressure chemical vapor deposition process includes 600 °C - 800 °C, such as 600 °C, 700 °C, 800 °C, and the process duration includes 50 min - 70 min, such as 50 min, 60 min, 70 min.

[0108] In this implementation manner, selecting a thickness of 600 Å - 800 Å can, while ensuring the performance of the polysilicon gate, avoid mechanical stress and strain problems caused by an overly thick film layer. An appropriate thickness helps to ensure good conductivity and structural strength; the temperature range of 600 °C - 800 °C is suitable for the characteristics of the low-pressure chemical vapor deposition process and can promote the uniform deposition of polysilicon; the time range of 50 min - 70 min can ensure the uniformity and stability of the film layer, reduce interface defects, and is conducive to improving the success rate of subsequent processing steps. This low-pressure chemical vapor deposition process is carried out at a lower pressure, which can effectively improve the uniformity and controllability of the deposition process. This process can reduce the influence brought by uneven gas flow, ensure the consistency of the polysilicon film on the entire substrate, and thus improve the overall performance and reliability of the device.

[0109] Exemplarily, when preparing the polysilicon gate using a low-pressure chemical vapor deposition process, the process temperature is 600 °C, the process duration is 60 min, and the thickness of the prepared polysilicon gate is 600 Å; or, with a process temperature of 800 °C and a process duration of 60 min, the thickness of the prepared polysilicon gate is 800 Å; or, with a process temperature of 700 °C and a process duration of 70 min, the thickness of the barrier oxide layer is 720 Å; or with a process temperature of 800 °C and a process duration of 50 min, the thickness of the prepared polysilicon gate is 710 Å; and so on.

[0110] The present disclosure also provides a SONOS flash device, which is prepared according to the preparation method of the above SONOS flash device. Figure 4 The structural schematic diagram of a SONOS flash device provided by an embodiment of the present disclosure is shown, as Figure 4 shown, the SONOS flash device sequentially includes from bottom to top:

[0111] a silicon substrate 1, a tunneling oxide layer 2, a bottom silicon nitride layer 3, a blocking oxide layer 4, and a polysilicon gate 5.

[0112] Among them, the bottom silicon nitride layer 3 is successively subjected to ion bombardment treatment and plasma passivation treatment. The ion bombardment treatment can significantly increase the number of traps in the silicon nitride trapping layer, improve the number of charges that the memory can capture, and thereby expand the storage window of the SONOS flash device; although the ion bombardment can improve the storage window of the SONOS flash device, the increase in shallow-level traps will accelerate the leakage of the device in the vertical direction, seriously affecting the reliability of the SONOS flash device. The plasma passivation treatment can saturate the dangling bonds of shallow energy levels in the trapping layer, reduce the trap density at the interface, significantly reduce the number of shallow-level traps in the silicon nitride layer, and greatly improve the reliability of the device.

[0113] In a possible implementation manner, Figure 5 The structural schematic diagram of another SONOS flash device provided by an embodiment of the present disclosure is shown. The SONOS flash device further includes:

[0114] a top silicon nitride layer 6, and the top silicon nitride layer 6 is located between the bottom silicon nitride layer 3 and the blocking oxide layer 4.

[0115] In this implementation manner, there are two parts of the silicon nitride layer in the SONOS flash device, namely the bottom silicon nitride layer 3 and the top silicon nitride layer 6. Preparing the top silicon nitride layer 3 on the bottom silicon nitride layer 6 can further improve the reliability of the SONOS flash device.

[0116] An embodiment of the present disclosure also provides a chip, including the above SONOS flash device.

[0117] An embodiment of the present disclosure also provides an electronic device, including the above SONOS flash device.

[0118] The above description is only a preferred embodiment of the present disclosure and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) disclosed in the present disclosure that have similar functions.

Claims

1. A method for preparing a silicon-oxide-nitride-oxide-silicon SONOS flash memory device, characterized in that: include: forming a tunnel oxide layer on a silicon substrate; forming a bottom silicon nitride layer on the tunnel oxide layer; performing ion bombardment treatment on the bottom silicon nitride layer; Performing NH3 plasma passivation treatment on the bottom silicon nitride layer after the ion bombardment treatment, including: generating nitrogen and hydrogen radicals by exciting NH3 molecules, and reacting the free radicals with dangling bonds in the bottom silicon nitride layer to form a passivation layer, wherein the passivation layer saturates the dangling bonds at shallow energy levels in the bottom silicon nitride layer, reduces the trap density at the interface, and reduces the number of shallow energy level traps in the bottom silicon nitride layer; forming a blocking oxide layer above the bottom silicon nitride layer; A polysilicon gate is prepared on the blocking oxide layer.

2. The preparation method according to claim 1, characterized in that The ion bombardment treatment of the bottom silicon nitride layer comprises: The bottom silicon nitride layer is subjected to ion bombardment treatment using inert ions.

3. The preparation method according to claim 2, characterized in that The inert ions include argon ions.

4. The preparation method according to claim 3, characterized in that When argon ions are used to perform ion bombardment treatment on the bottom silicon nitride layer, the RF power is 180W-220W, the DC power is 4.5W-5.5W, the reaction temperature is 335°C-415°C, and the treatment time is 4.5s-5.5s.

5. The preparation method according to claim 1, characterized in that The step of performing NH3 plasma passivation treatment on the bottom silicon nitride layer after the ion bombardment treatment comprises: The bottom silicon nitride layer after ion bombardment treatment is subjected to NH3 plasma passivation treatment using high-density plasma chemical vapor deposition, wherein the RF power during the passivation treatment is 800W-1000W, the reaction temperature is 335℃-415℃, and the treatment time is 50s-70s.

6. The preparation method according to claim 1, characterized in that The preparation method further comprises: forming a top silicon nitride layer on the bottom silicon nitride layer; The step of preparing a blocking oxide layer above the bottom silicon nitride layer comprises: A blocking oxide layer is formed on the top silicon nitride layer.

7. The preparation method according to claim 1, characterized in that The step of preparing a bottom silicon nitride layer on the tunneling oxide layer comprises: A bottom silicon nitride layer with a thickness of 30 angstroms to 40 angstroms is prepared on the tunnel oxide layer using a low-pressure chemical vapor deposition process, wherein the reaction temperature includes 550°C to 750°C, the reaction time includes 20s to 30s, the reaction gas source includes ammonia and dichlorosilane, and the ratio of ammonia to dichlorosilane in the reaction gas source is 10:

1.

8. The preparation method according to claim 6, characterized in that The step of preparing a top silicon nitride layer on the bottom silicon nitride layer comprises: A top silicon nitride layer with a thickness of 40 angstroms to 50 angstroms is prepared on the bottom silicon nitride layer using a low-pressure chemical vapor deposition process, wherein the reaction temperature includes 550°C to 750°C, the reaction time includes 35s to 45s, the reaction gas source includes ammonia and dichlorosilane, and the ratio of ammonia to dichlorosilane in the reaction gas source is 10:

1.

9. The preparation method according to claim 1, characterized in that The step of preparing a tunneling oxide layer on a silicon substrate comprises: An in-situ water vapor generation process is used to prepare a tunnel oxide layer with a thickness of 30 angstroms to 40 angstroms on the silicon substrate, wherein the process temperature of the in-situ water vapor generation process includes 950° C. to 1150° C. and the process time includes 20s to 40s.

10. The preparation method according to claim 1, characterized in that The step of preparing a blocking oxide layer above the bottom silicon nitride layer comprises: A high-temperature thermal oxidation process is used to prepare a barrier oxide layer with a thickness of 50 angstroms to 60 angstroms on the bottom silicon nitride layer, wherein the process temperature of the high-temperature thermal oxidation process includes 700° C. to 850° C. and the process time includes 25 minutes to 45 minutes.

11. The preparation method according to claim 1, characterized in that The method of preparing a polysilicon gate on the blocking oxide layer comprises: A polysilicon gate having a thickness of 600-800 angstroms is prepared on the blocking oxide layer by a low-pressure chemical vapor deposition process, wherein the process temperature of the low-pressure chemical vapor deposition process includes 600° C.-800° C., and the process time includes 50 min-70 min.

12. A silicon-oxide-nitride-oxide-silicon SONOS flash memory device, characterized in that: The SONOS flash memory device is prepared according to the method for preparing a SONOS flash memory device according to any one of claims 1 to 11, and the SONOS flash memory device comprises, from bottom to top: Silicon substrate, tunnel oxide layer, bottom silicon nitride layer, blocking oxide layer and polysilicon gate.

13. The SONOS flash memory device according to claim 12, wherein: The SONOS flash memory device further includes: A top silicon nitride layer is located between the bottom silicon nitride layer and the blocking oxide layer.

14. A chip, characterized in that: The SONOS flash memory device according to claim 12 or 13.

15. An electronic device, characterized in that: The SONOS flash memory device according to claim 12 or 13.

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