Method for reducing miller capacitance of super junction MOSFET
By embedding thick oxygen in the super junction MOSFET structure or adopting a sub-gate structure, the problem of larger gate leakage capacitance in the traditional super junction MOSFET structure is solved, and the effect of reducing gate leakage capacitance and improving switching characteristics is achieved.
Patent Information
- Application Number
- CN202411535779.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-18
AI Technical Summary
The larger gate leakage capacitor in the traditional super junction MOSFET structure will affect the opening speed and increase leakage power consumption under the large switch current.
The gate leakage capacitance is reduced by embedding thick oxygen between the gate polysilicon and above the JFET region or adopting a separate gate structure.
It effectively reduces the gate leakage capacitance of super junction devices, improves switching characteristics, and does not require additional lithographic planning in existing processes, which has lower process costs.
Smart Images
Figure CN119486173A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for reducing the Miller capacitance of a super junction MOSFET. Background Art
[0002] like Figure 1 As shown in the figure, in the conventional super junction MOSFET structure, a whole planar gate 6 is covered above the JFET region 4 in the cell region, and the thinner gate oxide 5 makes the gate-drain capacitance (Cgd) larger. During the MOS part opening process, the current is first charged through the gate-source capacitance (Cgs), and then gradually increases through the gate-drain capacitance (Cgd). A larger gate-drain capacitance (Cgd) will affect the opening speed and increase the leakage power consumption under a larger switching current. Summary of the invention
[0003] In view of this, the present invention provides a method for reducing the Miller capacitance of a super junction MOSFET, which is used to reduce the Miller capacitance (gate-drain capacitance) of a super junction device and improve switching characteristics.
[0004] The present invention provides a method for reducing the Miller capacitance of a super junction MOSFET, comprising the following steps:
[0005] Step 1: providing a substrate, and forming an epitaxial layer on the substrate;
[0006] Step 2: Define the formation area of the super junction structure according to photolithography, and etch the epitaxial layer to form a groove;
[0007] Step 3: Filling the groove with P-type material to form a P-type column;
[0008] Step 4: forming a JFET region, gate polysilicon, and a thick oxide or split gate structure therebetween;
[0009] Step 5: perform ion implantation and advancement on the epitaxial layer to form a well region and a source region.
[0010] Preferably, the substrate in step one is a silicon substrate.
[0011] Preferably, the super junction structure in step 2 is a P-type column.
[0012] Preferably, the P-type material in step three is P-type silicon.
[0013] Preferably, the P-type silicon is a P-type silicon epitaxial layer formed by epitaxial growth.
[0014] Preferably, step 4 includes the following steps:
[0015] Step a, defining a JFET formation region by means of a photomask, and performing ion implantation to form the JFET region, wherein the upper surface of the JFET region is flush with the upper surface of the epitaxial layer;
[0016] Step b, growing gate oxide and forming thick oxide above the JFET region;
[0017] Step c: depositing polysilicon and etching to form gate polysilicon.
[0018] Preferably, in step a, the upper surface of the JFET region is flush with the upper surface of the epitaxial layer.
[0019] Preferably, step 4 includes the following steps:
[0020] Step d, defining a JFET formation area by means of a photomask, firstly etching to form a groove, and then performing ion implantation to form the JFET area;
[0021] Step e, filling the trench to form thick oxide;
[0022] Step f, growing gate oxide, depositing polysilicon and etching to form gate polysilicon.
[0023] Preferably, in step f, the upper surface of the gate oxide is flush with the upper surface of the thick oxide.
[0024] Preferably, step 4 includes the following steps:
[0025] Step g, defining a JFET formation area by means of a photomask, firstly performing etching to form a groove, and then performing ion implantation to form the JFET area;
[0026] Step h, growing gate oxide, wherein the gate oxide extends to the sidewall and bottom surface of the trench;
[0027] Step i: deposit polysilicon and etch to form a split gate structure of gate polysilicon in the channel region and source polysilicon above the JFET region.
[0028] The present invention reduces the gate-drain capacitance by embedding thick oxygen between the bottom of the gate polysilicon and the top of the JFET region, or shields the gate-drain capacitance by using a split-gate structure, thereby reducing the gate-drain capacitance of the superjunction device and improving the switching characteristics. Moreover, the present invention can achieve process realization without adding an additional photomask in the existing process, and the process cost is low. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0030] Figure 1 Shown is a schematic diagram of a conventional superjunction MOSFET structure;
[0031] Figure 2 A flow chart showing a method for reducing Miller capacitance of a super junction MOSFET according to an embodiment of the present invention;
[0032] Figures 3 to 5 Shown is a schematic diagram of a super junction MOSFET structure according to an embodiment of the present invention.
[0033] Description of reference numerals:
[0034] 1-P-type pillar; 2-well region; 3-source region; 4-JFET region; 5-gate oxide; 6-gate polysilicon; 7 / 8-thick oxide; 9-split gate structure. DETAILED DESCRIPTION
[0035] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.
[0036] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.
[0037] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".
[0038] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0039] Figure 2 A flow chart showing a method for reducing Miller capacitance of a super junction MOSFET according to an embodiment of the present invention; Figures 3 to 5 It is a schematic diagram showing the structure of a super junction MOSFET according to an embodiment of the present invention. Figure 2 As shown, the method for reducing the Miller capacitance of a super junction MOSFET according to an embodiment of the present invention comprises the following steps:
[0040] Step 1: providing a substrate and forming an epitaxial layer on the substrate.
[0041] The constituent material of the substrate may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in an embodiment of the present invention, the substrate is a silicon substrate. An epitaxial layer is formed on the substrate by epitaxial growth. Here, a hard mask layer is also formed on the epitaxial layer, which is removed later and will not be described here.
[0042] Step 2: Define the formation area of the super junction structure according to photolithography, and etch the epitaxial layer to form a groove.
[0043] In an embodiment of the present invention, the super junction structure is a P-type column, and the method for etching the epitaxial layer is dry etching. The dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single manufacturing method may also be used, or more than one manufacturing method may also be used. The source gas of the dry etching may include HBr and / or CF4 gas. In an embodiment of the present invention, the depth of the groove is less than the thickness of the epitaxial layer.
[0044] Step 3: Fill the trench with P-type material to form a P-type column.
[0045] In the embodiment of the present invention, the P-type material is P-type silicon, and the P-type silicon is a P-type silicon epitaxial layer formed by epitaxial growth. When forming the P-type column, epitaxial growth is performed first and then chemical mechanical polishing (CMP) is performed.
[0046] Step 4: forming a JFET region, gate polysilicon, and a thick oxide or split gate structure therebetween.
[0047] In the embodiment of the present invention, there are three implementation methods for step 4. The first implementation method includes the following steps:
[0048] Step a: define a JFET formation region by using a photomask, and perform ion implantation to form the JFET region, wherein the upper surface of the JFET region is flush with the upper surface of the epitaxial layer.
[0049] Step b: grow gate oxide and form thick oxide above the JFET region.
[0050] Step c: depositing polysilicon and etching to form gate polysilicon.
[0051] In this implementation, the gate-drain capacitance is reduced by embedding thick oxygen between below the gate polysilicon and above the JFET region, and the thick oxygen is a planar thick oxide layer formed above the epitaxial layer.
[0052] The second implementation method includes the following steps:
[0053] Step d: define the JFET formation area through a photomask, first perform etching to form a groove, and then perform ion implantation to form the JFET area.
[0054] Step e: filling the trench to form thick oxide.
[0055] Step f, growing gate oxide, depositing polysilicon and etching to form gate polysilicon.
[0056] Among them, in step f, the upper surface of the gate oxide is flush with the upper surface of the thick oxide. In this implementation, the gate-drain capacitance is also reduced by embedding thick oxide between the bottom of the gate polysilicon and the top of the JFET region. The difference is that the thick oxide is a trench thick oxide layer formed in the epitaxial layer. After the JFET formation region is defined by the mask, the trench is first etched, and then ion implantation is performed to form the JFET region. Compared with the first method, the position of the JFET region moves downward, the position of the thick oxide also moves downward, and the upper surface of the gate oxide is flush with the upper surface of the thick oxide.
[0057] The third implementation method includes the following steps:
[0058] Step g: define a JFET formation area by using a mask, first perform etching to form a groove, and then perform ion implantation to form the JFET area.
[0059] Step h: growing gate oxide, which extends to the sidewalls and bottom surface of the trench.
[0060] Step i: deposit polysilicon and etch to form a split gate structure of gate polysilicon in the channel region and source polysilicon above the JFET region.
[0061] In this implementation, a split-gate structure is adopted to shield the gate-drain capacitance, and a trench is first formed above the JFET region and then the split-gate structure is formed.
[0062] Step 5: Ion implantation is performed on the epitaxial layer and the implantation is carried out to form a well region and a source region.
[0063] Among them, the ion conduction types used for ion implantation in the well region and the source region formed in step five are different, and the details are not repeated here.
[0064] Figures 3 to 5 Shown is a schematic diagram of a super junction MOSFET structure according to an embodiment of the present invention. Figure 3 A super junction MOSFET structure formed corresponding to the first implementation method described above; Figure 4 A super junction MOSFET structure formed corresponding to the second implementation method described above; Figure 5 The super junction MOSFET structure formed by the third implementation method described above. Figures 3 to 5As shown, the embodiments of the present invention reduce the gate-drain capacitance by embedding thick oxygen between the bottom of the gate polysilicon and the top of the JFET region, or use a split gate structure to shield the gate-drain capacitance, thereby reducing the gate-drain capacitance of the super junction device and improving the switching characteristics.
[0065] Of course, the follow-up also includes: forming an interlayer film, forming an opening for a contact hole passing through the interlayer film; filling metal in the opening to form a complete contact hole; forming a front metal layer, and patterning the front metal layer to form a source and a gate; thinning the back side of the epitaxial layer and forming a drain region on the back side of the thinned epitaxial layer, and then forming a back side metal layer, and the back side metal layer constitutes a drain, which is not shown in the figure.
[0066] The embodiment of the present invention achieves the purpose of reducing the gate-drain capacitance of the super junction device and improving the switching characteristics by embedding thick oxygen or a split gate structure between the bottom of the gate polysilicon and the top of the JFET region. Moreover, the present invention can achieve the process realization without adding an additional photomask in the existing process, and the process cost is low.
[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for reducing the Miller capacitance of a super junction MOSFET, characterized in that: The following steps are involved: Step 1: providing a substrate, and forming an epitaxial layer on the substrate; Step 2: Define the formation area of the super junction structure according to photolithography, and etch the epitaxial layer to form a groove; Step 3: Filling the groove with P-type material to form a P-type column; Step 4: forming a JFET region, gate polysilicon, and a thick oxide or split gate structure therebetween; Step 5: perform ion implantation and advancement on the epitaxial layer to form a well region and a source region.
2. The method for reducing the Miller capacitance of a super junction MOSFET according to claim 1, characterized in that: The substrate in step 1 is a silicon substrate.
3. The method for reducing Miller capacitance of super junction MOSFET according to claim 1, characterized in that: The super junction structure described in step 2 is a P-type column.
4. The method for reducing Miller capacitance of super junction MOSFET according to claim 1, characterized in that: The P-type material in step three is P-type silicon.
5. The method for reducing Miller capacitance of super junction MOSFET according to claim 4, characterized in that: The P-type silicon is a P-type silicon epitaxial layer formed by epitaxial growth.
6. The method for reducing Miller capacitance of super junction MOSFET according to claim 1, characterized in that: Step 4 includes the following steps: Step a, defining a JFET region by means of a photomask, and performing ion implantation to form the JFET region, wherein the upper surface of the JFET region is flush with the upper surface of the epitaxial layer; Step b, growing gate oxide and forming thick oxide above the JFET region; Step c: depositing polysilicon and etching to form gate polysilicon.
7. The method for reducing Miller capacitance of super junction MOSFET according to claim 6, characterized in that: In step a, the upper surface of the JFET region is flush with the upper surface of the epitaxial layer.
8. The method for reducing Miller capacitance of super junction MOSFET according to claim 1, characterized in that: Step 4 includes the following steps: Step d, defining the JFET region by means of a photomask, firstly etching to form a groove, and then performing ion implantation to form the JFET region; Step e, filling the trench to form thick oxide; Step f, growing gate oxide, depositing polysilicon and etching to form gate polysilicon.
9. The method for reducing Miller capacitance of super junction MOSFET according to claim 8, characterized in that: In step f, the upper surface of the gate oxide is flush with the upper surface of the thick oxide.
10. The method for reducing Miller capacitance of super junction MOSFET according to claim 1, characterized in that: Step 4 includes the following steps: Step g, defining the JFET region by means of a photomask, firstly performing etching to form a groove, and then performing ion implantation to form the JFET region; Step h, growing gate oxide, wherein the gate oxide extends to the sidewall and bottom surface of the trench; Step i: deposit polysilicon and etch to form a split gate structure of gate polysilicon in the channel region and source polysilicon above the JFET region.