Semiconductor element
By adjusting the profile of the fin structure using bevel ion implantation and etching in the MOSCAP element, the problem of poor stability in thermal annealing treatment is solved, achieving higher thermal stability and lower manufacturing costs.
Patent Information
- Application Number
- CN202311058968.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-07
- Filing Date
- 2023-08-22
- Publication Date
- 2025-02-18
AI Technical Summary
In thermal annealing, existing MOSCAP elements are prone to chemical deterioration or physical embrittlement of other layers outside the binary metal layer, and have poor thermal stability, which increases the difficulty of the production process and manufacturing cost.
The bevel ion implantation production process is used to inject dopant into the MOSCAP region to form a fin structure, and the etching is used to remove some insulating layers to form shallow groove isolation, and the profile of the fin structure is adjusted to improve the stability of the capacitance structure.
Adjusting the profile of the fin structure through bevel ion implantation and etching improves the thermal stability of the MOSCAP element, reduces manufacturing costs, and improves the overall performance of the capacitance structure.
Smart Images
Figure CN119486236A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor element, and in particular to a Metal-Oxide-Semiconductor Capacitor (MOSCAP) element. Background Art
[0002] The capacitor structure of the semiconductor device may be a metal-oxide-semiconductor capacitor (MOSCAP) structure, which is commonly used in the gate structure of a metal oxide semiconductor field effect transistor (MOSFET). The manufacture of this capacitor structure includes depositing an oxide layer on one side of a substrate layer, depositing a metal layer (as a bottom electrode layer) on the other side of the substrate layer, and depositing a binary metal layer (as a top electrode layer) on the oxide layer to obtain a stacked layer.
[0003] Since this binary metal layer does not have a work function that can be applied to the capacitor structure of MOS, it must be subjected to thermal annealing treatment to give it an appropriate work function before it can be applied to the capacitor structure of MOS. For example, the work functions of the capacitor structures suitable for P-type MOS and N-type MOS can be not less than 4.7eV and not more than 4.3eV, respectively. However, this thermal annealing treatment may cause changes in other layers outside the binary metal layer, such as chemical deterioration or physical embrittlement. In addition, the heat treatment (such as heating treatment or thermal annealing treatment) performed on other layers may also cause damage to the binary metal layer with poor thermal stability. Accordingly, the existing MOS capacitor structure must adjust and strictly control the temperature, time and atmosphere of the thermal annealing treatment, which increases the difficulty of the manufacturing process and increases the manufacturing cost. In view of this, it is urgent to develop a new MOSCAP component to improve the above-mentioned shortcomings. Summary of the invention
[0004] An embodiment of the present invention discloses a semiconductor element, which mainly includes a lower half, a middle half, an upper half and a base arranged between the lower half and the substrate, wherein the lower half is surrounded by shallow trench isolation, the gate oxide layer is arranged on the fin structure and the shallow trench isolation, the bottom surface of the gate oxide layer is higher than the top surface of the base, the top surface of the lower half or the width of the top surface is preferably greater than the bottom surface of the lower half or more than half of the width of the bottom surface, and the top of the upper half includes a tapered portion.
[0005] Another embodiment of the present invention discloses a semiconductor element, which mainly includes a lower half, a middle half, an upper half and a base arranged between the lower half and the substrate, wherein the lower half is surrounded by shallow trench isolation, the gate oxide layer is arranged on the fin structure and the shallow trench isolation, the bottom surface of the gate oxide layer is higher than the top surface of the base, the top surface of the lower half or the width of the top surface is preferably greater than the bottom surface of the lower half or more than half of the width of the bottom surface, and the top of the upper half includes a circular portion. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figures 1 to 6 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0007] Figure 7 It is a schematic diagram of the structure after arsenic (As) is implanted into the fin structure by using an ion implantation process according to one embodiment of the present invention;
[0008] Figure 8 FIG. 1 is a schematic diagram of a structure after phosphorus (P) is implanted into a fin structure using an ion implantation process according to an embodiment of the present invention.
[0009] Explanation of symbols
[0010] 12: Base
[0011] 14: Non-MOSCAP area
[0012] 16: MOSCAP area
[0013] 18: Base
[0014] 20: Fin structure
[0015] 22: Shallow Trench Isolation
[0016] 24: Doping layer
[0017] 26: Covering layer
[0018] 28: Annealing process
[0019] 30: Gate oxide layer
[0020] 32: Gate electrode
[0021] 34: Gate electrode
[0022] 36: Gate material layer
[0023] 38: Interlayer dielectric layer
[0024] 46: High dielectric constant dielectric layer
[0025] 48: Work function metal layer
[0026] 50: Low impedance metal layer
[0027] 52: Insulation layer
[0028] 54: Patterned mask
[0029] 56: Ion implantation process
[0030] 58: Peak annealing process
[0031] 62: Lower half
[0032] 64: Middle half
[0033] 66: Upper part
[0034] 68: Base
[0035] 72:Metal gate
[0036] 74: Hard mask DETAILED DESCRIPTION
[0037] Please refer to Figures 1 to 6 , Figures 1 to 6 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, first, a substrate 12 is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which at least two regions are defined, including a non-MOSCAP region 14 and a MOSCAP region 16, wherein the non-MOSCAP region 14 can be used to prepare input / output (I / O) components or low-voltage components in subsequent manufacturing processes, and the MOSCAP region 16 is preferably used to prepare MOSCAP components.
[0038] Then, a base 18 and a fin structure 20 can be formed on the substrate 12 of the non-MOSCAP area 16, and a plurality of fin structures 20 can be formed on the substrate 12 of the MOSCAP area 18. According to a preferred embodiment of the present invention, the fin structure 20 is preferably obtained by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers or mandrels can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then a fin structure cutting process (fin cut) is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.
[0039] In addition, the formation method of the base 18 and the fin-shaped structure 20 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the base 18 and the fin-shaped structure 20. In addition, the formation method of the base 18 and the fin-shaped structure 20 may also include first making a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed to the patterned hard mask layer, and this semiconductor layer can serve as the corresponding base 18 and the fin-shaped structure 20. These embodiments of forming the base 18 and the fin-shaped structure 20 are all within the scope of the present invention.
[0040] Then, a flowable chemical vapor deposition (FCVD) process is performed to form an insulating layer 52 made of silicon oxide on the base 18 and the fin structure 20 and fill the groove between the base 18 and the fin structure 20. Then, a planarization process is performed, such as chemical mechanical polishing (CMP), to remove a portion of the insulating layer 52 so that the remaining insulating layer 52 is roughly aligned with the top surface of the fin structure 20.
[0041] Then as Figure 2 As shown, a patterned mask 54 such as a patterned photoresist is first formed in the non-MOSCAP region 14 or even a portion of the MOSCAP region 16 to expose a portion of the insulating layer 52 and the top surface of the fin structure 20 in the MOSCAP region 16, and then an ion implantation process 56 is performed using the patterned mask 54 as a mask to implant dopants such as arsenic (As) or phosphorus (P) into the fin structure 20. It should be noted that the ion implantation process 56 performed in this stage is preferably an oblique ion implantation process, thereby implanting the above ions into the fin structure 20 in the MOSCAP region 16 at an oblique angle. According to a preferred embodiment of the present invention, the angle of the oblique ion implantation process is preferably between 0-25 degrees or preferably about 15 degrees. Since the ion implantation process performed in this stage only implants ions into the fin structure 20 of the MOSCAP region 16 but not into the fin structure 20 of the non-MOSCAP region 14, the overall concentration of the fin structure 20 of the MOSCAP region 16 is preferably greater than the overall concentration of the fin structure 20 of the non-MOSCAP region 14, and the fin structure 20 of the MOSCAP region 16 implanted with ions can be used as the lower electrode of the MOSCAP element in the subsequent manufacturing process.
[0042] like Figure 3As shown, a heat treatment process or more specifically a spike annealing process 58 is then performed to diffuse the implanted dopants into the fin structure 20 using high temperature. According to a preferred embodiment of the present invention, the temperature of the spike annealing process 58 is preferably between 950 and 1250 degrees Celsius and the time is preferably between 0 and 3 seconds. The patterned mask 54 of the MOSCAP region 16 can then be removed. It should be noted that although the patterned mask 54 is removed after the spike annealing process 58 is completed in this embodiment, it is not limited thereto. According to other embodiments of the present invention, the patterned mask 54 can be completely removed before the spike annealing process 58 is performed, and this sequence is also within the scope of the present invention.
[0043] like Figure 4 As shown, etching may then be used to remove a portion of the insulating layer 52 in the non-MOSCAP region 14 and the MOSCAP region 16, so that the top surface of the remaining insulating layer 52 is slightly lower than the top surface of the fin structure 20 to form a shallow trench isolation (STI) 22. Then, an oxide growth process such as a rapid thermal oxidation (RTO) process or an in-situ steam generation (ISSG) process is performed to form a gate oxide layer 30 composed of silicon oxide on the substrate 12 and the fin structure 20 in the non-MOSCAP region 14 and the MOSCAP region 16.
[0044] Then as Figure 5 As shown, gate electrodes 32 and 34 can be formed on the substrate 12 and the fin structure 20 of the non-MOSCAP region 14 and the MOSCAP region 16, respectively. The gate electrode 32 of the non-MOSCAP region 14 can be used as a gate electrode of an I / O device or a low voltage device, and the gate electrode 34 of the MOSCAP region 16 can be used as an upper electrode of a MOSCAP device. The gate electrodes 32 and 34 can be manufactured by a gate first manufacturing process, a high-k first manufacturing process of a gate last manufacturing process, or a high-k last manufacturing process of a gate last manufacturing process according to the manufacturing process requirements.
[0045] Taking the post-high-k dielectric layer manufacturing process of the present embodiment as an example, a gate material layer 36 composed of polysilicon and a selective hard mask (not shown) can be sequentially formed on the substrate 12, and a pattern transfer manufacturing process is performed using a patterned photoresist (not shown) as a mask to remove a portion of the gate material layer 36 and a portion of the gate oxide layer 30 by a single etching or successive etching steps, and then the patterned photoresist is stripped off to form gate electrodes 32 and 34 composed of the patterned gate material layer 36 on the substrate 12 and the fin structure 20 in the non-MOSCAP area 14 and the MOSCAP area 16.
[0046] Then, at least one spacer (not shown) is formed on the sidewalls of the gate electrodes 32 and 34, respectively, and then a source / drain region (not shown) and / or an epitaxial layer are formed in the fin structure 20 and / or the substrate 12 on both sides of the spacer in the non-MOSCAP region 14, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region and / or the epitaxial layer. In the present embodiment, the spacer may be a single spacer or a composite spacer, for example, the details may include an offset spacer and a main spacer. The offset spacer and the main spacer may include the same or different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. The source / drain region may include different dopants depending on the conductivity type of the transistor to be prepared, for example, it may include P-type dopants or N-type dopants.
[0047] Next, an interlayer dielectric layer 38 is formed to cover the gate electrodes 32 and 34 , and then a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 38 and expose the gate electrodes 32 and 34 made of polysilicon material, so that the upper surface of the gate electrodes 32 and 34 is flush with the upper surface of the interlayer dielectric layer 38 .
[0048] like Figure 6 As shown, a metal gate replacement process is then performed to convert the gate electrodes 32 and 34 formed of polysilicon material in the non-MOSCAP region 14 and the MOSCAP region 16 into metal gates. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 36 and even the gate oxide layer 30, so as to form a groove in the interlayer dielectric layer 38 (not shown).
[0049] Then, a selective dielectric layer (not shown) or a gate dielectric layer, a high dielectric constant dielectric layer 46, a work function metal layer 48 and a low impedance metal layer 50 are sequentially formed in the groove, and then a planarization process is performed, such as using CMP to remove part of the low impedance metal layer 50, part of the work function metal layer 48 and part of the high dielectric constant dielectric layer 46 to form a metal gate 72. Taking the gate structure manufactured by the post high dielectric constant dielectric layer manufacturing process in this embodiment as an example, each formed metal gate 72 preferably includes a dielectric layer or a gate oxide layer 30, a U-shaped high dielectric constant dielectric layer 46, a U-shaped work function metal layer 48 and a low impedance metal layer 50. The heavily doped fin structure 20 is preferably used as the lower electrode of the MOSCAP element, the gate oxide layer 30 and / or the high dielectric constant dielectric layer 46 are preferably used as the capacitor dielectric layer of the MOSCAP element, and the gate electrode 34 composed of materials such as the work function metal layer 48 and the low resistance metal layer 50 can be used as the upper electrode of the MOSCAP element.
[0050] In the present embodiment, the high-k dielectric layer 46 includes a dielectric material with a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.
[0051] The work function metal layer 48 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 48 and the low resistance metal layer 50, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and other materials. The low resistance metal layer 50 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalttungsten phosphide, CoWP) or a combination thereof. Since converting a dummy gate into a metal gate according to a metal gate replacement manufacturing process is a well-known technique in this field, it will not be further described here. Then, a portion of the high dielectric constant dielectric layer 46, a portion of the work function metal layer 48 and a portion of the low resistance metal layer 50 may be removed to form a groove (not shown), and then a hard mask 74 is filled in the groove and the hard mask 74 is flush with the surface of the interlayer dielectric layer 38, wherein the hard mask 74 may be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon nitride carbide.
[0052] Afterwards, a pattern transfer process may be performed, for example, a pattern mask may be used to remove a portion of the interlayer dielectric layer 38 beside the gate electrode 32 in the non-MOSCAP region to form a plurality of contact holes (not shown) and expose the source / drain region. Then, the required metal material is filled into each contact hole, for example, a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalt tungsten phosphide, CoWP), or a combination thereof. Afterwards, a planarization process is performed, for example, chemical mechanical polishing is used to remove a portion of the metal material to form contact plugs (not shown) in each contact hole to electrically connect the source / drain region. At this point, the fabrication of the semiconductor element of the preferred embodiment 1 of the present invention is completed.
[0053] Please continue to refer to Figure 7 and Figure 8 , Figure 7 and Figure 8They are respectively enlarged schematic diagrams of the fin structure 20 after dopants are implanted into the fin structure 20 of the MOSCAP region 16 by an ion implantation process according to an embodiment of the present invention, wherein Figure 7 This is a schematic diagram of the structure after arsenic (As) is implanted into the fin structure using the ion implantation process. Figure 8 This is a schematic diagram of the structure after phosphorus (P) is implanted into the fin structure using the ion implantation process. In order to highlight the contour features of the fin structure itself, Figure 7 and Figure 8 It is preferred to omit the gate electrodes 32, 34 and other structures above the gate oxide layer 30. Figure 7 As shown, the arsenic-doped fin structure 20 mainly includes a lower half 62, a middle half 64, an upper half 66, and a base 68 disposed between the lower half 62 and the substrate 12, wherein the base 68 is surrounded by the shallow trench isolation 22, the gate oxide layer 30 is disposed on the fin structure 20 and the shallow trench isolation 22, the bottom surface of the gate oxide layer 30 can be cut flush with or higher than the top surface of the base 68, the top surface or the top surface width of the lower half 62 is preferably greater than half of the bottom surface or the bottom surface width of the lower half 62, and the top of the upper half 66 includes a tapered portion. In this embodiment, the definition of the so-called tapered portion may include, for example, that the angle between the top surface of the upper half 66 and the two side walls may be between 0-30 degrees or more preferably less than 20 degrees.
[0054] From a detailed perspective, the bottom surface or bottom surface width of the lower half 62 is preferably smaller than the height of the lower half 62, the bottom surface or bottom surface width of the middle half 64 is preferably equal to twice the top surface or top surface width of the middle half 64, the height of the middle half is preferably smaller than the height of the lower half 62, the bottom surface or bottom surface width of the upper half 66 is preferably equal to the height of the upper half 66, and the height of the upper half 66 is preferably smaller than the height of the middle half 64.
[0055] According to one embodiment of the present invention, the bottom surface width of the lower half 62 is preferably between 13 and 15 nanometers or more preferably about 14 nanometers, the height of the lower half 62 is preferably between 15 and 17 nanometers or more preferably about 16 nanometers, the top surface width of the lower half 62 or the bottom surface width of the middle half 64 is preferably between 7 and 9 nanometers or more preferably about 8 nanometers, the height of the middle half 64 is preferably between 10 and 12 nanometers or more preferably about 11 nanometers, the top surface width of the middle half 64 or the bottom surface width of the upper half 66 is preferably between 3 and 5 nanometers or more preferably about 4 nanometers, and the height of the upper half 66 is preferably between 3 and 5 nanometers or more preferably about 4 nanometers.
[0056] In addition, Figure 8As shown, the phosphorus-doped fin structure 20 also includes a lower half 62, a middle half 64, an upper half 66, and a base 68 disposed between the lower half 62 and the substrate 12, wherein the base 68 is surrounded by the shallow trench isolation 22, and the gate oxide layer 30 is disposed on the fin structure 20 and the shallow trench isolation 22. The bottom surface of the gate oxide layer 30 can be cut flush with or higher than the top surface of the base 68, and the top surface or top surface width of the lower half 62 is preferably greater than half of the bottom surface or bottom surface width of the lower half 62. Figure 7 The top of the fin structure 20 in the embodiment is roughly conical, and the top of the fin structure 20 or the top of the upper half 66 in the embodiment is a rounded portion. In the embodiment, the definition of the so-called rounded portion may include that the top surface of the upper half 66 is an arc-shaped surface, and the angle between the arc-shaped top surface and the two side walls of the upper half 66 may be between 30 and 50 degrees or more preferably between 30 and 40 degrees.
[0057] In detail, the bottom surface or bottom surface width of the lower half 62 of the present embodiment is preferably smaller than the height of the lower half 62, the bottom surface or bottom surface width of the middle half 64 is preferably smaller than half the height of the lower half 62, the height of the middle half 64 is preferably smaller than the height of the lower half 62, the bottom surface or bottom surface width of the upper half 66 is preferably greater than the height of the upper half 66, and the height of the upper half 66 is preferably smaller than the height of the middle half 64.
[0058] According to one embodiment of the present invention, the bottom surface width of the lower half 62 is preferably between 12 and 14 nanometers or more preferably about 13 nanometers, the height of the lower half 62 is preferably between 16 and 18 nanometers or more preferably about 17 nanometers, the top surface width of the lower half 62 or the bottom surface width of the middle half 64 is preferably between 6 and 8 nanometers or more preferably about 7 nanometers, the height of the middle half 64 is preferably between 12 and 14 nanometers or more preferably about 13 nanometers, the top surface width of the middle half 64 or the bottom surface width of the upper half 66 is preferably between 4 and 6 nanometers or more preferably about 5 nanometers, and the height of the upper half 66 is preferably between 3 and 5 nanometers or more preferably about 4 nanometers.
[0059] In summary, the present invention discloses a method for manufacturing a MOSCAP device in a MOSCAP region using an oblique angle ion implantation process, wherein the fin structure in the MOSCAP device can be different according to the implanted dopant and at Figure 4 When a portion of the insulating layer 52 is removed by etching to form the shallow trench isolation 22, different profiles are obtained by adjusting the etching. Figure 7 As shown, the top of the fin structure implanted with arsenic preferably forms a roughly pointed conical portion, and Figure 8 The top of the fin structure into which phosphorus is injected is preferably formed into a slightly arc-shaped round portion. Both profiles can be prepared according to the manufacturing process or product requirements, and Figure 8The fin-shaped structure has a wider top area overall, so it can be used to increase the overall capacitance value of the MOSCAP component.
[0060] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A semiconductor element, characterized in that: Include: A fin-shaped structure is disposed on the substrate, and the fin-shaped structure comprises: a lower half, wherein the top surface of the lower half is larger than half of the bottom surface of the lower half; middle half; and The upper half includes a tapered portion at the top. 2 . The semiconductor device as claimed in claim 1 , further comprising a base disposed between the lower half and the substrate. 3 . The semiconductor device as claimed in claim 2 , further comprising a gate oxide layer disposed on the fin structure, wherein a bottom surface of the gate oxide layer is higher than a top surface of the base. The semiconductor device as claimed in claim 1 , wherein the bottom surface of the lower portion is smaller than the height of the lower portion. 5 . The semiconductor device as claimed in claim 1 , wherein the bottom surface of the middle portion is equal to twice the width of the top surface of the middle portion. The semiconductor device as claimed in claim 1 , wherein a height of the middle portion is smaller than a height of the lower portion. The semiconductor device as claimed in claim 1 , wherein the bottom surface of the upper portion is equal to the height of the upper portion. The semiconductor device as claimed in claim 1 , wherein a height of the upper portion is smaller than a height of the middle portion. 9 . The semiconductor device as claimed in claim 1 , wherein a surface of the fin structure comprises arsenic.
10. A semiconductor element, characterized in that: Include: A fin-shaped structure is disposed on the substrate, and the fin-shaped structure comprises: a lower half, wherein the top surface of the lower half is larger than half of the bottom surface of the lower half; middle half; and The upper part includes a circular portion at the top. 11 . The semiconductor device as claimed in claim 10 , further comprising a base disposed between the lower half and the substrate. 12 . The semiconductor device as claimed in claim 11 , further comprising a gate oxide layer disposed on the fin structure, wherein a bottom surface of the gate oxide layer is higher than a top surface of the base. 13 . The semiconductor device as claimed in claim 10 , wherein the bottom surface of the lower portion is smaller than the height of the lower portion. The semiconductor device as claimed in claim 10 , wherein a bottom surface of the middle half is smaller than half the height of the lower half. The semiconductor device as claimed in claim 10 , wherein a height of the middle portion is smaller than a height of the lower portion. The semiconductor device as claimed in claim 10 , wherein the bottom surface of the upper portion is larger than the height of the upper portion. The semiconductor device as claimed in claim 10 , wherein a height of the upper portion is smaller than a height of the middle portion. The semiconductor device as claimed in claim 10 , wherein a surface of the fin structure comprises phosphorus.