Display substrate and manufacturing method thereof, display panel

Abstract

The embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display panel. The display substrate includes a base substrate and a plurality of gate lines, a plurality of data lines, a plurality of gate leads, and a plurality of data leads located on the surface of the base substrate. The base substrate has a display area and a peripheral area. In the display area, the plurality of gate lines and data lines intersect to define a plurality of pixel areas. A plurality of gate leads and data leads located in the peripheral area and at different layers are alternately arranged in a first direction, and the gate leads and data lines are electrically connected to the gate lines and data leads respectively. There is a first lead among the gate leads and the data leads, and the first lead includes M first lead segments and M-1 second lead segments alternately arranged in a second direction, and a plurality of connecting segments. Each first lead segment is located between two adjacent second leads, and the second lead segment is spaced apart from the first lead segment by at least two second leads in the first direction. The present disclosure can improve the display defects that occur when the display panel is refreshed.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Display devices are widely used in people's daily lives, such as mobile phones, monitors, and tablet computers. The display panel is an important component of the display device. The display panel includes a first substrate and a second substrate arranged opposite to each other.

[0003] In the related art, the first substrate includes a base substrate and a plurality of gate lines, a plurality of data lines, a plurality of data leads, and a plurality of gate leads located on the surface of the base substrate. The base substrate has a display area and a peripheral area, and the peripheral area surrounds the display area. In the display area, the plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas. The plurality of data leads are located in the peripheral area, one end of the data lead is connected to a driver chip, and the other end of the data lead is connected to the corresponding data line. The plurality of gate leads are in the same layer as the plurality of data leads and are arranged alternately in a first direction. One end of the gate lead is connected to the driver chip, and the other end of the gate lead is connected to the corresponding gate line.

[0004] Due to the large coupling capacitance between the data lead and the gate lead, display defects such as abnormal bright lines appear on the display panel. Summary of the Invention

[0005] The present disclosure provides a display substrate and a manufacturing method thereof, and a display panel, which can improve poor display caused by excessive coupling capacitance between data leads and gate leads.

[0006] On the one hand, a display substrate is provided, the display substrate comprising a base substrate and a plurality of gate lines, a plurality of data lines, a plurality of gate leads and a plurality of data leads located on a surface of the base substrate, the base substrate having a display area and a peripheral area, the peripheral area surrounding the display area; in the display area, the plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas; the plurality of gate leads and the plurality of data leads are both located in the peripheral area, the plurality of gate leads and the plurality of data leads are located in different layers, and the plurality of gate leads and the plurality of data leads are alternately arranged in a first direction, the plurality of gate leads are electrically connected to the plurality of gate lines in a one-to-one correspondence, and the plurality of data lines are electrically connected to the plurality of data leads in a one-to-one correspondence; the plurality of gate leads and the plurality of data leads are electrically connected to the plurality of data leads in a one-to-one correspondence There is at least one first lead among the multiple data leads, and the first lead includes M first lead segments, M-1 second lead segments and multiple connecting segments, wherein M is an integer and M is greater than 1, the M first lead segments and the M-1 second lead segments are alternately arranged in the second direction, and adjacent first lead segments and second lead segments are connected by one connecting segment, the second direction intersects with the first direction, the M first lead segments are all located between two adjacent second lead lines, and the second lead segment and the first lead segment are spaced apart by at least two second lead lines in the first direction; wherein, the first lead is the gate lead, and the second lead is the data lead; or, the first lead is the data lead, and the second lead is the gate lead.

[0007] Optionally, for any first lead, two second leads adjacent to the M-1 second lead segments are located on the same side of the M first lead segments in the first direction.

[0008] Optionally, the first lead is the gate lead, and the two second leads adjacent to the first lead segment and the two second leads adjacent to the second lead segment are four data leads continuously adjacent in the first direction; or, the first lead is the data lead, and the two second leads adjacent to the first lead segment and the two second leads adjacent to the second lead segment are four gate leads continuously adjacent in the first direction.

[0009] Optionally, for any first lead, two second leads adjacent to a part of the M-1 second lead segments are located on one side of the M first lead segments in the first direction, and two second leads adjacent to another part of the second lead segments in the M-1 second lead segments are located on the other side of the M first lead segments in the first direction, where M is greater than 2.

[0010] Optionally, the first lead is a gate lead, and the two adjacent second lead lines of the M first lead segments and the four adjacent second lead lines of the M-1 second lead segments are six data leads that are continuously adjacent in the first direction; or, the first lead is a data lead, and the two adjacent second lead lines of the first lead segment and the four adjacent second lead lines of the second lead segment are six gate leads that are continuously adjacent in the first direction.

[0011] Optionally, a ratio of the total length of the M first lead segments to the total length of the M-1 second lead segments is 0.5-2.

[0012] Optionally, the simplest integer ratio of the number of the multiple gate lines to the number of the multiple data lines is P:Q, and P<Q; on the side of the peripheral area close to the display area, the multiple gate leads and the multiple data leads are divided into multiple repeating units, and each of the repeating units includes P gate leads and Q data leads.

[0013] Optionally, P is equal to 2, Q is equal to 3; or, P is equal to 3, Q is equal to 4.

[0014] Optionally, the orthographic projection of the first lead segment on the surface does not overlap with the orthographic projections of two adjacent second leads on the surface, and the orthographic projection of the second lead segment on the surface does not overlap with the orthographic projections of two adjacent second leads on the surface.

[0015] Optionally, the connecting segment is perpendicular to the second lead line located between the first lead line segment and the second lead line segment connected by the connecting segment.

[0016] Optionally, the display substrate further includes a plurality of selection lines, the plurality of selection lines and the plurality of gate lines are in a different layer, and the gate line is connected to the corresponding gate lead through one of the plurality of selection lines.

[0017] Optionally, the gate line is connected to the corresponding selection line through a first via hole, and the first via hole is located in the display area; the selection line is connected to the corresponding gate lead through a second via hole, and the second via hole is located in the peripheral area.

[0018] Optionally, the selection line and the data line are in the same layer and extend in the same direction.

[0019] On the other hand, a method for manufacturing a display substrate is provided, the method comprising: providing a base substrate, the base substrate having a display area and a peripheral area, the peripheral area surrounding the display area; forming a plurality of gate lines, a plurality of data lines, a plurality of gate leads and a plurality of data leads on the surface of the base substrate; wherein, in the display area, the plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas, the plurality of gate leads and the plurality of data leads are both located in the peripheral area, the plurality of gate leads and the plurality of data leads are located in different layers, and the plurality of gate leads and the plurality of data leads are alternately arranged in a first direction, the plurality of gate leads are electrically connected to the plurality of gate lines in a one-to-one correspondence, and the plurality of data lines are electrically connected to the plurality of data leads in a one-to-one correspondence; the plurality of gate lines are electrically connected to the plurality of data leads in a one-to-one correspondence; There is at least one first lead among the gate lead and the multiple data leads, the first lead includes M first lead segments, M-1 second lead segments and multiple connecting segments, wherein M is an integer and M is greater than 1, the M first lead segments and the M-1 second lead segments are alternately arranged in the second direction, and adjacent first lead segments and second lead segments are connected by one connecting segment, the second direction intersects with the first direction, the M first lead segments are all located between two adjacent second lead lines, and the second lead segment and the first lead segment are spaced apart by at least two second lead lines in the first direction; the first lead is the gate lead, and the second lead is the data lead; or, the first lead is the data lead, and the second lead is the gate lead.

[0020] On the other hand, a display panel is provided, which includes a first substrate, a second substrate and a plurality of charged particles, wherein the plurality of charged particles are located between the first substrate and the second substrate, the first substrate and the second substrate respectively have electrodes, and the electrodes of the first substrate and the electrodes of the second substrate are used to form an electric field that drives the plurality of charged particles to move between the first substrate and the second substrate, and the first substrate is any of the aforementioned display substrates.

[0021] The beneficial effects brought about by the technical solution provided by the present disclosure include at least: In the embodiment of the present disclosure, the first lead (gate lead or data lead) is divided into a first lead segment and a second lead segment, and in the arrangement direction of the gate lead and the data lead (i.e., the first direction), at least two second lead segments are spaced between the first lead segment and the second lead segment. In this way, for each first lead, the first lead segment and the second lead segment are respectively adjacent to different second lead segments. Since the coupling capacitance between the first lead and an adjacent second lead is proportional to the length of the adjacent portions of the two first lead and the second lead, the coupling capacitance between the first lead and any adjacent second lead is reduced when part of the first lead is adjacent to two second lead segments and another part of the first lead is adjacent to the other two second lead segments compared to when the entire first lead is adjacent to the two second lead segments. That is, the coupling capacitance between the first lead and the second lead adjacent to the first lead segment is smaller than the coupling capacitance when the entire first lead is adjacent to the second lead, and the coupling capacitance between the first lead and the second lead adjacent to the second lead segment is also reduced. The coupling capacitance between the first lead and any adjacent second lead is reduced, which can improve the situation where the voltage on the data lead fluctuates with the voltage on the gate lead, thereby improving poor display when the display panel is refreshed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 This is a schematic structural diagram of a display substrate in the related art;

[0024] Figure 2 This is a schematic diagram of a display panel having poor display in the related art;

[0025] Figure 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0026] Figure 4 Schematic diagram of a wiring method of gate leads and data leads provided by an embodiment of the present disclosure;

[0027] Figure 5 is a schematic diagram of another wiring method of gate leads and data leads provided by an embodiment of the present disclosure;

[0028] Figure 6 is a schematic diagram of another wiring method of gate leads and data leads provided by an embodiment of the present disclosure;

[0029] Figure 7 is a schematic diagram of a partial structure of a first lead provided by an embodiment of the present disclosure;

[0030] Figure 8 is a simulation output waveform diagram provided by an embodiment of the present disclosure;

[0031] Figure 9 This is a comparison diagram of voltage fluctuations on data lines and gate lines when the wiring method in the embodiment of the present disclosure is not adopted / adopted;

[0032] Figure 10 is a schematic diagram of a cross-sectional structure of a display substrate provided by an embodiment of the present disclosure;

[0033] Figure 11 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0034] Figure 12 A method for manufacturing a display substrate is provided in an embodiment of the present disclosure.

[0035] Legend:

[0036] 1. Display substrate (first substrate) 2. Second substrate 3. Color particles

[0037] x, first direction y, second direction

[0038] 11. Base substrate 111, display area 112, peripheral area

[0039] 12. Gate line 13. Data line

[0040] 14. Gate lead 15. Data lead 16. Select line

[0041] 101, first lead segment 102, second lead segment 103, connecting segment

[0042] A. First via B. Second via

[0043] 1103, gate layer 1104, gate insulation layer 1105, semiconductor material layer

[0044] 1106, source and drain layer 1107, first passivation layer 1108, insulating layer

[0045] 1109, pixel electrode layer 1110, passivation layer DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0047] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the ordinary meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second", "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "a" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects.

[0048] Figure 1 This is a schematic diagram of the structure of a display substrate in the related art. Figure 1 As shown, the display substrate includes a base substrate 11 and a plurality of gate lines 12 , a plurality of data lines 13 , a plurality of gate leads 14 and a plurality of data leads 15 located on a surface of the base substrate 11 .

[0049] The base substrate 11 has a display area 111 and a peripheral area 112, and the peripheral area 112 surrounds the display area 111. In the display area 111, multiple gate lines 12 and multiple data lines 13 intersect and define multiple pixel areas. Multiple data leads 15 are located in the peripheral area, one end of the data lead 15 is connected to a driver IC (Integrated Circuit) (also known as a driver chip), and the other end of the data lead 15 is connected to the corresponding data line 13. Multiple gate leads 14 are in the same layer as the multiple data leads 15 and are arranged alternately in the first direction x. One end of the gate lead 14 is connected to the driver IC, and the other end of the gate lead 14 is connected to the corresponding gate line 12. The driver IC is located in the peripheral area 112 and is located on one side of the display area 111, for example, Figure 1 Located below the display area 111.

[0050] Each gate lead 14 includes a first segment 14a and a second segment 14b. The first segment 14a is located in the peripheral area 112, and the second segment 14b is located in the display area 111. One end of the first segment 14a is connected to the driver IC, the other end of the first segment 14a is connected to one end of the second segment 14b, and the other end of the second segment 14b is connected to the corresponding gate line 12.

[0051] In the peripheral area 112, the spacing between the first segment 14a of the gate lead 14 and the adjacent data lead 15 is small, resulting in a large coupling capacitance between the first segment 14a of the gate lead 14 and the adjacent data lead 15. When the display panel to which the display substrate belongs is refreshed, especially during a partial refresh, the data lead 15 may be affected by the large jump in the signal transmitted by the adjacent gate lead 14 due to the presence of this coupling capacitance, resulting in display defects such as abnormally bright lines on the display panel.

[0052] When the voltage of the signal transmitted in the gate lead 14 changes, it will abnormally pull the voltage on the adjacent data lead 15, causing a bright spot abnormality at the intersection of a corresponding group of gate lines 12 and data lines 13. When this problem occurs between multiple groups of adjacent data leads 15 and gate leads 14, it will cause abnormal bright lines. Figure 2 In the figure, black represents normal pixels and white represents abnormal pixels (with excessive brightness), which results in abnormally bright lines in the diagonal direction of the display panel. Here, "a corresponding set of gate lines 12 and data lines 13" refers to the gate lines 12 electrically connected to the gate leads 14, and the data lines 13 electrically connected to the data leads 15, respectively, where the gate leads 14 and the data leads 15 are adjacent to each other.

[0053] When the display panel is partially refreshed, for the non-refreshed area, the voltage on the corresponding data lead 15 is 0. At this time, the data lead 15 is more susceptible to the voltage on the gate lead 14 and generates voltage fluctuations, resulting in poor display.

[0054] Figure 3 It is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure. Figure 3 The structure of a part of the display substrate 1 is shown. Figure 3 As shown, the display substrate 1 includes a base substrate 11 and a plurality of gate lines (not shown in the figure), a plurality of data lines 13 , a plurality of gate leads 14 and a plurality of data leads 15 located on the surface of the base substrate 11 .

[0055] The base substrate 11 has a display area 111 and a peripheral area 112, with the peripheral area 112 surrounding the display area 111. In the display area 111, multiple gate lines 12 and multiple data lines 13 intersect and define multiple pixel areas. Multiple gate leads 14 and multiple data leads 15 are located in the peripheral area 112. The multiple gate leads 14 and the multiple data leads 15 are located in different layers and are arranged alternately in a first direction x. The multiple gate leads 14 are electrically connected to the multiple gate lines 12 in a one-to-one correspondence, and the multiple data lines 13 are electrically connected to the multiple data leads 15 in a one-to-one correspondence.

[0056] The following is an exemplary description using the example of the first lead being the gate lead 14 and the second lead being the data lead 15. In other embodiments, the first lead can also be the data lead 15 and the second lead can be the gate lead 14.

[0057] like Figure 4 As shown, each first lead includes M first lead segments 101, M-1 second lead segments 102 and a plurality of connecting segments 103, wherein M is an integer and M is greater than 1. For example, Figure 1 In the embodiment, M is equal to 2. M first lead segments 101 and M-1 second lead segments 102 are alternately arranged in the second direction y, and adjacent first lead segments 101 and second lead segments 102 are connected by a connecting segment 103. The second direction y intersects the first direction x. The M first lead segments 101 are each located between two adjacent second lead lines. The second lead segments 102 are spaced apart from the first lead segments 101 by at least two second lead lines in the first direction x.

[0058] It should be noted that if Figure 3 As shown, in the arrangement direction (first direction x) of multiple leads in the peripheral area 112, the outermost gate lead 14 has only one adjacent data lead 15, but the gate lead 14 also has a connected first lead segment 101, a second lead segment 102 and a connecting segment 103, and the distance between the second lead segment 102 and the adjacent second lead is greater than the distance between the first lead segment 101 and the adjacent second lead, so as to provide wiring space for the second lead segment of another adjacent gate lead 14.

[0059] The first lead (gate lead 14 or data lead 15) is divided into a first lead segment 101 and a second lead segment 102, and at least two second lead lines (data lead 15 or gate lead 14) are spaced between the first lead segment 101 and the second lead segment 102 in the arrangement direction of the gate leads and the data leads (i.e., the first direction). In this way, for each first lead, the first lead segment 101 and the second lead segment 102 are adjacent to different second lead lines. Since the coupling capacitance between the first lead and an adjacent second lead is proportional to the length of the adjacent parts of the two first leads and the second lead, compared with the case where the entire first lead is adjacent to the two second leads, the coupling capacitance between the first lead and any adjacent second lead is reduced when part of the first lead is adjacent to the two second leads and another part of the first lead is adjacent to the other two second leads. That is, the coupling capacitance between the first lead and the second lead adjacent to the first lead segment is smaller than the coupling capacitance when the entire first lead is adjacent to the second lead, and the coupling capacitance between the first lead and the second lead adjacent to the second lead segment is also reduced.

[0060] The coupling capacitance between the first lead and any adjacent second lead can be reduced, which can improve the situation of the voltage on the data lead fluctuating with the voltage on the gate lead, thereby improving the display defects that occur correspondingly when the display panel is refreshed, such as abnormal bright lines.

[0061] In Figure 3 the illustrated embodiment, the number of data lines 13 is greater than the number of gate lines (not shown in the figure). Correspondingly, the number of data leads 15 is also greater than the number of gate leads 14. Therefore, Figure 3 in the illustrated embodiment, two gate leads 14 are interspersed among every three data leads 15.

[0062] Figure 4 FIG. is a schematic diagram of another wiring method of gate leads and data leads provided by an embodiment of the present disclosure. As Figure 4 shown, for any first lead, the two second leads adjacent to M - 1 second lead segments 102 are located on one side of M first lead segments 101 in the first direction x, that is: M - 1 second lead segments 102 are located between the two second leads, and these two second leads are different from the two second leads adjacent to M first lead segments 101. Compared with the situation where the entire first lead is adjacent to two second leads, the first lead segments 101 and second lead segments 102 extending in the second direction y of the first lead are adjacent to different two sets of second leads, which can reduce the coupling capacitance between the first lead and the adjacent second lead, thereby improving the display defect.

[0063] Exemplarily, as Figure 4 shown, the first lead is the gate lead 14, and the two second leads adjacent to the first lead segment 101 and the two second leads adjacent to the second lead segment 102 are four consecutive adjacent data leads 15 in the first direction x. In this design method, two second leads are spaced between the first lead segment 101 and the second lead segment 102 in the first lead, which can reduce the coupling capacitance between two adjacent first leads and second leads as much as possible while minimizing the wiring space in the first direction x.

[0064] Exemplarily, as Figure 4 shown, when M is 2, the first lead includes two first lead segments 101 and one second lead segment 102. As Figure 4 shown, the first lead is in a "Ji" shape.

[0065] Since multiple first leads are all in a "Ji" shape, in some examples, the first lead segment 101 of one first lead and the second lead segment 102 of another first lead are located between the same two second leads. That is, the second lead segments 102 of multiple first leads are arranged oppositely to save wiring space.

[0066] Figure 5 Schematic diagram of another wiring method of gate leads and data leads provided by an embodiment of the present disclosure, such as Figure 5 As shown, when M is greater than 2, two adjacent second lead wires of the M-1 second lead wire segments 102 are both located on one side of the first lead wire segment 101, and there are multiple "J" shapes in the first lead wire, and the multiple "J" shapes are all facing the same side of the first lead wire segment 101 in the first direction x.

[0067] Figure 6 Schematic diagram of another wiring method of gate leads and data leads provided by an embodiment of the present disclosure, such as Figure 6 As shown, for any first lead, two second leads adjacent to a portion of the M-1 second lead segments 102 are located on one side of the M first lead segments 101 in the first direction x, and two second leads adjacent to another portion of the M-1 second lead segments 102 are located on the other side of the M first lead segments 101 in the first direction x. When M is greater than 2, for any first lead, a portion of the M-1 second lead segments 102 are adjacent to the two second leads located on one side of the M first lead segments 101 in the first direction x, and another portion of the M-1 second lead segments 102 are adjacent to the two second leads located on the other side of the M first lead segments 101 in the first direction x. The lead segments in the first lead are arranged in multiple "J" shapes, and the multiple "J" shapes face different sides of the first lead segment 101 in the first direction x.

[0068] Alternatively, as Figure 6 As shown, two second leads are spaced between the first lead segment 101 and the second lead segment 102, and the first lead is the gate lead 14. Figure 6 As shown, two adjacent second lead lines of the M first lead segments 101 and four adjacent second lead lines of the M-1 second lead segments 102 constitute six data lead lines 15 that are continuously adjacent in the first direction x. Alternatively, two second lead lines are spaced between the first lead segment 101 and the second lead segment 102, and the first lead lines are data lead lines 15. The two adjacent second lead lines of the first lead segment 101 and the four adjacent second lead lines 14 of the second lead segment constitute six gate lead lines 14 that are continuously adjacent in the first direction x.

[0069] The above-mentioned design methods can all play a role in effectively reducing the coupling capacitance between adjacent first leads and second leads. A selection can be made among the above-mentioned different design methods according to actual wiring space.

[0070] It should be noted that Figures 4 to 6 for Figure 3 A partial enlarged schematic diagram of the surrounding area. Figures 4 to 6The figure is only used to illustrate the positional relationship between the first lead segment 101, the second lead segment 102 and the second lead.

[0071] Figure 7 : is a partial structural diagram of the first lead provided by the embodiment of the present disclosure. Figure 7 As shown, the ratio of the total length a of the M first lead segments 101 to the total length b of the M-1 second lead segments 102 is 0.5 to 2, for example, 0.5, 0.8, 1, 1.5, and 2. The total length of the first lead is L, and the total length a of the M first lead segments 101 = Lb. When the ratio of the total length of the first lead segments 101 to the total length of the second lead segments 102 is 1, the overall effect of reducing coupling capacitance is best.

[0072] This is because, for adjacent first and second leads Y10 and Y20, the shorter the length of the adjacent region, the smaller the coupling capacitance between the first and second leads Y10 and Y20, until the ratio of the length of the portion of the first lead Y10 adjacent to the second lead Y20 to the total length of the first lead Y10 reaches 1 / 2, that is, the ratio of the total length a of the first lead segment 101 to the total length b of the second lead segment 102 is 1:1. When the ratio of the length of the portion of the first lead Y10 adjacent to the second lead Y20 to the total length of the first lead Y10 is less than 1 / 2, this means that the ratio of the length of the portion of the first lead Y10 adjacent to the second lead Y21 to the total length of the first lead Y10 is greater than 1 / 2. Overall, the coupling capacitance between the first lead Y10 and the adjacent second lead increases. Therefore, in the first lead, when the ratio of the total length of the first lead segment 101 to the total length of the second lead segment 102 is 0.5 to 2, the overall coupling capacitance is small, and under ideal conditions, when the ratio of the total length of the first lead segment 101 to the total length of the second lead segment 102 is 1, the overall coupling capacitance is minimum.

[0073] See again Figure 3 The display substrate further includes a driver IC located in the peripheral area, which is used to provide drive signals for inputting each gate line and each data line. The driver IC has a plurality of pins, and the plurality of pins are arranged along a first direction. Each pin is used to connect to a lead (gate lead or data lead). On the side close to the driver IC, the arrangement order of the gate lead 14 and the data lead 15 depends on the arrangement order of the plurality of pins of the driver chip.

[0074] In the embodiment of the present disclosure, Figure 3As shown, on the side of the peripheral area 112 near the display area 111, multiple gate leads and multiple data leads are divided into multiple repeating units, each of which includes P gate leads 14 and Q data leads 15. The simplest integer ratio of the number of gate lines 12 to the number of data lines 13 is P:Q, where P < Q. Here, it is assumed that the resolution of a certain product is p:q, p / q = P / Q, and p:q reflects the ratio of the width to length of the actual product display area. In each repeating unit, P data leads 15 are interspersed with Q gate leads 14, which can ensure a uniform distribution of the gate leads 14 and avoid uneven display.

[0075] For example, Figure 3 Two repeating units are shown. Figure 3 As shown, P is equal to 2, Q is equal to 3, that is, each repeating unit includes two gate leads 14 and three data leads 15. This corresponds to a horizontal screen product with a display area aspect ratio of 3:2. Figure 3 In the figure, from right to left, on the side of the peripheral area 112 near the display area 111, the first repeating unit is G1, S1, S2, G2, S3, and the second repeating unit is G3, S4, S5, G4, S6, and so on. Here, G represents the gate lead and S represents the data lead. On the side near the driver IC, from right to left, the order is: G1, S1, S2, G2, S3, S4, G3, S5, S6, G4, and so on.

[0076] Alternatively, in other embodiments, P is equal to 3 and Q is equal to 4, meaning each repeating unit includes three gate leads 14 and four data leads 15. This corresponds to a horizontal display product with a display area aspect ratio of 4:3. Practical verification has found that horizontal EPD products are most likely to exhibit display defects such as the aforementioned abnormal bright lines.

[0077] In other embodiments, the aspect ratio of the display area may also be other ratios besides 3:2 and 4:3, and the present disclosure does not impose any limitation on this.

[0078] For example, Figure 4 、 Figure 5 or Figure 6 As shown, the orthographic projection of the first lead segment 101 on the surface of the substrate 11 does not overlap with the orthographic projections of the two adjacent second leads on the surface of the substrate 11, and the orthographic projection of the second lead segment 102 on the surface of the substrate 11 does not overlap with the orthographic projections of the two adjacent second leads on the surface of the substrate 11. This can minimize the relative area between adjacent first and second leads, thereby reducing the coupling capacitance between adjacent first and second leads.

[0079] It should be noted that when the resolution of the product is too high, the orthographic projection of the first lead segment 101 or the second lead segment 102 on the surface of the base substrate 11 may overlap with the orthographic projection of the second lead on the surface of the base substrate 11, so as to arrange more gate leads 14 and data leads 15 in a smaller wiring space.

[0080] In the embodiment of the present disclosure, the spacing between two adjacent gate leads 14 can be 2μm to 5μm; the spacing between two adjacent data leads 15 can be 2μm to 5μm. The line width of the lead (gate lead 14 or data lead 15) can be set according to actual needs, for example, 2μm to 5μm. Generally, the spacing between two adjacent data leads is greater than the line width of a single gate lead, and the spacing between two adjacent gate leads is greater than the line width of a single data lead, so as to achieve that the orthographic projection of the first lead segment 101 or the second lead segment 102 on the surface of the base substrate 11 does not overlap with the orthographic projection of the second lead on the surface of the base substrate 11.

[0081] For example, Figure 4 、 Figure 5 or Figure 6 As shown, the connecting segment 103 is perpendicular to the second lead line located between the first lead line segment 101 and the second lead line segment 102 connected by the connecting segment 103. The connecting segment 103 being perpendicular to the second lead line can minimize the relative area between adjacent first and second lead lines, thereby reducing the coupling capacitance between adjacent first and second lead lines.

[0082] Optionally, in other embodiments, the angle between the connecting segment 103 and the second lead located between the first lead segment 101 and the second lead segment 102 connected by the connecting segment 103 is an acute angle or an obtuse angle, which is also beneficial to reducing the relative area between adjacent first leads and second leads, thereby reducing the coupling capacitance between adjacent first leads and second leads.

[0083] like Figure 3 As shown, the display substrate 1 further includes a plurality of select lines 16. The plurality of select lines 16 are located in a different layer from the plurality of gate lines 12. The gate lines 12 are connected to corresponding gate leads 14 via one of the plurality of select lines 16. Both the gate lines 12 and the data lines 13 need to be electrically connected to the driver chip. The select lines 16 can transfer the signals on the horizontally extending gate lines 12 to the longitudinally extending connection lines 16, which extend to the peripheral area 112, facilitating electrical connection to the IC chip.

[0084] For example, Figure 8As shown, the gate line 12 is connected to the corresponding select line 16 through a first via A, which is located in the display area 111. The select line 16 is connected to the corresponding gate lead 14 through a second via B, which is located in the peripheral area 112. The provision of the first via A and the second via B facilitates the connection between the gate line 12, the select line 16, and the gate lead 14. The placement of the first via A in the display area 112 saves wiring space, and the placement of the second via B in the peripheral area 112 minimizes the impact on the display area 111.

[0085] Optionally, the plurality of first via holes A are arranged diagonally in the display area 111 .

[0086] Optionally, the arrangement direction of the plurality of second via holes B is parallel to a side of the display area 111 close to the driver IC.

[0087] For example, Figure 8 As shown, the select line 16 and the data line 13 are in the same layer and extend in the same direction. The select line 16 and the data line 13 can be manufactured simultaneously to reduce the number of film layers. In other possible embodiments, the select line 16 and the data line 13 can also be located in different layers, for example, the select line 16 can be manufactured as a separate layer.

[0088] Figure 8 This is a simulation output waveform diagram provided by the embodiment of the present disclosure. Figure 8 As shown, Figure 8 Part (a) shows the output voltage of the data line in the non-refresh area during partial refresh; Figure 8 Part (b) shows the output voltage of the n-th row gate line Gn; Figure 8 Part (c) represents the output voltage of the gate line Gn+1 next to Gn; Figure 8 Part (d) represents the voltage change of pixel p1 corresponding to row Gn on the diagonal line; Figure 8 Part (e) represents the voltage change of pixel p2 which is adjacent to pixel p1.

[0089] Depend on Figure 8 It can be seen that if the design of the gate lead and data lead in the embodiment of the present disclosure is not adopted, the voltage on the data line is affected by the voltage on the corresponding adjacent gate line, and has two fluctuation peaks, and the time when the fluctuation peaks are generated corresponds to the time when the voltage on the corresponding adjacent gate line Gn starts and ends. Here, "correspondingly adjacent" means that the data lead corresponding to the data line is adjacent to the gate lead of the gate line, that is, the voltage signal on the gate line will affect the voltage on the corresponding adjacent data line. Figure 8 As can be seen from part (d), at the moment when the fluctuation peak is generated in part (a), Figure 8 The pixel voltage in part (d) also fluctuates, and the amplitude and sign of the fluctuation are related to the fluctuation peak. Figure 8Parts (c) and (e) of Figure 8 The same applies to parts (b) and (d).

[0090] Table 1 is a table of the corresponding coupling capacitance and the peak value of the fluctuating voltage on the data line when the wiring method in the embodiment of the present disclosure is not adopted / adopted. Figure 9 This is a comparison diagram of voltage fluctuations on the data line and gate line when the wiring method in the embodiment of the present disclosure is not adopted or adopted. Figure 10 As shown, after adopting the wiring method in the embodiment of the present disclosure, the corresponding coupling capacitance can be reduced from 1.0p to 0.5p, a reduction of about 50%, and the peak value of the fluctuating voltage on the data line is reduced from 0.908V to 0.468V, a reduction of about 48%. Therefore, the embodiment of the present disclosure can effectively improve the display defects such as abnormal bright lines caused by large coupling capacitance.

[0091] Table 1. The corresponding coupling capacitance and the peak value of the fluctuating voltage on the data line when the wiring method in the embodiment of the present disclosure is not adopted or adopted.

[0092] Original wiring method Wiring method of the embodiment of the present disclosure Improve the situation Gn row gate line coupling capacitance 1.0p 0.5p 50% reduction Peak voltage fluctuation of the data line 0.908V 0.468V 48% reduction

[0093] Figure 10 Schematic diagram of the cross-sectional structure of a display substrate provided by an embodiment of the present disclosure. Figure 10 As shown, the display substrate includes a base substrate 11 and a driving circuit layer located on the surface of the base substrate 11. The driving circuit layer includes a gate layer 1103, a gate insulating layer 1104, a semiconductor material layer 1105, a source and drain electrode layer 1106, a first passivation layer 1107, an insulating layer 1108, a pixel electrode layer 1109, and a second passivation layer 1110, which are sequentially stacked on the surface of the base substrate 11. Optionally, the pixel electrode layer 1109 includes a plurality of pixel electrodes, each of which is electrically connected to the source and drain electrode layer 1106 through a via.

[0094] Optionally, the base substrate 11 may be a glass substrate or a plastic substrate, etc. Optionally, the semiconductor material layer 1105 may be amorphous silicon, polycrystalline silicon or a metal oxide semiconductor, etc.

[0095] Optionally, the gate insulating layer 1104 may be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0096] Alternatively, the gate layer 1103 may be a single-layer metal film of molybdenum, copper, titanium, or the like, or a sequentially stacked molybdenum layer, aluminum layer, and molybdenum layer, or a sequentially stacked titanium layer, aluminum layer, and titanium layer, or a multi-layer metal film. The source / drain electrode layer 1106 may be a single-layer metal film of molybdenum, copper, titanium, or the like, or a sequentially stacked molybdenum layer, aluminum layer, and molybdenum layer, or a sequentially stacked titanium layer, aluminum layer, and titanium layer, or a multi-layer metal film.

[0097] In the embodiments of the present disclosure, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. For example, when the first pixel electrode 1101 and the second pixel electrode 1102 are formed by performing one or more steps of the same patterning process on the same layer of material, they are in the same layer. The term "same layer" does not always mean that the thickness of the layer or the layer size in a cross-sectional view are the same.

[0098] Figure 11 Schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 11 As shown, the display panel includes a first substrate 1, a second substrate 2 and a plurality of charged particles 3, wherein the plurality of charged particles 3 are located between the first substrate 1 and the second substrate 2. The structure of the first substrate 1 is the same as that of the aforementioned display substrate and will not be repeated here.

[0099] Exemplarily, the second substrate 2 includes a transparent substrate and a common electrode located on one side of the transparent substrate. The common electrode can form an electric field with the pixel electrode layer 1109 of the first substrate 1, and the electric field is used to drive the multiple charged particles to move between the first substrate 1 and the second substrate 2.

[0100] Optionally, the display panel includes a plurality of sub-pixels, each of which includes a microcavity unit, wherein the microcavity unit includes a solvent and a plurality of charged particles 3 moving in the solvent. The plurality of charged particles 3 may include a plurality of black particles and a plurality of white particles, wherein the charge carried by the black particles is opposite in polarity to the charge carried by the white particles. Each pixel electrode belongs to a sub-pixel, and for each sub-pixel, a driving electric field is formed between the pixel electrode of the first substrate 1 and the common electrode of the second substrate 2, and the driving electric field can drive the pigment particles 3 in the corresponding sub-pixel to move toward or away from the second substrate 2.

[0101] When black particles move toward the second substrate 2 and white particles move away from it, the corresponding sub-pixel displays black. When white particles move toward the second substrate 2 and black particles move away from it, the corresponding sub-pixel displays white. By controlling multiple sub-pixels on the display panel to display black or white, the display function of the display panel can be achieved.

[0102] Alternatively, in other embodiments, the charged particles 3 may be other colors, and the second substrate 2 may be a color filter substrate. That is, in addition to the transparent substrate and the common electrode, the second substrate 2 may also include a plurality of color resist blocks. Optionally, the second substrate 2 may also include a black matrix located between the plurality of color resist blocks.

[0103] The present disclosure also provides a display device, which includes Figure 11The display panel shown. The display device may also be called EPD (Electrophoretic Displays, electrophoretic display).

[0104] Optionally, the display device can be any product or component with a display function, such as a laptop computer, a mobile phone, a tablet computer, a television, a monitor, a wearable device, a digital photo frame, a navigator, or the like.

[0105] Figure 12 A method for manufacturing a display substrate provided by an embodiment of the present disclosure is as follows: Figure 12 As shown, the method includes:

[0106] In step S1, a base substrate is provided.

[0107] The base substrate has a display area and a peripheral area, and the peripheral area surrounds the display area.

[0108] In step S2, a plurality of gate lines, a plurality of data lines, a plurality of gate leads and a plurality of data leads are formed on the surface of the base substrate.

[0109] In which, in the display area, multiple gate lines and multiple data lines intersect and define multiple pixel areas, multiple gate leads and multiple data leads are all located in the peripheral area, multiple gate leads and multiple data leads are located in different layers, and multiple gate leads and multiple data leads are alternately arranged in a first direction, multiple gate leads are electrically connected to the multiple gate lines in a one-to-one correspondence, and multiple data lines are electrically connected to the multiple data leads in a one-to-one correspondence; there is at least one first lead among the multiple gate leads and the multiple data leads, the first lead includes M first lead segments, M-1 second lead segments and multiple connecting segments, wherein M is an integer and M is greater than 1, the M first lead segments and M-1 second lead segments are alternately arranged in the second direction, and adjacent first lead segments and second lead segments are connected by a connecting segment, the second direction intersects with the first direction, the M first lead segments are all located between two adjacent second lead segments, and the second lead segments are spaced apart from the first lead segments by at least two second lead segments in the first direction. The first lead is a gate lead, and the second lead is a data lead; or the first lead is a data lead, and the second lead is a gate lead.

[0110] For example, to form Figure 11 For illustration purposes, step S2 may include:

[0111] In the first step, an initial gate material layer is formed on a substrate by deposition, for example. A photoresist structure is then formed through processes such as photoresist coating, exposure, and development. The initial gate material layer is then etched using this photoresist structure as a mask to form a gate layer. The gate layer includes multiple gate lines in the display area and multiple gate leads in the peripheral area. A gate insulating layer is formed on the gate layer by deposition, for example, to cover the gate layer.

[0112] In the second step, an initial semiconductor material layer is formed on the gate insulating layer by, for example, deposition, and a photoresist structure is obtained through processes such as photoresist coating, exposure, and development. The initial semiconductor material layer is etched using the photoresist structure as a mask to form a semiconductor material layer.

[0113] In the third step, an initial source and drain electrode layer is formed on the semiconductor material layer by, for example, deposition. A photoresist structure is obtained through processes such as photoresist coating, exposure, and development. The initial source and drain electrode layer is then etched using the photoresist structure as a mask to form the source and drain electrode layer. The source and drain electrode layer includes multiple data lines and select lines in the display area, as well as multiple data leads in the peripheral area.

[0114] Step 4: Form an initial first passivation layer and an initial insulating layer on the source and drain electrode layers, for example, by deposition. Through a series of processes such as photoresist coating, exposure, etching, and stripping, multiple vias are formed to expose the source and drain electrode layers, thereby obtaining the first passivation layer and the insulating layer.

[0115] Step 5: In the via hole of the exposed source and drain layer obtained by etching in the fourth step, a pixel electrode layer is formed by a series of processes such as deposition, photoresist coating, exposure, etching, and stripping. The pixel electrode layer includes a first pixel electrode and a second pixel electrode located in the display area.

[0116] Step 6: forming a second passivation layer on the pixel electrode layer by, for example, deposition.

[0117] The materials of each layer are as described in the above embodiments and will not be described again here.

[0118] The above are merely optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate includes a base substrate and a plurality of gate lines, a plurality of data lines, a plurality of gate leads and a plurality of data leads located on a surface of the base substrate, wherein the base substrate has a display area and a peripheral area, and the peripheral area surrounds the display area; In the display area, the plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas; The plurality of gate leads and the plurality of data leads are both located in the peripheral area, the plurality of gate leads and the plurality of data leads are located in different layers, and the plurality of gate leads and the plurality of data leads are alternately arranged in a first direction, the plurality of gate leads are electrically connected to the plurality of gate lines in a one-to-one correspondence, and the plurality of data lines are electrically connected to the plurality of data leads in a one-to-one correspondence; At least one first lead line is present among the plurality of gate leads and the plurality of data leads, the first lead line comprising M first lead segments, M-1 second lead segments, and a plurality of connecting segments, wherein M is an integer and is greater than 1, the M first lead segments and the M-1 second lead segments are alternately arranged in a second direction, and adjacent first lead segments and second lead segments are connected by one connecting segment, the second direction intersects the first direction, the M first lead segments are each located between two adjacent second lead lines, and the second lead segment and the first lead segment are spaced apart by at least two second lead lines in the first direction; The first lead is the gate lead, and the second lead is the data lead; or the first lead is the data lead, and the second lead is the gate lead.

2. The display substrate according to claim 1, wherein: For any first lead, two second lead lines adjacent to the M-1 second lead segments are located on the same side of the M first lead segments in the first direction.

3. The display substrate according to claim 2, wherein: The first lead is the gate lead, and two adjacent second lead lines of the first lead segment and two adjacent second lead lines of the second lead segment are four data lead lines continuously adjacent in the first direction; or, The first lead is the data lead, and two adjacent second lead lines in the first lead segment and two adjacent second lead lines in the second lead segment are four gate leads continuously adjacent in the first direction.

4. The display substrate according to claim 1, wherein: For any first lead, two second leads adjacent to a part of the M-1 second lead segments are located on one side of the M first lead segments in the first direction, and two second leads adjacent to another part of the second lead segments in the M-1 second lead segments are located on the other side of the M first lead segments in the first direction, where M is greater than 2.

5. The display substrate according to claim 4, wherein: The first lead is a gate lead, and the two adjacent second lead lines of the M first lead segments and the four adjacent second lead lines of the M-1 second lead segments are six data lead lines continuously adjacent in the first direction; or, The first lead is a data lead, and two adjacent second lead lines of the first lead segment and four adjacent second lead lines of the second lead segment constitute six gate leads that are continuously adjacent in the first direction.

6. The display substrate according to any one of claims 1 to 5, characterized in that The ratio of the total length of the M first lead segments to the total length of the M-1 second lead segments is 0.5-2.

7. The display substrate according to any one of claims 1 to 5, characterized in that The simplest integer ratio of the number of the plurality of gate lines to the number of the plurality of data lines is P:Q, and P<Q; On a side of the peripheral area close to the display area, the plurality of gate leads and the plurality of data leads are divided into a plurality of repeating units, and each of the repeating units includes P gate leads and Q data leads.

8. The display substrate according to claim 7, wherein: P equals 2, Q equals 3; or, P equals 3, Q equals 4.

9. The display substrate according to any one of claims 1 to 5, characterized in that: The orthographic projection of the first lead segment on the surface does not overlap with the orthographic projections of two adjacent second leads on the surface, and the orthographic projection of the second lead segment on the surface does not overlap with the orthographic projections of two adjacent second leads on the surface.

10. The display substrate according to any one of claims 1 to 5, characterized in that The connecting segment is perpendicular to the second lead line located between the first lead line segment and the second lead line segment connected by the connecting segment.

11. The display substrate according to any one of claims 1 to 5, characterized in that The display substrate further includes a plurality of selection lines, which are located in a different layer from the plurality of gate lines. The gate line is connected to the corresponding gate lead through one of the plurality of selection lines.

12. The display substrate according to claim 11, wherein: The gate line is connected to the corresponding selection line through a first via hole, and the first via hole is located in the display area; The selection line is connected to the corresponding gate lead through a second via hole, and the second via hole is located in the peripheral area.

13. The display substrate according to claim 11, wherein: The selection line and the data line are in the same layer and extend in the same direction.

14. A method for manufacturing a display substrate, characterized in that: The method comprises: Providing a base substrate, the base substrate having a display area and a peripheral area, the peripheral area surrounding the display area; forming a plurality of gate lines, a plurality of data lines, a plurality of gate leads and a plurality of data leads on the surface of the base substrate; Wherein, in the display area, the plurality of gate lines and the plurality of data lines intersect and define a plurality of pixel areas, the plurality of gate leads and the plurality of data leads are both located in the peripheral area, the plurality of gate leads and the plurality of data leads are located in different layers, and the plurality of gate leads and the plurality of data leads are alternately arranged in a first direction, the plurality of gate leads are electrically connected to the plurality of gate lines in a one-to-one correspondence, and the plurality of data lines are electrically connected to the plurality of data leads in a one-to-one correspondence; At least one first lead line is present among the plurality of gate leads and the plurality of data leads, the first lead line comprising M first lead segments, M-1 second lead segments, and a plurality of connecting segments, wherein M is an integer and is greater than 1, the M first lead segments and the M-1 second lead segments are alternately arranged in a second direction, and adjacent first lead segments and second lead segments are connected by one connecting segment, the second direction intersects the first direction, the M first lead segments are each located between two adjacent second lead lines, and the second lead segment and the first lead segment are spaced apart by at least two second lead lines in the first direction; The first lead is the gate lead, and the second lead is the data lead; or the first lead is the data lead, and the second lead is the gate lead.

15. A display panel, characterized in that: The display panel includes a first substrate, a second substrate and a plurality of charged particles, wherein the plurality of charged particles are located between the first substrate and the second substrate, the first substrate and the second substrate respectively have electrodes, and the electrodes of the first substrate and the electrodes of the second substrate are used to form an electric field that drives the plurality of charged particles to move between the first substrate and the second substrate, and the first substrate is the display substrate according to any one of claims 1 to 13.

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