Light-emitting chip, semiconductor device, light-emitting device, and image forming and printing apparatus

Abstract

The invention provides a light-emitting chip, a semiconductor device, a light-emitting device, and an imaging printing apparatus. The light-emitting chip comprises a first semiconductor device, the first semiconductor device comprises a first substrate, a plurality of light-emitting elements and a first joint part, the light-emitting elements and the first joint part are arranged on the first substrate, and the first joint part is electrically connected with the light-emitting elements; the second semiconductor device comprises a second substrate, a driving integrated circuit layer and a second joint part, the driving integrated circuit layer and the second joint part are arranged on the second substrate, the driving integrated circuit layer is electrically connected with the second joint part, the first joint part is jointed with the second joint part, and the first joint part is electrically connected with the second joint part. The problem that in the prior art, an LED printing head is low in yield is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of printing equipment, and in particular to a light-emitting chip, a semiconductor device, a light-emitting device, and an imaging printing device. Background Art

[0002] In today's global printing field, electronic photography printing imaging has become the mainstream of office printing, mainly including LED (Light-Emitting Diode) printing, laser printing and inkjet printing. Among them, LED printing, as an emerging dot matrix printing technology, is increasingly favored by users due to its advantages such as fast printing speed, good printing image effect, simple optical path, small size, long service life, energy saving and environmental protection.

[0003] At present, the core key component of conventional LED print heads of LED printers, integrated light-emitting driver IC, mainly includes a substrate and an LED epitaxial film and a driver integrated circuit layer film arranged on the substrate. However, the LED epitaxial film and the driver integrated circuit layer film are formed on their respective substrates, and through thin film transfer and other technologies, the LED epitaxial film and the driver integrated circuit layer film are peeled off from the original substrate and migrated to a fixed position on the substrate. The thin film transfer technology has high requirements for process stability and precision to ensure that the migrated film is evenly combined with the substrate and maintains good conductive properties. Any slight deviation may affect the yield of the LED print head.

[0004] That is to say, the LED print head in the prior art has the problem of low yield. Summary of the invention

[0005] The main purpose of the present invention is to provide a light-emitting chip, a semiconductor device, a light-emitting device, and an imaging printing device to solve the problem of low yield of LED print heads in the prior art.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, there is provided a light-emitting chip, comprising: a first semiconductor device, the first semiconductor device comprising a first substrate, a plurality of light-emitting elements and a first bonding portion arranged on the first substrate, the first bonding portion being electrically connected to the plurality of light-emitting elements; a second semiconductor device, the second semiconductor device comprising a second substrate, a driving integrated circuit layer and a second bonding portion arranged on the second substrate, the driving integrated circuit layer being electrically connected to the second bonding portion, the first bonding portion being bonded to the second bonding portion, and the first bonding portion being electrically connected to the second bonding portion.

[0007] Furthermore, the first bonding portion includes: a plurality of first bonding pads, each of which is electrically connected to the first electrodes of the plurality of light-emitting elements in a one-to-one correspondence; at least one second bonding pad, each of which is electrically connected to the second electrode of at least one light-emitting element, and the first bonding pads and the second bonding pads are abutted against the second bonding portion.

[0008] Furthermore, the first semiconductor device further includes: a plurality of first connection wires, one end of each of the first connection wires is connected to the first bonding pad, and the other end of each of the first connection wires is connected to the first electrode of the light emitting element.

[0009] Furthermore, the first semiconductor device further includes at least one connection terminal, the connection terminal is used to connect to an external signal source, and each connection terminal is electrically connected to each second bonding pad correspondingly.

[0010] Furthermore, the first semiconductor device further includes at least one second connection line, one end of the second connection line is connected to the second bonding pad, and the other end of the second connection line is connected to the connection terminal.

[0011] Furthermore, the plurality of first bonding pads are arranged in an array.

[0012] Furthermore, the driving integrated circuit layer includes multiple light-emitting driving sub-circuits and at least one control processing sub-circuit, and the second bonding portion includes: multiple third bonding pads, the multiple third bonding pads are electrically connected to the output ports of the multiple light-emitting driving sub-circuits one by one, and the multiple third bonding pads are correspondingly abutted with the multiple first bonding pads; at least one fourth bonding pad, at least one control processing sub-circuit is electrically connected to the fourth bonding pad, and each fourth bonding pad is correspondingly abutted with each second bonding pad.

[0013] Furthermore, the first bonding portion also includes a first bonding layer, the first bonding layer surrounds the first bonding pad and the second bonding pad, and the orthographic projection of the first bonding layer on the first substrate is spaced apart from the orthographic projection of the first bonding pad on the first substrate and the orthographic projection of the second bonding pad on the first substrate; the second bonding portion also includes a second bonding layer, the second bonding layer surrounds the first bonding pad and the second bonding pad, and the orthographic projection of the second bonding layer on the second substrate is spaced apart from the orthographic projection of the first bonding pad on the second substrate and the orthographic projection of the second bonding pad on the second substrate, and the first bonding layer abuts the second bonding layer.

[0014] Furthermore, the light-emitting chip satisfies at least one of the following: the first bonding layer and the second bonding layer are metal layers, and the first bonding layer, the second bonding layer and the ground layer are connected; the thickness of the first bonding layer is greater than or equal to 100nm and less than or equal to 200nm; the width of the first bonding layer is greater than or equal to 100um and less than or equal to 200um; the thickness of the second bonding layer is greater than or equal to 100nm and less than or equal to 200nm; the width of the second bonding layer is greater than or equal to 100um and less than or equal to 200um.

[0015] Furthermore, the first semiconductor device also includes a first bonding medium layer, the first bonding medium layer, the first bonding portion and the light emitting element are located on the same side of the first substrate, and a surface of the first bonding portion away from the first substrate is flush with a surface of the first bonding medium layer away from the first substrate.

[0016] Furthermore, the second semiconductor device also includes a second bonding dielectric layer, the second bonding dielectric layer and the second bonding portion are located on the same side of the second substrate, and a surface of the second bonding portion away from the second substrate is flush with a surface of the second bonding dielectric layer away from the second substrate, and the second bonding dielectric layer is in contact with the first bonding dielectric layer.

[0017] Furthermore, the first base substrate has a first bonding area, the orthographic projection of the first bonding portion on the first base substrate is located within the first bonding area, the ratio of the width W2 of the first bonding area to the width W1 of the first base substrate is greater than or equal to 0.3 and less than or equal to 0.5; the ratio of the length L2 of the first bonding area to the length L1 of the first base substrate is greater than or equal to 0.5 and less than or equal to 1.

[0018] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; and the above-mentioned light-emitting chip, wherein the light-emitting chip is arranged on the substrate.

[0019] According to another aspect of the present invention, a light emitting device is provided, comprising the above-mentioned semiconductor device.

[0020] According to another aspect of the present invention, an imaging printing device is provided, comprising the above-mentioned light emitting device.

[0021] Furthermore, the resolution of the imaging printing device is at least 600 DPI.

[0022] Applying the technical solution of the present invention, the light-emitting chip includes a first semiconductor device and a second semiconductor device, the first semiconductor device includes a first substrate, a plurality of light-emitting elements and a first bonding portion arranged on the first substrate, and the first bonding portion is electrically connected to the plurality of light-emitting elements; the second semiconductor device includes a second substrate, a driving integrated circuit layer and a second bonding portion arranged on the second substrate, the driving integrated circuit layer is electrically connected to the second bonding portion, the first bonding portion is bonded to the second bonding portion, and the first bonding portion is electrically connected to the second bonding portion.

[0023] By setting a first joint on the first semiconductor device and a second joint on the second semiconductor device, the first joint is joined with the second joint, the film stripping and migration steps are avoided, and the process complexity in the production process is simplified. This not only reduces the demand for high-end, expensive semiconductor equipment, such as film stripping machines, mass transfer equipment, etc., but also reduces the equipment use cost and maintenance cost. In addition, simplified processes usually mean shorter production cycles and higher production efficiency, thereby further reducing manufacturing costs. Since the first joint and the second joint in the present application are directly joined without the need for mass transfer, physical stress in the mass transfer process is avoided, thereby enhancing the structural stability of the first semiconductor device and the second semiconductor device, reducing internal damage to the chip caused by uneven stress, and effectively improving the yield of the product.

[0024] In addition, the traditional thin film transfer technology will directly affect the connectivity of the interconnection lines and the uniformity of the light emission of the light-emitting element due to the uniformity of the film's combination with the substrate after migration and the height of the steps formed. The technical solution of the present application avoids these potential problems by directly forming a joint between the first semiconductor device and the second semiconductor device, thereby improving the uniformity and consistency of the chip's light emission, reducing the probability of interconnection line short circuit failure, and enhancing the reliability of the chip. In the present application, by directly joining the first semiconductor device and the second semiconductor device, there is no need to peel off the film, which can significantly improve the yield of the light-emitting chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0026] Figure 1 A schematic structural diagram of a light-emitting chip according to an optional embodiment of the present invention is shown;

[0027] Figure 2 Shows Figure 1 A schematic diagram of the internal structure of the first semiconductor device;

[0028] Figure 3 Shows Figure 2 A partial enlarged view of the first semiconductor device;

[0029] Figure 4 Shows Figure 1 an angled view of a second semiconductor device;

[0030] Figure 5 Shows Figure 1 An angled view of the light-emitting chip;

[0031] Figure 6 Shows Figure 1 A schematic diagram of a bonding process between a first semiconductor device and a second semiconductor device;

[0032] Figure 7 Shows Figure 6 A schematic diagram of a structure after the first semiconductor device and the second semiconductor device are bonded together;

[0033] Figure 8 A schematic diagram showing a process of combining a first semiconductor device and a second semiconductor device in another optional embodiment of the present invention is shown;

[0034] Fig. 9 Shows Figure 8 A schematic diagram of a structure after the first semiconductor device and the second semiconductor device are bonded together;

[0035] Fig.10 A schematic structural diagram of a light emitting chip according to another optional embodiment of the present invention is shown;

[0036] Fig.11 A schematic structural diagram of a semiconductor device in an optional embodiment of the present invention is shown;

[0037] Fig.12 A schematic structural diagram of a light emitting device in an optional embodiment of the present invention is shown;

[0038] Fig.13 Shows Fig.12 An angled view of the lens assembly;

[0039] Fig.14 Shows Fig.12 The positional relationship between the lens components and the object and image planes;

[0040] Fig.15 A schematic structural diagram of an imaging printing device in an optional embodiment of the present invention is shown.

[0041] The above drawings include the following reference numerals:

[0042] 10. First semiconductor device; 11. First substrate; 111. First bonding region; 12. Light emitting element; 13. First bonding portion; 131. First bonding pad; 132. Second bonding pad; 133. First bonding layer; 14. First connecting wire; 15. Connecting terminal; 16. Second connecting wire; 17. First bonding dielectric layer; 20. Second semiconductor device; 21. Second substrate; 22. Driver integrated circuit layer; 23. Second bonding portion; 231. Third bonding pad; 232. Fourth bonding pad ; 233, second bonding layer; 24, second bonding medium layer; 25, third connecting line; 30, substrate; 40, light-emitting chip; 50, socket; 100, semiconductor device; 200, frame; 201, first opening; 202, second opening; 300, lens component; 301, support body; 302, cylindrical optical lens; 410, light-emitting device; 420, photosensitive drum; 430, charging roller; 440, toner cartridge; 450, transfer roller; 460, fixing roller; 470, paper receiving component; 480, paper issuing component. DETAILED DESCRIPTION

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meanings as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0045] In the present invention, unless otherwise specified, the directional words used, such as "up, down, top, bottom", usually refer to the directions shown in the drawings, or to the components themselves in the vertical, perpendicular or gravity directions; similarly, for ease of understanding and description, "inside and outside" refer to the inside and outside relative to the outline of each component itself, but the above-mentioned directional words are not used to limit the present invention.

[0046] In order to solve the problem of low yield of LED print heads in the prior art, the present invention provides a light-emitting chip, a semiconductor device, a light-emitting device, and an imaging printing device.

[0047] like Figures 1 to 10As shown, the light-emitting chip 40 includes a first semiconductor device 10 and a second semiconductor device 20. The first semiconductor device 10 includes a first base substrate 11 and a plurality of light-emitting elements 12 and a first bonding portion 13 arranged on the first base substrate 11, and the first bonding portion 13 is electrically connected to the plurality of light-emitting elements 12; the second semiconductor device 20 includes a second base substrate 21 and a driving integrated circuit layer 22 and a second bonding portion 23 arranged on the second base substrate 21, the driving integrated circuit layer 22 is electrically connected to the second bonding portion 23, the first bonding portion 13 is bonded to the second bonding portion 23, and the first bonding portion 13 is electrically connected to the second bonding portion 23.

[0048] By setting a first joint portion 13 on the first semiconductor device 10 and a second joint portion 23 on the second semiconductor device 20, the first joint portion 13 is joined with the second joint portion 23, the film stripping and migration steps are avoided, and the process complexity in the production process is simplified. This not only reduces the demand for high-end, expensive semiconductor equipment, such as film stripping machines, mass transfer equipment, etc., but also reduces the equipment use cost and maintenance cost. In addition, simplified processes usually mean shorter production cycles and higher production efficiency, thereby further reducing manufacturing costs. Since the first joint portion 13 and the second joint portion 23 in the present application are directly joined without the need for mass transfer, physical stress in the mass transfer process is avoided, thereby enhancing the structural stability of the first semiconductor device 10 and the second semiconductor device 20, reducing internal damage to the chip caused by uneven stress, and effectively improving the yield of the product.

[0049] In addition, the traditional thin film transfer technology will directly affect the connectivity of the interconnection line and the uniformity of the light emission of the light-emitting element 12 due to the uniformity of the combination of the thin film with the substrate after migration and the height of the steps formed. The technical solution of the present application avoids these potential problems by directly forming a bond between the first semiconductor device 10 and the second semiconductor device 20, thereby improving the uniformity and consistency of the chip's light emission, reducing the probability of the interconnection line breaking failure, and enhancing the reliability of the chip. In the present application, by directly bonding the first semiconductor device 10 and the second semiconductor device 20, there is no need to peel off the thin film, which can significantly improve the yield of the light-emitting chip 40.

[0050] In some optional embodiments, the first bonding portion 13 and the second bonding portion 23 may be connected by thermal compression bonding or bonding.

[0051] In some optional embodiments, the first substrate 11 has a planarized surface. The first substrate 11 can be made of GaAs, sapphire, SiC and the like. The second substrate 21 has a planarized surface. The second substrate 21 can be made of silicon, or other compound semiconductors, organic semiconductors and insulators such as sapphire and glass.

[0052] In some optional embodiments, the thickness of the first base substrate 11 is greater than or equal to 200um and less than or equal to 400um, while ensuring the structural strength of the first base substrate 11, the thickness of the first base substrate 11 is avoided to be too large, which is not conducive to the miniaturization of the first semiconductor device 10. For example, the thickness of the first base substrate 11 is 300um. The thickness of the second base substrate 21 is greater than or equal to 200um and less than or equal to 400um, while ensuring the structural strength of the second base substrate 21, the thickness of the second base substrate 21 is avoided to be too large, which is not conducive to the miniaturization of the second semiconductor device 20. For example, the thickness of the second base substrate 21 is 300um.

[0053] Optionally, the light emitting element 12 is an LED.

[0054] In some alternative embodiments, see Figures 1 to 4 The light emitting elements 12 may be arranged in a single row, and may be formed by high-density and equidistant arrangement of a plurality of light emitting elements 12 of the same power, and the array density of the light emitting elements 12 may reach a resolution greater than or equal to 600 DPI. In addition, the light emitting elements 12 are not limited to being arranged in a single row, but may also be arranged in a multi-row array, or in a chirping arrangement, which is not specifically limited here.

[0055] In some alternative embodiments, see Figure 2The first bonding portion 13 includes a plurality of first bonding pads 131 and at least one second bonding pad 132, each of which is electrically connected to the first electrodes of the plurality of light-emitting elements 12 in a one-to-one correspondence; each of which is electrically connected to the second electrode of at least one light-emitting element 12, and the first bonding pads 131 and the second bonding pads 132 are in contact with the second bonding portion 23. Through the one-to-one correspondence between the first bonding pads 131 and the first electrodes (usually the control electrode or cathode) of the light-emitting element 12, and the connection between the second bonding pads 132 and the second electrodes (usually the common electrode or anode) of the light-emitting element 12, it is ensured that each light-emitting element 12 can obtain a stable electrical input and output path. This precise electrical pairing reduces interference and attenuation during signal transmission, and enhances the response speed and consistency of light output of the light-emitting element 12. By directly forming the first bonding pads 131 and the second bonding pads 132 on the first semiconductor device 10, complex and expensive steps such as film stripping, transfer and repair are omitted, simplifying the chip manufacturing process. This not only reduces the investment cost of manufacturing equipment, but also reduces losses during the process, improves the yield rate, and ultimately reduces the production cost of a single chip.

[0056] In some alternative embodiments, see Figure 2 and Figure 3 , the first semiconductor device 10 also includes a plurality of first connection wires 14, one end of the first connection wire 14 is connected to the first bonding pad 131, and the other end of the first connection wire 14 is connected to the first electrode of the light-emitting element 12. By using the first connection wire 14, a stable electrical connection can be ensured between the first electrode of the light-emitting element 12 and the first bonding pad 131. The first connection wire 14 can be made of a variety of conductive materials, such as gold, aluminum, copper or palladium, etc. These materials have good conductivity and mechanical strength, can effectively reduce the resistance of the connection and maintain long-term connection stability. Each first connection wire 14 is directly connected to the first electrode of a light-emitting element 12, which can optimize the distribution of current in the array of light-emitting elements 12, ensure that each light-emitting element 12 can obtain the required working current, thereby achieving a uniform light-emitting effect. In particular, in the array of common anode light-emitting elements 12, this connection method can accurately control the driving current of each light-emitting element 12, avoiding the problem of uneven distribution of current among multiple light-emitting elements 12.

[0057] In some optional embodiments, all light-emitting elements 12 may share one second electrode, or several light-emitting elements 12 may share one second electrode, which is not specifically limited here. When the driving current of the light-emitting element 12 needs to be larger, the number of the second bonding pads 132 may be further increased, and the group driving may be performed according to the number of light-emitting elements 12, the effective current of the light-emitting element 12, and the current carrying capacity of the interconnection line. The second electrode may be connected to the second bonding pad 132 through an interconnection line (not shown in the figure), and the current carrying capacity of the interconnection line is greater than the current carrying capacity of the first connection line 14. For example, the current carrying capacity of the interconnection line is N times the current carrying capacity of the first connection line 14, and N is a natural number greater than or equal to 2. For example, the COM electrode is the anode, the control electrode is the cathode, the anode is the second electrode, and the cathode is the first electrode.

[0058] In some optional embodiments, the first connection line 14 is formed inside the first semiconductor device 10, rather than an external lead. For example, the first connection line 14 is a conductive film, and the conductive film can be made of materials including gold, palladium, aluminum, polysilicon, conductive oxide, etc. For another example, the conductive film can be a single-layer film, such as a gold film, or a multi-layer film, such as a multi-layer film having a titanium layer, a platinum layer, and a gold layer, a multi-layer film having a palladium layer and a gold layer, etc. When the first connection line 14 with a thickness of 0.5um and a width of 5um passes through, several milliamperes of current can be provided, and the material, thickness, and width of the first connection line 14 can be designed according to the current demand of the light-emitting element 12. The first connection line 14 is formed by chemical vapor deposition (CVD) or sputtering technology. Of course, the first connection line 14 can also be formed by other processes, and no specific restrictions are made here.

[0059] In some alternative embodiments, see Figure 2 and Figure 3 The first bonding pad 131 is connected to the end of the first connecting wire 14, and the width of the first bonding pad 131 is greater than the width of the first connecting wire 14 to ensure that the first bonding pad 131 is stably connected to the first connecting wire 14. At the same time, the size of the first bonding pad 131 is designed to be larger, which is convenient for reducing the bonding alignment tolerance when the first bonding pad 131 is bonded to the third bonding pad 231, which is beneficial to improving the yield of the product.

[0060] In some optional embodiments, the first bonding pad 131 may be a conductive film. The material of the first bonding pad 131 is the same as the material of the first bonding layer 133 or the material of the first connecting line 14, or may be different materials, as long as there is no mutual diffusion of atoms between different materials to avoid defects in the connection area.

[0061] In some alternative embodiments, see Figure 2 and Figure 3, the first semiconductor device 10 also includes at least one connecting terminal 15, which is used to connect to an external signal source, and each connecting terminal 15 is electrically connected to each second bonding pad 132. The presence of the connecting terminal 15 enables the first semiconductor device 10 to be directly electrically connected to an external signal source (such as a control system, a power supply, etc.) without the need for additional cables or complex wiring structures. This not only simplifies the assembly process of the LED print head, but also provides convenience in the maintenance and upgrading of the equipment, reducing the possibility of connection errors. In addition, since the connecting terminal 15 is directly electrically connected to the second bonding pad 132 on the first semiconductor device 10, and the distance between the connecting terminal 15 and the second bonding pad 132 is relatively close, the signal transmission path is greatly shortened, thereby reducing signal delay, attenuation and interference, and improving the integrity of signal transmission. This is particularly important for LED print heads because it requires high-precision signal transmission to control the accurate lighting of each light-emitting element 12 to achieve high-quality printed images.

[0062] Optionally, the external signal source may include a power signal, a clock signal, a data signal, and other control signals.

[0063] In some alternative embodiments, see Figure 2 and Figure 3 , the first semiconductor device 10 also includes at least one second connecting wire 16, one end of the second connecting wire 16 is connected to the second bonding pad 132, and the other end of the second connecting wire 16 is connected to the connecting terminal 15. By setting the second connecting wire 16, it can be ensured that a stable and efficient electrical connection is established between the array of light-emitting elements 12 and the external circuit. This connection method reduces potential breakpoints in the signal transmission path, enhances the robustness of the electrical connection, and maintains stable performance even under long-term operation or harsh environments. The second connecting wire 16 can be designed to have a higher current carrying capacity. Compared with the first connecting wire 14, the second connecting wire 16 can more effectively distribute large currents and avoid local overheating or electromigration caused by current concentration, thereby improving the thermal stability of the chip and the uniformity of current distribution.

[0064] In some optional embodiments, the first connection lines 14 and the second connection lines 16 are in the same layer, that is, the first connection lines 14 and the second connection lines 16 can be manufactured in the same process step.

[0065] In some optional embodiments, the first bonding pad 131 , the second bonding pad 132 and the connection terminal 15 are located in the same layer, that is, the first bonding pad 131 , the second bonding pad 132 and the connection terminal 15 can be manufactured in the same process step.

[0066] In some alternative embodiments, see Figure 2 and Figure 3 , multiple first bonding pads 131 are arranged in an array. The first bonding pads 131 arranged in an array can ensure that the first electrode of each light-emitting element 12 (such as an LED) has a direct and independent electrical connection point. This design reduces the crossover and interference in the signal transmission path, improves the integrity of the signal and the reliability of the electrical connection, especially in high-resolution print heads, where precise control of each light-emitting element 12 becomes critical. The first bonding pads 131 arranged in an array make the design of the first semiconductor device 10 simpler and easier to package. This design allows a high-density electrical connection to be established between the first semiconductor device 10 and the second semiconductor device 20, reduces the length and complexity of the wires inside the chip, and helps to achieve a more compact chip layout and design.

[0067] In some alternative embodiments, see Figure 4 and Figure 7 The driver integrated circuit layer 22 includes a plurality of light-emitting driving subcircuits and at least one control processing subcircuit. The second bonding portion 23 includes a plurality of third bonding pads 231 and at least one fourth bonding pad 232. The plurality of third bonding pads 231 are electrically connected to the output ports of the plurality of light-emitting driving subcircuits in a one-to-one correspondence, and the plurality of third bonding pads 231 are correspondingly abutted against the plurality of first bonding pads 131; at least one control processing subcircuit is electrically connected to the fourth bonding pad 232, and each fourth bonding pad 232 is correspondingly abutted against each second bonding pad 132. The design of the plurality of light-emitting driving subcircuits enables each light-emitting element 12 to be controlled by an independent driving circuit, which can not only realize the precise adjustment of the brightness of each light-emitting element 12, but also can respond quickly according to the image data and optimize the quality of image printing. Since the light-emitting driving subcircuits correspond to the third bonding pads 231 in a one-to-one correspondence, they are directly electrically connected to the first bonding pads 131 on the first semiconductor device 10, thereby ensuring the rapid transmission and precise control of the signal. By directly abutting the first bonding pad 131 and the third bonding pad 231, the signal reflection and crosstalk that may be generated in the traditional wire bonding or thin film transfer steps are reduced, ensuring the high-quality transmission of the drive signal and enhancing the clarity and contrast of the printed image. The direct electrical connection between the third bonding pad 231 and the first bonding pad 131 forms a direct path for heat conduction, reduces thermal resistance, and helps to quickly dissipate the heat generated by the light-emitting element 12, thereby extending the service life of the light-emitting element 12 and the integrated circuit, and improving the thermal stability during printing. The connection between the control processing subcircuit and the fourth bonding pad 232, as well as the direct abutment with the second bonding pad 132, improves the speed and accuracy of signal processing. This enables the chip to quickly process high-speed data streams to meet the needs of high-resolution print heads, while ensuring accurate conversion and control of image data.

[0068] A plurality of third bonding pads 231 are bonded to a plurality of first bonding pads 131 in correspondence, and each fourth bonding pad 232 is bonded to each second bonding pad 132 in correspondence, and multiple light-emitting elements 12 are driven to emit light through control timing logic and data. The driving integrated circuit layer 22 includes an array driving part, a control timing logic processing part, a data processing part, and a COM part, etc. Each part is interconnected through a plurality of connecting wires, and is electrically connected to the corresponding bonding pads in the first semiconductor device 10 through the connecting wires and their bonding pads. The control timing logic processing part, the data processing part, etc. correspond to the clock signal, data signal and other control signals connected to the first semiconductor device 10, and they are each connected to the corresponding bonding pad through a connecting wire. In particular, the COM part corresponds to the COM pole of the first semiconductor device 10, and it is connected to the corresponding bonding pad through a corresponding connecting wire. In some optional embodiments, at least one second bonding pad 132 is connected to the COM pole of the first semiconductor device 10.

[0069] In some alternative embodiments, see Figure 6 and Figure 7 The first bonding portion 13 also includes a first bonding layer 133, the first bonding layer 133 surrounds the first bonding pad 131 and the second bonding pad 132, and the orthographic projection of the first bonding layer 133 on the first base substrate 11 is spaced apart from the orthographic projection of the first bonding pad 131 on the first base substrate 11 and the orthographic projection of the second bonding pad 132 on the first base substrate 11; the second bonding portion 23 also includes a second bonding layer 233, the second bonding layer 233 surrounds the third bonding pad 231 and the fourth bonding pad 232, and the orthographic projection of the second bonding layer 233 on the second base substrate 21 is spaced apart from the orthographic projection of the first bonding pad 131 on the second base substrate 21 and the orthographic projection of the second bonding pad 132 on the second base substrate 21, and the first bonding layer 133 abuts against the second bonding layer 233. By setting a first bonding layer 133 on the first bonding part 13 and setting a second bonding layer 233 on the second bonding part 23, the first bonding layer 133 and the second bonding layer 233 are bonded to improve the bonding stability between the first bonding part 13 and the second bonding part 23, avoid the risk of disconnection between the first bonding pad 131 and the third bonding pad 231, and between the second bonding pad 132 and the fourth bonding pad 232, and improve the working stability of the light-emitting chip 40.

[0070] In addition, the first bonding layer 133 surrounds the first bonding pad 131 and the second bonding pad 132, and the second bonding layer 233 surrounds the third bonding pad 231 and the fourth bonding pad 232. This surrounding design provides additional protection for the bonding pads, which can prevent the external structure from affecting the bonding between the bonding pads during the bonding process, and can also reduce the risk of pad breakage caused by external force or thermal expansion during bonding and use. This reinforcement effect helps to improve the mechanical stability and durability of the light-emitting chip 40. By introducing the first bonding layer 133 and the second bonding layer 233, the bonding process in the manufacture of the light-emitting chip 40 can be simplified. The presence of the bonding layer allows stable bonding at lower temperatures and pressures, avoiding high temperature or high pressure conditions that may damage the light-emitting chip 40 in the traditional bonding process, and reducing the process difficulty and cost. The spacing between the first bonding layer 133 and the second bonding layer 233 and the bonding pads ensures the isolation between different electrical networks and avoids the occurrence of short circuit failures. This precise electrical isolation is essential for maintaining the normal operation of the complex circuits inside the chip.

[0071] It should be noted that the first bonding layer 133 surrounding the first bonding pad 131 and the second bonding pad 132 may include a variety of situations, the first bonding layer 133 may be connected end to end to form a ring structure, the first bonding pad 131 and the second bonding pad 132 may be surrounded on its inner side, or the first bonding layer 133 may surround a portion of the first bonding pad 131 and the second bonding pad 132, and no specific restrictions are made here. The first bonding layer 133 may be a continuous structure or a discontinuous structure. For example, the first bonding layer 133 has an avoidance interval to avoid the first connecting line 14 to avoid a short circuit between the first connecting line 14 and the first bonding layer 133. The second bonding layer 233 surrounding the third bonding pad 231 and the fourth bonding pad 232 may include a variety of situations, the second bonding layer 233 may be connected end to end to form a ring structure, the third bonding pad 231 and the fourth bonding pad 232 may be surrounded on its inner side, or the second bonding layer 233 may surround a portion of the third bonding pad 231 and the fourth bonding pad 232, and no specific restrictions are made here. The second bonding layer 233 may be a continuous structure or a discontinuous structure. For example, the second bonding layer 233 has an escape gap for escaping the third connection line 25 to avoid a short circuit between the third connection line 25 and the second bonding layer 233 .

[0072] In some optional embodiments, the portion of the first bonding layer 133 corresponding to the first connection line 14 may be an insulating material to avoid a short circuit between the first bonding layer 133 and the first connection line 14. For example, the first bonding layer 133 includes a metal sublayer and an isolation insulating sublayer, and the isolation insulating sublayer is closer to the first connection line 14 than the metal sublayer. In other words, the isolation insulating sublayer is located between the first connection line 14 and the metal sublayer.

[0073] In some optional embodiments, the portion of the second bonding layer 233 corresponding to the third connection line 25 may be an insulating material to avoid a short circuit between the second bonding layer 233 and the third connection line 25. For example, the second bonding layer 233 includes a metal sublayer and an isolation insulating sublayer, and the isolation insulating sublayer is closer to the third connection line 25 than the metal sublayer. In other words, the isolation insulating sublayer is located between the third connection line 25 and the metal sublayer.

[0074] In some optional embodiments, the first bonding layer 133 and the second bonding layer 233 are metal layers, and both the first bonding layer 133 and the second bonding layer 233 are connected to the ground layer; the first bonding layer 133 and the second bonding layer 233 are set as metal layers, so that the structural strength of the first bonding layer 133 and the second bonding layer 233 is increased, and the first bonding layer 133 and the second bonding layer 233 are stably bonded. The metal layer has good thermal conductivity and can be used as part of the heat dissipation path to quickly conduct the heat generated when the chip is working. The connection between the first bonding layer 133, the second bonding layer 233 and the ground layer forms a continuous heat transfer path, which helps to improve the thermal stability of the entire light-emitting chip 40.

[0075] In addition, the first bonding layer 133 and the second bonding layer 233 are connected to the ground layer, which can effectively provide a low-impedance path, reduce the potential difference between components, and avoid chip damage caused by static electricity or voltage fluctuations. At the same time, the first bonding layer 133 and the second bonding layer 233 can serve as an effective electrostatic shielding layer to reduce the impact of external electromagnetic fields on the internal signals of the driver integrated circuit layer, and at the same time, they can also suppress the external radiation of internal signals, protect the chip from interference, and improve the purity and stability of the signal. The setting of the first bonding layer 133 and the second bonding layer 233 can effectively reduce interference during signal transmission, and is suitable for equipment that requires high signal integrity, such as high-resolution printers, high-definition display screens, etc., and can significantly improve the signal transmission quality and printing / display effects of the equipment.

[0076] In some optional embodiments, the first bonding layer 133 and the second bonding layer 233 may be made of materials such as palladium, gold, or palladium-gold.

[0077] In some optional embodiments, the first bonding layer 133 and the second bonding layer 233 can be manufactured using mature and cost-effective processes such as chemical vapor deposition (CVD) and sputtering. Compared with complex processes such as film peeling and transfer, the direct deposition of the metal layer and the connection with the ground layer simplifies the chip production process, reduces manufacturing costs and process difficulty, and improves production yield.

[0078] In some optional embodiments, the first bonding layer 133 , the first bonding pad 131 and the second bonding pad 132 are located in the same layer, that is, the first bonding layer 133 , the first bonding pad 131 and the second bonding pad 132 may be formed in the same process step.

[0079] In some optional embodiments, the second bonding layer 233 , the third bonding pad 231 , and the fourth bonding pad 232 are located in the same layer, that is, the second bonding layer 233 , the third bonding pad 231 , and the fourth bonding pad 232 can be formed in the same process step.

[0080] In some optional embodiments, the thickness of the first bonding layer 133 is greater than or equal to 100nm and less than or equal to 200nm; the width of the first bonding layer 133 is greater than or equal to 100um and less than or equal to 200um; the thickness of the first bonding layer 133 is set between 100nm and 200nm, which can ensure the shielding effect of the first bonding layer 133 on the inner first bonding pad 131 and the second bonding pad 132, and reduce the generation of static electricity. The width of the first bonding layer 133 is set between 100um and 200um, which facilitates the bonding of the first bonding layer 133 with the second bonding layer 233, while avoiding the first bonding layer 133 from occupying too much space, which is not conducive to the miniaturization of the first semiconductor device 10.

[0081] In some optional embodiments, the thickness of the second bonding layer 233 is greater than or equal to 100nm and less than or equal to 200nm; the width of the second bonding layer 233 is greater than or equal to 100um and less than or equal to 200um; the thickness of the second bonding layer 233 is set between 100nm and 200nm, which can ensure the shielding effect of the second bonding layer 233 on the inner third bonding pad 231 and the fourth bonding pad 232, and reduce the generation of static electricity. The width of the second bonding layer 233 is set between 100um and 200um, which facilitates the bonding of the first bonding layer 133 and the second bonding layer 233, while avoiding the first bonding layer 133 from occupying too much space, which is not conducive to the miniaturization of the first semiconductor device 10. Preferably, the width of the first bonding layer 133 is the same as that of the second bonding layer 233.

[0082] In some optional embodiments, the first bonding pad 131 and the second bonding pad 132 are located in the same layer, the first connection line 14 and the second connection line 16 are located in the same layer, and the first bonding pad 131 and the first connection line 14 are located in different layers, and the first connection line 14 is located between the first bonding pad 131 and the first base substrate 11. The thickness of the first bonding layer 133 is the same as the sum of the thickness of the first bonding pad 131 and the thickness of the first connection line 14.

[0083] In some alternative embodiments, see Figure 6 and Figure 7 The second semiconductor device 20 further includes a plurality of third connection wires 25, the two ends of the third connection wires 25 are respectively connected to the light-emitting driving subcircuit and the third bonding pad 231, the third bonding pad 231 and the fourth bonding pad 232 are located in the same layer, and the third bonding pad 231 and the third connection wires 25 are located in different layers, and the third connection wires 25 are located within the driving integrated circuit layer 22 between the third bonding pad 231 and the second base substrate 21. The thickness of the second bonding layer 233 is the same as the sum of the thickness of the third bonding pad 231 and the thickness of the driving integrated circuit layer 22.

[0084] In some optional embodiments, the third connection line 25 is formed inside the second semiconductor device 20, rather than an external lead. For example, the third connection line 25 is a conductive film, which can be made of materials including gold, palladium, aluminum, polysilicon, conductive oxide, etc. For another example, the conductive film can be a single-layer film, such as a gold film, or a multi-layer film, such as a multi-layer film with a titanium layer, a platinum layer, and a gold layer, a multi-layer film with a palladium layer and a gold layer, etc. When the third connection line 25 with a thickness of 0.5um and a width of 5um passes through, several milliamperes of current can be provided. The material, thickness, and width of the third connection line 25 can be designed according to the current demand of the light-emitting element 12. The third connection line 25 is formed by chemical vapor deposition (CVD) or sputtering technology. Of course, the third connection line 25 can also be formed by other processes, which are not specifically limited here.

[0085] In some optional embodiments, the third bonding pad 231 is connected to the end of the third connecting line 25, and the width of the third bonding pad 231 is greater than the width of the third connecting line 25 to ensure that the third bonding pad 231 is stably connected to the third connecting line 25. At the same time, the size of the third bonding pad 231 is designed to be larger to facilitate the bonding alignment tolerance when the first bonding pad 131 and the third bonding pad 231 are bonded, which is beneficial to improving the yield of the product.

[0086] In some optional embodiments, the third bonding pad 231 may be a conductive film. The material of the third bonding pad 231 is the same as the material of the second bonding layer 233 or the material of the third connecting line 25, or may be different materials, as long as there is no mutual diffusion of atoms between different materials to avoid defects in the connection area.

[0087] In some optional embodiments, the thickness of the second bonding layer 233 is greater than or equal to 100nm and less than or equal to 200nm; the width of the second bonding layer 233 is greater than or equal to 100um and less than or equal to 200um. Setting the thickness of the second bonding layer 233 between 100nm and 200nm can ensure the shielding effect of the second bonding layer 233 on the inner third bonding pad 231 and the fourth bonding pad 232, and reduce the generation of static electricity. Setting the width of the second bonding layer 233 between 100um and 200um can facilitate the bonding between the first bonding layer 133 and the second bonding layer 233, while avoiding the second bonding layer 233 from occupying too much space, which is not conducive to the miniaturization of the second semiconductor device 20.

[0088] In some optional embodiments, the first semiconductor device 10 further includes a first bonding dielectric layer 17, and the first bonding dielectric layer 17, the first bonding portion 13 and the light emitting element 12 are located on the same side of the first substrate 11, and the surface of the first bonding portion 13 away from the first substrate 11 is flush with the surface of the first bonding dielectric layer 17 away from the first substrate 11. By providing the first bonding dielectric layer 17 and the first bonding dielectric layer 17 being flush with the first bonding portion 13, it is convenient to bond the first semiconductor device 10 with the second semiconductor device 20, and the bonding difficulty of the two is effectively reduced. In addition, the first bonding dielectric layer 17 can also isolate multiple electrical structures inside the first bonding portion 13, which helps to reduce electromagnetic interference between signals. At the same time, the first bonding dielectric layer 17 can also protect the structure between it and the first substrate 11, reducing damage to the internal structure during bonding and other processes.

[0089] In some optional embodiments, the first bonding dielectric layer 17 is an insulating layer to prevent short circuits between electrical structures in the first semiconductor device 10 .

[0090] In some optional embodiments, the first bonding medium layer 17 is a light-transmitting layer, and the first bonding medium layer 17 is located and covers the light-emitting element 12 to ensure that the light emitted by the light-emitting element 12 can be emitted from the first bonding medium layer 17 .

[0091] In some other optional embodiments, the first bonding medium layer 17 has a plurality of through holes, and the plurality of light emitting elements 12 are located at the plurality of through holes to ensure that the light emitted by the light emitting elements 12 can be emitted. In this embodiment, the first bonding medium layer 17 can be a light-transmitting layer or a non-light-transmitting layer.

[0092] In some alternative embodiments, see Figures 6 to 9, the second semiconductor device 20 also includes a second bonding dielectric layer 24, the second bonding dielectric layer 24 and the second bonding portion 23 are located on the same side of the second substrate 21, and the side surface of the second bonding portion 23 away from the second substrate 21 is flush with the side surface of the second bonding dielectric layer 24 away from the second substrate 21, and the second bonding dielectric layer 24 is in contact with the first bonding dielectric layer 17. By providing the second bonding dielectric layer 24, and the second bonding dielectric layer 24 is flush with the second bonding portion 23, it is convenient to bond the first semiconductor device 10 and the second semiconductor device 20, and the bonding difficulty of the two is effectively reduced. In addition, the second bonding dielectric layer 24 can also isolate multiple electrical structures inside the second bonding portion 23, which helps to reduce electromagnetic interference between signals. At the same time, the second bonding dielectric layer 24 can also protect the structure between it and the second substrate 21, reducing damage to the internal structure during bonding and other processes.

[0093] In some alternative embodiments, see Figure 2 and Figure 3 The first base substrate 11 has a first bonding area 111, the orthographic projection of the first bonding portion 13 on the first base substrate 11 is located in the first bonding area 111, the ratio of the width W2 of the first bonding area 111 to the width W1 of the first base substrate 11 is greater than or equal to 0.3 and less than or equal to 0.5; the ratio of the length L2 of the first bonding area 111 to the length L1 of the first base substrate 11 is greater than or equal to 0.5 and less than or equal to 1. This facilitates the optimization of the positional relationship between the first bonding area 111 and the light emitting element 12, which is conducive to a more compact structure of the first semiconductor device 10 and a reduction in the size of the first semiconductor device 10. The compact design not only reduces the size of the device, but also reduces the energy consumption of the device and improves the energy efficiency of the device. For a portable printer, this design can make the device lighter and easier to carry. At the same time, the highly integrated design also prolongs the battery life of the device and improves the practicality of the device.

[0094] In some optional embodiments, the width W1 of the first base substrate 11 is greater than or equal to 1.5 mm and less than or equal to 2.52 mm, and the length L1 of the first base substrate 11 is greater than or equal to 9 mm and less than or equal to 15 mm. This configuration is conducive to the miniaturization of the first semiconductor device 10. For example, the width W1 of the first base substrate 11 is 2 mm, and the length L1 is 10.8288 mm.

[0095] In some optional embodiments, the width W2 of the first bonding area 111 is greater than or equal to 0.6 mm and less than or equal to 1 mm, and the length L2 of the first bonding area 111 is greater than or equal to 6 mm and less than or equal to 13 mm. For example, the width W2 of the first bonding area 111 is 0.8 mm, and the length L2 is 7.84 mm.

[0096] In some optional embodiments, the minimum distance D between the light-emitting element 12 and the side of the first substrate 11 is greater than or equal to 3um and less than or equal to 5um, which ensures the miniaturization of the first semiconductor device 10 and avoids the influence of the external structure on the light-emitting element 12, while effectively ensuring the spacing between the two light-emitting elements 12 next to each other after the subsequent two light-emitting chips are installed and spliced ​​in a straight line.

[0097] In some optional embodiments, the width of the first connecting line 14 is greater than or equal to 3um and less than or equal to 8um, and the thickness of the first connecting line 14 is greater than or equal to 0.3um and less than or equal to 0.8um, so as to ensure the current carrying capacity of the first connecting line 14 while reducing the size of the first connecting line 14.

[0098] In some optional embodiments, the area of ​​the first bonding pad 131 is smaller than the area of ​​the second bonding pad 132 to ensure the current carrying capacity of the second bonding pad 132. For example, the size of the first bonding pad 131 is greater than or equal to 50um*60um and less than or equal to 70um*90um. For example, the size of the second bonding pad 132 is greater than or equal to 60um*80um and less than or equal to 90um*120um.

[0099] After the second semiconductor device 20 is bonded to the first semiconductor device 10 , the second semiconductor device 20 is located in the first bonding region 111 . The size of the second semiconductor device 20 is the same as the size of the first bonding region 111 , which is not further limited herein.

[0100] In a specific embodiment, the width W1 of the first base substrate 11 is 2 mm, and the length L1 is 10.8288 mm. The width W2 of the first bonding area 111 is 0.8 mm, and the length L2 is 7.84 mm. The number of light-emitting elements 12 on the first base substrate 11 is 256, and the width W3 of the light-emitting element 12 is 22.3 um, the height H is 40 um, and the arrangement period T is 42.3 um, reaching 600 DPI. The minimum distance D between the light emitting element 12 and the first substrate 11 is 5um; the width of the first connecting wire 14 is preferably 5um wide and 0.5um thick, and the closest wiring spacing of the first connecting wire 14 is 5um; the size of the first bonding pad 131 is 60um*80um, and the number of the first bonding pads 131 corresponds to the number of the light emitting elements 12, which is 256; the size of the second bonding pad 132 is 80um*100um, and the number can be 20; further, the number of the connecting terminals 15 corresponds to the second bonding pad 132, which is 20, and the size of the connecting terminals 15 can be 80um*100um. The width and length of the second substrate 21 are the same as the width and length of the first bonding area 111, and the size of the third connecting wire 25 inside the second semiconductor device 20 is the same as the size of the first connecting wire 14, the size and number of the third bonding pad 231 are the same as the first bonding pad 131, and the size and number of the fourth bonding pad 232 are the same as the second bonding pad 132.

[0101] Preferably, the first semiconductor device 10 and the second semiconductor device 20 are bonded and abutted against each other using the same material.

[0102] When the first semiconductor device 10 is joined with the second semiconductor device 20 , the second semiconductor device 20 can be placed upside down, joined with the second joining portion 23 through the first joining portion 13 to achieve electrical connection, and an ohmic contact or a contact with a relatively low resistivity is formed at the joining pad to form the light-emitting chip 40 .

[0103] During the bonding process, after using a conventional bonding process, in order to ensure the bonding strength, a sintering process may be performed, such as sintering at 250 degrees Celsius, so that a high-strength structural connection is formed between the bonding layer and the bonding pad. At the same time, sintering can reduce the contact resistance between the bonding pads to a certain extent.

[0104] The above-mentioned technical solution of the present application mainly provides a light-emitting chip 40, whose manufacturing process does not involve the stripping and migration of thin films, avoids the need for existing integrated chip thin film transfer technology and mass migration technology, reduces the need for the use of many expensive semiconductor manufacturing equipment such as thin film stripping, mass transfer, thin film migration, and repair, reduces the high stability and high precision process requirements required for migration, simplifies the process manufacturing process and difficulty, reduces the manufacturing cost of the light-emitting chip 40, and improves the light emission uniformity, reliability and other performance of the light-emitting chip 40.

[0105] In some optional embodiments, such as Figure 8 and Fig. 9 In the embodiment shown, the first joint portion 13 does not have the first joint layer 133, but only has the first joint pad 131 and the second joint pad 132, and the second joint portion 23 does not have the second joint layer 233, but only has the third joint pad 231 and the fourth joint pad 232. The surfaces of the first semiconductor device 10 and the second semiconductor device 20 are treated by appropriate chemical methods to remove contaminants and provide a planarized surface, such as planarized to the order of ≤2nm or higher atomic layer, for example, the first joint medium layer 17 is flush with the surface of the first joint pad 131 and the second joint pad 132 away from the first substrate 11, and the second joint medium layer 24 is flush with the surface of the third joint pad 231 and the fourth joint pad 232 away from the second substrate 21. Thereafter, the two surfaces are placed in close contact and bonded together by heating and pressurizing, and objects of the same material are in close contact. At the same time, the bonding pads also form an ohmic contact with a lower resistivity. At this time, in order to obtain effective and firm bonding, although the heating temperature is higher than the bonding temperature of the aforementioned bonding layer, the growth process of the bonding layer is omitted at this time, and the problems caused by bonding defects of the bonding layer are also avoided.

[0106] In some optional embodiments, such as Figure 1 In the illustrated embodiment, the length of the second semiconductor device 20 is smaller than that of the first semiconductor device 10 . This arrangement can reduce the use of materials and lower costs.

[0107] In some optional embodiments, such as Fig.10 In the embodiment shown, the length of the second semiconductor device 20 can be the same as that of the first semiconductor device 10, and the length of the first bonding area 111 is the same as that of the first substrate 11. This arrangement can effectively avoid defects caused by different local stresses due to the inconsistent lengths of the first semiconductor device 10 and the second semiconductor device 20, which may further lead to internal damage. At the same time, this arrangement will lead to an increase in raw material costs, and can be designed according to specific usage requirements.

[0108] like Fig.11As shown, the semiconductor device 100 includes a substrate 30 and the above-mentioned light-emitting chip 40, and the light-emitting chip 40 is arranged on the substrate 30. A socket 50 can be installed on the substrate 30, and the socket 50 serves as an interface for the substrate 30 to communicate with the outside to obtain signals such as power signals, clock signals, data signals and other control signals required for the normal operation of the semiconductor device 100. The substrate 30 can be a rectangular substrate with a printed circuit printed with a circuit pattern such as a ceramic substrate, PCB or glass. In particular, the substrate 30 contains binding pads electrically connected to the connection terminals 15 of the light-emitting chip 40, and these binding pads are simultaneously connected to different circuit networks on the substrate 30. In addition, the substrate can also preferably include other resistors, capacitors, storage chips, ESD chips, operational amplifier chips, etc. necessary for the operation of the semiconductor device 100.

[0109] like Fig.11 As shown, a plurality of light-emitting chips 40 can be pasted on the same substrate 30, and the plurality of light-emitting chips 40 can be installed in a straight line along the length direction of the substrate 30 by using adhesive such as adhesive tape, and the spacing between two adjacent light-emitting chips 40 is greater than or equal to 8um and less than or equal to 12um, so as to ensure that the distance between two adjacent light-emitting elements 12 in two adjacent light-emitting chips 40 is greater than or equal to 38um and less than or equal to 44um, further ensuring that the resolution of the semiconductor device 100 can reach 600DPI.

[0110] The connection terminals 15 of the light emitting chip 40 are bonded to the substrate 30 by gold wire bonding and are electrically connected to the corresponding bonding pads, so that the circuit network on the substrate 30 is connected to the circuit inside the light emitting chip 40 to provide various signals required for the normal operation of the light emitting chip 40.

[0111] The number of light emitting chips 40 attached to the semiconductor device 100 must be an integer, and the length of the semiconductor device 100 is not specifically limited. The arrangement of the plurality of light emitting chips 40 is not limited to a single-row straight-line arrangement, but may also be a multi-row arrangement, a chirping arrangement, or any other arrangement, which may be designed according to actual needs.

[0112] like Fig.12As shown, the light emitting device 410 includes the semiconductor device 100 described above. The light emitting device 410 having the semiconductor device 100 described above has high resolution. The light emitting device 410 is, for example, an LED print head. The light emitting device 410 includes a frame 200 and a lens component 300, wherein the frame 200 plays a supporting role, the frame 200 has a receiving cavity and a first opening 201 and a second opening 202 connected to the receiving cavity, the first opening 201 and the second opening 202 are arranged opposite to each other, and the area of ​​the first opening 201 is smaller than the area of ​​the second opening 202, the semiconductor device 100 is arranged in the receiving cavity and located at the second opening 202, the lens component 300 is located at the first opening 201, and the light emitted by the semiconductor device 100 is emitted through the lens component 300. The frame 200 preferably uses a material with excellent heat dissipation performance to prevent the performance from being degraded due to poor heat dissipation and excessive temperature during normal light emitting operation.

[0113] Fig.13 The front view of the lens component 300 is shown, which is also called a self-focusing lens or a radial variable refractive index lens, and mainly includes a side support 301 and a cylindrical optical lens 302. The main function of the lens component 300 is the cylindrical optical lens 302, whose refractive index distribution is gradually changed along the radial direction and has focusing and imaging functions. The cylindrical optical lenses 302 are preferably arranged in 2 rows, and can also be arranged in 1 row, 3 rows, 4 rows, etc.

[0114] like Fig.14 As shown, there are focal positions on both sides of the cylindrical optical lens 302. The "object plane" mark is the first focal position, which corresponds to the light-emitting surface of the array light-emitting element 12 inside the cavity, that is, the surface of the first semiconductor device 10. The length of the focal position determines the distance between the light-emitting chip 40 and the lower surface of the lens component 300. The "image plane" mark is the second focal position, that is, the image plane position on the other side of the cylindrical optical lens 302. This distance determines the position of the surface exposure of the photosensitive drum when the printer is subsequently assembled. The light emitted by the light-emitting chip 40 will be imaged on the surface of the photosensitive drum of the printer after being imaged upright by the lens component 300, so as to form a latent image by exposing the surface of the photosensitive drum.

[0115] Preferably, the length of the light emitting device 410 is the same as that of the semiconductor device 100, and is determined by the specific parameters and functions of the printing format of the light emitting device 410. The light emitting chip 40 is a key component of the light emitting device 410, and its cost determines the price of the light emitting device 410.

[0116] like Fig.15 As shown, the imaging printing device includes the above-mentioned light emitting device 410. The imaging printing device can be a printer.

[0117] Fig.15The present invention is a schematic diagram of the structure of an imaging printing device, which mainly includes the above-mentioned light-emitting device 410, a photosensitive drum 420, a charging roller 430, a toner cartridge 440, a transfer roller 450, a fixing roller 460, a paper receiving member 470 and a paper sending member 480. A layer of photosensitive semiconductor material, such as selenium, is coated on the surface of the photosensitive drum 420. The photosensitive semiconductor material is an insulator when it is not exposed to light, and it becomes a conductor when it encounters light. When printing, the photosensitive drum 420 rotates at a constant speed. First, a high voltage is generated by a high-voltage circuit, and the surface of the photosensitive drum 420 is charged through the charging roller 430, so that the surface of the photosensitive drum 420 is evenly charged. After the photosensitive drum 420 is irradiated by the light of the light-emitting device 410, the charge of the irradiated part disappears, while the non-irradiated part remains charged. The light emitted by the light-emitting device 410 is modulated according to the image data received by the imaging printing device, so that a latent image is formed on the surface of the photosensitive drum 420. The toner in the toner cartridge 440 is charged with the same polarity as the photosensitive drum 420. When the photosensitive drum 420 passes through the toner cartridge 440, according to the principle that like charges repel and opposite charges attract, the toner in the toner cartridge 440 will be adsorbed on the light-irradiated part of the photosensitive drum 420, while the unirradiated part will not be attached with toner, so that the image is developed. When the inked photosensitive drum 420 rotates to the paper surface, the toner is transferred to the paper because the transfer roller 450 with opposite charges is under the paper. After being heated by the fixing roller 460, the toner melts and penetrates into the printing paper to form a stable image. Among them, the light-emitting device 410 is a key component of the imaging printing device, and the light-emitting device 410 is an important component of the production cost of the imaging printing device.

[0118] From the above, it can be seen that by utilizing the technical solution of the present application, compared with the light-emitting device 410 including the existing conventional semiconductor composite chip, the present application reduces the complexity of the semiconductor chip manufacturing process, saves the manufacturing process cost of the light-emitting device 410, and further reduces the production cost of the imaging printing equipment.

[0119] Specifically, the resolution of the imaging printing device reaches 600 DPI. Further, by using multiple rows of light emitting elements 12 arranged in a plover pattern or installing the light emitting chips 40 in a plover pattern and further encrypting the light emitting elements 12, a resolution of 1200 DPI or higher can be achieved. The imaging printing device having the above-mentioned light emitting device 410 has good resolution.

[0120] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0121] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0122] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0123] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A light-emitting chip, characterized in that: include: A first semiconductor device (10), comprising a first substrate (11), a plurality of light-emitting elements (12) and a first bonding portion (13) arranged on the first substrate (11), wherein the first bonding portion (13) is electrically connected to the plurality of light-emitting elements (12); A second semiconductor device (20), the second semiconductor device (20) comprising a second base substrate (21) and a driving integrated circuit layer (22) and a second bonding portion (23) arranged on the second base substrate (21), the driving integrated circuit layer (22) being electrically connected to the second bonding portion (23), the first bonding portion (13) being bonded to the second bonding portion (23), and the first bonding portion (13) being electrically connected to the second bonding portion (23).

2. The light-emitting chip according to claim 1, characterized in that: The first engaging portion (13) comprises: A plurality of first bonding pads (131), each of the first bonding pads (131) being electrically connected to a first electrode of a plurality of the light-emitting elements (12) in a one-to-one correspondence; At least one second bonding pad (132), each of the second bonding pads (132) is electrically connected to the second electrode of at least one of the light-emitting elements (12), and the first bonding pad (131) and the second bonding pad (132) are in contact with the second bonding portion (23).

3. The light-emitting chip according to claim 2, characterized in that: The first semiconductor device (10) further comprises: A plurality of first connection wires (14), one end of each of the first connection wires (14) being connected to the first bonding pad (131), and the other end of each of the first connection wires (14) being connected to the first electrode of the light emitting element (12).

4. The light-emitting chip according to claim 2, characterized in that: The first semiconductor device (10) further comprises at least one connection terminal (15), wherein the connection terminal (15) is used to connect to an external signal source, and each of the connection terminals (15) is electrically connected to each of the second bonding pads (132) accordingly.

5. The light emitting chip according to claim 4, characterized in that: The first semiconductor device (10) further comprises at least one second connection wire (16), one end of the second connection wire (16) being connected to the second bonding pad (132), and the other end of the second connection wire (16) being connected to the connection terminal (15).

6. The light emitting chip according to claim 2, characterized in that: A plurality of the first bonding pads (131) are arranged in an array.

7. The light-emitting chip according to claim 2, characterized in that: The driving integrated circuit layer (22) comprises a plurality of light-emitting driving sub-circuits and at least one control processing sub-circuit, and the second joint portion (23) comprises: A plurality of third bonding pads (231), the plurality of third bonding pads (231) being electrically connected to the output ports of the plurality of light-emitting drive sub-circuits in a one-to-one correspondence, and the plurality of third bonding pads (231) being abutted against the plurality of first bonding pads (131) in a corresponding manner; At least one fourth bonding pad (232), at least one of the control processing sub-circuit is electrically connected to the fourth bonding pad (232), and each of the fourth bonding pads (232) is correspondingly abutted against each of the second bonding pads (132).

8. The light emitting chip according to claim 7, characterized in that: The first bonding portion (13) further comprises a first bonding layer (133), the first bonding layer (133) surrounds the first bonding pad (131) and the second bonding pad (132), and an orthographic projection of the first bonding layer (133) on the first base substrate (11) is arranged at an interval from an orthographic projection of the first bonding pad (131) on the first base substrate (11) and an orthographic projection of the second bonding pad (132) on the first base substrate (11); The second bonding portion (23) further comprises a second bonding layer (233), wherein the second bonding layer (233) surrounds the first bonding pad (131) and the second bonding pad (132), and an orthographic projection of the second bonding layer (233) on the second base substrate (21) is spaced from an orthographic projection of the first bonding pad (131) on the second base substrate (21) and an orthographic projection of the second bonding pad (132) on the second base substrate (21), and the first bonding layer (133) abuts against the second bonding layer (233).

9. The light emitting chip according to claim 8, characterized in that: The light-emitting chip (40) satisfies at least one of the following conditions: The first bonding layer (133) and the second bonding layer (233) are metal layers, and the first bonding layer (133) and the second bonding layer (233) are connected to a ground layer; The thickness of the first bonding layer (133) is greater than or equal to 100 nm and less than or equal to 200 nm; The width of the first bonding layer (133) is greater than or equal to 100 um and less than or equal to 200 um; The thickness of the second bonding layer (233) is greater than or equal to 100 nm and less than or equal to 200 nm; The width of the second bonding layer (233) is greater than or equal to 100 um and less than or equal to 200 um.

10. The light emitting chip according to any one of claims 1 to 9, characterized in that: The first semiconductor device (10) further comprises a first bonding medium layer (17); the first bonding medium layer (17), the first bonding portion (13) and the light emitting element (12) are located on the same side of the first substrate (11); and a surface of a side of the first bonding portion (13) away from the first substrate (11) is flush with a surface of a side of the first bonding medium layer (17) away from the first substrate (11).

11. The light-emitting chip according to claim 10, characterized in that: The second semiconductor device (20) further comprises a second bonding dielectric layer (24), wherein the second bonding dielectric layer (24) and the second bonding portion (23) are located on the same side of the second base substrate (21), and a surface of the second bonding portion (23) on a side away from the second base substrate (21) is flush with a surface of the second bonding dielectric layer (24) on a side away from the second base substrate (21), and the second bonding dielectric layer (24) is in contact with the first bonding dielectric layer (17).

12. The light-emitting chip according to any one of claims 1 to 9, characterized in that: The first base substrate (11) has a first bonding area (111), and the orthographic projection of the first bonding portion (13) on the first base substrate (11) is located in the first bonding area (111). The ratio of the width W2 of the first bonding area (111) to the width W1 of the first base substrate (11) is greater than or equal to 0.3 and less than or equal to 0.5; A ratio of a length L2 of the first bonding area (111) to a length L1 of the first base substrate (11) is greater than or equal to 0.5 and less than or equal to 1.

13. A semiconductor device, characterized in that: include: substrate(30); At least one light emitting chip (40) according to any one of claims 1 to 12, the light emitting chip (40) being arranged on the substrate (30).

14. A light emitting device, characterized in that: A semiconductor device (100) comprising the semiconductor device (100) according to claim 13.

15. An imaging printing device, characterized in that: It comprises the light emitting device (410) as claimed in claim 14.

16. The imaging printing device according to claim 15, characterized in that: The resolution of the imaging printing device is at least 600 DPI.

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