Method for measuring temperature or thermal resistance and monitoring thermal resistance

Abstract

A method for measuring temperature in a power electronic system comprising at least one power unit (PU) comprising at least one semiconductor switch (S) having a die connected to a heat sink (HS, 5) via a stack of m layers of material Mi, i = 1, 2... m, and wherein the at least one semiconductor switch is thermally connected in parallel with a heat source (10) via a connecting layer Mj of the stacked material layers Mi, the method comprising: providing a limited current in the at least one semiconductor switch (S) when the at least one semiconductor switch (S) is in an open state such that it does not dissipate heat, the limited current is adapted to measure a first temperature T1 of the at least one semiconductor switch using a thermosensitive parameter of the at least one semiconductor switch in the open circuit state; and calculating the temperature TMj of the connecting layer Mj to be equal to the first temperature T1.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronic systems having power semiconductors, more precisely power switching semiconductors, and to a method for monitoring thermal resistance in such power electronic systems. Background Art

[0002] In order to achieve higher current density in power modules, as an alternative to increasing the die area of ​​such modules, multi-die power module architectures are increasingly being adopted, in which several semiconductor dies are electrically connected in parallel and perform the same function of a single switch. In the prior art, the life of a power module is limited by the temperature swing of the semiconductor junction during the mission distribution. The classic wear mechanism is caused by mechanical stresses between different layers of the power module caused by thermal cycles and thermal expansion coefficient (CTE) mismatch. These mechanical deformations and excessive strains applied at the interfaces of different materials can cause the power module to deteriorate or even fail due to the formation of cracks and / or voids. In addition, for given load conditions, degradation of the layer between the semiconductor and the cooling system (such as a heat sink) leads to an increase in thermal resistance and, therefore, an increase in the amplitude of the temperature swing. The most critical failure mechanism involves the electrical interconnect package closest to the semiconductor die, and is wire bond fall-off and die attachment degradation, in particular due to delamination of Sn-based solder or Ag-based sintered layers. Literature discussing these issues is, for example:

[0003] N. Degrenne, J. Ewanchuk, E. David, R. Bolddrjew, and S. Mollov, “A Review of Power Diagnostics and Health Management,” Annual Meeting of the Diagnostics and Health Management Society, (2015) 1-11;

[0004] Mauro Ciappa, “Typical failure mechanisms of modern power modules,” Microelectronics Reliability, 42 (2002) 653-667;

[0005] Pichon and J. Brandeleo, “Relative importance of solder and wire bond defects at maximum junction temperature of IGBT devices,” Microelectronics Reliability, 126 (2021) 114250.

[0006] In this context, there is a high technical value in monitoring the health of these layers and assessing the remaining lifetime of the power module before the module actually fails. Specifically, online condition monitoring of the die attach layer is a key technology for monitoring degradation levels, avoiding failures, planning maintenance, and developing strategies to extend the lifetime of the power module based on this monitoring.

[0007] There are some test methods, and document CN103175861A discloses a junction-case thermal resistance test method, document CN103792476A relates to a thermal resistance measurement method for semiconductor devices, document EP0708327B1 relates to a method and apparatus for thermal impedance evaluation of packaged semiconductor components, document US7,356,441B2 relates to a junction temperature prediction method and apparatus for a power conversion module, and document CN107219016A provides a method and system for calculating the transient junction temperature of an IGBT module.

[0008] Thermal impedance is defined as Zth j-ref =(T(t)-T ref ) / Pdiss; where Pdiss is the change in dissipated power, T(t) is the temperature response of the device to this power change, and Tref is the reference temperature, such as the heat sink temperature THS or the cooling fluid temperature TCF or the cooling device temperature TCM. Thermal resistance is defined as Rth j-ref =lim(Zth)(t->∞).

[0009] In the prior art, different techniques are used to measure and monitor the degradation level of the packaging layer based on thermal impedance measurement:

[0010] - Utilize thermistors, i.e. calibrated temperature-sensitive resistors, which are usually built into classic power modules, thermally connected to the ceramic isolation plate of the semiconductor die and electrically connected to the terminals of the power module. These devices allow the temperature of the ceramic plate to be monitored during the lifetime of the module. By monitoring the temperature evolution at the location of the device, the changes in the thermal impedance between the heat sink and the module can be monitored.

[0011] - the temperature of the semiconductor die is measured during the operation of such semiconductors using several thermally sensitive electrical parameters (TSEP). TSEP is a temperature-sensitive electrical parameter of the semiconductor that can be calibrated and can therefore give information about the semiconductor temperature. Thus, information on the thermal resistance between the semiconductor and the heat sink can be extracted during the lifetime of the module, as long as the power dissipated in the semiconductor Pdiss is known;

[0012] -Through thermal impedance measurement technology, which is a transient thermal response technology that can give information about the degradation of different interfaces of the power module. This technology usually includes:

[0013] First, a startup steady-state thermal condition is imposed on the power module using semiconductor switches as active devices. The startup condition can be a zero power condition, or a condition where a recorded constant power is dissipated at the semiconductor.

[0014] Secondly, a controlled power step increase (in case the start-up condition is a zero power condition) or a power step decrease (in case the start-up condition is a constant power condition) is applied and the power variation and then the evolution of the semiconductor temperature is recorded until a new steady-state thermal condition is reached.

[0015] Finally, the temperature transient behavior of the recordings is described by using an equivalent Foster or Cauer network representing the thermal structure of the power module with several RC elements. Fitting the temperature transients using the Foster equation allows to extract the resistance and capacitance of the different parts of the power module, giving information on the evolution of thermal resistance and capacitance.

[0016] These techniques are particularly sensitive to solder attachment and degradation of the different layers constituting the power module.Typically, thermal impedance measurements are mainly performed under offline conditions by mounting the device in a measurement test bench and by controlling the load, measuring the dissipated power in the device and measuring the temperature transients using dedicated sensors.

[0017] Several experiments have been reported in the literature that demonstrated a clear correlation between solder layer degradation and the evolution of thermal transient behavior after power cycling of power modules.

[0018] Existing transient thermal techniques (e.g., thermal impedance ZTH) are difficult to implement in the online operation of power modules because of the difficulty in measuring cooling / heating transient temperatures at a sufficiently high data acquisition rate during the operation of the power devices, and to measure thermal impedance, the power dissipation of each device must be controlled and known, especially in the case of multi-chip power modules, because the current is shared between different parallel-interconnected dies, further increasing the measurement difficulty.

[0019] Available online TSEP monitoring technology allows real-time monitoring of semiconductor die temperature and can detect semiconductor and heat sink Rth j-HS The increase in thermal resistance between the two devices is sufficient as long as similar power dissipation conditions can be reproduced during the measurement. j-HS Knowledge of does not allow distinguishing which layer or interface has the greatest degree of degradation in the package stack.

[0020] The thermistor is usually thermally connected to an intermediate layer of the power module package stack, usually thermally connected to a ceramic isolation board, and the monitoring of its evolution together with the evolution of the semiconductor die thermally connected to the same ceramic isolation board (i.e., a copper-ceramic substrate corresponding to a DBC direct bond of copper and ceramic) makes it possible in principle to distinguish the junction Rth j-DBC Thermal resistance or junction heat sink and heat sink Rth DBC-HSWhich of the thermal resistances between the two deteriorates more seriously. However, integrated thermistors represent additional production costs, require additional external leads, additional ceramic isolation board area, and thus generally increase the cost, volume, and weight of the power module. Therefore, usually only one thermistor is integrated on the power module, so the temperature measured by it only represents the temperature of the closest semiconductor chip. Summary of the invention

[0021] In view of this prior art, the present disclosure proposes to use individual control of semiconductor switches in a power module to provide an open circuit state configuration of such switches, wherein TSEP measurements are performed in order to obtain temperature measurements. This is performed for modules having one or more semiconductor switches and each die in a multi-chip power module in order to detect degraded layer portions of the power module. This will allow determining which portion of the equipment using such a module is in a degraded state in order to manage a better maintenance plan.

[0022] More specifically, the present disclosure relates to a method for measuring temperature or thermal resistance in a power electronic system, the power electronic system comprising at least a first power unit and a heat source thermally connected to a cooling device via a connection layer, the method comprising: while the first power unit is in an open circuit state so that the first power unit does not dissipate heat, providing a limited current in the first power unit, the limited current cannot put the first power unit in a power-on state, measuring a temperature T1 of the first power unit using a thermally sensitive electrical parameter TSEP of the first power unit, because the first power unit in the open circuit state does not generate heat, and measuring a temperature T1 of the connection layer. CL Calculated to be equal to such first temperature T1.

[0023] This method allows for simple measurement of the junction temperature without the need for a thermistor.

[0024] The heat source may be a second power unit or any heating element.

[0025] The method may also include measuring the temperature T of the cooling device of the power unit CM And calculate the temperature difference T1-T between the connection layer and the cooling device CM .

[0026] This allows obtaining information about the thermal resistance between the connection layer and the cooling device.

[0027] When the heat source is a second power unit, the method may further include:

[0028] - measuring the temperature T2 of the second power unit using the TSEP of the second power unit,

[0029] - The difference T1-T CMand the difference T2-T CM For comparison,

[0030] - The thermal resistance R between the second power unit and the connection layer is calculated as follows: 2-CL The thermal resistance R between the connection layer and the cooling device CL-CM For comparison:

[0031] R 2-CL / R CL-CM =(T CL -T CM ) / (T2-T CL )=(T1-T CM ) / (T2-T1), since T1=T CL , this calculation is independent of Q, where Q is the value of the heat flow applied between the second power unit and the connecting layer.

[0032] This gives information on the thermal resistance of the layer without the need for sensors other than those on the cooling device.

[0033] The first power unit and the second power unit may be semiconductor switches thermally connected to the connection layer via a first stack of material layers, and the cooling device may be a heat sink, wherein the connection layer is thermally connected to the heat sink via a second stack of material layers.

[0034] The first power unit and the second power unit may be semiconductor switches, and the connection layer is a ceramic layer, such as a directly bonded copper ceramic layer or an active metal brazing layer attached directly to the heat sink or attached to the heat sink via a base plate BP.

[0035] The first power cell may be a first half-bridge power cell including a first top switch and a first bottom switch, the first top switch and the first bottom switch having a die attached to a first ceramic layer such as a directly bonded copper ceramic layer or an active metal brazing layer via a first die attach layer, and the second power cell is a second half-bridge power cell including a second top switch and a second bottom switch, the top switch and the bottom switch having a die attached to a second directly bonded copper ceramic layer via a second die attach layer, and wherein the first directly bonded copper ceramic layer and the second directly bonded copper ceramic layer are attached to a common heat sink via a solder layer and a substrate layer, the method including turning off both the first top switch and the first bottom switch of the first half-bridge power cell while the second top switch and the second bottom switch of the second half-bridge power cell are in an activated state, and

[0036] - measuring the temperature T2 of the second top switch by means of the TSEP of the second top switch, measuring the temperature T1 of the first top switch or the first bottom switch by means of the TSEP of the first top switch or the first bottom switch by providing a limited current in the first top switch or the first bottom switch, the limited current not being able to put the first top switch unit in a power-on state, calculating the temperature difference R between the second top switch and the substrate, taking into account that the temperature of the substrate is equal to the temperature T1 2-BP =T2-T BP =T2-T1,

[0037] -Measure the temperature T of the heat sink HS , then calculate the ratio r2 = (T2-T BP ) / (T BP -T HS ) to compare the thermal resistance of the second die attach layer, the second DBC layer, the solder layer with the thermal resistance between the substrate and the heat sink.

[0038] Each power unit can be shut down in turn while other power units are activated to complete the measurement of all power units.

[0039] The power electronic system may include more than one half-bridge power unit, and one of the half-bridges may be shut down to provide a temperature measurement of the substrate while thermal resistance and thermal resistance ratio measurements are performed on the other half-bridges of the half-bridge, each of the half-bridges being shut down in turn while the other half-bridges are activated to provide a complete test of the half-bridges of the power electronic system.

[0040] The power electronic system may include a first power module having a first pair of half bridges, each of the first pair of half bridges having a top switch, a bottom switch, and a DBC layer connected to a first substrate, and the power electronic system includes a second power module having a second pair of half bridges, each of the second pair of half bridges having a top switch, a bottom switch, and a DBC layer connected to a second substrate, the first substrate and the second substrate being attached to a heat sink in contact with a cooling fluid via a thermal contact material, the power electronic system further comprising a gate driver circuit independent of each of the switches, the method comprising measuring a thermal resistance R between a top switch or a bottom switch of the first power module and the heat sink PU1-HS and the thermal resistance R between the heat sink and the cooling fluid HS-CF , and compare the thermal resistance by the following steps:

[0041] - keeping all devices of the second power module open circuit while the switching function of the power electronic system is performed by the switches of the first power module, and measuring the temperature T of the heat sink contact surface using TSEP temperature measurement of one or a combination of the switches of the second power module HS , and at the same time measure the temperature T2 of at least one device of the first power module by means of its TSEP, measure the temperature T CF ,as well as

[0042] - Calculate the ratio r3 = (T2-T HS ) / (T HS -T CF ) to compare the thermal resistance of the first power module, the first substrate, and the first thermal contact material with the thermal resistance between the heat sink contact surface and the cooling fluid, the method also including performing the same steps when the switch of the first power module is open while the switching function of the power electronic system is implemented by the switch of the second power module.

[0043] By combining the switch-level, power cell-level, and module-level approaches, measurements of thermal resistance ratios can be obtained at multiple levels in the module stack above the heat sink and cooling fluid.

[0044] The first power unit may be forced to be in the open circuit state during the measurement of the temperature or thermal resistance.

[0045] This allows scheduling of measurement sequences.

[0046] The present disclosure also relates to a method for monitoring the thermal resistance of a power unit of a power electronic system, comprising: obtaining an initial thermal resistance of such a power unit by the disclosed method; storing the initial thermal resistance and the ratio between the initial thermal resistance between the power unit and a connection layer of such a power unit and the thermal resistance between the connection layer and a cooling device; repeating the method during the life of the power electronic system to obtain further thermal resistance and further ratio; comparing the further thermal resistance and the further ratio with the initial thermal resistance and the initial ratio to detect changes in the thermal resistance and the ratio.

[0047] The method for monitoring may comprise comparing the change in the thermal resistance with a predetermined threshold and issuing a warning if the value of the thermal resistance or the ratio is above the threshold.

[0048] The method may include:

[0049] - at time interval t samping Periodically recording a temperature Tj of at least one semiconductor device j of the power electronic system, such as a power converter, and storing the data in a memory;

[0050] -Use data samples Tnj ... Tmj at time interval t eval Periodically calculate the average temperature T of at least semiconductor j mean，j and standard deviation σ mean，j , for example, the integration time t averging is at least a significant portion of the thermal constant of the power converter;

[0051] - At least if condition T is met mean，j >C1×T HS , and σ mean，j <C2×(T mean，j -T HS ) then the measurement process is repeated, where C1 is a constant greater than 1, and C2 is a constant less than 1.

[0052] C1 may be a constant in the range between 1.1 and 5.

[0053] C2 is a constant between 0.2 and 0.05, condition σ mean，j <C2×(T mean，j -T HS ) is a condition that detects the steady-state nature of operation by comparing the standard deviation of temperature samples to the average temperature difference between the semiconductor and the heat sink during the sampling time.

[0054] The time interval t samping It can be a multiple of the inverse of the switching frequency of the power converter: t samping =n / f PWM .

[0055] The temperature T can be calculated using the arithmetic mean or median of the data samples Tnj . . . Tmj. mean,j .

[0056] The integration time t averging may be greater than a thermal constant of the power electronic system.

[0057] The time interval t evval Can be greater than t averging time interval.

[0058] The switches of the power unit PUx, x=1 to n, where n is the total number of switches, may be controlled independently of each other, and the method may include measuring the coupling impedance between the power unit PUi and the power unit Puj i≠j by the following sequence, the sequence comprising:

[0059] -1 / Turn off all switches of power unit PUj and keep the switches of power unit PUi activated,

[0060] -2 / Measure the temperature Tx of all power units PUx,

[0061] -3 / Measure the temperature T of the radiator HS ,

[0062] -4 / Calculate the temperature difference ΔTx = Tx-T HS ,

[0063] -5 / Compare ΔTi with ΔTx to detect changes in the coupled thermal resistance.

[0064] The sequence may be repeated multiple times during the life of the product.

[0065] The method may include: using the electrical model Pi (IL, Vbus, fPWM, Ti, α, ...) of the power unit to measure the power dissipated in the power unit PUi, where IL is the measured load power, Ti is the measured temperature of the power unit PUi, Vbus is the known or measured bus voltage of the power unit PUi, fPWM is the switching frequency of the power unit, and α is the duty cycle of the power unit; and calculating the coupling resistance as ΔTx / Pi.

[0066] The present disclosure also relates to software including instructions for implementing the method when executed in a controller of the power system, and to a computer-readable non-volatile medium having the software recorded thereon.

[0067] A detailed description of exemplary embodiments of the present invention will be discussed below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] [ Figure 1 ]

[0069] Figure 1 A schematic diagram of an embodiment of a power electronics system having a power cell with one semiconductor die suitable for use with the process of the present disclosure is shown.

[0070] [ Figure 2 ]

[0071] Figure 2 A schematic diagram of an embodiment of a power electronics system having a power cell with two semiconductor dies suitable for use with the process of the present disclosure is shown.

[0072] [ Figure 3 ]

[0073] Figure 3 A schematic diagram of an embodiment of a power electronics system having two power cells, each cell having a pair of semiconductor switch dies on a single DBC substrate, suitable for use with the process of the present disclosure is shown.

[0074] [ Figure 4 ]

[0075] Figure 4 Shows Figure 3 Circuits of power electronic systems.

[0076] [ Figure 5 ]

[0077] Figure 5 A schematic diagram of an embodiment of a power electronics system having three power cells, each having a pair of semiconductor switch dies on a single DBC substrate, suitable for the process of the present disclosure is shown.

[0078] [ Figure 6 ]

[0079] Figure 6 Shows Figure 5 Circuits of power electronic systems.

[0080] [ Figure 7 ]

[0081] Figure 7 A schematic diagram of an embodiment of a power electronics system having two power cells, each with four semiconductor dies, suitable for the process of the present disclosure is shown.

[0082] [ Figure 8 ]

[0083] Figure 8 Shows Figure 7 Circuits of power electronic systems.

[0084] [ Fig.9A ]

[0085] Fig.9A A flow chart showing an example of an implementation of the method steps.

[0086] [ Fig. 9B ]

[0087] Fig. 9B A flow chart showing an example of an implementation of the method steps.

[0088] [ Fig. 9C ]

[0089] Fig. 9C A flow chart showing an example of an implementation of the method steps.

[0090] [ Fig.9D ]

[0091] Fig.9D A flow chart showing an example of an implementation of the method steps.

[0092] [ Fig.10 ]

[0093] Fig.10 An exemplary general flow chart is shown. DETAILED DESCRIPTION

[0094] The disclosed method for measuring temperature in a power electronics system allows for several measurements depending on the type of system. Figure 1 In FIG. 5 , the power unit PU comprises a semiconductor switch having a die 1a connected to a heat sink HS,5 via a stack of m material layers Mi (i=1,2,...m). In this stack, layers M1 to Mj-1 are located between the die 1a and a layer Mj which may be a DBC layer. The semiconductor switch is connected to the heat sink HS,5 via a layer Mj3 of the material layers Mi forming the stack. SRC The lower portion is thermally connected in parallel with the heat source 10.

[0095] Below the layer Mj is a further stack 4 of layers Mj+1 to Mm, the layer Mm being connected to a heat sink HS 5 .

[0096] The method comprises providing a limited current in the at least one semiconductor switch 1a in the open state, the limited current being adapted to measure a first temperature T1 of the at least one semiconductor switch using a thermal sensitive parameter (TSEP) of the at least one semiconductor switch in the open state.

[0097] In this case, the temperature of the semiconductor switch that does not dissipate heat is close to or equal to the temperature of the DBC layer Mj 3. Then the temperature T of the connecting layer Mj can be calculated. Mj is equal to the first temperature T1 obtained by TSEP measurement.

[0098] TSEP measurements may use parameters such as gate resistance or other parameters that can be measured using existing electrical measurement features of the power cell.

[0099] Conventional semiconductor switches typically operate at a V of approximately -8V. GE voltage is blocked and at approximately +15V V GE voltage conduction, and can drive tens or hundreds of amperes of current.

[0100] In the present case, the measurement of T1 by means of the TSEP parameter is performed by injecting a small current (e.g. a pulse of tens of milliamperes (e.g. 25 mA)) in the gate-emitter junction by means of a current source for a period of less than tens of microseconds, which allows the gate / emitter resistance of the semiconductor to be measured. With such a small current injection, the VGE voltage of such a semiconductor does not rise to a level sufficient to make the switch conduct.

[0101] Using the measurement of the internal gate resistance Rg1 of at least one semiconductor of the switch of PU1 allows avoiding the measurement of the junction temperature T1 with any additional external sensor. It is thus possible to determine the temperature of the layer Mj using only the control terminals of the power electronics system PS.

[0102] The temperature T1 of S1 is measured using the calibration curve and the gate resistance Rg1 of S1. For example, the calibration curve relates T1 to the gate resistance of switch S1 as:

[0103] T1=δR1×Rg1+R01

[0104] The semiconductor switch may be a semiconductor switch in a silicon insulated gate bipolar transistor (IGBT) or MOSFET configuration, such as silicon, silicon carbide or GaAs semiconductor.

[0105] The general principle of the present disclosure is that since the switch of the power unit PU is intentionally kept open and its temperature can be measured, it can be advantageously used as a temperature sensor to measure the temperature of the layer Mj. Therefore, the semiconductor switch plays an additional function of a temperature sensor of the layer Mj.

[0106] exist Figure 1 In the case of , the heat source 10 can be any system that generates heat losses and has a thermal connection with the layer Mj, which causes the temperature of Mj to be different from the temperature of the heat sink even if the power unit PU does not generate losses. For example, the heat source can be a resistor for the flow of current, a mechanical system that generates losses via friction, an inductor affected by magnetic flux, a thermal radiation source that changes the temperature of Mj, or any source that has a radiation, convection, induction, conduction thermal connection with the layer Mj.

[0107] To allow such measurement, the method may include maintaining said semiconductor switch 1a in an open circuit state so that it does not dissipate heat, or detecting that such a semiconductor switch is in said open circuit state. In one embodiment, the power cell may be thermally connected to the motor body, not transferring energy, and used to monitor the temperature of the motor body.

[0108] By measuring with the switch open, the main electrical function of the semiconductor switch is not affected, as the switch is inactive and does not transfer energy. An additional function is to measure the temperature only when the switch is not powered.

[0109] The method of the present disclosure is suitable for power modules in which the material structure above the semiconductor die 1a does not dissipate a large amount of heat compared to the layer stack between the semiconductor switch die and the connection layer Mj 3. Therefore, advantageously, even if the thermal contact between the semiconductor switch die 1a and the layer Mj is poor (e.g., because the thermal contact deteriorates), the temperature T of the material Mj at a location below this die 1a is MjIt is also close enough to the temperature of the semiconductor die 1a so that these temperatures can be approximately considered to be the same. For example, the thermal resistance between the top of the semiconductor die 1a and the heat sink is more than 5 times, typically more than 10 times, and often more than 20 times the thermal resistance between the semiconductor die 1a and Mj. In an embodiment, only a small surface area of ​​the top surface of the semiconductor die 1a is connected to the heat sink via metal, for example, the contact area is less than 10% or less than 5%, and the area is minimized so as to provide only sufficient electrical connections, such as wire connections to terminals, for example, of the top surface. In another embodiment, most of the top surface area of ​​the semiconductor die 1a (typically 90% to 95%) is covered by a thermal insulating material, such as an epoxy-based potting compound of a silicone compound with a thermal conductivity of less than 2W / (mK) (most thermally conductive epoxy resins have a thermal conductivity range of 1 to 1.6W / (mK)), or preferably a thermal conductivity of less than 1W / (mK), such a thermal insulating material provides very limited losses to the heat transfer between the die and the layer Mj.

[0110] In this case, assuming that the temperature T SRC The heat source is in contact with the layer Mj, then the semiconductor switch can be used as a temperature sensor of the heat source 10:

[0111] T1=T Mj =T src or close to T src .

[0112] exist Figure 2 In , the power electronic system is a power unit PU1 comprising two semiconductor switches, each having a die 1a, 2a connected via a similar stack of m material layers Mi (i=1, 2...m) to a heat sink HS 5. The two semiconductor switches are thermally connected in parallel via a connection layer Mj 3 of the stack.

[0113] In this case, each of the two semiconductor switches may form the heat source and may be used alternately to measure the temperature using the method disclosed herein.

[0114] In this case, if Fig.9A The methods described include:

[0115] - keeping the first of the two semiconductor switches (e.g. the switch S1 on the die 1a) in an open circuit state so that it does not dissipate heat, or detecting that the first of the two semiconductor switches is in the open circuit state and at least the second switch S2 on the die 2a is in a conducting state to form the heat source 100, then injecting a gate current into the gate of the semiconductor S1 and measuring a first temperature T1 of the die 1a of the first switch S1 using a thermal parameter of the first semiconductor switch 110,

[0116] - Calculate the temperature T of the connection layer CL is equal to the first temperature T1 because the first switch S1 does not generate heat.

[0117] - At step 120 the temperature T of the heat sink of the power electronics system is measured HS ,

[0118] - The difference T1-T HS and the difference T2-T HS For comparison,

[0119] In this case, the method may comprise measuring the temperature T2 of the die 2a of the second switch S2 in the conducting state, this measurement preferably also being performed using the TSEP parameter of said second switch S2 (step 130).

[0120] - The thermal resistance R between the die and the layer Mj of the second one S2 of the at least two semiconductor switches is calculated at step 140 S2,Mj The thermal resistance R between Mj and the heat sink Mj,HS For comparison:

[0121] R S2,Mj =Q / (T2-T Mj,S2 )

[0122] R Mj,HS =Q / (T Mj,S2 -T HS )

[0123] R S2,Mj / R Mj,HS =(T Mj,S2 -T HS ) / (T2-T Mj,S2 ) becomes independent of Q, where Q is the value of the heat flow applied between the second semiconductor of the at least two semiconductors and the connecting layer Mj.

[0124] This measurement benefits from:

[0125] Semiconductor S1 is located on layer Mj so that it measures the temperature T of Mj. Mj’ Temperature near the semiconductor S2: T Mj’ ,S2≈T Mj For example, the thermal impedance between point Mj' under semiconductor S2 and point Mj under semiconductor S1 is a small fraction, such as <20%, typically <10%, of the thermal impedance between Mj and heat sink HS.

[0126] When the temperature T below the semiconductor S1 Mj When the temperature of semiconductor S1 is close enough, these temperatures can be approximated to be the same: T Mj =T1.

[0127] In this embodiment, T Mj =T Mj’ = T1. The semiconductor S1 is used as a sensor for measuring the temperature of Mj at a position below the semiconductor S1, and the temperature of Mj' below the semiconductor S2 can be approximately regarded as the same as the temperature of the semiconductor of S1.

[0128] Under these conditions, the ratio of the thermal resistance between the semiconductor of S2 and the layer Mj to the thermal resistance between the layer Mj and the heat sink HS can be expressed as:

[0129] r=R S2-Mj / R Mj-HS =(T1-T HS ) / (T2-T1).

[0130] Thus, advantageously, without additional temperature sensors other than the temperature measurement of the semiconductors S1 and S2 and the temperature measurement of HS, it is possible to obtain information about the relative thermal resistance R S2,M j and R M j- HS By performing this reverse measurement with S2 open, the relative thermal resistance R S1,M j / R M j- HS。

[0131] Using the disclosed method, the thermal resistance R between the die and the layer Mj of the second semiconductor S2 can be S2，Mj With M j The resistance R between the heat sink and Mj，HS The comparison is made without knowing the power dissipated in this semiconductor.

[0132] Therefore, this method allows:

[0133] Assuming thermal resistance R Mj，HS Unchanged, monitoring of thermal resistance Rs during the life of the power electronic system PS 2,Mj changes, or

[0134] Assuming thermal resistance R S2-Mj remains unchanged, the thermal resistance R is monitored during the life of the power electronic system PS Mj,HS changes.

[0135] Temperatures T1, T2 and T HS The measurements are preferably taken under or close to steady-state thermal conditions, and the measurements are repeated alternating switches S1 and S2 to monitor possible degradation of one of the resistances of the intermediate layers between S1 and Mj or between S2 and Mj.

[0136] As described above, when the switch S2 is in an open state and the switch S1 is conducting, a similar measurement process can be performed to obtain the thermal resistance R between the die and the layer Mj of the first semiconductor S1. S1,M j and M j The resistance R between the heat sink and Mj，HS to obtain thermal data on the complete unit.

[0137] Here, the temperatures T1 and T2 of switches S1 and S2 are measured using the gate resistances of S1 and S2 using the corresponding calibration curves. For example, the calibration curves linearly relate T1 to Rg1, T2 to Rg2, respectively, as:

[0138] T1=δR1×Rg1+R01

[0139] T2=δR2×Rg2+R02

[0140] Two situations allow the use of this method. In a first type of circuit, the semiconductors with dies 1a, 2a are not electrically connected in parallel, have separate gate commands and do not perform the function of a single switch. In this case, where each switch has its own gate driver, the method is implemented when one of the switches is in an open circuit state during operation of the module. In a second type of circuit, the two semiconductor switches are connected in parallel, but are driven by separate gate driver commands, and in this case, one of the switches remains in an open circuit state while the other conducts for a sufficient period of time to implement the method. This method can be performed periodically, for a limited duration, such as hundreds of milliseconds to one second, to provide thermal data about the module. The method requires that the gate commands of the switches are separate or include different control lines.

[0141] For experts in the field of power electronic module design, the conditions in the embodiments given here are generally met. For example, in such a module, the layer Mj is a direct bonded copper (DBC) ceramic substrate, which is mainly made of an aluminum oxide (Al2O3) substrate with a thermal conductivity of between 20 and 30 W / (mK) and several millimeters thick, and the semiconductor chip spacing of S1 and S2 is less than 5 mm, such as TMj,S2≈TMj,S1. In addition, the power electronic module has a packaging compound material with low thermal conductivity.

[0142] exist Figure 3 and Figure 4In the embodiment, the first power unit PU1 includes two semiconductor switches S11, S12, each having a freewheeling diode and driven by a gate driver 61a, 62a, wherein the switch S11 is the top switch of the half bridge and the switch S12 is the bottom switch of the half bridge. The switch is made of a die 1a, 2a bonded to a single ceramic substrate 3a, and the second power unit PU2 includes two semiconductor switches S21, S22, each having a freewheeling diode and driven by a gate driver 61b, 62b, wherein the switch S21 is the top switch of the half bridge and the switch S22 is the bottom switch of the half bridge. Such switches are made of a die 1b, 2b bonded to a single ceramic substrate 3b.

[0143] Each of said power cells is connected to a single heat sink 5 via a layer 3 ′ and one or more sub-layers 4 ′ forming a base plate.

[0144] In such designs, the directly bonded copper ceramic layers 3a, 3b are usually the most critical layers and can limit the lifetime of the power module, so it is of interest to measure the temperature of such DBC layers. To obtain information on die attach thermal resistance degradation, this method (similar to Fig.9A The method comprises the following steps:

[0145] A – Keep an adjacent semiconductor open that shares the same DBC layer as the target die and use its gate driver to evaluate thermal resistance or damage indicators. Figure 4 As shown in , since the open semiconductor is electrically connected in parallel with another die, the power converter can still perform its task, but the maximum rated current is reduced.

[0146] For example, during TSEP measurement, semiconductor switch S11 is kept in an open circuit state to avoid dissipating heat. In an embodiment, if semiconductor S11 can be a silicon-based IGBT, its gate voltage is kept at -8V, while other semiconductors electrically connected in parallel with S11 are in an electrically activated state and perform normal operation of the switch.

[0147] B – Measure the temperature T of the target die die , using the temperature T of the DBC layer of the deactivated adjacent die DBC and the temperature of the heat sink T HS .

[0148] In an embodiment, keeping switch S11 on die 1a open allows measurements to be made on die 2a which shares DBC layer Mj1 with die 1a, while the converter will still pass current using switch S21 on die 1b.

[0149] Such steps are repeated at regular time intervals during the life of the product and the temperature difference T between the target die and the DBC layer is calculated.die -T DBC The temperature difference between the DBC layer and the heat sink is T DBC -T HS The ratio between r1=(T die -T DBC ) / (T DBC -T HS ), the change in the thermal resistance of the die attach layer can be monitored. In an embodiment, in the case where the thermal coupling between the parallel dies is weak, and referring to the previous embodiment, in the case where the thermal coupling between the parallel dies S11 and S21 is negligible, an increase in this ratio means that the thermal resistance of the die attach layer increases in the same proportion.

[0150] Using this approach, it can be shown that, within a reasonable approximation, and under steady-state thermal conditions (typically after a few seconds of operation at a steady power), the above ratio r1 corresponds to the thermal resistance R between the die and the DBC layer. dier，DBC The thermal resistance R between the DBC layer and the heat sink DBC，HS The ratio between them.

[0151] Therefore, it is preferred to apply the method during a steady-state thermal event of the power converter, which steady-state operation may be intentionally generated during a diagnostic procedure of the power converter or detected during operation of the converter.

[0152] However, this method can still be used to generate damage indicators in thermal transient situations because the ratio r1 = (T die -T DBC ) / (T DBC -T HS ) can still be independent of the dissipated power in some cases, so the method is not limited to steady-state thermal situations. The ratio r1 can no longer be interpreted as a thermal resistance ratio, but rather as a damage indicator, whose trend can still be monitored to assess the health of the power module.

[0153] For example, step B may be performed less than 100 milliseconds after step A, the sequence may be repeated at regular time intervals during the life of the product, and the temperature difference T between the target die and the DBC layer may be calculated. die -T DBC The temperature difference between the DBC layer and the heat sink is T DBC -T HS The ratio between r1=(T die -T DBC ) / (T DBC -T HS ), the change of the damage parameter R of the die attach layer can be monitored.

[0154] Again, the method starts with measuring the temperature of the switch held open by means of the TSEP method, and measuring the temperature of the heat sink T HS , and calculate the first temperature T1 and the heat sink temperature T HS The temperature difference between T1-T HS To obtain the thermal resistance value between the semiconductor switch in the off state and the heat sink.

[0155] Using the same principle of keeping any switch open while another switch of the same die is functional, measurements can be made on all dies and layers below such dies.

[0156] Figure 5 and Figure 6 An embodiment is shown in which three half bridges are connected in parallel to the output terminals.

[0157] The power electronic system comprises three top switches S11 , S21 , S31 respectively located on the dies 1 a , 1 b , 1 c and three bottom switches S12 , S22 , S32 respectively located on the dies 2 a , 2 b , 2 c .

[0158] Each top and bottom switch has its own gate driver circuit: gate driver circuit 61a for switch S11; gate driver circuit 61b for switch S21; gate driver circuit 61c for switch S31; gate driver circuit 62a for switch S12; gate driver circuit 62b for switch S22; and gate driver circuit 62c for switch S32. The three half-bridges 1a, 2a; 1b, 2b and 1c, 2c have their own DBC layers 3a, 3b, 3c attached to a common substrate 4' which in turn is attached to a heat sink 5.

[0159] Corresponds to Fig. 9B This embodiment is used to disclose another measurement to obtain the thermal resistance between the die and the substrate.

[0160] When S11 and S12 of the first power unit PU1 are kept open in step 200, the thermal resistance between the switch S11 and the baseplate can be compared with the thermal resistance between the baseplate 4' and the heat sink 5 by keeping the top switch S11 and the bottom switch S12 of the half bridge open and measuring the temperature T of the baseplate using the temperature measurement of the switch S11 and the switch S12. B , in this case because the switches are off, the temperature T is provided in step 210: S11 =T S12 Equal to T B, the switching function is performed only by the top switches S21, S31 on the one hand and only by the bottom switches S22, S32 on the other hand, and at the same time the temperature of at least the top switch S21 is measured (T2=T in step 220) PU2 The thermal resistance of the second power unit is calculated in step 230 by measuring the temperature of the heat sink in step 225: R PU2 =(T S21 -T B ) / (T B-THS ) or R PU2 =(T S22 -T B ) / (T B -T HS ) to compare the thermal resistance between the die and the substrate with the thermal resistance between the substrate and the heat sink. The same measurements are made on the other switches, which allows to obtain a complete knowledge of all the ratios between the die attach layers 3a, 3b, 3c and the substrate, and between the substrate and the heat sink. In this configuration where there are three half bridges, the maximum current capacity of the converter is reduced by approximately a factor of 1 / 3.

[0161] This measurement can be performed in a Figure 3 and Figure 4 The design is carried out, however, in this case the current capability of the unit is reduced by 50%, which may limit the operating conditions of the unit under measurement.

[0162] To characterize degradation of the cell, the method comprises storing, for each switch, an initial ratio of a first thermal resistance between the die of the switch and a common layer with other switches and a second thermal resistance between the common layer and a common heat sink of the disclosed method, and repeating the method during the lifetime of the power electronic system to store further ratios between the first thermal resistance and the second thermal resistance, and:

[0163] - monitoring the variation of said second thermal resistance during the lifetime of the power electronic system, assuming that the first thermal resistance does not change, or

[0164] - Monitoring the change of said first thermal resistance during the lifetime of the power electronic system, assuming that the second thermal resistance does not change.

[0165] In the present disclosure, one or more temperature sensors of the prior art (such as thermocouples, thermistors or infrared detectors) are used to obtain the temperature T of the heat sink. HS .

[0166] According to the present disclosure, the thermal resistance between all switches Sx (x=1 to n) and the connection layer (such as DBC layer Mj) that thermally connects them to the heat sink of the module, as well as the resistance between such connection layer and the heat sink, can be measured or at least evaluated under initial conditions and during the life of the module to monitor the evolution of such thermal resistance and the aging of the device. When a substrate is present to receive several connection or DBC layers, the resistance between the substrate and the switches can also be monitored.

[0167] The different measurement methods and steps may be implemented by software implemented in a processor of a controller of the power electronics system, the processor being further configured to provide commands to the one or more power units to place the at least one semiconductor switch in the open circuit state, and to provide commands to generate the limited current in the at least one semiconductor switch in the open circuit state.

[0168] Such software may be incorporated in a computer readable non-volatile medium such as a ROM or other medium.

[0169] One of the technical uses of this method in which the semiconductor switch is temporarily deactivated is to monitor the temperature of a target layer Mj in a power electronic system made of one or more power cells or modules. The thermal resistance of a specific layer of a power module can be estimated by comparing the temperature difference between the semiconductor die and the target layer Mj with the temperature difference between the layer Mj and the heat sink. This measurement can be performed online during the nominal operation of the power electronic module when each gate of the parallel die is individually controlled by its own gate driver (multi-chip configuration). Regular repetition of this measurement during the life of the power module allows monitoring the local degradation state of the power module. This will allow a better understanding of the degradation state of such a module and therefore the management of a better maintenance plan. In addition, the application of the present invention eliminates the need for integrated thermistors in the power module, since the semiconductor die itself can perform the task when the method of the present invention is applied. Finally, the present invention also does not require the knowledge or measurement of the power dissipated by the semiconductor die, which is a major limitation of other thermal impedance methods.

[0170] like Figure 7 and Figure 8 As described in , further types of measurements can be performed on the power electronics system PS5.

[0171] In this design, the four power units PU1, PU2, PU3, and PU4 include a top switch S11 on die 1a, a top switch S21 on die 1b, a top switch S31 on die 1c, a top switch S41 on die 1d, and a bottom switch S12 on die 2a, a bottom switch S22 on die 2b, a bottom switch S32 on die 2c, and a bottom switch S42 on die 2d, and the top switches are connected in parallel and the bottom switches are connected in parallel.

[0172] The top and bottom switch dies of each power cell are attached to a common DBC layer 3a, 3b, 3'a, 3'b, and two power cells PU1, PU2 are regrouped in a first power module MO1 on a first substrate 41, while two other power cells PU3, PU4 are regrouped in a second power module MO2 on a second substrate 42. The substrates 41 and 42 are then attached to a heat sink 5 via connection layers 81, 82 (e.g. thermal paste). The heat sink is in contact with a cooling fluid 7.

[0173] exist Figure 8 , independent gate driver circuits 61a, 62a, 61b, 62 and 61'a, 62'a, 61'b, 62'b are shown for each device.

[0174] In this configuration, the temperature T of the heat sink contact surface is measured by keeping all devices of the power module MO2 including PU3 and PU4 open circuit and using temperature measurement of one or a combination of the devices of the power module MO2. HS , the switching function is performed by the devices of the module MO1, and at the same time the temperature T2 (eg, the temperature T S21 ) and the temperature of the cooling fluid T CF , then calculate R = (T2-T HS ) / (T HS -T CF ) to compare the thermal resistance of the module MO1 and its connection layer 41 with the thermal resistance between the heat sink contact surface and the cooling fluid, and the thermal resistance R between S21 and / or S11 and S22 and the heat sink 5 PU1-HS The thermal resistance R between the heat sink 5 and the cooling fluid 7 HS-CF Make a comparison.

[0175] The same measurement is performed keeping all switches of power module MO1 open and the switching functions performed by the devices of module MO2 to compare the thermal resistance of module MO2 and its connection layer 42 with the thermal resistance between the heat sink contact surface and the cooling fluid.

[0176] Thus, in this configuration, if measurements are performed repeatedly during the life of the power electronic system, it is possible to monitor the degradation of the material of the connection layers 41, 42. Alternatively, it is possible to monitor the degradation of the mechanical contact between the module MO1 and the heat sink contact surface due to loosening of the fixing system or due to a reduction in contact pressure caused by degradation of the thermal interface material 81 (e.g. thermal paste pumping out).

[0177] Fig.9DA generalized flow chart is provided, wherein after an initialization phase at steps 375, 380, the measurement is repeated, wherein at step 400, the MOi module is off, the MOj module is off and j≠i, and T is measured. HS , at step 410, T2 of module MOj is measured, and at step 420, T CF , where layer CF is the substrate, the ratio r3 is measured at step 430 = (T2-T HS ) / (T HS -T CF ), storing the ratio r3 of the module at step 450, and repeating the test until all j modules have been tested to compare the ratio r3 values ​​at step 365 in order to detect differences in these ratios.

[0178] The material of the connection layers 41 and 42 can be thermally conductive paste, carbon-based foil or any material placed between the power module and the heat sink contact surface.

[0179] By combining measurements at the die level, power cell level, and module level, the thermal resistance from die to DBC, the thermal resistance from DBC to baseplate, and the thermal resistance from baseplate to heat sink can be monitored.

[0180] The measurements benefit from being made at steady state operation of the power electronics system, and to detect this steady state operation and then monitor the thermal resistance ratio, the process may include:

[0181] - at time interval t samping Periodically recording a temperature Tj of at least one semiconductor device j of a power electronic system such as a power converter and storing the data in a memory;

[0182] -Use data samples Tnj ... Tmj at time interval t eval Periodically calculate the temperature T of at least semiconductor j mean，j and standard deviation σ mean，j , for example, the integration time t averging At least a significant portion of the thermal constant of the power converter;

[0183] - At least if condition T is met mean，j >C1×T HS , and σ mean，j <C2×(T mean，j -T HS ), the measurement process is carried out.

[0184] C1 is, for example, a constant greater than 1, such as when there is a significant temperature difference between the heat sink and the semiconductor die of the power converter, and such that acceptable measurement accuracy can be achieved. For example, if T HS =30℃, with C1=3, then only when T mean，j>90°C allows the measurement to be applied, ensuring that there is a sufficient thermal gradient in the power converter. Alternatively, C1 may have a different value, such as C1=1.1, or preferably C1=2, or preferably C1=5.

[0185] Condition σ mean，j <C2×(T mean，j -T HS ) is a condition that detects the steady-state nature of the operation by comparing the standard deviation of the temperature samples to the average temperature difference between the semiconductor and the heat sink during the sampling time. C2 is a constant that is preferably minimized and is subject to T mean，j -T HS For example, C2=0.2, preferably C2=0.1, preferably C2=0.05.

[0186] During near-thermal steady-state operation of the power converter, the ratio (T1-T HS ) / (T2-T1) is the ratio between:

[0187] - The temperature T1 of the element in the disconnected state The thermal resistance between the connecting layer (layer Mj) and the cooling device, i.e. the temperature T CM Equal to T HS or T CF ;as well as

[0188] - The thermal resistance between the active semiconductor (temperature T2) and the layer Mj (temperature T1), without errors introduced by delays in obtaining thermal equilibrium, making it possible to carry out the measurement online without significantly affecting the converter performance or interrupting its operation.

[0189] An advantage of steady-state detection is that the converter does not therefore need to be forced to apply electrical steady-state conditions to achieve thermal steady-state conditions.In this method, thermal steady-state conditions are detected during normal operation of the converter and when detected, a measurement method is processed.

[0190] Time interval t samping It can be a multiple of the inverse of the switching frequency of the power converter: t samping =n / f PWM For example, n = 100, preferably n = 10. For example, f PWM =10kHz, and t sampling In another embodiment, n is the number of active semiconductor dies of the converter, and the temperature of each die is measured one by one in each switching cycle.

[0191] In another embodiment, the temperature T mean，jThe arithmetic mean (the median of the data samples Tnj ... Tjm) may be used for calculation. The definition of standard deviation is any definition of standard deviation generally accepted in the field of statistical analysis.

[0192] Time interval t averging is a sufficiently long time compared to the thermal constant of the power converter or the area to be investigated. The thermal impedance can be chosen a priori by performing a thermal impedance measurement and measuring the time to reach a quasi-steady-state thermal state and taking into account a safety margin to account for possible thermal impedance degradation. For example, in the case of a power converter with a thermal constant of 3 minutes, for layers close to the die, the time to reach a quasi-steady state is faster than the thermal constant of the power converter, t averging can be 1 minute, and for a complete converter measurement, t averging It can be about 3 minutes or even 9 minutes. In another embodiment, the thermal constant of the power converter is 30 seconds, for the inner layer, t averging It can be between 15s and 30s. For the entire converter, t averging Up to 270s.

[0193] Time interval t eval For example, if it is greater than t averging The time interval, for example, t eval =t averging , or t eval =1.5*t averging , or eval =10*t averging .

[0194] In designs where the switches of the power units PU can be controlled independently of each other, in addition to measuring the thermal impedance between the power unit and the heat sink, the coupling impedance between the power unit PUi and the power unit PUj (i≠j) can be measured by Fig. 9C The sequence shown to measure includes:

[0195] 1 / Turn off all PUj at step 300 and keep Pui activated,

[0196] 2 / At step 310, the temperature Ti of all PUi is measured,

[0197] 3 / Measure the temperature T of the heat sink at step 320 HS ,

[0198] 4 / Calculate the temperature difference ΔTi=Ti-T at step 330 HS ,

[0199] 5 / At step 340 , ΔTi between power cells is compared to detect changes in coupling thermal resistance.

[0200] Optionally, the power dissipated in PU1 may be estimated.

[0201] This sequence according to step 350 may also be repeated several times during the life of the product and may also be applied sequentially to several PUi's out of all the PUi's of the PS.

[0202] Thus, advantageously, the thermal impedance of PUi and / or the change of the coupling term with PUj (i≠j) can be measured.

[0203] When the measurement sequence is applied to all PUi in sequence and the power Pi dissipated in PUi is measured or estimated and the thermal steady state is obtained before starting the sequence, the data representation consists in arranging the temperature measurements in n matrices n×n: When power is dissipated only in PU1:

[0204]

[0205] When power is dissipated only in PUi:

[0206]

[0207] Therefore, by applying the principles of superposition and summation, the matrix Mi is as follows:

[0208]

[0209] A thermal resistance matrix including coupled terms (off-diagonal terms) is generated. Therefore, by applying this method multiple times during the product life, the thermal resistance R ii Or coupling resistor R ij (i≠j) changes.

[0210] An embodiment of measuring the power dissipated in PUi of a converter is to use the electrical model Pi(IL, Vbus, fPWM, Ti, α, ...) of PU, where IL is the measured load power, Ti is the measured temperature of PUi, Vbus is the known or measured bus voltage of PUi or the converter, fPWM is the switching frequency, and α is the duty cycle.

[0211] Alternatively, without measuring the dissipated power, the ratio between the thermal resistance of PU1 and the coupling resistance with PUi is measured, and the temperature measurements ΔTi are arranged into a vector giving:

[0212]

[0213] By dividing each temperature ΔT i Normalized relative to ΔT1, the state vector D is obtained, which represents the thermal resistance coupling state of PUi at the measurement time t:

[0214]

[0215] By repeating the measurement several times and comparing the vector D(t), changes in the coupling resistance between PUi can be detected.

[0216] Thus, the method of the present disclosure can provide a simple way to measure temperature parameters in power electronic systems, wherein a semiconductor switch can be used in the off state to measure the temperature of a connection layer between such a semiconductor switch and a heat source, or the temperature of a connection layer between such a semiconductor switch and other semiconductor switches in operation. Knowing the temperature of a final temperature dissipation layer located opposite the die relative to such a connection layer, the method allows the contact degradation between the die and the common connection layer to be measured. The method is directed to power electronic converters in which individual semiconductor devices are driven independently so that the temperature can be measured sequentially on each semiconductor using independently controllable gates, and in which several dies share a thermal connection via layer Mj. This is typically the case in multi-chip configurations in which several semiconductors are electrically connected in parallel to perform the function of a single switch and share current.

[0217] Fig.10 A general flow chart of an online measurement method is provided that provides measurements over the life of the system 500, storage 510, comparison to previous measurements 530, providing a warning when a value such as thermal resistance or thermal resistance ratio is above a threshold 540, and repeating the measurement after a determined time delay 520.

[0218] This method allows measuring the temperature of individual switching devices in multi-chip power modules with different configurations in order to estimate the thermal resistance of the layer between a cold device and a hot device. The change in thermal resistance due to power module aging will be correlated to the degradation of the layer.

[0219] The disclosed method can be particularly useful in DC / DC power converters, AC / AC power converters and DC / AC power inverters comprising parallel current conducting switches having separate gate inputs, such as converters used in wind power systems, photovoltaic inverters, electric vehicles and traction applications.

Claims

1. A method for measuring temperature or thermal resistance in a power electronic system, the power electronic system comprising at least a first power unit and a heat source thermally connected to a cooling device via a connection layer, the method comprising: When the first power unit is in an open circuit state so that the first power unit does not dissipate heat, a limited current is provided in the first power unit, and the limited current cannot make the first power unit in a power-on state, and the temperature T1 of the first power unit is measured using the thermal electrical parameter TSEP of the first power unit. Because the first power unit in the open circuit state does not generate heat, the temperature T1 of the connection layer is measured. CL Calculated to be equal to the first temperature T1.

2. The method according to claim 1, wherein: The heat source is a second power unit.

3. The method according to claim 2 further comprises measuring the temperature T of the cooling device CM And calculate the temperature difference T1-T between the connection layer and the cooling device CM .

4. The method according to claim 3, further comprising: - measuring the temperature T2 of the second power unit using the TSEP of the second power unit, - The difference T1-T CM and the difference T2-T CM Make a comparison - The thermal resistance R between the second power unit and the connection layer is calculated as follows: 2-CL The thermal resistance R between the connection layer and the cooling device CL-CM For comparison: R 2-CL / R CL-CM =(T CL -T CM ) / (T2-T CL )=(T1-T CM ) / (T2-T1), since T1=T CL , this calculation is independent of Q, where Q is the value of the heat flow applied between the second power unit and the connecting layer.

5. The method according to claim 4, wherein: The first power unit and the second power unit are semiconductor switches thermally connected to the connecting layer Mj via a first stack of material layers M1, ..., Mj-1, wherein the cooling device is a heat sink, and wherein the connecting layer is thermally connected to the heat sink via a second stack of material layers Mj+1, ..., Mn.

6. The method according to claim 5, wherein: The first power unit and the second power unit are semiconductor switches, and the connection layer is a ceramic layer, such as a directly bonded copper ceramic layer or an active metal brazing layer attached directly to the heat sink or attached to the heat sink via a base plate BP.

7. The method according to claim 4, wherein: The first power unit is a first half-bridge power unit including a first top switch and a first bottom switch, the first top switch and the first bottom switch having a die attached to a first ceramic layer DBC1 such as a directly bonded copper ceramic layer or an active metal brazing layer via a first die attach layer, and the second power unit is a second half-bridge power unit including a second top switch and a second bottom switch, the top switch and the bottom switch having a die attached to a second directly bonded copper ceramic layer DBC2 via a second die attach layer, and wherein the first directly bonded copper ceramic layer DBC1 and the second directly bonded copper ceramic layer DBC2 are attached to a common heat sink HS via a solder layer and a substrate layer BP, the method including turning off both the first top switch and the first bottom switch of the first half-bridge power unit while the second top switch and the second bottom switch of the second half-bridge power unit are in an activated state, and - measuring the temperature T2 of the second top switch by means of the TSEP of the second top switch, measuring the temperature T1 of the first top switch or the first bottom switch by means of the TSEP of the first top switch or the first bottom switch by providing a limited current in the first top switch or the first bottom switch, the limited current not being able to put the first top switch unit in a power-on state, calculating the temperature difference R between the second top switch and the substrate, taking into account that the temperature of the substrate is equal to the temperature T1 2-BP =T2-T BP =T2-T1, -Measure the temperature T of the heat sink HS , then calculate the ratio r2 = (T2-T BP ) / (T BP -T HS ) to compare the thermal resistance of the second die attach layer, the second DBC layer, the solder layer with the thermal resistance between the substrate and the heat sink.

8. The method according to any one of claims 4 to 7, wherein: Each power unit is shut down in turn while the other power units are active.

9. The method according to claim 7, wherein: The power electronic system includes more than one half-bridge power unit, and wherein one of the half-bridges is shut down to provide a temperature measurement of the substrate while the thermal resistance and thermal resistance ratio are measured for the other half-bridges, and each of the half-bridges is shut down in turn while the other half-bridges are activated to provide a complete test of the half-bridges of the power electronic system.

10. The method according to claim 4, wherein: The power electronic system comprises a first power module, the first power module having a first pair of half-bridge power cells, the first pair of half-bridge power cells each having a top switch, a bottom switch and a DBC layer connected to a first substrate, and the power electronic system comprises a second power module, the second power module having a second pair of half-bridge power cells, the second pair of half-bridge power cells each having a top switch, a bottom switch and a DBC layer connected to a second substrate, the first substrate and the second substrate being attached to a heat sink HS in contact with a cooling fluid CF via a thermal contact material, the power electronic system further comprising a gate driver circuit independent of each of the switches, the method comprising measuring a thermal resistance R between a top switch or a bottom switch of the first power module and the heat sink PU1-HS and the thermal resistance R between the heat sink and the cooling fluid HS-CF , and compare the thermal resistance by the following steps: - keeping all devices of the second power module open circuit while the switching function of the power electronic system is performed by the switches of the first power module, and measuring the temperature T of the heat sink contact surface using TSEP temperature measurement of one or a combination of the switches of the second power module HS , and at the same time measure the temperature T2 of at least one device of the first power module by means of its TSEP, measure the temperature T CF ,as well as - Calculate the ratio r3 = (T2-T HS ) / (T HS -T CF ) to compare the thermal resistance of the first power module, the first substrate, and the first thermal contact material with the thermal resistance between the heat sink contact surface and the cooling fluid, the method also including performing the same steps when the switch of the first power module is open while the switching function of the power electronic system is performed by the switch of the second power module.

11. The method according to any one of claims 1 to 10, wherein: The first power cell is forced into the open circuit state during the measurement of temperature or thermal resistance.

12. A method for monitoring thermal resistance of a power unit of a power electronic system, the method comprising: Obtaining the initial thermal resistance of the power unit by the method according to any one of claims 4 to 11; Storing the initial thermal resistance and the ratio between the initial thermal resistance between the power unit and the connection layer of the power unit and the thermal resistance between the connection layer and the cooling device; repeating the method during the life of the power electronic system to obtain further thermal resistances and further ratios; comparing the further thermal resistances and the further ratios with the initial thermal resistances and the initial ratios to detect changes in thermal resistances and ratios.

13. A method according to claim 12, comprising comparing the change in the thermal resistance with a predetermined threshold and issuing a warning if the value of the thermal resistance or the ratio is above the threshold.

14. The method according to any one of claims 1 to 13, comprising: - at time interval t samping Periodically recording a temperature Tj of at least one semiconductor device j of the power electronic system and storing the temperature Tj in a memory; - An integration time of at least half the thermal constant of the power converter t averging , using data samples Tnj…Tmj at time interval t eval Periodically calculate the average temperature T of at least the semiconductor device j mean，j and standard deviation σ mean，j ; - At least if condition T is met mean，j >C1×T HS , and σ mean，j <C2×(T mean，j -T HS ), wherein C1 is a constant greater than 1, and C2 is a constant less than 1, the measurement process according to any one of claims 4 to 10 is performed.

15. The method according to claim 14, wherein: C1 is a constant in the range of 1.1 to 5.

16. The method according to claim 14 or 15, wherein: C2 is a constant between 0.2 and 0.05, condition σ mean，j <C2×(T mean，j -T HS ) is a condition that detects the steady-state nature of operation by comparing the standard deviation of temperature samples to the average temperature difference between the semiconductor and the heat sink during the sampling time.

17. The method according to any one of claims 14, 15 or 16, wherein: The time interval t samping is a multiple of the reciprocal of the switching frequency of the power converter: t samping =n / f PWM .

18. The method according to any one of claims 14 to 17, wherein: The temperature T is calculated using the arithmetic mean or median of the data samples Tnj...Tmj. mean，j .

19. The method according to any one of claims 14 to 18, wherein: The integration time t averging Greater than the thermal constant of the power electronic system.

20. The method according to any one of claims 14 to 19, wherein: The time interval t evval is greater than t averging time interval.

21. The method according to any one of claims 7, 9 or 10, wherein: The switches of the power unit PUx are controlled independently of each other, where x=1 to n, n being the total number of switches, the method comprises measuring the coupling impedance between the power unit PUi and the power unit Puj, where i≠j, by the following sequence, the sequence comprising: -1 / Turn off all switches of module PUj and keep the switches of module PUi activated, -2 / Measure the temperature Tx of all modules PUx, -3 / Measure the temperature T of the radiator HS , -4 / Calculate the temperature difference ΔTx = Tx-T HS , -5 / Compare ΔTi with ΔTx in order to detect changes in the coupling thermal resistance between the modules.

22. The method according to claim 21, wherein: The sequence is repeated many times during the life of the product.

23. The method according to claim 21 or 22, comprising: measuring the power dissipated in the power unit PUi using an electrical model of the power unit Pi(IL, Vbus, fPWM, Ti, α, ...), where IL is the measured load power, Ti is the measured temperature of PUi, Vbus is the known or measured bus voltage of the power unit PUi, fPWM is the switching frequency of the power unit, and α is the duty cycle of the power unit; And the coupling resistance is calculated as ΔTk / Pi.

24. Software comprising instructions for implementing the method according to any one of claims 1 to 23 when executed in a controller of the power electronic system.

25. A computer readable non-volatile medium having recorded thereon the software according to claim 24.

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