High throughput LED with low operating voltage using two p-n junctions connected in parallel and with one tunnel junction

Abstract

An LED consisting of first and second p-n junctions sequentially deposited on the same wafer is provided. The first and second junctions have opposite n-layer and p-layer deposition sequences. One light emitting active region is embedded between the n-layer and the p-layer of the first junction, and the other light emitting active region is embedded between the n-layer and the p-layer of the second junction. The contacts are processed such that a forward current can pass through the two junctions in parallel using a single voltage source. For a given forward current, the LED operates at a lower voltage, with higher luminous flux and efficiency.

Description

[0001] Government licensing rights

[0002] This invention was made with U.S. Government support under Award No. DE-EE009163 awarded by the Department of Energy (DOE). The U.S. Government has certain rights in this invention. Technical Field

[0003] Embodiments of the present disclosure generally relate to arrays of light emitting diode (LED) devices and methods of manufacturing the same. More particularly, embodiments are directed to light emitting diode devices having first and second pn junctions sequentially deposited on the same wafer, the first and second junctions having opposite deposition orders of n-layers and p-layers. One light emitting active region is embedded between the n-layer and p-layer of the first junction, and another light emitting active region is embedded between the n-layer and p-layer of the second junction. Background Art

[0004] A light emitting diode (LED) is a semiconductor light source that emits visible light when an electric current flows through it. LEDs combine a p-type semiconductor with an n-type semiconductor. LEDs typically use Group III compound semiconductors. Group III compound semiconductors provide stable operation at higher temperatures than devices using other semiconductors. Group III compounds are typically formed on a substrate formed of sapphire or silicon carbide (SiC).

[0005] In general, Indium Gallium Nitride (InGaN) based LEDs (and green LEDs in particular) suffer from a problem known as "efficiency droop". Droop refers to the non-thermal reduction in the external quantum efficiency (EQE) of an LED as current density increases. Droop is caused by the increase in the non-radiative Auger recombination rate as carrier density increases. Optimizing multiple quantum well designs to minimize Auger recombination (droop) has been the subject of extensive research for many years. For green LEDs in particular, it has been found that the design changes required to improve droop also unfortunately increase the forward voltage. The interaction between droop and forward voltage makes it difficult to further improve the lumens / watt and power conversion efficiency (PCE) of green LEDs operating at high current densities.

[0006] Reducing the current density is a known direct way to reduce the forward voltage and increase the EQE and PCE. Increasing the total emitter area would be a way to reduce the current density while maintaining a fixed light output, but this method increases the system cost and is not possible for applications that require a small light source size. The tunnel junction cascade LED is a device design that has been proposed for obtaining high flux from a small light source size at a lower current density. In a cascade LED, two or more pn junctions of the same polarity are stacked (each pn junction surrounds a light emitting active area), and current passes in series through each of the pn junctions. Since light is emitted from both junctions, the same light output can be obtained with a reduced current density and higher efficiency.

[0007] However, a disadvantage of cascaded LEDs is their high operating voltage (inevitable for multiple junctions connected in series). Even with the efficiency gain from lowering the current density, cascaded LEDs still require a high current density of 10A / cm2. 2 The above operation is to match the 40A / cm 2 The forward voltage of a cascaded LED will exceed 6V, and such a high voltage limits the range of possible applications. For example, a 6V cascaded LED cannot be used to upgrade an existing lighting system designed with a 3.5V driver.

[0008] Therefore, there is a need for improved LED devices. Summary of the invention

[0009] Embodiments of the present disclosure are directed to LED devices and methods for manufacturing LED devices. In one or more embodiments, a light emitting diode (LED) device includes: a first light emitting stack on a second light emitting stack, wherein the first light emitting stack includes a first n-type layer on a first tunnel junction, a first tunnel junction on a first p-type layer, and a first p-type layer on a first light emitting active region, the second light emitting stack includes a second n-type layer in contact with the first light emitting active region and on the second light emitting active region, a second light emitting active region on the second p-type layer; and a metal contact on the second light emitting stack and extending to the first light emitting stack.

[0010] Additional embodiments of the present disclosure are directed to methods for manufacturing LED devices. In one or more embodiments, a method for manufacturing a light emitting diode (LED) die includes: epitaxially growing a first light emitting stack and a second light emitting stack on an epitaxial wafer, the first light emitting stack including a first n-type layer on a first tunnel junction, a first tunnel junction on a first p-type layer, and a first p-type layer on a first light emitting active region, the second light emitting stack including a second n-type layer in contact with the first light emitting active region and on the second light emitting active region, a second light emitting active region on the second p-type layer; and forming at least one metal contact on the second pn junction.

[0011] Another embodiment of the present disclosure is directed to a method for manufacturing a thin film flip chip (TFFC) die. In one or more embodiments, a method for manufacturing a thin film flip chip (TFFC) die includes: sequentially forming two pn junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack including at least one n-type layer and at least one p-type layer, and having a light-emitting active region embedded between the at least one n-type layer and the at least one p-type layer; dry etching the epitaxial stack to form two through holes of different depths; conformally depositing a dielectric layer in the two through holes; removing a portion of the dielectric layer to form a contact opening; depositing one or more of an anode layer and a cathode layer in the contact opening; depositing a bonding metal layer on one or more of the anode layer or the cathode layer; singulating the thin film flip chip (TFFC) die; and bonding the thin film flip chip (TFFC) die to a substrate (submount). BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To facilitate a detailed understanding of the above-listed features of the present disclosure, the present disclosure briefly summarized above may be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and therefore should not be considered to limit its scope, as the present disclosure may allow for other equivalent embodiments. The embodiments as described herein are illustrated in the figures of the accompanying drawings by way of example and not limitation, in which similar reference numerals indicate similar elements.

[0013] Figure 1 shows a schematic cross-sectional view of an epitaxial configuration according to one or more embodiments;

[0014] Figure 2 shows a cross-sectional schematic diagram of an alternative epitaxial configuration according to one or more embodiments;

[0015] Figure 3 FIG. 1 shows a thin film flip chip (TFFC) device after being processed into a thin film flip chip (TFFC) device according to one or more embodiments. Figure 1 A schematic cross-sectional view of an epitaxial configuration;

[0016] Figure 4 FIG. 1 shows a thin film flip chip (TFFC) device after being processed into a thin film flip chip (TFFC) device according to one or more embodiments. Figure 2 Schematic cross-sectional view of an alternative epitaxial configuration;

[0017] Figure 5 FIG. 1 shows a schematic diagram of a lateral die after processing into a lateral die according to one or more embodiments. Figure 2 A schematic cross-sectional view of an epitaxial configuration;

[0018] Figure 6A process flow chart showing a method of forming an LED die according to one or more embodiments;

[0019] Figure 7 A process flow diagram illustrating a method of forming a thin film flip chip (TFFC) device according to one or more embodiments;

[0020] Figure 8 An example of a general device according to some embodiments is shown;

[0021] Fig. 9 An example lighting system according to some embodiments is shown;

[0022] Fig.10 shows an example hardware arrangement for implementing the above disclosed subject matter according to some embodiments;

[0023] Fig.11 A block diagram illustrating an example of a system according to some embodiments; and

[0024] Fig.12 An example method of making a lighting device according to some embodiments is shown.

[0025] To facilitate understanding, where possible, the same reference numerals have been used to denote common elements in the drawings. The drawings are not drawn to scale. For example, the height and width of the countertops are not drawn to scale. DETAILED DESCRIPTION

[0026] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0027] According to one or more embodiments, the term "substrate" as used herein refers to an intermediate or final structure having a surface or a portion of a surface on which a process is performed. Additionally, in some embodiments, reference to a substrate also refers to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, according to some embodiments, reference to depositing on a substrate includes depositing on a bare substrate, or depositing on a substrate having one or more layers, films, features, or materials deposited or formed thereon.

[0028] In one or more embodiments, "substrate" means any substrate or material surface formed on a substrate on which film processing is performed during a fabrication process. In exemplary embodiments, depending on the application, the substrate surface on which processing is performed includes materials such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material (such as metals, metal nitrides, Group III nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials). Substrates include, but are not limited to, light emitting diode (LED) devices. In some embodiments, the substrate is exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps is also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0029] In this disclosure, the terms "wafer" and "substrate" will be used interchangeably. Thus, as used herein, a wafer is used as a substrate to form the LED devices described herein.

[0030] Examples of different light illumination systems and / or light emitting diode (LED) embodiments will be described more fully below with reference to the accompanying drawings. These examples are not mutually exclusive, and features found in one example can be combined with features found in one or more other examples to achieve additional embodiments. Therefore, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only, and they are not intended to limit the present disclosure in any way. Like numbers always refer to like elements.

[0031] Semiconductor light emitting devices or optical power emitting devices (such as devices that emit ultraviolet (UV) or infrared (IR) optical power) are one of the most efficient light sources currently available. These devices may include light emitting diodes, resonant cavity light emitting diodes, vertical cavity laser diodes, edge emitting lasers, etc. (hereinafter referred to as "LEDs"). For example, due to their compact size and low power requirements, LEDs may be attractive candidates for many different applications. For example, they can be used as light sources (e.g., flashlights and camera flashes) for handheld battery-powered devices (such as cameras and mobile phones). They can also be used for, for example, automotive lighting, head-up display (HUD) lighting, horticultural lighting, street lighting, video flashlights (torch for video), general lighting (e.g., home, store, office and studio lighting, theater / stage lighting, and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, as backlights for displays, and IR spectroscopy. A single LED can provide less bright light than an incandescent light source, and therefore, multi-junction devices or LED arrays (such as monolithic LED arrays, micro-LED arrays, etc.) can be used for applications where higher brightness is desired or required.

[0032] The present disclosure generally relates to the manufacture of green light sources for use in high power general lighting systems.

[0033] The embodiments described herein describe LED devices and methods for forming LED devices. In particular, the present disclosure describes an LED device and a method for manufacturing an LED device, the LED device consisting of a first and a second pn junction sequentially deposited on the same wafer, the first and second pn junctions having opposite deposition orders of n-layers and p-layers. A light-emitting active region is embedded between the n-layer and the p-layer of the first junction, and another light-emitting active region is embedded between the n-layer and the p-layer of the second junction. In one or more embodiments, the two active regions emit the same color, and the efficiency benefit is expected to be mainly for cyan or longer wavelength light. The contact is processed so that the forward current can pass through the two junctions in parallel using a single voltage source. For a given forward current, the disclosed LED operates at a lower voltage, has a higher luminous flux and efficiency, compared to a standard LED with a similar light-emitting active region.

[0034] As used herein, the term "pn junction" refers to the boundary between two semiconductor layers of opposite conductivity types (p-type and n-type). The "p" side contains an excess of holes, while the "n" side contains an excess of electrons. Excess holes and electrons can be obtained by intentionally doping with acceptor or donor impurities, respectively, and / or can be generated by the presence of natural crystal defects. The boundary is not necessarily steep, planar or smooth. The boundary may include an impurity concentration gradient and / or an intrinsic (neutral) conductivity type layer between the p-type layer and the n-type layer. The boundary may be characterized by a p-type semiconductor protruding into an n-type semiconductor, or vice versa.

[0035] One or more embodiments call for nitride epitaxy with a p-type layer grown before the quantum wells (p-side down), as opposed to the usual case of having an n-type layer grown before the quantum wells. There has been a widely held belief that high efficiency p-side down LEDs are not feasible due to unintentional acceptor dopant incorporation in the quantum wells. However, in one or more embodiments, unintentional acceptor dopant incorporation in the quantum wells is advantageously mitigated using special growth conditions to produce high efficiency p-side down LEDs. For current densities relevant to lighting, the EQE deficit between p-side down LEDs and conventional LEDs is currently not large and can be further reduced.

[0036] In one or more embodiments, there are two general epitaxial configurations for making the desired dual active area LEDs. Although the examples discussed herein are for a thin film flip chip (TFFC) die architecture, the same epitaxial design can be processed into other die architectures using similar fabrication methods. Chip scale packaging, vertical thin film, and lateral die are other possible architectures. Figure 1 In the first epitaxial configuration depicted in , all metal contacts can be made into n-type layers, and the polarity of the contacts is the same as in conventional devices. Figure 2 In the second or alternative epitaxial configuration depicted in , only one tunnel junction needs to be grown, making the epitaxial growth easier.

[0037] Embodiments of the present disclosure are described by the accompanying drawings, which illustrate devices and processes for forming devices according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0038] One or more embodiments of the present disclosure are described with reference to the accompanying drawings. Figure 1 A schematic cross-sectional view of an epitaxial configuration 100 “Configuration A” is shown in accordance with one or more embodiments. Figure 2 A cross-sectional schematic diagram of an alternative epitaxial configuration 200 “Configuration B” is shown in accordance with one or more alternative embodiments. Figure 3 and Figure 4 As shown in , additional aspects of the present disclosure relate to a method of fabricating a thin film flip chip (TFFC) device by an epitaxial configuration.

[0039] refer to Figure 1 , a dual active region LED wafer 100 is manufactured by forming a plurality of Group III nitride layers on a substrate 102 to form two pn junction LEDs (which include light emitting active regions) on the substrate. The two pn junctions are connected in parallel. The light emitting active regions include a first light emitting active region 106a and a second light emitting active region 106b. Any order of stacking different active regions is within the scope of the present disclosure.

[0040] According to some specific embodiments, the dual active area LED chip 100 includes a first light emitting stack 105a, the first light emitting stack 105a having a first n-type layer 104a formed on a substrate 102, a first light emitting active area 106a grown on the first n-type layer 104a, a first p-type layer 108a formed on the first light emitting active area 106a, and a first tunnel junction 110a formed on the first p-type layer 108a.

[0041] In one or more embodiments, the first light-emitting active region 106a is a green light-emitting active region. In the illustrated embodiment, there is a first tunnel junction 110a on the first junction, particularly on the first p-type layer 108a. The tunnel junction is a structure that allows electrons to tunnel from the valence band of the p-type layer to the conduction band of the n-type layer under reverse bias. When electrons tunnel, holes are left in the p-type layer, so that carriers are generated in both regions. Therefore, in a diode-like electronic device, in which only a small leakage current flows under reverse bias, a large current can be transmitted across the tunnel junction under reverse bias. The tunnel junction includes a specific alignment of the conduction band and the valence band at the p / n tunnel junction. This can be achieved by using very high doping (e.g., in a p++ / n++ junction). In addition, group III nitride materials have inherent polarization, which generates an electric field at the heterogeneous interface between different alloy components. In some cases, this polarization field can also be used to achieve band alignment for tunneling.

[0042] Still refer to Figure 1, the dual active area LED wafer 100 also includes a second light emitting stack 105b on the first light emitting stack 105a. The second light emitting stack 105b includes a second n-type layer 104b on the first tunnel junction 110a, a second tunnel junction 110b on the second n-type layer 104b, a second light emitting active region 106b grown on the second p-type layer 108b, and a third n-type layer 104c on the second light emitting active region 106b. In one or more embodiments, the second light emitting active region 106b is also a green light emitting active region. In the illustrated embodiment, there is a second tunnel junction 110b on the second light emitting stack 105a, particularly on the second n-type layer 104b.

[0043] In one or more embodiments, a nucleation layer (not shown) and a dislocation density control layer (not shown) are grown on a suitable substrate 102 (such as patterned or non-patterned sapphire). In one or more embodiments, the nucleation layer comprises a Group III nitride material. In a specific embodiment, the nucleation layer comprises gallium nitride (GaN) or aluminum nitride (AlN).

[0044] In one or more embodiments, the first n-type layer 104a is grown on the substrate 102, the nucleation layer and / or the dislocation density control layer. In one or more embodiments, the first n-type layer 104a is formed on the substrate 102. The substrate 102 can be any substrate known to those skilled in the art, which is configured to be used in the formation of an LED device. In one or more embodiments, the substrate 102 includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate 102 is a transparent substrate. In a specific embodiment, the substrate 102 includes sapphire. In one or more embodiments, the substrate 102 is not patterned before forming the LED. Therefore, in some embodiments, the substrate 102 is not patterned and can be considered to be flat or substantially flat. In other embodiments, the substrate 102 is a patterned substrate.

[0045] In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c may include any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also known as III-nitride materials. Therefore, in some embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a specific embodiment, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c include gallium nitride (GaN). In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c are independently doped with n-type dopants, such as silicon (Si) or germanium (Ge). In one or more embodiments, the dopant concentration is from 1e17 to 2e19 cm 3 In one or more embodiments, the first n-type layer 104a may have a thickness in the range from 1 μm to 3 μm to ensure a wide process margin for a subsequent etching step for contacting the layer.

[0046] In one or more embodiments, the group III nitride material layer may be deposited by one or more of sputtering deposition, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0047] As used herein, "sputter deposition" refers to a physical vapor deposition (PVD) method of thin film deposition by sputtering. In sputter deposition, a material, such as a Group III nitride, is ejected from a target as a source onto a substrate. The technique is based on ion bombardment of the source material (target). The ion bombardment generates vapor due to a purely physical process, i.e., sputtering of the target material.

[0048] As used in accordance with some embodiments herein, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a vapor phase technique for depositing a thin film on a substrate surface. The ALD process involves exposing a substrate surface or a portion of a substrate to alternating precursors, i.e., two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into a reaction zone of a process chamber, and the substrate or a portion of the substrate is exposed to the precursors individually.

[0049] As used herein in accordance with some embodiments, "chemical vapor deposition" refers to the process of depositing a film of material from a vapor phase by decomposition of a chemical on a substrate surface. In CVD, the substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. A specific subset of CVD processes commonly used in LED manufacturing uses metal organic precursor chemicals and is referred to as MOCVD or metal organic vapor phase epitaxy (MOVPE). As used herein, "substantially simultaneously" means that the majority of the exposures of the precursors co-flow or there is overlap.

[0050] As used herein according to some embodiments, "plasma enhanced atomic layer deposition (PEALD)" refers to a technique for depositing a thin film on a substrate. In some examples of the PEALD process relative to the thermal ALD process, the material can be formed from the same chemical precursors, but at a higher deposition rate and a lower temperature. In the PEALD process, in general, a reactant gas and a reactant plasma are sequentially introduced into a processing chamber having a substrate in the chamber. The first reactant gas is pulsed in the processing chamber and adsorbed onto the surface of the substrate. Thereafter, the reactant plasma is pulsed into the processing chamber and reacts with the first reactant gas to form a deposited material, such as a thin film on a substrate. Similar to the thermal ALD process, a purge step can be performed between the delivery of each reactant.

[0051] As used herein according to one or more embodiments, "plasma enhanced chemical vapor deposition (PECVD)" refers to a technique for depositing thin films on substrates. In a PECVD process, a source material in a gas phase or liquid phase, such as a vapor of a gas phase III-nitride material or a liquid phase III-nitride material, is introduced into a PECVD chamber, where the gas phase or liquid phase III-nitride material has been entrained in a carrier gas. A plasma-induced gas is also introduced into the chamber. The generation of a plasma in the chamber generates excited free radicals. The excited free radicals chemically bond to the surface of the substrate located in the chamber, forming a desired film thereon.

[0052] In one or more embodiments, the μLED array 100 is fabricated by placing the substrate 102 in a metal organic vapor phase epitaxy (MOVPE) reactor such that the μLED array layers are epitaxially grown.

[0053] In one or more embodiments, after growing the first n-type layer 104a, the first light emitting active region 106a is grown. The first light emitting active region 106a is composed of a plurality of quantum wells and may include (one or more) electron blocking layers grown after the quantum wells and a strain control layer grown before the quantum wells. The process of growing the strain control layer may produce V-shaped pit defects before growing the first quantum well. The number of quantum wells typically used for green LEDs ranges from 4 to 12, the typical barrier thickness ranges from 5nm to 25nm, the well thickness ranges from 1nm to 5nm, and the well indium concentration ranges from 15% indium to 25% indium. In some embodiments, the active region may be doped with Si or Ge, while in other embodiments, the active region is undoped. After growing the first light emitting active region 106a, a first p-type layer 108a is grown on the first light emitting active region.

[0054] In one or more embodiments, the first p-type layer 108a and the second p-type layer 108b may independently include any III-V semiconductor, including binary, ternary and quaternary alloys of gallium (Ga), aluminum (Al), indium (In) and nitrogen (N), also known as III-nitride materials. Therefore, in some embodiments, the first p-type layer 108a and the second p-type layer 108b independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (GaAlN), indium gallium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum indium nitride (InAlN), etc. In one or more embodiments, magnesium (Mg) is an acceptor dopant for the first p-type layer 108a. Then, the first tunnel junction 110a is grown, which consists of a heavily doped p-GaN layer and an n-GaN layer, wherein the doping concentration is between 10 19 -10 21 cm -3 The first tunnel junction 110a may also utilize a thin InGaN or graded InGaN layer disposed between highly doped GaN layers.

[0055] In some embodiments, the first p-type layer 108a and the second p-type layer 108b independently include a series of doped p-type layers. In one or more embodiments, the first p-type layer 108a and the second p-type layer 108b independently include gallium nitride (GaN) layers. The first p-type layer 108a and the second p-type layer 108b can be independently doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 108a and the second p-type layer 108b can be independently doped with magnesium (Mg). In one or more embodiments, the first p-type layer 108a and the second p-type layer 108b independently include a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0056] In one or more embodiments, a second n-type layer 104b is grown. To ensure uniform current distribution within the device, it may be advantageous to match the sheet resistance of the first and second n-type layers 104a, 104b, however, non-matched embodiments are possible where the spacing of the first and second sets of contact vias is different, as will be discussed below. In one or more embodiments, the second n-type layer 104b has a thickness of at least 100nm to enable subsequent placement of etched contacts within the layer. An AlGaN layer (not shown) may be embedded within the second n-type layer 104b to facilitate controlled etching to a specific depth.

[0057] After the second n-type layer is grown, the second tunnel junction 110b is grown. The design of the second tunnel junction may be the same as or different from the first tunnel junction 110a.

[0058] In one or more embodiments, after the second tunnel junction 110b is grown, the second p-type layer 108b is grown, followed by the second light-emitting active region 106b. The general range of parameter limits is the same for the second light-emitting active region 106b as for the first light-emitting active region 106a, however, some differences in specific details may be required to obtain similar characteristics for the first and second active regions with opposite polarities. It is desirable to match their characteristics to ensure that for a given voltage, the current flowing through the first and second active regions is similar.

[0059] In one or more embodiments, the epitaxy ends with the growth of the third n-type layer 104c. Figure 3 and Figure 4 In the embodiment depicted in , the third n-type layer 104c is not a current spreading layer, and therefore it may be grown with a lower thickness and doping than the first two n-type layers.

[0060] Figure 3 Shows that Figure 1A cross-sectional schematic diagram of a first variant 100 after processing into a thin film flip chip (TFFC) die design. The die design has electrical contacts so that the "middle" n-type layer of the structure is the common cathode (or common anode) to all two pn junctions in the stack. It is used Figure 1 The first variant A 100 has a common anode and is used Figure 2 The second variant B200 has a common cathode. Figure 3 and Figure 4 An example of a possible thin film flip chip (TFFC) die design is shown in . In one or more embodiments, an additional set of contact vias is required that is not required in a standard LED die (or cascaded LED), however, the EQE drop and voltage advantages of sharing current through two active areas can outweigh the disadvantage of losing some active area due to the additional vias.

[0061] After epitaxial growth, the wafer is processed through the following manufacturing steps to produce the current Figure 3 LED die in cross section as shown in . For growth on patterned sapphire substrates, the last step on the list can be omitted. The main difference between the standard TFFC die design and the design of one or more embodiments herein is the second set of vias required to contact the second n-type layer 104b.

[0062] refer to Figure 3 , two sets of vias 120a, 120b are dry etched to form the TFFC die design 150. The vias 120a, 120b have different depths D1, D2. In one or more embodiments, D2 may range from 0.1 micron to 1.0 micron, and D1 may range from 0.4 micron to 3 microns.

[0063] In one or more embodiments, Figure 1 The epitaxial stack of is first subjected to an acceptor activation anneal. In some embodiments, it is preferred to perform an acceptor activation anneal after dry etching in order to allow hydrogen to escape from the buried p-type layer through the via sidewalls.

[0064] In one or more embodiments, a conformal dielectric layer 112 is deposited in the through holes 120a, 120b. As used herein, the term "dielectric" refers to an electrical insulator material that can be polarized by an applied electric field. In one or more embodiments, the dielectric layer includes, but is not limited to: oxides, such as silicon oxide (SiO2), aluminum oxide (Al2O3); nitrides, such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer includes a multilayer of silicon nitride (Si3N4), silicon oxide (SiO2), or silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric layer is non-stoichiometric relative to an ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbide (SiOC)) and nitrogen oxides (e.g., silicon oxycarbonitride (SiNCO)).

[0065] Still refer to Figure 3 In one or more embodiments, a portion of the dielectric layer 112 is removed by dry etching to form contact openings 122, 124. A cathode metal layer 116 is deposited in the contact opening 122 in the deeper through hole 120a along the sidewalls of the through hole 120a. The cathode metal layer 116 may include any suitable material known to those skilled in the art. In one or more embodiments, the cathode metal layer 116 is any high reflectivity metal that makes ohmic contact with the n-type layer. In one or more specific embodiments, the cathode metal layer 116 includes an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0066] In one or more embodiments, the anode metal layer 118 is deposited in the contact opening 124 in the shallower through hole 120b along the sidewall of the through hole 120b. The anode metal layer 118 may include any suitable material known to those skilled in the art. In one or more embodiments, the anode metal layer 118 is any high reflectivity metal that makes ohmic contact with the n-type layer. In some embodiments, the anode metal layer 118 and the cathode metal layer 116 include the same material and are deposited in the same step and patterned using techniques such as stripping or dry etching. In one or more specific embodiments, the anode metal layer 118 includes an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0067] In one or more embodiments, a bonding metal layer 114 is deposited in the contact openings 122, 124. In some embodiments, the bonding metal layer 114 is a metal layer of different composition that is thicker than the cathode metal layer 116 and the anode metal layer 118 to facilitate subsequent bonding to the substrate. In one or more embodiments, the metal of the bonding metal layer 114 can be composed of any suitable material known to those skilled in the art. In one or more embodiments, the bonding metal layer 114 includes one or more of titanium (Ti) and gold (Au).

[0068] refer to Figure 3 In one or more embodiments, the die is singulated. The die is then bonded to substrate 126 using a technique such as gold-gold interconnect bonding. The final step is laser lift-off followed by photoelectrochemical etching to texture surface 128.

[0069] Figure 2 A cross-sectional schematic diagram of an alternative epitaxial configuration 200 "Configuration B" is shown according to one or more alternative embodiments. Additional aspects of the present disclosure relate to a method of manufacturing a thin film flip chip (TFFC) device from an epitaxial configuration, such as Figure 4 as shown in .

[0070] refer to Figure 2 , a dual active region LED 200 is manufactured by forming a plurality of Group III nitride layers on a substrate 202 to form two pn junction LEDs (which include light emitting active regions) on the substrate. The two pn junctions are connected in parallel. The light emitting active regions include a first light emitting active region 206a and a second light emitting active region 206b. Any order of stacking different active regions is within the scope of the present disclosure.

[0071] According to some specific embodiments, the dual active region LED 200 includes a first light emitting stack 205a, the first light emitting stack 205a having a first n-type layer 204a formed on a substrate 202, a first tunnel junction 210a formed on the first n-type layer 204a, a first p-type layer 208a formed on the first tunnel junction 210a, and a first light emitting active region 206a grown on the first p-type layer 208a.

[0072] In one or more embodiments, the first light emitting active region 206a is a green light emitting active region. In the embodiment shown, on the first junction, in particular on the first n-type layer 204a, there is a first tunnel junction 210a.

[0073] Still refer to Figure 2, the dual active area LED 200 further includes a second light emitting stack 205b on the first light emitting stack 205a. The second light emitting stack 205b includes a second n-type layer 204b on the first light emitting active area 206a, a second light emitting active area 206b on the second n-type layer 204b, and a second p-type layer 208b on the second light emitting active area 206b. In one or more embodiments, the second light emitting active area 206b is also a green light emitting active area.

[0074] In one or more embodiments, a nucleation layer (not shown) and a dislocation density control layer (not shown) are grown on a suitable substrate 202 (such as patterned or non-patterned sapphire). In one or more embodiments, the nucleation layer comprises a Group III nitride material. In a specific embodiment, the nucleation layer comprises gallium nitride (GaN) or aluminum nitride (AlN).

[0075] In one or more embodiments, the first n-type layer 204a is grown on the substrate 202, the nucleation layer and / or the dislocation density control layer. In one or more embodiments, the first n-type layer 204a is formed on the substrate 202. The substrate 202 can be any substrate known to those skilled in the art, which is configured to be used in the formation of an LED device. In one or more embodiments, the substrate 202 includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate 202 is a transparent substrate. In a specific embodiment, the substrate 202 includes sapphire. In one or more embodiments, the substrate 202 is not patterned before forming the LED. Therefore, in some embodiments, the substrate 202 is not patterned and can be considered to be flat or substantially flat. In other embodiments, the substrate 202 is a patterned substrate.

[0076] In one or more embodiments, the first n-type layer 204a and the second n-type layer 204b may include any III-V semiconductor, including binary, ternary and quaternary alloys of gallium (Ga), aluminum (Al), indium (In) and nitrogen (N), also known as III-nitride materials. Therefore, in some embodiments, the first n-type layer 204a and the second n-type layer 204b independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a specific embodiment, the first n-type layer 204a and the second n-type layer 204b include gallium nitride (GaN). In one or more embodiments, the first n-type layer 204a and the second n-type layer 204b are independently doped with n-type dopants, such as silicon (Si) or germanium (Ge). In one or more embodiments, the dopant concentration is from 1e17 to 2e19 cm 3 In one or more embodiments, the first n-type layer 204a may have a thickness in the range from 1 μm to 3 μm to ensure a wide process margin for a subsequent etching step for contacting the layer.

[0077] In one or more embodiments, the dual active region LED 200 is fabricated by placing the substrate 202 in a metal organic vapor phase epitaxy (MOVPE) reactor such that the dual active region LED layers are epitaxially grown.

[0078] In one or more embodiments, after the growth of the first n-type layer 204a, the first tunnel junction 210a is grown, followed by the growth of the first p-type layer 208a. In one or more embodiments, the first tunnel junction 110a is composed of a heavily doped p-GaN layer and an n-GaN layer, wherein the doping concentration is between 10 and 20%. 19 -10 21 cm -3and the layer thickness is generally less than 50 nm. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b may independently include any III-V semiconductor, including binary, ternary and quaternary alloys of gallium (Ga), aluminum (Al), indium (In) and nitrogen (N), also known as III-nitride materials. Therefore, in some embodiments, the first p-type layer 208a and the second p-type layer 208b independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum indium nitride (InAlN), etc. In one or more embodiments, magnesium (Mg) is an acceptor dopant for the first p-type layer 208a.

[0079] In some embodiments, the first p-type layer 208a and the second p-type layer 208b independently include a series of doped p-type layers. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b independently include gallium nitride (GaN) layers. The first p-type layer 208a and the second p-type layer 208b can be independently doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b can be independently doped with magnesium (Mg). In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b independently include a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0080] The first light emitting active region 206a is then grown. The first light emitting active region 206a consists of a plurality of quantum wells and may include (one or more) electron blocking layers grown after the quantum wells and a strain control layer grown before the quantum wells. The process of growing the strain control layer may produce V-shaped pit defects before growing the first quantum well. The number of quantum wells typically used for green LEDs ranges from 4 to 12, typical barrier thicknesses range from 5nm to 25nm, well thicknesses range from 1nm to 5nm, and well indium concentrations range from 15% indium to 25% indium. In some embodiments, the active region may be doped with Si or Ge, while in other embodiments, the active region is undoped.

[0081] In one or more embodiments, the second n-type layer 204a is grown on the first light emitting active region 206a. To ensure uniform current distribution within the device, it may be advantageous to match the sheet resistance of the first and second n-type layers 204a, 204b, however, non-matching embodiments are possible where the spacing of the first and second sets of contact vias is different, as will be discussed below. In one or more embodiments, the second n-type layer 204b has a thickness of at least 100nm so that etching contacts can be subsequently placed within the layer. An AlGaN layer (not shown) may be embedded within the second n-type layer 204b to facilitate controlled etching to a specific depth.

[0082] After the second n-type layer 204b is grown, the second light emitting active region 206b is grown, followed by the second p-type layer 208b. The general range of parameter limits is the same for the second light emitting active region 206b as for the first light emitting active region 206a, however, some differences in specific details may be required to obtain similar characteristics for the first and second active regions with opposite polarities. It is desirable to ensure that, for a given voltage, the current flowing through the first and second active regions is similar.

[0083] Figure 4 Shows that Figure 2 A cross-sectional view of a second variant 200 of a thin film flip chip (TFFC) die design. After epitaxial growth, the wafer is processed through the following manufacturing steps to produce the present Figure 4 LED die in cross section as shown in . For growth on patterned sapphire substrates, the last step on the list can be omitted. The main difference between the standard TFFC die design and the design of one or more embodiments herein is the second set of vias required to contact the second n-type layer 204b.

[0084] refer to Figure 4 , two sets of vias 220a, 220b are dry etched to form the TFFC die design 250. The vias 220a, 220b have different depths D1, D2. In one or more embodiments, D2 may range from 0.1 micron to 1.0 micron, and D1 may range from 0.4 micron to 3 microns.

[0085] In one or more embodiments, Figure 2 The epitaxial stack of is first subjected to an acceptor activation anneal. In some embodiments, it is preferred to perform an acceptor activation anneal after dry etching in order to allow hydrogen to escape from the buried p-type layer through the via sidewalls.

[0086] In one or more embodiments, a conformal dielectric layer 212 is deposited in the through holes 220a, 220b. In one or more embodiments, the dielectric layer includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3); nitrides such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer includes silicon nitride (Si3N4), silicon oxide (SiO2), or a multilayer of silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric layer is non-stoichiometric relative to an ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbide (SiOC)), and nitrogen oxides (e.g., silicon oxycarbonitride (SiNCO)).

[0087] Still refer to Figure 4 In one or more embodiments, a portion of the dielectric layer 212 is removed by dry etching to form contact openings 222 and 224. A cathode metal layer 216 is deposited in the contact opening 224 in the deeper through hole 220a along the sidewalls of the through hole 220a. The cathode metal layer 216 may include any suitable material known to those skilled in the art. In one or more embodiments, the cathode metal layer 216 is any high reflectivity metal that makes ohmic contact with the n-type layer. In one or more specific embodiments, the cathode metal layer 216 includes an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0088] In one or more embodiments, the anode metal layer 218 is deposited in the contact opening 222 in the shallower through hole 220b along the sidewall of the through hole 220b. The anode metal layer 218 may include any suitable material known to those skilled in the art. In one or more embodiments, the anode metal layer 218 is any high reflectivity metal that makes ohmic contact with the n-type layer. In some embodiments, the anode metal layer 218 and the cathode metal layer 216 include the same material and are deposited in the same step and patterned using techniques such as stripping or dry etching. In one or more specific embodiments, the anode metal layer 218 includes an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0089] In one or more embodiments, a bonding metal layer 214 is deposited in the contact openings 222, 224. In some embodiments, the bonding metal layer 214 is a metal layer of different composition that is thicker than the cathode metal layer 216 and the anode metal layer 218 to facilitate subsequent bonding to the substrate. In one or more embodiments, the metal of the bonding metal layer 214 can be composed of any suitable material known to those skilled in the art. In one or more embodiments, the bonding metal layer 214 includes one or more of titanium (Ti) and gold (Au).

[0090] refer to Figure 4 In one or more embodiments, the die is singulated. The die is then bonded to substrate 226 using a technique such as gold-gold interconnect bonding. The last step is laser lift-off followed by photoelectrochemical etching to texture surface 228.

[0091] Figure 5 After being processed into a lateral die 275 Figure 2 20. In one or more embodiments, the lateral die 275 includes a dual active area LED having a first light emitting stack 205a, the first light emitting stack 205a having a first n-type layer 204a formed on the substrate 202, a first tunnel junction 210a formed on the first n-type layer 204a, a first p-type layer 208a formed on the first tunnel junction 210a, and a first light emitting active area 206a grown on the first p-type layer 208a, and a second junction 205b on the first light emitting stack 205a. The second light emitting stack 205b includes a second n-type layer 204b on the first light emitting active area 206a, a second light emitting active area 206b on the second n-type layer 204b, and a second p-type layer 208b on the second light emitting active area 206b.

[0092] In one or more embodiments, the cathode metal layer 216 extends from the second n-type layer 204b to the second p-type layer 208b. In some embodiments, the cathode metal layer 216 is not in electrical contact with the second p-type layer because the dielectric layer 212 is adjacent to the tube core and the cathode metal layer 216. In other embodiments not shown, the cathode metal layer 216 does not extend all the way to the top of the tube core. Extending the cathode metal layer 216 to the top allows additional space to include the wire bonding pad 232, thereby maintaining the narrow width of the cathode metal layer 216 on the mesa side of the tube core. The cathode metal layer 216 may include any suitable metal known to those skilled in the art. In one or more specific embodiments, the cathode metal layer 216 includes an n-contact material selected from one or more of silver (Ag) and aluminum (Al).

[0093] In one or more embodiments, the anode contact 218 is formed on the top surface of the second p-type layer 208b and extends to the first n-type layer 104a. The anode contact 218 may include any suitable material known to those skilled in the art. In one or more embodiments, the anode contact includes transparent indium tin oxide (ITO).

[0094] In one or more embodiments, a dielectric layer 212 is formed on the die 275 to isolate the die from one or more of the anode contact 218 and the cathode metal layer 216. In one or more embodiments, the dielectric layer 212 includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3); nitrides such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer includes silicon nitride (Si3N4), silicon oxide (SiO2), or a multilayer of silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric layer 212 is non-stoichiometric relative to an ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbide (SiOC)), and nitrogen oxides (e.g., silicon oxycarbonitride (SiNCO)).

[0095] In one or more embodiments, the lateral die 275 is mounted to the substrate 226. The wire 230a may connect the positive terminal 232 of the substrate 226 to the die 275. The wire 230b may connect the negative terminal 234 of the substrate 226 to the die 275.

[0096] Figure 6 A process flow diagram of a method 60 of manufacturing a dual active area LED die according to one or more embodiments is shown. In the method, at operation 62, two pn junctions are epitaxially and sequentially grown on the same epitaxial wafer. At operation 64, a metal contact is formed on the second pn junction.

[0097] Figure 7 A process flow diagram of a method 50 for manufacturing a thin film flip chip (TFFC) die design according to one or more embodiments of the present disclosure is shown. Figure 7In one or more embodiments, the method begins at operation 52: forming an epitaxial stack by sequentially forming two pn junctions on the same epitaxial wafer, the epitaxial stack comprising at least one n-type layer and at least one p-type layer, and having a light-emitting active region embedded between at least one n-type layer and at least one p-type layer. At operation 54, two sets of through holes of different depths are dry-etched into the epitaxial stack. At operation 56, a dielectric layer is conformally deposited in the through hole. At operation 58, a portion of the dielectric layer is removed to form a contact opening in the through hole, which exposes at least one n-type layer. At operation 60, cathode metal and anode metal are deposited in the through hole on the dielectric layer. At operation 62, a bonding metal layer is deposited. At operation 64, die singulation is performed. At operation 66, the die is bonded to a substrate. At operation 68, laser lift-off is performed.

[0098] Figure 8 An example of a common device according to some embodiments is shown. Device 600 may be, for example: a mobile device such as a laptop computer (PC), a tablet PC, a smart phone, or augmented reality (AR) / virtual reality (VR); or an automotive device. Various elements may be provided on the backplane described above, while other elements may be local or remote. As described herein, an example may include logic or several components, modules, or mechanisms, or may operate on several components, modules, or mechanisms.

[0099] Modules and components are tangible entities (e.g., hardware) that can perform specified operations and can be configured or arranged in a certain manner. In one example, circuits can be arranged as modules in a specified manner (e.g., internally or relative to external entities such as other circuits). In one example, all or part of one or more computer systems (e.g., independent, client or server computer systems) or one or more hardware processors can be configured by firmware or software (e.g., instructions, application parts, or applications) as modules for performing specified operations. In one example, the software can reside on a machine-readable medium. In one example, the software, when executed by the underlying hardware of the module, causes the hardware to perform the specified operation.

[0100] Thus, the term "module" (and "component") should be understood to encompass a tangible entity, i.e., a physically constructed, specially configured (e.g., hardwired), or temporarily (e.g., temporarily) configured (e.g., programmed) entity that operates in a specified manner or performs part or all of any of the operations described herein. Considering an example where a module is temporarily configured, each module need not be instantiated at any one time. For example, where a module includes a general-purpose hardware processor configured using software, the general-purpose hardware processor can be configured into corresponding different modules at different times. The software can configure the hardware processor accordingly, for example, to constitute a particular module at one time and to constitute different modules at different times.

[0101] The electronic device 600 may include a hardware processor (or equivalent processing circuit) 602 (e.g., a central processing unit (CPU), a GPU, a hardware processor core, or any combination thereof), a memory 604 (which may include a main memory and a static memory), some or all of which may communicate with each other via an interconnect (e.g., a bus) 608. The memory 604 may include any or all of removable and non-removable storage, volatile memory, or non-volatile memory. The electronic device 600 may also include a display / light source 610 (such as the above-mentioned LED or video display), an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In one example, the display / light source 610, the input device 612, and the UI navigation device 614 may be a touch screen display. The electronic device 600 may additionally include a storage device (e.g., a drive unit) 616, a signal generating device 618 (e.g., a speaker), a network interface device 620, one or more cameras 628, and one or more sensors 630 (such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors such as those described herein). The electronic device 600 may also include an output controller, such as a serial connection (e.g., a universal serial bus (USB)), a parallel connection, or other wired or wireless connections (e.g., infrared (IR), near field communication (NFC), etc.), to communicate or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0102] The storage device 616 may include a non-transitory machine-readable medium 622 (hereinafter referred to as a machine-readable medium) on which is stored one or more sets of data structures or instructions 624 (e.g., software) that embody or are used by any one or more of the techniques or functions described herein. The instructions 624 may also reside completely or at least partially within the memory 604 and / or within the hardware processor 602 during execution of the instructions 624 by the electronic device 600. Although the machine-readable medium 622 is shown as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store one or more instructions 624.

[0103] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by the electronic device 600 and causing the electronic device 600 to perform any one or more of the techniques of the present disclosure; or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. Specific examples of machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as built-in hard disks and removable disks; magneto-optical disks; random access memory (RAM); and CD-ROM and DVD-ROM disks.

[0104] Instructions 624 can also be transmitted or received by any one of several wireless local area network (WLAN) transmission protocols or SPI or CAN bus via network interface device 620 using transmission medium 626 through a communication network. Example communication networks may include local area networks (LAN), wide area networks (WAN), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), simple old telephone (POTS) networks, and wireless data networks. The communication over the network may include one or more different protocols, such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi, the IEEE 802.16 family of standards known as WiMax, the IEEE 802.16.4 family of standards, the long-term evolution (LTE) family of standards, the universal mobile telecommunications system (UMTS) family of standards, peer-to-peer (P2P) networks, next generation (NG) / sixth generation (6G) standards, etc. In one example, the network interface device 620 may include one or more physical jacks (e.g., Ethernet jacks, coaxial jacks, or telephone jacks) or one or more antennas to connect to the transmission medium 626.

[0105] Note that the term "circuit" as used herein refers to, is part of, or includes a hardware component, such as an electronic circuit, a logic circuit, a processor (shared, dedicated, or group) and / or a memory (shared, dedicated, or group), an application specific integrated circuit (ASIC), a field programmable device (FPD) (e.g., a field programmable gate array (FPGA), a programmable logic device (PLD), a complex PLD (CPLD), a high capacity PLD (HCPLD), a structured ASIC, or a programmable SoC), a digital signal processor (DSP), etc., which is configured to provide the described functions. In some embodiments, the circuit can execute one or more software or firmware programs to provide at least some of the described functions. The term "circuit" may also refer to a combination of one or more hardware elements (or a combination of circuits used in an electrical or electronic system) and a program code for performing the functions of the program code. In these embodiments, the combination of hardware elements and program code may be referred to as a specific type of circuit.

[0106] As used herein, the term "processor circuit" or "processor" therefore refers to, is part of, or includes a circuit that is capable of sequentially and automatically performing a series of arithmetic or logical operations or recording, storing, and / or transmitting digital data. The term "processor circuit" or "processor" may refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single-core or multi-core processor, and / or any other device capable of executing or otherwise operating computer-executable instructions (such as program code, software modules, and / or functional processes).

[0107] The camera 628 can sense light of one or more wavelengths emitted by at least the LED. The camera 628 can include an optical device (e.g., at least one camera lens) that can collect reflected light of the illumination reflected from and / or emitted by the illumination area. The camera lens can direct the reflected light onto a multi-pixel sensor (also referred to as a light sensor) to form an image on the multi-pixel sensor.

[0108] The processor 602 can control and drive the LEDs via one or more drivers. For example, the processor 602 can optionally control one or more LEDs in the LED array independently of one or more LEDs in the LED array to illuminate an area in a specified manner.

[0109] Additionally, sensor 630 may be incorporated into camera 628 and / or light source 610. Sensor 630 may sense visible light and / or infrared light, and in addition to receiving reflected light from the LEDs, may also sense ambient light and / or changes / flickering in ambient light. Similar to an LED array, a sensor may have one or more segments (which may be capable of sensing the same wavelength / range of wavelengths or different wavelengths / ranges of wavelengths).

[0110] Fig. 9 An example lighting system according to some embodiments is shown. As described above, some elements shown in lighting system 700 may not be present, while other additional elements may be provided in lighting system 700. Lighting system 700 may include a controller 702 that controls lighting using a pixel array 710 including a plurality of individual pixels 712.

[0111] In some embodiments, some or all of the components described as controller 702 may be disposed on a backplane, such as, for example, a complementary metal oxide semiconductor (CMOS) backplane. Controller 702 may be coupled to or include one or more processors 704. Processor 704 may receive image data (in frames) via an interface, and may process the image data to control generator 706a, e.g., to control an analog signal or PWM duty cycle and / or on time, so that illumination system 700 generates an image indicated by the image data.

[0112] The controller 702 may further include a frame buffer 708. The frame buffer 708 may store one or more images prior to the one or more processors 704 and store instructions for implementation by the one or more processors 704.

[0113] The generator 706a can be controlled by the processor 704 and can generate a driving signal according to the instructions. The generator 706a can be connected to the driver 706b to drive the pixel array 710 so that the pixels 712 provide the desired light intensity.

[0114] Each pixel 712 can include one or more LEDs 714. LEDs 714 can be different colors and can be controlled individually or in groups. As shown, for each pixel 712 or LED 714, pixel 712 can include a PWM switch and a current source. Pixel 712 can be driven by driver 706b. The signal from generator 706a can cause the switch to open and close according to the value of the signal. The signal corresponding to the light intensity can cause the current source to generate current, thereby causing the pixel 712 to produce the corresponding light intensity.

[0115] The lighting system 700 may further include a power source 720. In some embodiments, the power source 720 may be a battery that generates power for the controller 702.

[0116] Fig.10 An example hardware arrangement for implementing the above disclosed subject matter according to some embodiments is shown. In particular, the hardware arrangement 800 may include an LED die 802, which includes (one or more) LED arrays and a backplane, such as a CMOS backplane 804. The LED die 802 may be coupled to the CMOS backplane 804 via one or more interconnects 810, wherein the interconnects 810 may provide signal transmission between the LED die 802 and the CMOS backplane 804. The interconnects 810 may include one or more solder bump joints, one or more copper pillar bump joints, other types of interconnects known in the art, or some combination thereof.

[0117] The LED die 802 may include circuits for implementing the above-described LED array. In particular, the LED die 802 may include a plurality of LEDs. The LED die 802 may include a shared active layer and a shared substrate for the LED array, and thereby the LED array may be a monolithic LED array. Each LED of the LED array may include a separate segmented active layer and / or substrate. In some embodiments, the LED die 802 may further include a switch and a current source to drive the LED array as described above. In other embodiments, the switch and the current source may be included in the CMOS backplane 804. The LED may be a micro-LED or an LED larger than a micro-LED.

[0118] The CMOS backplane 804 may include circuits for implementing the control module. The CMOS backplane 804 may provide a driving signal and an intensity signal to the LED array using the interconnect 810 so that the LED array generates light according to the signal and the intensity.

[0119] The hardware arrangement 800 may further include a PCB 806. The PCB 806 may include circuits for implementing the various functions described herein. The PCB 806 may be coupled to the CMOS backplane 804. For example, the PCB 806 may be coupled to the CMOS backplane 804 via one or more wire bonds 812. The PCB 806 and the CMOS backplane 804 may exchange image data, power, and / or feedback, among other signals, via the coupling.

[0120] As shown, the LEDs and the circuits supporting the LED arrays can be packaged and include a substrate or printed circuit board for powering the LEDs and controlling the light produced by the LEDs. The PCB supporting the LED array may include electrical vias, heat sinks, ground planes, electrical traces, and flip-chip or other mounting systems. The substrate or PCB may be formed of any suitable material (e.g., ceramic, silicon, aluminum, etc.). If the substrate material is conductive, an insulating layer may be formed over the substrate material, and a metal electrode pattern may be formed over the insulating layer to contact the micro LED array. The substrate may act as a mechanical support, thereby providing an electrical interface between the electrodes on the LED array and the power supply, and also providing a heat sink function.

[0121] In general, LED arrays can support a variety of applications. Such applications can include independent applications that provide general lighting (e.g., inside a room or vehicle or outside a room or vehicle) or provide specific images. In addition to devices such as lamps, projectors, mobile devices, the system can also be used to provide AR and VR-based applications. Visualization systems (such as VR systems and AR systems) are becoming more and more popular in many fields such as entertainment, education, medicine, and business. Various types of devices can be used to provide AR / VR to users, including headphones, glasses, and projectors. Such AR / VR systems may include components similar to those described above: micro-LED arrays, displays or screens (which may include touch screen elements), micro-LED array controllers, sensors, and controllers, and the like. AR / VR components may be arranged in a single structure, or one or more of the components shown may be installed separately and connected via wired or wireless communications. Power and user data may be provided to the controller. User data input may include information provided by audio instructions, tactile feedback, eye or pupil positioning, or a connected keyboard, mouse, or game controller. Sensors may include cameras, depth sensors, audio sensors, accelerometers, two-axis or three-axis gyroscopes, and other types of motion and / or environmental / wearer sensors that provide user input data. Other sensors may include, but are not limited to, air pressure, strain sensors, temperature sensors, or any other suitable sensor for local or remote environmental monitoring. In some embodiments, control inputs may include detected touches or taps, gesture inputs, or controls based on the position of headphones or displays. As another example, an estimated position of the AR / VR system relative to an initial position may be determined based on one or more measurement signals from one or more gyroscopes or position sensors that measure translational or rotational movement.

[0122] In some embodiments, the controller can control individual micro LEDs or one or more groups of LEDs to display content (AR / VR and / or non-AR / VR) to the user, while controlling other LEDs and sensors used in eye tracking to adjust the displayed content. The content display LEDs can be designed to emit light in the visible light band (approximately 400nm to 780nm), while the LEDs used for tracking can be designed to emit light in the IR band (approximately 780nm to 2200nm). In some embodiments, the tracking LEDs and content LEDs can be activated simultaneously. In some embodiments, the tracking LEDs can be controlled to emit tracking light during time periods when the content LEDs are deactivated and therefore no content is displayed to the user. The AR / VR system can be combined with optical devices (such as the optical devices described above) and / or AR / VR displays, for example to couple light emitted by the LED array to the AR / VR display.

[0123] In some embodiments, the AR / VR controller can use data from the sensor to time-integrate the measurement signal received from the accelerometer to estimate the velocity vector, and time-integrate the velocity vector to determine the estimated position of the reference point of the AR / VR system. In other embodiments, the reference point used to describe the position of the AR / VR system can be based on a depth sensor, a camera positioning view, or a light field flow. Based on changes in the position, orientation, or movement of the AR / VR system, the system controller can send an image or instruction to the light array controller. Changes or modifications to the image or instruction can also be made through user data input or automatic data input.

[0124] Generally speaking, in a VR system, a display can present a view of a scene (such as a three-dimensional scene) to a user. The user can move within the scene, such as by repositioning the user's head or by walking. The VR system can detect the user's movement and change the view of the scene to account for the movement. For example, when the user rotates the user's head, the system can present a view of the scene that changes in the view direction to match the user's gaze. In this way, the VR system can simulate the user's presence in the three-dimensional scene. In addition, the VR system can receive tactile sensory input such as from a wearable position sensor, and can optionally provide tactile feedback to the user.

[0125] On the other hand, in an AR system, the display can incorporate elements from the user's surroundings into the view of the scene. For example, an AR system can add text subtitles and / or visual elements to the view of the user's surroundings. For example, a retailer can use an AR system to show a user what a piece of furniture would look like in a room in the user's home by combining a visualization of the piece of furniture on top of a captured image of the user's surroundings. As the user walks around the user's room, the visualization interprets the user's movements and changes the visualization of the furniture in a manner consistent with the movement. For example, an AR system can place a virtual chair in a room. The user can stand in front of the virtual chair location in the room to view the front of the chair. The user can move to the area behind the virtual chair location in the room to view the back of the chair. In this way, the AR system can add elements to the dynamic view of the user's surroundings.

[0126] Fig.11 A block diagram of an example of a system according to some embodiments is shown. The system 900 may use micro-LEDs to provide AR / VR functionality. The system 900 may include a wearable housing 912, such as a headset or goggles. The housing 912 may mechanically support and accommodate the elements detailed below. In some examples, one or more of the elements detailed below may be included in one or more additional housings that may be separated from the wearable housing 912 and may be coupled to the wearable housing 912 wirelessly and / or via a wired connection. For example, a separate housing may reduce the weight of the wearable goggles, such as by including batteries, radios, and other elements. The housing 912 may include one or more batteries 914 that may power any or all of the elements detailed below. The housing 912 may include a circuit that may be electrically coupled to an external power source, such as a wall outlet, to charge the battery 914. The housing 912 may include one or more radios 916 to wirelessly communicate with a server or network via a suitable protocol, such as WiFi.

[0127] The system 900 may include one or more sensors 918, such as optical sensors, audio sensors, tactile sensors, thermal sensors, gyroscope sensors, time-of-flight sensors, triangulation-based sensors, and the like. In some examples, one or more of these sensors may sense the location, position, and / or orientation of the user. In some examples, one or more sensors 918 may generate sensor signals in response to the sensed location, position, and / or orientation. The sensor signal may include sensor data corresponding to the sensed location, position, and / or orientation. For example, the sensor data may include a depth map of the surrounding environment. In some examples, such as for an AR system, one or more sensors 918 may capture real-time video images of the surrounding environment near the user.

[0128] The system 900 may include one or more video generation processors 920. One or more video generation processors 920 may receive scene data representing a three-dimensional scene, such as a set of position coordinates of an object in the scene or a depth map of the scene. The data may be received from a server and / or a storage medium. One or more video generation processors 920 may receive one or more sensor signals from one or more sensors 918. In response to scene data representing the surrounding environment and at least one sensor signal representing the location and / or orientation of the user relative to the surrounding environment, one or more video generation processors 920 may generate at least one video signal corresponding to a view of the scene. In some examples, one or more video generation processors 920 may generate two video signals, one for each eye of the user, the two video signals representing views of the scene from the perspective of the left eye and right eye of the user, respectively. In some examples, one or more video generation processors 920 may generate more than two video signals, and combine these video signals to provide one video signal for both eyes, two video signals for both eyes, or other combinations.

[0129] The system 900 may include one or more light sources 922 that can provide light for a display of the system 900. For example, a suitable light source 922 may include the micro-LEDs described above. The one or more light sources 922 may include light emitting elements having different colors or wavelengths. For example, the light source may include a red light emitting diode that can emit red light, a green light emitting diode that can emit green light, and a blue light emitting diode that can emit blue light. The red light, green light, and blue light are combined in a specific ratio to produce any suitable color that is visually perceptible in the visible portion of the electromagnetic spectrum.

[0130] The system 900 may include one or more modulators 924. The modulator 924 may be implemented in one of at least two configurations. In the first configuration, the modulator 924 may include a circuit that can directly modulate the light source 922. For example, the light source 922 may include an array of light emitting diodes, and the modulator 924 may directly modulate the electrical power, voltage, and / or current directed to each light emitting diode in the array to form modulated light. The modulation may be performed in an analog manner and / or in a digital manner. In some examples, the light source 922 may include an array of red light emitting diodes, an array of green light emitting diodes, and an array of blue light emitting diodes, and the modulator 924 may directly modulate the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes to form modulated light to produce a particular image.

[0131] In a second configuration, the modulator 924 may include a modulation panel, such as a liquid crystal panel. The light source 922 may generate uniform illumination or near uniform illumination to illuminate the modulation panel. The modulation panel may include pixels. Each pixel may selectively attenuate a corresponding portion of the modulation panel area in response to an electrical modulation signal to form modulated light. In some examples, the modulator 924 may include a plurality of modulation panels that may modulate light of different colors. For example, the modulator 924 may include a red modulation panel that may attenuate red light from a red light source (such as a red light emitting diode), a green modulation panel that may attenuate green light from a green light source (such as a green light emitting diode), and a blue modulation panel that may attenuate blue light from a blue light source (such as a blue light emitting diode).

[0132] In some examples of the second configuration, the modulator 924 can receive uniform white light or nearly uniform white light from a white light source (such as a white light emitting diode). The modulation panel can include a wavelength selective filter on each pixel of the modulation panel. The panel pixels can be arranged in groups (such as three or four groups), where each group can form a pixel of a color image. For example, each group can include a panel pixel with a red filter, a panel pixel with a green filter, and a panel pixel with a blue filter. Other suitable configurations can also be used.

[0133] The system 900 may include one or more modulation processors 926 that may receive a video signal (such as from one or more video generation processors 920) and in response may generate an electrical modulation signal. For configurations in which the modulator 924 directly modulates the light source 922, the electrical modulation signal may drive the modulator 924. For configurations in which the modulator 924 includes a modulation panel, the electrical modulation signal may drive the modulation panel.

[0134] The system 900 may include one or more beam combiners 928 (also referred to as beam splitters) that may combine light beams of different colors to form a single polychromatic light beam. For configurations in which the light source 922 may include a plurality of light emitting diodes of different colors, the system 900 may include one or more wavelength-sensitive (e.g., dichroic) beam combiners 928 that may combine light of different colors to form a single polychromatic light beam.

[0135] The system 900 can direct the modulated light toward the eyes of the observer in one of at least two configurations. In the first configuration, the system 900 can be used as a projector and can include suitable projection optics 930 that can project the modulated light onto one or more screens 932. The screen 932 can be positioned at a suitable distance from the user's eyes. The system 900 can optionally include one or more lenses 934 that can position the virtual image of the screen 932 at a suitable distance from the eyes, such as a close-focus distance, such as 500mm, 750mm, or another suitable distance. In some examples, the system 900 can include a single screen 932 so that the modulated light can be directed toward both eyes of the user. In some examples, the system 900 can include two screens 932 so that the modulated light from each screen 932 can be directed toward the corresponding eye of the user. In some examples, the system 900 can include more than two screens 932. In the second configuration, the system 900 can direct the modulated light directly into one or both eyes of the observer. For example, projection optics 930 may form an image on the retina of one eye of a user, or may form an image on each retina of both eyes of a user.

[0136] For some configurations of the AR system, system 900 may include a display that is at least partially transparent so that the user can view the user's surroundings through the display. For such configurations, the AR system can generate modulated light corresponding to an enhancement of the surroundings, rather than the surroundings themselves. For example, in an example where a retailer displays chairs, the AR system can direct modulated light corresponding to the chairs, rather than the rest of the room, toward the screen or toward the user's eyes.

[0137] Fig.12 An example method of making a lighting device according to some embodiments is shown. Not all operations may be performed in method 1000, and / or there may be additional operations. These operations may be performed in different Fig.12 The order in which they occur is indicated in the order in which they occur.

[0138] At operation 1002, a temporary substrate is attached to an initial structure including a sapphire substrate and epitaxial layers including an n-type semiconductor layer, a p-type semiconductor layer, and an active region. If a TCO layer may have been deposited on the initial structure, the temporary substrate is attached to the TCO layer.

[0139] At operation 1004, the sapphire substrate is etched or otherwise removed, and the n-type semiconductor layer is etched such that the thickness of the remaining epitaxial layer is significantly less than the thickness of the initial structure.

[0140] In operation 1006, the epitaxial layer is formed into trapezoidal pixels via etching.

[0141] At operation 1008, an oxide layer is deposited over the pixels and then etched to expose the n-type semiconductor layer at the top of the pixels and the temporary substrate or TCO layer.

[0142] In operation 1010, a metal seed layer and a metal plating layer are deposited on the oxide layer and the openings and etched to electrically isolate portions of the metal plating layer. Another oxide layer is deposited on the metal plating layer, the openings are etched to expose portions of the metal plating layer, and a bonding layer is deposited and formed on the openings to provide bonding pads that contact the exposed portions of the metal plating layer.

[0143] At operation 1012 , the resulting structure is hybridized by attaching the monolithic structure to bond pads.

[0144] At operation 1014, the temporary substrate is removed from the hybridized structure.

[0145] At operation 1016, periodic nanostructures are patterned on the TCO layer, which may be deposited after removal of the temporary substrate (if not already present).

[0146] Although only certain features of the system and method have been illustrated and described herein, many modifications and variations will occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations. The method operations may be performed substantially simultaneously or in different orders.

[0147] Example

[0148] Various embodiments are listed below. It will be understood that the embodiments listed below can be combined with all aspects of the scope of the present invention and other embodiments.

[0149] Embodiment (a). A light emitting diode (LED), comprising: a first light emitting stack on a second light emitting stack, wherein the first light emitting stack comprises a first n-type layer on a first tunnel junction, a first tunnel junction on a first p-type layer, and a first p-type layer on a first light emitting active region, the second light emitting stack comprises a second n-type layer in contact with the first light emitting active region and on the second light emitting active region, a second light emitting active region on the second p-type layer; and a metal contact on the second light emitting stack and extending to the first light emitting stack.

[0150] Embodiment (b) The LED die of embodiment (a), wherein the metal contact comprises one or more of a cathode layer or an anode layer.

[0151] Embodiment (c) The LED die of embodiment (a) to embodiment (b), wherein a forward current is passed in parallel through the first light emitting stack and the second light emitting stack using a single voltage source.

[0152] Embodiment (d) The LED die according to embodiments (a) to (c) further comprises a substrate.

[0153] Embodiment (e). According to the LED die of embodiments (a) to (d), the first n-type layer, the second n-type layer and the third n-type layer independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0154] Embodiment (f) The LED die of embodiment (a) to embodiment (e), wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

[0155] Embodiment (g) The LED die of embodiment (a) to embodiment (f), wherein the cathode layer and the anode layer independently comprise one or more of aluminum (Al) or silver (Ag).

[0156] Embodiment (h) The LED die of embodiments (a) to (g), further comprising a dielectric layer on the LED die.

[0157] Embodiment (i) The LED die according to embodiments (a) to (h), further comprising a bonding metal layer.

[0158] Embodiment (j) The LED die of embodiment (a) to embodiment (i), wherein the bonding metal layer comprises one or more of titanium (Ti) and gold (Au).

[0159] Embodiment (k) The LED die of embodiments (a) to (j), wherein one or more of the first light emitting active region and the second light emitting active region emits green light.

[0160] Embodiment (1). A method for manufacturing a light emitting diode (LED) die, the method comprising: epitaxially growing a first light emitting stack and a second light emitting stack on an epitaxial wafer, the first light emitting stack comprising a first n-type layer on a first tunnel junction, a first tunnel junction on a first p-type layer, and a first p-type layer on a first light emitting active region, the second light emitting stack comprising a second n-type layer in contact with the first light emitting active region and on the second light emitting active region, and a second light emitting active region on the second p-type layer; and forming at least one metal contact on the second light emitting stack.

[0161] Embodiment (m) The method of embodiment (l), wherein the metal contact comprises one or more of a cathode layer or an anode layer.

[0162] Embodiment (n) The method of embodiment (l) to embodiment (m), wherein a single voltage source is used and the forward current is passed in parallel through the first light emitting stack and the second light emitting stack.

[0163] Embodiment (o) The method according to embodiment (l) to embodiment (n), further comprising mounting the LED die to a substrate.

[0164] Embodiment (p) The method according to embodiment (l) to embodiment (o), further comprising forming a dielectric layer on the LED die.

[0165] Embodiment (q) The method according to embodiment (l) to embodiment (p), further comprising forming a bonding metal layer.

[0166] Embodiment (r) The method according to embodiment (l) to embodiment (q), wherein one or more of the first light emitting active region and the second light emitting active region emits green light.

[0167] Embodiment(s). A method for manufacturing a thin film flip chip (TFFC) die, the method comprising: sequentially forming two pn junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack comprising at least one n-type layer and at least one p-type layer, and having a light emitting active region embedded between the at least one n-type layer and the at least one p-type layer; dry etching the epitaxial stack to form two through holes of different depths; conformally depositing a dielectric layer in the two through holes; removing a portion of the dielectric layer to form a contact opening; depositing one or more of an anode layer and a cathode layer in the contact opening; depositing a bonding metal layer on one or more of the anode layer or the cathode layer; singulating the thin film flip chip (TFFC) die; and bonding the thin film flip chip (TFFC) die to a substrate.

[0168] Embodiment (t). The method according to embodiment (s), wherein the epitaxial stack includes a first light-emitting stack and a second light-emitting stack, the first light-emitting stack includes a first n-type layer on a first tunnel junction, a first tunnel junction on a first p-type layer, and a first p-type layer on a first light-emitting active region, and the second light-emitting stack includes a second n-type layer in contact with the first light-emitting active region and on the second light-emitting active region, and a second light-emitting active region on the second p-type layer.

[0169] In the context of describing the materials and methods discussed herein (especially in the context of the following claims), the use of the terms "one" and "an" and "the" and similar references should be interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the description of the range of values ​​herein is intended only to be used as a shorthand method for individually referring to each individual value falling within the range, and each individual value is incorporated into this specification as if it were individually described herein. Unless otherwise indicated herein or clearly contradicted by the context otherwise, all methods described herein can be performed in any suitable order. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and unless otherwise claimed, does not limit the scope. Any language in this specification should not be interpreted as indicating that any unclaimed element is essential for practicing the disclosed materials and methods.

[0170] Throughout the specification, the terms first, second, third, etc. may be used to describe various elements herein, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0171] Throughout this specification, reference to a layer, region, or substrate being "on" or extending to another element means that it may be directly on or directly extending to another element, or there may be intermediate elements. When an element is referred to as being "directly on" or "directly extending to" another element, there may be no intermediate elements. In addition, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element and / or connected or coupled to another element via one or more intermediate elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element between the element and the other element. It will be understood that these terms are intended to cover different orientations of elements, in addition to any orientation depicted in the figures.

[0172] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0173] Throughout this specification, reference to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in an embodiment," or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0174] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrations of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A light emitting diode (LED) die, comprising: a first light emitting stack on a second light emitting stack, wherein The first light emitting stack includes a first n-type layer on a first tunnel junction, a first tunnel junction on a first p-type layer, and a first p-type layer on a first light emitting active region, The second light emitting stack includes a second n-type layer contacting the first light emitting active region and on the second light emitting active region, and a second light emitting active region on the second p-type layer; and A metal contact is on the second light emitting stack and extends to the first light emitting stack.

2. The LED die of claim 1, wherein the metal contact comprises one or more of a cathode layer or an anode layer.

3. The LED die of claim 1, wherein a forward current is passed in parallel through the first light emitting stack and the second light emitting stack using a single voltage source. The LED die of claim 1 , further comprising a substrate.

5. The LED die according to claim 1, wherein the first n-type layer, the second n-type layer and the third n-type layer independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

6. The LED die of claim 5, wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

7. The LED die of claim 1, wherein the cathode layer and the anode layer independently comprise one or more of aluminum (Al) or silver (Ag).

8. The LED die of claim 2, further comprising a dielectric layer on the LED die.

9. The LED die of claim 2, further comprising a bonding metal layer.

10. The LED die of claim 9, wherein the bonding metal layer comprises one or more of titanium (Ti) and gold (Au).

11. The LED die of claim 1, wherein one or more of the first light emitting active region and the second light emitting active region emits green light.

12. A method of manufacturing a light emitting diode (LED) die, the method comprising: Epitaxially growing a first light-emitting stack and a second light-emitting stack on the epitaxial wafer, wherein the first light-emitting stack includes a first n-type layer on the first tunnel junction, a first tunnel junction on the first p-type layer, and a first p-type layer on the first light-emitting active region, and the second light-emitting stack includes a second n-type layer contacting the first light-emitting active region and on the second light-emitting active region, and a second light-emitting active region on the second p-type layer; and At least one metal contact is formed on the second light emitting stack.

13. The method of claim 12, wherein the metal contact comprises one or more of a cathode layer or an anode layer.

14. The method of claim 12, wherein a forward current is passed in parallel through the first light emitting stack and the second light emitting stack using a single voltage source.

15. The method of claim 12, further comprising mounting the LED die to a substrate.

16. The method of claim 13, further comprising forming a dielectric layer on the LED die. The method of claim 13 , further comprising forming a bonding metal layer. 18 . The method of claim 12 , wherein one or more of the first light emitting active region and the second light emitting active region emits green light.

19. A method of manufacturing a thin film flip chip (TFFC) die, the method comprising: sequentially forming two pn junctions on the epitaxial wafer to form an epitaxial stack, the epitaxial stack comprising at least one n-type layer and at least one p-type layer, and having a light emitting active region embedded between the at least one n-type layer and the at least one p-type layer; dry etching the epitaxial stack to form two through holes of different depths; conformally depositing a dielectric layer in the two vias; removing a portion of the dielectric layer to form a contact opening; depositing one or more of an anode layer and a cathode layer in the contact opening; depositing a bonding metal layer on one or more of the anode layer or the cathode layer; Singulate thin film flip chip (TFFC) dies; and A thin film flip chip (TFFC) die is bonded to a substrate.

20. The method of claim 19, wherein the epitaxial stack comprises a first light-emitting stack and a second light-emitting stack, the first light-emitting stack comprising a first n-type layer on a first tunnel junction, a first tunnel junction on a first p-type layer, and a first p-type layer on a first light-emitting active region, and the second light-emitting stack comprises a second n-type layer in contact with the first light-emitting active region and on the second light-emitting active region, and a second light-emitting active region on the second p-type layer.

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