Gate drive circuit and display panel

Abstract

The invention provides a gate drive circuit and a display panel, the gate drive circuit comprises a plurality of cascaded gate drive units, and each gate drive unit comprises a high-potential write-in module, a low-potential write-in module and an output module which are all connected with a first node, the high-potential write-in module is configured to control the potential of a first node according to a first scanning signal output by an upper-stage gate driving unit and the first clock signal, and the low-potential write-in module is configured to control the potential of the first node according to a first scanning signal output by a lower-stage gate driving unit and a preset low-potential signal; the output module is configured to output a first scanning signal and a second scanning signal which are opposite in phase according to the potential of the first node. According to the gate drive circuit provided by the invention, the COM signals are coupled and offset mutually by arranging the anti-phase signal line parallel to the scanning signal, so that the stability of the common voltage is improved, and the cross grain phenomenon of the display panel is eliminated.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] In the related art, the touch sensor (TP sensor) of the embedded (incell) display panel is divided into blocks, such as WU incell pixels, and the touch sensor is divided into 60*48 sensor partitions, each of which has 1200 / 48=25 rows of pixels, that is, 25*2=50 rows of scanning lines (gates). Since each sensor partition is independent of each other, in two adjacent sensor partitions, when the first sensor partition runs to the last row, there are 4 downward gates that cannot be offset and will be coupled downward, while the second sensor partition has 4 upward scanning signals that cannot be offset in the first two rows and will be coupled upward. Since the two sensor partitions are coupled in opposite directions, the voltage levels of the two are different, which will eventually cause horizontal stripes to appear in the display area of ​​the display panel. Summary of the invention

[0003] The embodiments of the present application provide a gate driving circuit and a display panel to solve the problem of horizontal stripes appearing in a display area of ​​a display panel in the related art.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, the present application provides a gate driving circuit, comprising a plurality of cascaded gate driving units, each of the gate driving units comprising:

[0006] A high potential writing module is connected to the first scanning signal and the first clock signal output by the gate driving unit of the previous level and is connected to the first node, and the high potential writing module is configured to control the potential of the first node according to the first scanning signal and the first clock signal output by the gate driving unit of the previous level;

[0007] A low potential writing module is connected to the first scanning signal output by the gate driving unit of the next stage and the preset low potential, and is connected to the first node, and the low potential writing module is configured to control the potential of the first node according to the first scanning signal output by the gate driving unit of the next stage and the preset low potential signal;

[0008] an output module connected to the first node, the output module being configured to output a first scanning signal and a second scanning signal according to the potential of the first node;

[0009] Wherein, the first scanning signal and the second scanning signal are in opposite phases.

[0010] In one embodiment, the high potential writing module includes:

[0011] Second node;

[0012] a pull-up module, electrically connected to the second node and the first node, the pull-up module being configured to control the potential of the first node according to the potential of the second node;

[0013] A pull-up control module is electrically connected to the second node, and the pull-up control module is configured to control the potential of the second node according to the first scanning signal output by the gate driving unit of the previous stage.

[0014] In one embodiment, the low potential writing module includes:

[0015] a pull-down module, electrically connected to the high potential writing module and the first node, the pull-down module being at least configured to control the first node to access the preset low potential signal according to the first scanning signal output by the gate driving unit of the next stage;

[0016] A pull-down maintaining module is electrically connected to the pull-up module, the first node and the high potential writing module, and the pull-down maintaining module is at least configured to control the first node to access the preset low potential signal according to the first scanning signal output by the gate driving unit of the previous level.

[0017] In one embodiment, the output module includes:

[0018] The first inverter is electrically connected to the high potential writing module, and the first inverter is configured to output the second scanning signal according to the potential of the first node.

[0019] In one embodiment, the high potential writing module includes:

[0020] a first transistor, wherein a first electrode of the first transistor is connected to a first clock signal, a second electrode of the first transistor is connected to a first node, and a control electrode of the first transistor is connected to a second node;

[0021] A second transistor, wherein a first electrode and a control electrode of the second transistor are both connected to a first scanning signal output by the gate driving unit of a previous stage, and a second electrode of the second transistor is connected to the first node.

[0022] In one embodiment, the low potential writing module includes:

[0023] a third transistor, wherein a first electrode of the third transistor is connected to the second node, a second electrode of the third transistor is connected to a preset low potential signal, and a control electrode of the third transistor is connected to a scanning signal output by the gate driving unit of a next stage;

[0024] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the first node, a second electrode of the fourth transistor is connected to a preset low potential signal, and a control electrode of the fourth transistor is connected to a scanning signal of a next-stage gate driving unit;

[0025] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the second node, and a second electrode of the fifth transistor is connected to a preset low potential signal;

[0026] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to a preset low potential signal;

[0027] a seventh transistor, wherein a first electrode and a control electrode of the seventh transistor are connected to the second clock signal, and a second electrode of the seventh transistor is connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor; and

[0028] An eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, a second electrode of the eighth transistor is connected to a preset low potential signal, and a control electrode of the eighth transistor is connected to a second electrode of the second transistor.

[0029] In one embodiment, the output module includes:

[0030] a ninth transistor, wherein a first electrode of the ninth transistor is connected to a preset high potential signal;

[0031] a tenth transistor, wherein a first electrode of the tenth transistor is connected to a second electrode of the ninth transistor, a second electrode of the tenth transistor is connected to a preset low potential signal, and a control electrode of the tenth transistor is connected to the first node; and

[0032] An eleventh transistor, wherein a first electrode and a control electrode of the eleventh transistor are connected to the preset high potential signal, and a second electrode of the eleventh transistor is connected to the control electrode of the ninth transistor.

[0033] In one embodiment, the gate driving circuit further includes:

[0034] A bootstrap capacitor, a first electrode of the bootstrap capacitor is connected to the first node, and a second electrode of the bootstrap capacitor is connected to the second node.

[0035] In a second aspect, the present application also provides a display panel, comprising a plurality of scan lines, a plurality of data lines, a plurality of sub-pixels arranged in an array, and a gate driving circuit as described in any one of the above, wherein the gate driving circuit is electrically connected to the scan lines, and each of the sub-pixels is electrically connected to one of the scan lines and one of the data lines.

[0036] In one embodiment, the gate driving circuit includes a plurality of cascaded gate driving units, each of which includes at least:

[0037] A first output terminal connected to the first scanning line to output a first scanning signal;

[0038] A second output terminal connected to a second scanning line to output a second scanning signal;

[0039] The first scanning line and the second scanning line are arranged in parallel and connected to the display area of ​​the display panel, and the first scanning signal and the second scanning signal are in opposite phases.

[0040] The present application provides a gate drive circuit and a display panel, wherein the gate drive circuit includes a plurality of cascaded gate drive units, each of which includes: a high potential writing module, connected to the first scanning signal and the first clock signal output by the gate drive unit of the previous level, and connected to the first node, the high potential writing module is configured to control the potential of the first node according to the first scanning signal and the first clock signal output by the gate drive unit of the previous level; a low potential writing module, connected to the first scanning signal and the preset low potential output by the gate drive unit of the next level, and connected to the first node, the low potential writing module is configured to control the potential of the first node according to the first scanning signal and the preset low potential signal output by the gate drive unit of the next level; an output module, connected to the first node, the output module is configured to output the first scanning signal and the second scanning signal according to the potential of the first node; wherein the first scanning signal and the second scanning signal are inverted. Through the above scheme, when the gate drive circuit outputs the scanning signal, an inverted signal with an inverted phase to the scanning signal is produced and input to the display area of ​​the display panel, and the two inverted signals are synchronously coupled to the common voltage signal in the display panel, and offset each other, thereby improving the stability of the common voltage signal and eliminating the horizontal stripes in the display area of ​​the display panel. In addition, the inverted signal is set between the gate drive circuit and the display area, which can shield the static electricity of the gate drive circuit and ensure the normal display of the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0042] Attached Figure 1 It is a schematic diagram of the module structure of a display panel in the related art;

[0043] Attached Figure 2 A driving timing diagram of a display panel in the related art;

[0044] Attached Figure 3 A schematic diagram of a module of an optional gate drive unit in an embodiment of the present application

[0045] Attached Figure 4 A schematic diagram of a circuit structure of an optional gate driving unit in an embodiment of the present application;

[0046] Attached Figure 5 A schematic diagram of a specific circuit structure of another optional gate driving unit in an embodiment of the present application;

[0047] Attached Figure 6 This is a schematic diagram of the structure of an optional display panel in an embodiment of the present application;

[0048] Attached Figure 7 This is a schematic diagram of the structure of an optional display area of ​​a display panel in an embodiment of the present application;

[0049] Attached Figure 8 is a timing diagram of an inverted signal of a first scanning signal output by a gate driving unit at this stage in an embodiment of the present application;

[0050] Attached Fig. 9 1 is a timing diagram of each input or output node of the gate driving unit in the embodiment of the present application.

[0051] Description of reference numerals in the figures:

[0052] 1. Display panel; 10. Gate drive circuit; 100. Gate drive unit; 101. First output terminal; 102. Second output terminal; 103. First scan line; 104. Second scan line; 110. High potential write module; 111. Pull-up module; 112. Pull-up control module; 120. Low potential write module; 121. Pull-down module; 122. Pull-down maintaining module; 130. Output module; 131. First inverter; 140. Bootstrap capacitor. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0054] Reference Figure 1As shown, in the embedded touch display panel 1, the common electrode (ie, the touch sensor) is divided into blocks, for example, WU (wide viewing angle UV2 A) incell pixels, there are 60*48 sensor partitions, each sensor partition block has 25 rows of pixels and 50 rows of gates. Figure 2 As shown, since each sensor partition block is independent of each other, in two adjacent sensor partitions, when the first sensor partition runs to the last row, there are 4 downward gates that cannot be offset and will be coupled downward, while in the first two rows of the second sensor partition, there are 4 upward scanning signals that cannot be offset and will be coupled upward. Since the two sensor partitions are coupled in opposite directions, the voltage levels of the two are also different, which will eventually cause horizontal stripes to appear in the display area of ​​the display panel 1.

[0055] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present application, in order to distinguish the source and drain of the transistor, one of the poles is called the first pole, and the other pole is called the second pole. In addition, the gate of the transistor is called the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor. When the gate inputs a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a technician in the field can easily think of without paying creative labor, so it is also within the scope of protection of the embodiments of the present application.

[0056] Among them, since the transistors used in the embodiments of the present application are all N-type transistors, the working level signal in the embodiments of the present application refers to a high level signal, and the non-working level signal is a low level signal.

[0057] Reference Figure 3As shown, according to the first aspect of the present application, a gate driving circuit 10 is provided, comprising a plurality of cascaded gate driving units 100, at least one gate driving unit 100 comprising: a high potential writing module 110, a low potential writing module 120 and an output module 130. The high potential writing module 110 is connected to the first scanning signal G(N-1) and the first clock signal CK output by the gate driving unit of the previous stage, and connected to the first node O(N), and the high potential writing module 110 is configured to control the potential of the first node O(N) according to the first scanning signal G(N-1) and the first clock signal CK output by the gate driving unit of the previous stage; the low potential writing module 120 is connected to the first scanning signal and the preset low potential output by the gate driving unit of the next stage, and connected to the first node O(N), and the low potential writing module 120 is configured to control the potential of the first node O(N) according to the first scanning signal and the preset low potential signal output by the gate driving unit of the next stage; the output module 130 is connected to the first node O(N), and the output module 130 is configured to output the first scanning signal and the second scanning signal according to the potential of the first node. It should be noted that the first scanning signal and the second scanning signal are in anti-phase, and the common voltage signal can be coupled through these two anti-phase synchronous signals to offset each other, thereby improving the stability of the common voltage and eliminating the horizontal stripes on the display panel.

[0058] Reference Figure 3 As shown, specifically, in some embodiments of the present application, the high potential writing module 110 includes a second node Q(N), and by changing the potential of the second node Q(N), it is possible to control whether the first node O(N) is connected to the first clock signal CK, and the high potential writing module 110 also includes a pull-up module 111 and a pull-up control module 112. Among them, the pull-up module 111 is electrically connected to the second node Q(N) and the first node O(N), and the pull-up module 111 is configured to control the potential of the first node O(N) according to the potential of the second node Q(N). In particular, it is used to output a first scan signal with a duty cycle of 50% to the first node O(N) during the rising stage of the potential of the second node Q(N).

[0059] The pull-up control module 112 is electrically connected to the second node Q(N), and is configured to control the potential of the second node Q(N) according to the first scan signal output by the previous gate driving unit 100 .

[0060] More specifically, see Figure 4 As shown, in some embodiments of the present application, the pull-up module 111 includes a first transistor T1, a first electrode of the first transistor T1 is connected to the first clock signal CK, a second electrode of the first transistor T1 is connected to the first node O(N), and a control electrode of the first transistor T1 is connected to the second node Q(N).

[0061] The pull-up control module 112 includes a second transistor T2, a first electrode and a control electrode of the second transistor T2 are both connected to the first scan signal of the previous gate driving unit 100, and a second electrode of the second transistor T2 is connected to the second node Q(N). When the first scan signal output by the previous gate driving unit 100 is at a high level, the second transistor T2 is turned on and the high-level first scan signal is output to the second node Q(N) to pull up the potential of the second node Q(N).

[0062] It should be noted that in the gate drive circuit 10, for the first-stage gate drive unit 100, there is no previous-stage scan signal Gn[0], therefore, in the first-stage gate drive unit 100, a start signal STV can be set to replace the previous-stage scan signal Gn[0] of the first-stage gate drive unit 100, which will not be described one by one here. Similarly, the scan signal output by the last-stage gate drive unit 100 does not exist in the next-stage gate drive unit 100 for control. It should be noted that, in addition to the above differences, the circuit structures and signal connections of the remaining gate drive units 100 except the first-stage gate drive unit 100 are the same, which will not be described here.

[0063] Reference Figure 3 As shown, specifically, in some embodiments of the present application, the low potential writing module 120 includes a pull-down module 121 and a pull-down maintaining module 122. The pull-down module 121 is electrically connected to the first node O(N) and the second node Q(N) in the high potential writing module 110, and the pull-down module 121 is at least configured to control the second node Q(N) and the first node O(N) to access the preset low potential signal according to the first scanning signal output by the next-level gate driving unit 100. It should be noted that the preset low potential signal in the embodiment of the present application can be a VSS signal.

[0064] The pull-down maintaining module 122 is electrically connected to the pull-up module 111, the second node Q(N) and the first node O(N), and the pull-down maintaining module 122 is at least configured to control the first node to access the preset low potential signal according to the first scan signal output by the gate driving unit of the previous level. In some embodiments, the pull-down maintaining module 122 can also be configured to control the first node to access the preset low potential signal according to the second scan signal output by the gate driving unit of the previous level. More specifically, the pull-down maintaining module 122 is used to maintain the low potential output by the pull-down module 121 during the shutdown phase of the gate driving unit 100, that is, to maintain the potentials of the first node O(N) and the second node Q(N) as a preset low potential in response to the inverted signal of the first scan signal output by the gate driving unit 100 of the previous level.

[0065] More specifically, see Figure 4As shown, in some embodiments of the present application, the pull-down module 121 includes a third transistor T3 and a fourth transistor T4, the first electrode of the third transistor T3 is connected to the second node Q(N), the second electrode of the third transistor T3 is connected to a preset low potential signal, and the control electrode of the third transistor T3 is connected to the first scanning signal output by the next-level gate driving unit 100; the first electrode of the fourth transistor T4 is connected to the first node O(N), the second electrode of the fourth transistor T4 is connected to the preset low potential signal, and the control electrode of the fourth transistor T4 is connected to the first scanning signal of the next-level gate driving unit 100.

[0066] More specifically, see Figure 5 As shown, in some embodiments of the present application, the pull-down maintenance module 122 includes: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. Among them, the first electrode of the fifth transistor T5 is connected to the second node Q (N), the second electrode of the fifth transistor T5 is connected to the preset low potential signal, and the control electrode of the fifth transistor T5 is connected to the inverted signal of the first scanning signal output by the previous gate driving unit 100; the first electrode of the sixth transistor T6 is connected to the first node O (N), the second electrode of the sixth transistor T6 is connected to the preset low potential signal, and the control electrode of the sixth transistor T6 is connected to the inverted signal of the first scanning signal of the previous gate driving unit 100; the first electrode and the control electrode of the seventh transistor T7 are both connected to the second clock signal XCK, and the second electrode of the seventh transistor T7 is connected to the control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6; the first electrode of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7, the second electrode of the eighth transistor T8 is connected to the preset low potential signal, and the control electrode of the eighth transistor T8 is connected to the output end of the pull-up control module 112, and more specifically, the control electrode of the eighth transistor T8 is connected to the second electrode of the second transistor T2. It should be noted that the seventh transistor T7 and the eighth transistor T8 form an inverter, and the connection point between the seventh transistor T7 and the eighth transistor T8 is the output end of the inverter. In addition, the second clock signal XCK is in opposite phase to the first clock signal CK.

[0067] Reference Figure 4 As shown, in some embodiments of the present application, the output module 130 includes a first inverter 131, the first inverter 131 is electrically connected to the first node O(N), and the first inverter 131 is configured to output the second scanning signal XG(N) of the gate driving unit at this level according to the potential of the first node O(N).

[0068] Reference Figure 5As shown, more specifically, in some embodiments of the present application, the first inverter 131 includes a ninth transistor T9, a tenth transistor T10 and an eleventh transistor T11. Among them, the first electrode of the ninth transistor T9 is connected to a preset high potential signal; the first electrode of the tenth transistor T10 is connected to the second electrode of the ninth transistor T9, the second electrode of the tenth transistor T10 is connected to a preset low potential signal, and the control electrode of the tenth transistor T10 is connected to the first node O(N); the first electrode and the control electrode of the eleventh transistor T11 are both connected to a preset high potential signal, and the second electrode of the eleventh transistor T11 is connected to the control electrode of the ninth transistor T9. It should be noted that, in this embodiment, the preset high potential can be a gate-on voltage VGH, and the connection terminal between the ninth transistor T9 and the tenth transistor T10 is the output terminal of the first inverter 131.

[0069] In the above embodiment, the gate driving unit 100 of the present application further includes a bootstrap capacitor 140, the first electrode of the bootstrap capacitor 140 is connected to the first node O(N), the second electrode of the bootstrap capacitor 140 is connected to the second node Q(N), and the bootstrap capacitor 140 is used to lift and stabilize the potential of the pull-up control node during the output process through capacitive coupling, thereby increasing the charging speed of the scan line. It should be noted that in the pull-down module 121 and the pull-down maintenance module 122, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are all configured to conduct the path between the bootstrap capacitor 140 and VSS in response to an external signal, thereby releasing the charge stored in the storage capacitor.

[0070] Reference Fig. 9 As shown, it is a working timing diagram of the gate driving unit 100 of the present application. When the previous-stage gate driving unit 100 outputs a high-level first scanning signal to the current-stage gate driving unit 100, the second transistor T2 is turned on, the second node Q(N) is pulled high by the high-level first scanning signal, and the bootstrap capacitor 140 is charged. At this time, the first inverter outputs a low-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off. At the same time, since the second node Q(N) is at a high level, the first scanning signal output by the next-stage gate driving unit 100 is still in a low-level state at this time, the first transistor T1 is turned on, the third transistor T3 and the fourth transistor T4 are turned off, and the high-level first clock signal CK is output to the first node O(N) through the first transistor T1. Since the control electrode of the eleventh transistor T11 is connected to the preset high potential signal, the eleventh transistor T11 is in a normally open state, and the control electrode of the ninth transistor T9 is connected to the preset high potential signal and is also in a normally open state. When the signal output by the first node O(N) is a high level signal, the tenth transistor T10 is turned on, and the signal output by the first node O(N) is a low level signal; similarly, when the signal output by the first node O(N) is a low level signal, the tenth transistor T10 is turned off, and the first inverter 131 outputs a high potential signal.

[0071] Reference Figure 6 As shown, according to the second aspect of the present application, a display panel 1 is also provided, comprising a plurality of scan lines, a plurality of data lines, a plurality of sub-pixels arranged in an array, and a gate driving circuit 10 provided by any one of the above embodiments, wherein the gate driving circuit 10 is electrically connected to the scan lines, and each sub-pixel is electrically connected to a scan line and a data line. The gate driving circuit 10 comprises a plurality of cascaded gate driving units 100, referring to Figure 7 As shown, the gate driving unit 100 at least includes a first output terminal 101, connected to a first scan line 103 to output a first scan signal; a second output terminal 102, connected to a second scan line 104 to output a second scan signal; wherein the first scan line 103 and the second scan line 104 are arranged in parallel and connected to the display area of ​​the display panel 1, and the first scan signal and the second scan signal are in opposite phases. Figure 8 As shown, the two signals are coupled to the common voltage signal in anti-phase synchronization to cancel each other out, thereby improving the stability of the common voltage and eliminating the horizontal stripes on the display panel 1.

[0072] Therefore, when the display panel 1 provided in the embodiment of the present application includes the above-mentioned gate driving circuit 10, it has all the beneficial effects of the above-mentioned gate driving circuit 10, which will not be described in detail here.

[0073] It should be noted that the display panel 1 provided in the embodiment of the present application can be applied to any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display panel 1 can also be used in combination with a flexible circuit board, a printed circuit board and a backplane.

[0074] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of cascaded gate driving units, each of which comprises: A high potential writing module is connected to the first scanning signal and the first clock signal output by the gate driving unit of the previous level and is connected to the first node, and the high potential writing module is configured to control the potential of the first node according to the first scanning signal and the first clock signal output by the gate driving unit of the previous level; A low potential writing module is connected to the first scanning signal output by the gate driving unit of the next stage and the preset low potential, and is connected to the first node, and the low potential writing module is configured to control the potential of the first node according to the first scanning signal output by the gate driving unit of the next stage and the preset low potential signal; an output module connected to the first node, the output module being configured to output a first scanning signal and a second scanning signal according to the potential of the first node; Wherein, the first scanning signal and the second scanning signal are in opposite phases.

2. The gate driving circuit according to claim 1, characterized in that: The high potential writing module comprises: Second node; a pull-up module, electrically connected to the second node and the first node, the pull-up module being configured to control the potential of the first node according to the potential of the second node; A pull-up control module is electrically connected to the second node, and the pull-up control module is configured to control the potential of the second node according to the first scanning signal output by the gate driving unit of the previous stage.

3. The gate driving circuit according to claim 2, characterized in that: The low potential writing module comprises: a pull-down module, electrically connected to the high potential writing module and the first node, the pull-down module being at least configured to control the first node to access the preset low potential signal according to the first scanning signal output by the gate driving unit of the next stage; A pull-down maintaining module is electrically connected to the pull-up module, the first node and the high potential writing module, and the pull-down maintaining module is at least configured to control the first node to access the preset low potential signal according to the first scanning signal output by the gate driving unit of the previous level.

4. The gate driving circuit according to claim 1, characterized in that: The output module comprises: The first inverter is electrically connected to the first node, and the first inverter is configured to output the second scanning signal according to the potential of the first node.

5. The gate driving circuit according to claim 1, characterized in that: The high potential writing module comprises: a first transistor, wherein a first electrode of the first transistor is connected to a first clock signal, a second electrode of the first transistor is connected to a first node, and a control electrode of the first transistor is connected to a second node; A second transistor, wherein a first electrode and a control electrode of the second transistor are both connected to a first scanning signal output by the gate driving unit of a previous stage, and a second electrode of the second transistor is connected to the first node.

6. The gate driving circuit according to claim 5, characterized in that: The low potential writing module comprises: a third transistor, wherein a first electrode of the third transistor is connected to the second node, a second electrode of the third transistor is connected to a preset low potential signal, and a control electrode of the third transistor is connected to a scanning signal output by the gate driving unit of a next stage; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the first node, a second electrode of the fourth transistor is connected to a preset low potential signal, and a control electrode of the fourth transistor is connected to a scanning signal of a next-stage gate driving unit; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the second node, and a second electrode of the fifth transistor is connected to a preset low potential signal; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to a preset low potential signal; a seventh transistor, wherein a first electrode and a control electrode of the seventh transistor are connected to the second clock signal, and a second electrode of the seventh transistor is connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor; and An eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, a second electrode of the eighth transistor is connected to a preset low potential signal, and a control electrode of the eighth transistor is connected to a second electrode of the second transistor.

7. The gate driving circuit according to claim 6, characterized in that: The output module comprises: a ninth transistor, wherein a first electrode of the ninth transistor is connected to a preset high potential signal; a tenth transistor, wherein a first electrode of the tenth transistor is connected to a second electrode of the ninth transistor, a second electrode of the tenth transistor is connected to a preset low potential signal, and a control electrode of the tenth transistor is connected to the first node; and An eleventh transistor, wherein a first electrode and a control electrode of the eleventh transistor are connected to the preset high potential signal, and a second electrode of the eleventh transistor is connected to the control electrode of the ninth transistor.

8. The gate driving circuit according to any one of claims 1 to 7, characterized in that: The gate drive circuit further includes: A bootstrap capacitor, a first electrode of the bootstrap capacitor is connected to the first node, and a second electrode of the bootstrap capacitor is connected to the second node.

9. A display panel, characterized in that: It includes a plurality of scan lines, a plurality of data lines, a plurality of sub-pixels arranged in an array, and a gate driving circuit as described in any one of claims 1 to 8, wherein the gate driving circuit is electrically connected to the scan lines, and each of the sub-pixels is electrically connected to one of the scan lines and one of the data lines.

10. The display panel according to claim 9, characterized in that: The gate driving circuit comprises a plurality of cascaded gate driving units, each of which comprises at least: A first output terminal connected to the first scanning line to output a first scanning signal; A second output terminal connected to a second scanning line to output a second scanning signal; The first scanning line and the second scanning line are arranged in parallel and connected to the display area of ​​the display panel, and the first scanning signal and the second scanning signal are in opposite phases.

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