Memory, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory, an operation method thereof and a memory system. The memory includes: a memory cell array including: a plurality of memory cells; a peripheral circuit coupled to the memory cell array, the peripheral circuit configured to: receive at least one set of random data of a time sequence; wherein the time sequence comprises a plurality of random events; the random data is used for indicating the current states of the plurality of random events; respectively writing the random data into a plurality of storage units; wherein each storage unit in the plurality of storage units is in one-to-one correspondence with each random event in the plurality of random events; determining the correlation degree of the plurality of random events according to the distribution of the electrical parameters of the plurality of storage units; wherein the correlation degree is used for predicting future states of the plurality of random events.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory and an operating method thereof, and a memory system. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. With the continuous advancement of semiconductor manufacturing technology, the characteristic size of semiconductor devices has continued to shrink, the integration density of memory has become higher and higher, and its performance has become more and more powerful, which can be applied to massive data processing. For example, time correlation detection.

[0003] Time correlation detection is usually based on the traditional von Neumann architecture, that is, the storage and computation separation architecture, which uses memory to store raw data, intermediate data and computation results, and uses processors to perform operations on various data. However, the existing time correlation detection has problems such as complex computation process and low computation efficiency. Summary of the invention

[0004] The present disclosure provides a memory and an operating method thereof, and a memory system.

[0005] In a first aspect, the present disclosure provides a memory, comprising:

[0006] A memory cell array, comprising: a plurality of memory cells;

[0007] A peripheral circuit is coupled to the memory cell array, wherein the peripheral circuit is configured as follows:

[0008] Receive at least one set of random data of a time series; wherein the time series includes a plurality of random events; and the random data is used to indicate a current state of the plurality of random events;

[0009] Writing the random data into the plurality of storage units respectively; wherein each of the plurality of storage units corresponds to each of the plurality of random events in a one-to-one manner;

[0010] The correlation degree of the plurality of random events is determined according to the electrical parameter distribution of the plurality of storage units; wherein the correlation degree is used to predict the future states of the plurality of random events.

[0011] In some embodiments, the peripheral circuit is specifically configured as follows:

[0012] receiving the time series;

[0013] A set of the random data is generated according to the current states of the plurality of random events at a preset time.

[0014] In some embodiments, the current state includes a first current state and a second current state; the peripheral circuit is further specifically configured as:

[0015] Generate a first logic value according to the first current state of a first random event among the plurality of random events at a preset time; wherein the random data includes the first logic value;

[0016] and / or,

[0017] Generate a second logic value according to the second current state of a second random event among the plurality of random events at a preset time; wherein the random data includes the second logic value;

[0018] The second current state is different from the first current state, and the second logic value is different from the first logic value.

[0019] In some embodiments, the peripheral circuit is configured to:

[0020] Determine a pulse width of a write pulse and / or a peak value of a write pulse according to the number of the first logic values ​​or the number of the second logic values;

[0021] The random data are written into the plurality of storage cells respectively using the write pulse.

[0022] In some embodiments, the memory further comprises:

[0023] A common source line coupled to a plurality of storage strings in the storage cell array; wherein the storage string comprises a plurality of the storage cells connected in series, and the storage strings in the same column are coupled to a bit line;

[0024] The peripheral circuit comprises:

[0025] a counting circuit coupled to the common source line, the counting circuit being configured to: determine the number of the bit lines selected within the preset time according to the current of the common source line; wherein the number of the bit lines selected is equal to the number of the first logic values ​​or the number of the second logic values;

[0026] A modulation circuit is coupled to the counting circuit, and the modulation circuit is configured to determine the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the bit lines selected within the preset time.

[0027] In some embodiments, the counting circuit comprises:

[0028] A conversion circuit is coupled to the common source line, and the conversion circuit is configured to: generate a first voltage according to a current of the common source line;

[0029] A follower circuit is coupled to the conversion circuit, and the follower circuit is configured to: generate a counting voltage according to the first voltage; wherein the counting voltage is used to indicate the number of the selected bit lines.

[0030] In some embodiments, the modulation circuit comprises:

[0031] A charging circuit is coupled to the counting circuit and the first node respectively, and the charging circuit is configured to: charge the voltage of the first node to the counting voltage;

[0032] a discharge circuit coupled to the first node, the discharge circuit being configured to discharge the first node from the counting voltage to a second voltage;

[0033] The regulating circuit is coupled to the first node, and is configured to regulate the pulse width of the write pulse and / or the peak value of the write pulse according to the discharge time of the first node from the count voltage to the second voltage.

[0034] In some embodiments, the at least one set of random data includes N sets of random data, where N is an integer greater than 1; wherein the N sets of random data are used to indicate the current states of the plurality of random events at N preset times; and the peripheral circuit is further configured as:

[0035] Generate an i-th group of the random data according to the current states of the plurality of random events at the i-th preset time, where i is an integer greater than or equal to 1 and less than or equal to N;

[0036] Determine the pulse width of the i-th write pulse and / or the peak value of the i-th write pulse according to the number of the first logic values ​​or the number of the second logic values ​​in the i-th group of random data;

[0037] The i-th group of random data is written into the plurality of storage cells respectively using the i-th write pulse.

[0038] In some embodiments, the electrical parameter includes a threshold voltage; and the peripheral circuit is specifically configured as follows:

[0039] The correlation degree of the plurality of random events is determined according to the threshold voltage distribution of the plurality of memory cells.

[0040] In some embodiments, the storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein said 2 M each of the related levels and the 2 MEach of the threshold voltage intervals in the threshold voltage intervals corresponds one to one;

[0041] The peripheral circuit is also specifically configured as follows:

[0042] According to the threshold voltage interval of the storage unit, a correlation level of the random event corresponding to the storage unit is determined.

[0043] In a second aspect, the present disclosure provides an operating method of a memory, wherein the memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a plurality of memory cells, and the operating method comprises:

[0044] Receive at least one set of random data of a time series; wherein the time series includes a plurality of random events; and the random data is used to indicate a current state of the plurality of random events;

[0045] Writing the random data into the plurality of storage units respectively; wherein each of the plurality of storage units corresponds to each of the plurality of random events in a one-to-one manner;

[0046] The correlation degree of the plurality of random events is determined according to the electrical parameter distribution of the plurality of storage units; wherein the correlation degree is used to predict the future states of the plurality of random events.

[0047] In some embodiments, the operating method further includes:

[0048] receiving the time series;

[0049] A set of the random data is generated according to the current states of the plurality of random events at a preset time.

[0050] In some embodiments, the current state includes a first current state and a second current state; and generating a set of random data according to the current state at a preset time based on a plurality of random events includes:

[0051] Generate a first logic value according to the first current state of a first random event among the plurality of random events at a preset time; wherein the random data includes the first logic value;

[0052] and / or,

[0053] Generate a second logic value according to the second current state of a second random event among the plurality of random events at a preset time; wherein the random data includes the second logic value;

[0054] The second current state is different from the first current state, and the second logic value is different from the first logic value.

[0055] In some embodiments, the operating method further includes:

[0056] Determine a pulse width of a write pulse and / or a peak value of a write pulse according to the number of the first logic values ​​or the number of the second logic values;

[0057] The random data are written into the plurality of storage cells respectively using the write pulse.

[0058] In some embodiments, the memory further comprises a common source line coupled to a plurality of storage strings in the memory cell array, the storage strings comprising a plurality of the storage cells connected in series, and the storage strings in the same column are coupled to a bit line; the peripheral circuit comprises a counting circuit and a modulation circuit, the counting circuit is coupled to the common source line, and the modulation circuit is coupled to the counting circuit;

[0059] The step of determining the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the first logic values ​​or the number of the second logic values ​​comprises:

[0060] The counting circuit determines the number of the bit lines selected within the preset time according to the current of the common source line; wherein the number of the bit lines selected is equal to the number of the first logic values ​​or the number of the second logic values;

[0061] The modulation circuit determines the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the bit lines selected within the preset time.

[0062] In some embodiments, the counting circuit includes a conversion circuit and a follower circuit, the conversion circuit is coupled to the common source line, and the follower circuit is coupled to the conversion circuit;

[0063] The counting circuit determines the number of the bit lines selected within the preset time according to the current of the common source line, including:

[0064] The conversion circuit generates a first voltage according to the current of the common source line;

[0065] The follower circuit generates a counting voltage according to the first voltage; wherein the counting voltage is used to indicate the number of the selected bit lines.

[0066] In some embodiments, the modulation circuit includes a charging circuit, a discharging circuit and a regulating circuit, the charging circuit is coupled to the counting circuit and the first node respectively, the discharging circuit is coupled to the first node, and the regulating circuit is coupled to the first node;

[0067] The modulation circuit determines the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the bit lines selected within the preset time, including: the charging circuit charges the voltage of the first node to the counting voltage;

[0068] The discharge circuit discharges the first node from the counting voltage to a second voltage;

[0069] The regulating circuit adjusts the pulse width of the write pulse and / or the peak value of the write pulse according to the discharge time of the first node from the count voltage to the second voltage.

[0070] In some embodiments, the at least one set of random data includes N sets of random data, where N is an integer greater than 1; wherein the N sets of random data are used to indicate the current states of the plurality of random events at N preset times; and the operation method further includes:

[0071] Generate an i-th group of the random data according to the current states of the plurality of random events at the i-th preset time, where i is an integer greater than or equal to 1 and less than or equal to N;

[0072] Determine the pulse width of the i-th write pulse and / or the peak value of the i-th write pulse according to the number of the first logic values ​​or the number of the second logic values ​​in the i-th group of random data;

[0073] The i-th group of random data is written into the plurality of storage cells respectively using the i-th write pulse.

[0074] In some embodiments, the operating method further includes:

[0075] According to the number of the random events, the number of the storage units in the memory for writing the random data and the storage capacity in the memory for writing the random data are determined.

[0076] In a third aspect, the present disclosure provides a memory system, including the memory described in any embodiment of the first aspect;

[0077] A memory controller is coupled to the memory and is configured to control the memory.

[0078] In the embodiment of the present disclosure, the peripheral circuit is configured to write random data into multiple storage units respectively, and then determine the correlation degree of multiple random events according to the distribution of electrical parameters of the multiple storage units. In this way, the memory can be used to perform in-memory calculations to achieve time correlation detection. On the one hand, the present disclosure does not need to perform complex calculations through the processor in the storage and calculation separation architecture, and the calculation efficiency is high, which can meet the statistics and analysis of massive data streams; on the other hand, the random data of the present disclosure does not need to be transmitted back and forth between the processor and the memory through a serial bus, which can avoid the additional delay and power consumption caused by the von Neumann bottleneck; on the other hand, the memory provided by the present disclosure is calculated based on the threshold voltage (or other continuously changing electrical parameters) of the storage unit, and the calculation window is large, and the calculation window will not decrease due to the increase in the number of stacked layers of the three-dimensional memory, which can effectively avoid the attenuation of calculation accuracy and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 A schematic diagram of a system with a memory provided in an embodiment of the present disclosure;

[0080] Figure 2a A schematic diagram of a memory card provided by an embodiment of the present disclosure;

[0081] Figure 2b A schematic diagram of a solid state drive (SSD) provided in an embodiment of the present disclosure;

[0082] Figure 3 A schematic diagram of a storage-computing separation architecture provided in an embodiment of the present disclosure;

[0083] Figure 4 A schematic diagram of a time series provided by an embodiment of the present disclosure;

[0084] Figure 5 A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0085] Figure 6 A schematic diagram of determining the pulse width and peak value of a write pulse provided by an embodiment of the present disclosure;

[0086] Figure 7 A flow chart of writing multiple groups of random data into a storage cell array provided by an embodiment of the present disclosure;

[0087] Figure 8a to Figure 8g A schematic diagram of a process for performing time correlation detection on multiple random events using a memory provided by an embodiment of the present disclosure;

[0088] Fig. 9 A schematic diagram of another memory provided by an embodiment of the present disclosure;

[0089] Fig.10 A schematic diagram of a counting circuit and a modulation circuit provided in an embodiment of the present disclosure;

[0090] Fig.11 A timing diagram of a counting circuit provided in an embodiment of the present disclosure;

[0091] Fig.12 A timing diagram of a modulation circuit provided in an embodiment of the present disclosure;

[0092] Fig.13 A schematic diagram of a threshold voltage distribution of a memory cell provided in an embodiment of the present disclosure;

[0093] Fig.14 A schematic diagram of determining the number and storage capacity of storage units for writing random data in a memory provided by an embodiment of the present disclosure;

[0094] Fig.15 A schematic diagram of a memory system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0095] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0096] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0097] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0098] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0099] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0100] Figure 1 A schematic diagram of a system 100 having a memory according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0101] like Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0102] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CFCard), a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive or embedded Multi Media Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0103] The memory controller 106 may be configured to control the operation of the memory 104, such as read, erase, and write operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCIE) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced System Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0104] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (Smart Media, SM) card, a memory stick, a Multi Media Card (Multi Media Card, MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (Multi Media Card Micro, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (Univeral Flash Storage, UFS), etc. The memory card 202 may also include a method for connecting the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0105] In an embodiment of the present disclosure, each of the memory chips (Die) may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), tri-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memories may include one or more memory cell arrays, such as an SLC array, an MLC array, a TLC array, a QLC array, or any combination of such memory cell arrays.

[0106] Figure 3A schematic diagram of time correlation detection using a storage-computation separation architecture (i.e., von Neumann architecture) provided for an embodiment of the present disclosure. In the von Neumann architecture, computing and storage are separated, and the processor 11 includes but is not limited to a central processing unit in a host, a field programmable gate array (FPGA), etc., and the memory 12 includes but is not limited to SSD, eMMC, UFS, etc. The processor 11 can obtain at least one set of random data of a time series from the memory 12, and the time series includes multiple random events, and each set of random data is used to indicate the current state of multiple random events at a time (or time period). Next, the logic circuit in the processor 12 can perform a covariance matrix operation, thereby calculating the degree of correlation of each random event by a mathematical method, wherein the degree of correlation can be used to predict the future state of the random event.

[0107] For example, Figure 4 A schematic diagram of a time series provided by an embodiment of the present disclosure. The time series includes K random events (respectively denoted as X1 to X2). K ), T1 to T N Represents N different moments (or time periods), where N and K are both positive integers. The occurrence of a random event at a moment (or time period) is represented by a black square, and the non-occurrence of a random event at a moment (or time period) is represented by a white square. The "occurrence" and "non-occurrence" here are the "current state" of the above-mentioned random events. The processor can obtain N groups of random data of the time series from the memory, and then obtain the covariance matrix through logical operations, and finally generate the correlation degree distribution of K random events, wherein multiple random events with a correlation degree of "correlated" tend to occur at the same time or not occur at the same time, while multiple random events with a correlation degree of "non-correlated" occur or do not occur without correlation. In this way, the future state of multiple random events can be predicted.

[0108] Time series exist in various fields, such as sales records of goods on e-commerce platforms, stock data in financial markets, and monitoring performance indicators of Internet companies. With the advent of the big data era, the scale of time series is also increasing. Detecting time series can reveal the inherent laws of movement, change, and development of things. Time correlation detection can be used to filter out relevant information in massive random data streams (not limited to image information, but any random data).

[0109] However, when processing random data in temporal correlation detection, data is transferred back and forth between the processor and the memory through a serial bus, which causes additional delays and power consumption due to the von Neumann bottleneck. Moreover, the steps of covariance matrix calculation by the processor are complicated and computationally intensive, resulting in low computational efficiency.

[0110] In-memory computing uses the characteristics of the storage unit in the memory to perform calculations on specific tasks, thereby breaking through the bottleneck of the traditional von Neumann architecture and improving computing efficiency. However, in-memory computing generally uses the linear working area of ​​the storage unit in the memory and performs calculations through electric current. Since the range of the linear working area is small, and the increase in memory integration (such as the increase in the number of stacked layers of three-dimensional memory) will reduce the current, further reducing the range of the linear working area, resulting in a significant compression of the computing window.

[0111] Based on this, in order to solve one or more of the above technical problems, an embodiment of the present disclosure provides a memory.

[0112] like Figure 5 As shown, the present disclosure provides a memory 200, comprising: a memory cell array 210, comprising: a plurality of memory cells; a peripheral circuit 220, coupled to the memory cell array 210, the peripheral circuit 220 being configured to: receive at least one set of random data of a time series; wherein the time series comprises a plurality of random events; the random data is used to indicate the current state of the plurality of random events; the random data is written into the plurality of memory cells respectively; wherein each of the plurality of memory cells corresponds to each of the plurality of random events one by one; according to the electrical parameter distribution of the plurality of memory cells, determine the correlation degree of the plurality of random events; wherein the correlation degree is used to predict the future state of the plurality of random events.

[0113] In the embodiment of the present disclosure, the memory 200 includes, but is not limited to, any memory in which the electrical parameters of any memory cell continuously change, such as a flash memory, a phase change memory (PCM), a resistive random access memory (RRAM), etc. The memory 200 includes a memory cell array 210 and a peripheral circuit 220 for controlling the memory cell array 210 to perform various operations. The memory cell array 210 includes a plurality of memory cells arranged in an array.

[0114] The following description will be made by taking the memory 200 as a NAND type memory in a flash memory as an example. The peripheral circuit 220 is coupled to the memory cell array 210 through a plurality of word lines (Wordline, WL) and a plurality of bit lines (Bitline, BL). The memory cells in the same row are coupled to a word line, and the memory cells in the same column are coupled to a bit line ( Figure 5Only one bit line is shown in the figure). The memory cell array 210 also includes a plurality of memory strings (String), one memory string includes a plurality of memory cells connected in series, and the memory strings in the same column are coupled to a bit line. Each memory string also includes a top selection transistor coupled between the plurality of memory cells connected in series and the bit line, and a bottom selection transistor coupled between the plurality of memory cells connected in series and a common source line (Array Common Source, ACS). The gate of the top selection transistor is called the top selection gate (Top Selected Gate, TSG), and the gate of the bottom selection transistor is called the bottom selection gate (Bottom Selected Gate, BSG). By applying a certain voltage to the corresponding word line, bit line, top selection gate, bottom selection gate, and common source line, operations such as writing, reading, or erasing can be performed on the selected memory cell.

[0115] Exemplarily, if "1" is written to a memory cell, a write operation is performed on the memory cell; if "0" is written to the memory cell, no write operation is performed on the memory cell (the reverse is also possible and is not limited here). It should be noted that each time a write operation is performed on a memory cell, the charge in the channel will tunnel into the charge trapping layer of the memory cell and accumulate continuously, thereby increasing the threshold voltage (Threshold Voltage, Vt) of the memory cell. For phase change memory and resistive memory, the write operation will cause the resistance value of the memory cell to change.

[0116] refer to Figure 5 , the peripheral circuit 220 can receive at least one set of random data in a time series, wherein each set of random data is used to indicate the current state of multiple random events at a moment (or time period), where the time series may include multiple moments (or time periods), that is, there are multiple sets of random data. Exemplarily, the time series includes K random events (respectively denoted as X1 to X2). K ), T1 to T N Represents N different moments (or time periods). N and K are both positive integers. The occurrence of a random event at a moment (or time period) is represented by a black square, and the non-occurrence of a random event at a moment (or time period) is represented by a white square, where "occurrence" and "non-occurrence" are the "current state" of the above-mentioned random event. Each random event can correspond to one bit in a group of random data. Exemplarily, the current states of random events X1 to X5 at T1 are "occurrence, non-occurrence, non-occurrence, occurrence, occurrence", respectively, and the corresponding random data can be "10011". It should be noted that in the present disclosure, "occurrence" can correspond to a logical value "1", "non-occurrence" can correspond to a logical value "0", or "occurrence" can correspond to a logical value "0", and "non-occurrence" can correspond to a logical value "1", which is not limited here.

[0117] The peripheral circuit 220 may write at least one set of random data into the plurality of storage units. For example, the peripheral circuit 220 writes a set of random data corresponding to K random events at time T1 (or time period) into K storage units C1, C2, ..., C k , if the current states of random events X1 to X5 at T1 are "occurrence, non-occurrence, non-occurrence, occurrence, occurrence", respectively, and the corresponding random data is "10011", then the storage cells C1, C4, and C5 are written, and the storage cells C2 and C3 are not written. At this time, the threshold voltages of the storage cells C1, C4, and C5 increase, while the threshold voltages of the storage cells C2 and C3 remain substantially unchanged. In this way, writing at least one set of random data corresponding to at least one moment (or time period) into K storage cells will cause the threshold voltages of the K storage cells to be distributed in different intervals. For example, the threshold voltages of the storage cells corresponding to multiple random events (i.e., multiple related random events) that tend to occur simultaneously will be significantly higher than other storage cells after multiple write operations. Finally, the peripheral circuit 220 determines the correlation degree of the K random events as "correlated" or "non-correlated" according to the threshold voltage distribution of the K storage cells. Here, the correlation degree can be used to predict the future state of each random event. For example, multiple "related" random events are more likely to occur simultaneously in the future. It can be understood that the degree of correlation here can also be used to predict random events with opposite tendencies, such as if random event X1 occurs, random event X2 tends not to occur.

[0118] In this way, the present disclosure utilizes a memory to perform in-memory calculations to achieve time correlation detection. On the one hand, the present disclosure does not need to perform complex covariance matrix operations through a processor in a storage-computation separation architecture, but instead achieves statistics and analysis through continuous changes in the physical properties of the storage unit, with high computational efficiency, which can meet the statistics and analysis of massive data streams; on the other hand, the random data in the present disclosure does not need to be transmitted back and forth between the processor and the memory through a serial bus, which can avoid the additional delay and power consumption caused by the von Neumann bottleneck; on the other hand, the memory provided by the present disclosure is calculated based on the threshold voltage (or other continuously changing electrical parameters) of the storage unit, and the calculation window is large, and the calculation window will not decrease due to the increase in the number of stacked layers of the three-dimensional memory, which can effectively avoid the attenuation of calculation accuracy and reliability.

[0119] In some embodiments, the peripheral circuit is specifically configured to: receive the time series; and generate a set of the random data according to the current states of a plurality of the random events at a preset time.

[0120] In the embodiments of the present disclosure, the preset time may be any moment or time period in the above embodiments, and the time sequence may include multiple different preset times. Figure 5 As shown, the time series includes N preset times T1 to T N In this way, the peripheral circuit generates a corresponding set of random data according to the current states of K random events in a preset time. That is to say, when the current states of multiple random events at N preset times are obtained by statistics, the time series can correspond to N sets of random data.

[0121] In some embodiments, the current state includes a first current state and a second current state; the peripheral circuit is further specifically configured as:

[0122] Generate a first logic value according to the first current state of a first random event among the plurality of random events at a preset time; wherein the random data includes the first logic value;

[0123] and / or,

[0124] Generate a second logic value according to the second current state of a second random event among the plurality of random events at a preset time;

[0125] The random data includes the second logic value; the second current state is different from the first current state, and the second logic value is different from the first logic value.

[0126] In the embodiments of the present disclosure, the current state may include a first current state and a second current state, such as "occurrence" and "non-occurrence" in the above embodiments. It is worth noting that the current state in the present disclosure may also refer to other states of random events, such as if the random event is "a user of an e-commerce platform purchases a beverage", the first current state is "purchase of carbonated beverage", and the second current state is "purchase of non-carbonated beverage". The present disclosure does not impose too many restrictions on the types of "random events" and "current state". For ease of understanding, the following explanation is made using the first logical value of "1" and the second logical value of "0", but this is not used as a limitation, that is, the first logical value may be "0" and the second logical value may be "1".

[0127] The peripheral circuit can generate a first logic value according to the first current state of the first random event among the K random events at a preset time. For example, the peripheral circuit generates a first logic value "1" according to the occurrence of the first random events X1, X4, and X5 at the preset time T1, and generates a second logic value "0" according to the non-occurrence of the second random events X2 and X3 at the preset time T1. At this time, the random data generated by the peripheral circuit according to the random events X1 to X5 is "10011". That is to say, the K random events may include several first random events in the first current state and several second random events in the second current state at the preset time T1. It is understandable that in a preset time, there may be only the first random event in the first current state, or only the second random event in the second current state. Exemplarily, the K random events X1 to X3 may be in the first current state, and the first random event in the second current state may be in the second current state. K All of the random events X1 to X1 occur at the preset time T1. K All of them are first random events. At this time, a group of random data generated by the peripheral circuit contains only the first logic value "1", that is, the group of random data includes K first logic values ​​"1".

[0128] In some embodiments, Figure 6 As shown, the peripheral circuit is configured to: determine the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the first logic values ​​or the number of the second logic values; and use the write pulse to write the random data into the plurality of storage cells respectively.

[0129] In the embodiment of the present disclosure, the peripheral circuit can also determine the pulse width of the write pulse and / or the peak value of the write pulse for writing the group of random data into the memory cell array according to the number of the first logic value "1" or the number of the second logic value "0". Exemplarily, if there are m first random events in the first current state (1≤m≤K) at the preset time T1, the number of the first logic value "1" in the group of random data is m, so the peripheral circuit determines the pulse width of the write pulse and / or the peak value of the write pulse according to the number m of the first logic value "1".

[0130] It should be noted that the larger m is, the larger the pulse width of the write pulse and / or the peak value of the write pulse is, and the more the threshold voltage of the corresponding storage unit increases. This means that the more random events tend to occur simultaneously in a preset time, the stronger the correlation between these random events. Therefore, a larger magnitude of write operation is required, so that the threshold voltages of the storage units corresponding to "related" and "unrelated" random events can be distinguished to form different threshold voltage distribution areas.

[0131] In this way, the more random events that are in the first current state (or in the second current state) within a preset time, the more corresponding storage units that need to write the first logic value (or the second logic value) when writing the group of random data, the larger the pulse width and / or peak value of the write pulse, thereby accelerating the rate of the write operation; on the contrary, if the fewer random events that are in the first current state (or in the second current state) within a preset time, the fewer corresponding storage units that need to write the first logic value (or the second logic value) when writing the group of random data, the smaller the pulse width and / or peak value of the write pulse, thereby reducing the power consumption of the memory. It can be understood that the embodiment of the present disclosure can accurately adjust the pulse width of each write pulse and / or the peak value of the write pulse according to the number of the first logic value (or the second logic value), while meeting the pulse required for the write operation, it can also greatly reduce power consumption.

[0132] In some embodiments, the at least one group of random data includes N groups of random data, N is an integer greater than 1; wherein the N groups of random data are used to indicate the current states of multiple random events at N preset times; the peripheral circuit is further configured to: generate the i-th group of random data according to the current states of multiple random events at the i-th preset time, i is an integer greater than or equal to 1 and less than or equal to N; determine the pulse width of the i-th write pulse and / or the peak value of the i-th write pulse according to the number of first logic values ​​or the number of second logic values ​​in the i-th group of random data; and use the i-th write pulse to write the i-th group of random data into multiple storage units respectively.

[0133] In the embodiment of the present disclosure, the time sequence includes N preset times, that is, the peripheral circuit can generate N groups of random data according to the current states of multiple random events in the N preset times. Figure 7 As shown, first, the peripheral circuits are operated according to random events T1 to T N A corresponding first group of random data is generated in the current state at the preset time T1, wherein the occurrence of the random event corresponds to the first logic value "1" in the random data, and the non-occurrence of the random event corresponds to the second logic value "0" in the random data; then, the peripheral circuit determines the pulse width of the first write pulse and / or the peak value of the first write pulse according to the number of the first logic value "1" or the number of the second logic value "0" in the first group of random data, and uses the first write pulse to write the first group of random data into the K storage cells C1 to C k Repeat the above steps, the peripheral circuit will be based on the random events T1 to T N At the preset time T iThe peripheral circuit determines the pulse width of the i-th write pulse and / or the peak value of the i-th write pulse according to the number of the first logic value "1" or the number of the second logic value "0" in the i-th random data, and writes the i-th group of random data into the K storage cells C1 to C1 respectively by using the i-th write pulse. k Finally, the peripheral circuits are based on the storage cells C1 to C k The electrical parameter distribution determines the random events X1 to X K degree of relevance.

[0134] In some embodiments, the pulse width of the i-th write pulse is the same as or different from the pulse width of the i+j-th write pulse; and / or, the peak value of the i-th write pulse is the same as or different from the peak value of the i+j-th write pulse; wherein j is an integer greater than 0, and i+j is less than or equal to N.

[0135] It can be understood that if the number of first logic values ​​in the i-th group of random data and the i+j-th group of random data is equal, and the number of second logic values ​​in the i-th group of random data and the i+j-th group of random data is equal, then the pulse width of the i-th write pulse is the same as the pulse width of the i+j-th write pulse, and the peak value of the i-th write pulse is the same as the peak value of the i+j-th write pulse. If the number of first logic values ​​in the i-th group of random data and the i+j-th group of random data is not equal, and the number of second logic values ​​in the i-th group of random data and the i+j-th group of random data is not equal, then the pulse width of the i-th write pulse is different from the pulse width of the i+j-th write pulse, and the peak value of the i-th write pulse is different from the peak value of the i+j-th write pulse.

[0136] In this way, on the one hand, by determining the pulse width of the i-th write pulse and / or the peak value of the i-th write pulse according to the number of the first logic value or the second logic value in the i-th group of random data, each write operation can be precisely controlled to meet the requirements of write rate and power consumption at the same time; on the other hand, after writing N groups of random data, the threshold voltages of the storage cells corresponding to random events with different degrees of correlation are quite different, so as to form different threshold voltage distribution areas, which is convenient for subsequent prediction and analysis.

[0137] Figure 8a to Figure 8g FIG. 1 shows a schematic diagram of the process of using a memory to detect the time correlation of multiple random events. Figure 8a As shown, the 66 random events correspond to the 66 storage cells in the memory; the initial states of the threshold voltages corresponding to the 66 storage cells are as follows: Figure 8b As shown, each square represents the threshold voltage of a memory cell. The darker the color of the square, the higher the threshold voltage of the memory cell. Figure 8cAs shown in FIG. 1 , at a preset time, only 6 random events occur among 66 random events. At this time, the pulse width of the write pulse for writing to the 6 storage cells corresponding to the 6 random events is only 6us, and the threshold voltage rise of the corresponding 6 storage cells is relatively small. Figure 8d As shown, at another preset time, 36 random events occur out of 66 random events. At this time, the pulse width of the write pulse for writing the 36 storage cells corresponding to the 36 random events is 36us, and the threshold voltage of the corresponding 36 storage cells rises greatly. In this way, multiple groups of random data are continuously input, such as Figure 8e As shown, the threshold voltage of the storage unit corresponding to multiple random events that tend to occur simultaneously (the degree of correlation is "correlated") will increase significantly, thereby being distinguished from the threshold voltage of the storage unit corresponding to multiple random events with a correlation degree of "uncorrelated"; Figure 8f As shown, the peripheral circuit can determine the correlation degree of the corresponding multiple random events according to the distribution of the threshold voltages (or other electrical parameters) of the multiple storage cells; illustratively, as Figure 8g As shown, after multiple groups of random data are written into the memory cell array multiple times, the threshold voltages of 23 memory cells corresponding to 23 random events with a correlation degree of "correlated" among the 66 random events are higher, so the colors of the corresponding blocks are darker; the threshold voltages of memory cells corresponding to other random events with a correlation degree of "uncorrelated" among the 66 random events are lower, so the colors of the corresponding blocks are lighter.

[0138] In some embodiments, Fig. 9 As shown, the memory 200 further includes: a common source line ACS, coupled to a plurality of memory strings 211 in the memory cell array 210; wherein the memory string 211 includes a plurality of memory cells connected in series, and the memory strings 211 in the same column are coupled to a bit line BL; the peripheral circuit 220 includes: a counting circuit 221, coupled to the common source line ACS, and the counting circuit 221 is configured to: according to the current I of the common source line ACS ACS , determine the bit line BL selected within the preset time sel wherein the selected bit line BL sel The number of bits is equal to the number of the first logic value or the number of the second logic value; a modulation circuit 222 coupled to the counting circuit 221, the modulation circuit 222 is configured to: according to the bit line BL selected within the preset time sel The number of pulse widths of the write pulse and / or the peak value of the write pulse is determined.

[0139] In the embodiment of the present disclosure, if there are L random events occurring in the preset time T1 among K random events, 1≤L≤K, then L first logic values ​​"1" can be written into L storage cells respectively, that is, the write operation is performed on the L selected storage cells corresponding to the L random events. Here, the K storage cells corresponding to the K random events can be coupled to a selected word line WL sel and K bit lines BL, thus, the bits coupled to a selected word line WL sel A write pulse is applied to select L bit lines BL among K bit lines BL respectively coupled to K memory cells. sel Applying a bit line write pulse to write (KL) non-selected bit lines BL among K bit lines BL respectively coupled to K memory cells unsel By applying a bit line write inhibit pulse, a write operation can be performed on L selected memory cells.

[0140] The peripheral circuit 220 includes a counting circuit 221 and a modulation circuit 222. Specifically, before performing a write operation on the L selected memory cells, the peripheral circuit 220 may apply a power supply voltage V to the common source line ACS. dd , and for a selected word line WL sel Apply a write pulse to the L selected bit lines BL sel Apply a bit line write pulse to (KL) unselected bit lines BL unsel Applying a bit line write inhibit pulse, so that the two ends of the memory string 211 where the L selected memory cells are located are respectively coupled to the selected bit line BL sel and the common source line ACS, the selected memory cell has current flowing through the memory string 211, while the unselected memory cell has no current flowing through the memory string 211. At this time, the counting circuit 221 can count the current I ACS , determine the bit line BL selected within the preset time T1 sel It can be understood that the bit line BL selected here sel The modulation circuit 222 can be configured to generate a plurality of bit lines BL1 and BL2 according to the selected bit line BL. sel The number of pulse widths of the write pulses and / or the peak values ​​of the write pulses is determined.

[0141] In some embodiments, Fig.10 As shown, the counting circuit 221 includes: a conversion circuit 223, coupled to the common source line ACS, and the conversion circuit 223 is configured to: according to the current I ACS , generating a first voltage V c1A follower circuit 224 is coupled to the conversion circuit 223, and the follower circuit 224 is configured to: according to the first voltage V c1 , generating a counting voltage V1; wherein the counting voltage V1 is used to indicate the selected bit line BL sel The number of

[0142] In the embodiments of the present disclosure, Fig.10 As shown, the counting circuit 221 is mainly responsible for counting the number of memory cells in the memory cell array that need to be written, and generating a counting voltage V1 as an input of the subsequent modulation circuit 222. Fig.11 As shown, at time t1, through transistor M PCH Apply V to the gate DD +V th The voltage of capacitor C1 is precharged to V c1 =V DD , where V th is the threshold voltage of the n-type transistor, and SW Apply V to the gate of the transistor ACS +V th The voltage at the ACS terminal reaches V ACS At time t3, the top selection transistor and bottom selection transistor of the memory cell array and all word lines are turned on, and V is applied to the ACS terminal. ACS The voltage of the selected memory cell corresponds to the selected bit line BL sel The voltage of the unselected bit line BL is 0, and the unselected memory cell corresponds to the unselected bit line BL. unsel The voltage is V ACS Therefore, only the memory string where the selected memory cell is located will generate current. At this time, the total current I ACS The selected bit line BL sel The physical essence of this process is to complete the addition operation through Kirchhoff's law.

[0143] M PCH The voltage on the transistor starts to drop from time t2, and capacitor C1 starts to discharge. When the discharge is finished, the voltage V c1 Depends on the discharge current I ACS . M PCH The voltage on the transistor drops to V at time t3. safe , V safe The role is to clamp V c1 voltage, preventing V c1 The drop in ACS voltage V ACS , so that the voltage at the ACS terminal is stabilized at V during the discharge of capacitor C1. ACS Therefore, Vsafe Need to meet: V safe -V th >V ACS .

[0144] like Fig.11 Medium V c1 As shown in the solid line part, when the discharge current I ACS When it is smaller, it means that the selected bit line BL sel The number of cells that need to be written is small, that is, the number of storage cells that need to be written is small. At this time, the voltage V c1 The change is slow and still close to V DD status.

[0145] like Fig.11 Medium V c1 As shown by the dashed line, when the discharge current I ACS When it is larger, it means that more storage cells need to be written. At this time, the voltage V c1 will quickly drop to a lower voltage level, V c1 Satisfaction: V c1 =V DD -I ACS (t4-t2) / C1.

[0146] Then, through the transistor M DF and the follower circuit 224 formed by the resistor R1, converts the first voltage V c1 is converted into a counting voltage V1, and the resistor R1 serves as a load of the follower circuit 224. Here, the follower circuit 224 can be a drain follower. c1 When the transistor M DF The current drops, and the transistor M DF The voltage drop on the resistor R1 in the same series branch causes the counting voltage V1 to rise. Therefore, the counting voltage V1 and the ACS terminal current I ACS There is a positive correlation, that is, the more storage cells that need to be written, the higher the counting voltage V1 is, thereby realizing the function of the counting circuit.

[0147] In some embodiments, Fig.10As shown, the modulation circuit 222 includes: a charging circuit 225, respectively coupled to the counting circuit 221 and the first node B, the charging circuit is configured to: charge the voltage of the first node to the counting voltage; a discharging circuit 226, coupled to the first node, the discharging circuit is configured to discharge the first node from the counting voltage to a second voltage; and a regulating circuit 227, coupled to the first node, the regulating circuit is configured to adjust the pulse width of the write pulse and / or the peak value of the write pulse according to the discharge time of the first node from the counting voltage to the second voltage.

[0148] In the embodiment of the present disclosure, the count voltage V1 output by the count circuit 221 is used as the input voltage of the modulation circuit 222. The count voltage V1 will determine the pulse width and / or size of the peak voltage V2 of the write pulse. The following is an example of the modulation circuit 222 modulating the pulse width of the peak voltage V1 of the write pulse according to the count voltage V1. The charging circuit 225 includes a transistor M p1 , transistor M p2 and capacitor C2, the charging circuit 225 is coupled to the first node B and the counting circuit 221; the discharging circuit 226 includes a transistor M p3 , transistor M n1 and transistor M n2 , the discharge circuit 226 is coupled to the first node B; the regulating circuit 227 includes a transistor M p4 , transistor M n3 , transistor M n4 , transistor M p5 , transistor M p6 and transistor M n5 , the regulating circuit 227 is coupled to the first node B.

[0149] like Fig.12 As shown, at time T1, the clock signal CLK=0, CLK#=1, and the transistor M p1 Open and M p2 Turn off, capacitor C2 is charged to V C2 = V1. At the same time, transistor M p5 Turn on so that the D node voltage V D =V DD , by transistor M p6 and M n5 The inverter formed makes V2=0, that is, the low level of the write pulse.

[0150] At time T2, when the clock signal switches to CLK=1, CLK#=0, transistor M p2 Open and M p1 Close, the voltage V on capacitor C2 C2 can be transmitted to node B, i.e. VB =V C2 = V1. At the same time, transistor M p5 Close, M n3 Open so that M p4 and M n4 The inverter formed can work normally, V B So that transistor M n4 Open and M p4 When the voltage at node D is V D = 0 so that M p6 Open and M n5 Close, so V2 = V DD , that is, the high level of the write pulse.

[0151] Since CLK#=0, transistor M p3 Turn on so that the voltage at node A is V A =V DD , by transistor M n1 and M n2 The current mirror starts to make the voltage V B Discharge is carried out, and the discharge current is related to the transistor M n1 The current I n1 Equal. Since transistor M n1 The drain voltage remains unchanged, so the discharge current I n1 remains unchanged, that is, the first node B is always discharged at a constant rate. B Reduced to a certain threshold V th (Second voltage) makes M n4 Close and M p4 When turned on, the voltage V at node D D =V DD So that V2 = 0, that is, the high level of the write pulse ends. In summary, the pulse width W of the write pulse depends on the voltage V B Discharge from the first voltage V1 to the second voltage V th Time: W = (V B -V th )C2 / I n1 .

[0152] Since the capacitor C2 and the second voltage V th is a fixed value, and the discharge current I n1 is constant, so the pulse width W of the write pulse is positively correlated with the amplitude of the first voltage V1. Fig.12 Medium V B As shown by the solid line, when the first voltage V1 is high, the discharge time of the capacitor C2 is long, and the pulse width W of the write pulse is long. Fig.12 Medium V BAs shown by the dotted line, when the first voltage V1 is low, the discharge time is short, and the pulse width W of the write pulse is correspondingly reduced. ACS There is a positive correlation between the write pulse width W and the write pulse width W, so the pulse width W of the write pulse can reflect the number of storage units that need to be written, that is, the number of random events that "occur" within a preset time.

[0153] In some embodiments, Fig. 9 and Fig.10 As shown, the peripheral circuit 220 may further include a boost circuit 228, which is used to amplify the write pulse output by the modulation circuit 222, so that the voltage value of the write pulse matches the word line programming voltage of the memory cell.

[0154] After the pulse width of the write pulse reaches the design requirement, its amplitude is V DD Therefore, a boost circuit is required to convert the amplitude. The output voltage V2 of the modulation circuit 222 is converted from V to V by a level converter (Level Shifter) in the boost circuit. DD Raised to word line programming voltage V pgm Since resistors R2 and R3 are in the same series branch, according to the voltage division law of series circuit: V pgm / V DD =(R2+R3) / R3.

[0155] Since V DD and V pgm The values ​​of R2 and R3 are known, so we only need to select the resistance values ​​of R2 and R3 according to the ratio of the two to realize the function of the boost circuit. Finally, the write pulse output by the boost circuit is applied to the selected word line to complete the write process. Similarly, by adjusting the resistance values ​​of R2 and R3, we can also get the pass voltage V required for the non-selected word line during the write operation. pass Wait for the signal.

[0156] In some embodiments, the electrical parameter includes a threshold voltage; and the peripheral circuit is specifically configured to: determine the correlation degree of the plurality of the random events according to the threshold voltage distribution of the plurality of the storage cells.

[0157] In the disclosed embodiment, the memory 200 may be a flash memory, so that each time a set of random data is written into the memory cell array, the threshold voltage of the memory cell corresponding to the "related" random event in the memory cell array will increase. After writing multiple sets of random data, the peripheral circuit can determine the correlation degree of multiple random events according to the threshold voltage distribution of multiple memory cells.

[0158] For phase change memory and resistive change memory, the write operation will cause the resistance value of the memory cell to change. At this time, the peripheral circuit can determine the correlation degree of multiple random events based on the resistance value distribution of multiple memory cells.

[0159] In some embodiments, the storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein said 2 M each of the related levels and the 2 M Each of the threshold voltage intervals has a one-to-one correspondence; the peripheral circuit is further specifically configured to: determine the correlation level of the random event corresponding to the storage unit according to the threshold voltage interval in which the storage unit is located.

[0160] In the embodiment of the present disclosure, the memory 200 may be a NAND type memory, and the types of storage units include SLC, MLC, TLC, etc.

[0161] For example, Fig.13 As shown, an SLC type storage cell can store 1 bit of data, and the storage cell can have 2 threshold voltage intervals, corresponding to 2 storage states with logical values ​​of "0" and "1", respectively. After writing multiple groups of random data into the storage cell array, the threshold voltages of multiple storage cells have 2 distribution intervals, where each distribution interval corresponds to a correlation level, that is, the correlation degree of multiple random events can be divided into 2 correlation levels, such as the first threshold voltage interval corresponds to "non-correlation" and the second threshold voltage interval corresponds to "correlation". In this way, correlation detection of multiple random events can be achieved.

[0162] For example, Fig.13 As shown, an MLC type storage cell can store 2 bits of data, and the storage cell can have 4 threshold voltage intervals, corresponding to 4 storage states with logic values ​​of "11", "10", "01", and "00". After writing multiple sets of random data into the storage cell array, the threshold voltages of multiple storage cells have 4 distribution intervals, each of which corresponds to a correlation level. That is to say, the correlation degree of multiple random events can be divided into 4 correlation levels, such as the first threshold voltage interval corresponds to "non-correlation", the second threshold voltage interval corresponds to "low correlation", the third threshold voltage interval corresponds to "moderate correlation", and the fourth threshold voltage interval corresponds to "high correlation".

[0163] By analogy, the threshold voltage of a TLC type storage cell has 8 distribution intervals, and the 8 distribution intervals correspond to different degrees of correlation levels; the threshold voltage of a QLC type storage cell has 16 distribution intervals, and the 16 distribution intervals correspond to different degrees of correlation levels; in this way, a more refined time correlation detection can be performed on multiple random events in a time series, thereby producing more accurate correlation analysis results.

[0164] In some embodiments, the above 2 M The relevance levels include at least: relevant and non-relevant.

[0165] Based on the above memory, the present disclosure also provides an operating method of the memory, wherein the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory cells, and the operating method includes:

[0166] Receive at least one set of random data of a time series; wherein the time series includes a plurality of random events; the random data is used to indicate the current state of the plurality of random events; write the random data into the plurality of storage units respectively; wherein each of the plurality of storage units corresponds to each of the plurality of random events one by one; determine the correlation degree of the plurality of random events according to the distribution of electrical parameters of the plurality of storage units; wherein the correlation degree is used to predict the future state of the plurality of random events.

[0167] In some embodiments, the operating method further includes: receiving the time series; and generating a set of the random data according to the current states of a plurality of the random events at a preset time.

[0168] In some embodiments, the current state includes a first current state and a second current state; generating a set of the random data according to the current state of the plurality of random events at a preset time includes: generating a first logic value according to the first current state of a first random event among the plurality of random events at a preset time; wherein the random data includes the first logic value; and / or generating a second logic value according to the second current state of a second random event among the plurality of random events at a preset time; wherein the random data includes the second logic value; wherein the second current state is different from the first current state, and the second logic value is different from the first logic value.

[0169] In some embodiments, the operating method further includes: determining a pulse width of a write pulse and / or a peak value of a write pulse according to the number of the first logic values ​​or the number of the second logic values; and using the write pulse to write the random data into the plurality of storage cells respectively.

[0170] In some embodiments, the memory also includes a common source line coupled to multiple storage strings in the memory cell array, the storage strings include multiple storage cells connected in series, and the storage strings located in the same column are coupled to a bit line; the peripheral circuit includes a counting circuit and a modulation circuit, the counting circuit is coupled to the common source line, and the modulation circuit is coupled to the counting circuit; the pulse width of the write pulse and / or the peak value of the write pulse is determined according to the number of the first logic values ​​or the number of the second logic values, including: the counting circuit determines the number of the bit lines selected within the preset time according to the current of the common source line; wherein the number of the selected bit lines is equal to the number of the first logic values ​​or the number of the second logic values; the modulation circuit determines the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the bit lines selected within the preset time.

[0171] In some embodiments, the counting circuit includes a conversion circuit and a follower circuit, the conversion circuit is coupled to the common source line, and the follower circuit is coupled to the conversion circuit; the counting circuit determines the number of the bit lines selected within the preset time based on the current of the common source line, including: the conversion circuit generates a first voltage based on the current of the common source line; the follower circuit generates a counting voltage based on the first voltage; wherein the counting voltage is used to indicate the number of the selected bit lines.

[0172] In some embodiments, the modulation circuit includes a charging circuit, a discharging circuit and a regulating circuit, the charging circuit is respectively coupled to the counting circuit and the first node, the discharging circuit is coupled to the first node, and the regulating circuit is coupled to the first node; the modulation circuit determines the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the bit lines selected within the preset time, including: the charging circuit charges the voltage of the first node to the counting voltage; the discharging circuit discharges the first node from the counting voltage to the second voltage; the regulating circuit adjusts the pulse width of the write pulse and / or the peak value of the write pulse according to the discharge time of the first node from the counting voltage to the second voltage.

[0173] In some embodiments, the at least one group of random data includes N groups of random data, N is an integer greater than 1; wherein the N groups of random data are used to indicate the current states of multiple random events at N preset times; the operating method also includes: generating the i-th group of random data according to the current states of multiple random events at the i-th preset time, i is an integer greater than or equal to 1 and less than or equal to N; determining the pulse width of the i-th write pulse and / or the peak value of the i-th write pulse according to the number of first logic values ​​or the number of second logic values ​​in the i-th group of random data; and using the i-th write pulse to write the i-th group of random data into multiple storage units respectively.

[0174] In some embodiments, the operating method further includes: determining the number of storage units in the memory for writing the random data and the storage capacity in the memory for writing the random data according to the number of the random events.

[0175] In the embodiment of the present disclosure, the peripheral circuit can also determine the number of storage units in the memory for writing random data and the storage capacity in the memory for writing random data according to the total number of random events (such as the above-mentioned K random events). Fig.14 As shown, if the written random data corresponds to 512×287=146944 random events, the number of storage units in the memory for writing random data is 146944, and the storage capacity in the memory for writing random data is 18KB.

[0176] The present disclosure provides a memory system 20, such as Fig.15 As shown, the memory 200 includes any one of the above embodiments;

[0177] The memory controller 210 is coupled to the memory 200 and is configured to control the memory 200 .

[0178] The memory system 20 may correspond to Figure 1 The memory system 102 and the memory 200 in the embodiment shown may correspond to the reference Figure 1 The memory 104 in the embodiment shown, and the memory controller 210 may correspond to the reference Figure 1 The memory controller 106 in the illustrated embodiment will not be further described herein with respect to the functions, applications and interaction between the memory 200 and the memory controller 210 .

[0179] The present disclosure utilizes a memory to perform in-memory calculations to achieve time correlation detection. On the one hand, the present disclosure does not need to perform complex covariance matrix operations through a processor in a storage-computation separation architecture, but instead achieves statistics and analysis through continuous changes in the physical properties of a storage unit, with high computational efficiency, which can meet the statistics and analysis of massive data streams; on the other hand, the random data of the present disclosure does not need to be transmitted back and forth between the processor and the memory through a serial bus, which can avoid the additional delay and power consumption caused by the von Neumann bottleneck; on the other hand, the memory provided by the present disclosure is calculated based on the threshold voltage (or other continuously changing electrical parameters) of the storage unit, and the calculation window is large, and the calculation window will not decrease due to the increase in the number of stacked layers of the three-dimensional memory, which can effectively avoid the attenuation of calculation accuracy and reliability.

[0180] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0181] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: include: A memory cell array, comprising: a plurality of memory cells; A peripheral circuit is coupled to the memory cell array, wherein the peripheral circuit is configured as follows: Receive at least one set of random data of a time series; wherein the time series includes a plurality of random events; and the random data is used to indicate a current state of the plurality of random events; Writing the random data into the plurality of storage units respectively; wherein each of the plurality of storage units corresponds to each of the plurality of random events in a one-to-one manner; The correlation degree of the plurality of random events is determined according to the electrical parameter distribution of the plurality of storage units; wherein the correlation degree is used to predict the future states of the plurality of random events.

2. The memory according to claim 1, characterized in that: The peripheral circuit is specifically configured as follows: receiving the time series; A set of the random data is generated according to the current states of the plurality of random events at a preset time.

3. The memory according to claim 2, characterized in that: The current state includes a first current state and a second current state; the peripheral circuit is further specifically configured as: Generate a first logic value according to the first current state of a first random event among the plurality of random events at a preset time; wherein the random data includes the first logic value; and / or, Generate a second logic value according to the second current state of a second random event among the plurality of random events at a preset time; wherein the random data includes the second logic value; The second current state is different from the first current state, and the second logic value is different from the first logic value.

4. The memory according to claim 3, characterized in that: The peripheral circuit is configured as: Determine a pulse width of a write pulse and / or a peak value of a write pulse according to the number of the first logic values ​​or the number of the second logic values; The random data are written into the plurality of storage cells respectively using the write pulse.

5. The memory according to claim 4, characterized in that: The memory also includes: A common source line coupled to a plurality of storage strings in the storage cell array; wherein the storage string comprises a plurality of the storage cells connected in series, and the storage strings in the same column are coupled to a bit line; The peripheral circuit comprises: a counting circuit coupled to the common source line, the counting circuit being configured to: determine the number of the bit lines selected within the preset time according to the current of the common source line; wherein the number of the bit lines selected is equal to the number of the first logic values ​​or the number of the second logic values; A modulation circuit is coupled to the counting circuit, and the modulation circuit is configured to determine the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the bit lines selected within the preset time.

6. The memory according to claim 5, characterized in that: The counting circuit comprises: A conversion circuit is coupled to the common source line, and the conversion circuit is configured to: generate a first voltage according to a current of the common source line; A follower circuit is coupled to the conversion circuit, and the follower circuit is configured to: generate a counting voltage according to the first voltage; wherein the counting voltage is used to indicate the number of the selected bit lines.

7. The memory according to claim 6, characterized in that: The modulation circuit comprises: A charging circuit is coupled to the counting circuit and the first node respectively, and the charging circuit is configured to: charge the voltage of the first node to the counting voltage; a discharge circuit coupled to the first node, the discharge circuit being configured to discharge the first node from the counting voltage to a second voltage; The regulating circuit is coupled to the first node, and is configured to regulate the pulse width of the write pulse and / or the peak value of the write pulse according to the discharge time of the first node from the count voltage to the second voltage.

8. The memory according to claim 1, characterized in that: The at least one set of random data includes N sets of random data, where N is an integer greater than 1; wherein the N sets of random data are used to indicate the current states of the plurality of random events at N preset times; and the peripheral circuit is further configured as: Generate an i-th group of the random data according to the current states of the plurality of random events at the i-th preset time, where i is an integer greater than or equal to 1 and less than or equal to N; Determine the pulse width of the i-th write pulse and / or the peak value of the i-th write pulse according to the number of the first logic values ​​or the number of the second logic values ​​in the i-th group of random data; The i-th group of random data is written into the plurality of storage cells respectively using the i-th write pulse.

9. The memory according to claim 1, characterized in that: The electrical parameter includes a threshold voltage; the peripheral circuit is specifically configured as follows: The correlation degree of the plurality of random events is determined according to the threshold voltage distribution of the plurality of memory cells.

10. The memory according to claim 9, characterized in that: The storage unit is configured to store M bits of data, and a plurality of the storage units have 2 M threshold voltage intervals, M is a positive integer; the correlation degree includes 2 M relevant levels; wherein the 2 M each of the related levels and the 2 M Each of the threshold voltage intervals in the threshold voltage intervals corresponds one to one; The peripheral circuit is also specifically configured as follows: According to the threshold voltage interval of the storage unit, a correlation level of the random event corresponding to the storage unit is determined.

11. A method for operating a memory, characterized in that: The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; The memory cell array includes a plurality of memory cells, and the operation method includes: Receive at least one set of random data of a time series; wherein the time series includes a plurality of random events; and the random data is used to indicate a current state of the plurality of random events; Writing the random data into the plurality of storage units respectively; wherein each of the plurality of storage units corresponds to each of the plurality of random events in a one-to-one manner; The correlation degree of the plurality of random events is determined according to the electrical parameter distribution of the plurality of storage units; wherein the correlation degree is used to predict the future states of the plurality of random events.

12. The operating method according to claim 11, characterized in that: The operation method also includes: receiving the time series; A set of the random data is generated according to the current states of the plurality of random events at a preset time.

13. The operating method according to claim 12, characterized in that: The current state includes a first current state and a second current state; the generating a set of random data according to the current state of the plurality of random events at a preset time includes: Generate a first logic value according to the first current state of a first random event among the plurality of random events at a preset time; wherein the random data includes the first logic value; and / or, Generate a second logic value according to the second current state of a second random event among the plurality of random events at a preset time; wherein the random data includes the second logic value; The second current state is different from the first current state, and the second logic value is different from the first logic value.

14. The operating method according to claim 13, characterized in that: The operation method also includes: Determine a pulse width of a write pulse and / or a peak value of a write pulse according to the number of the first logic values ​​or the number of the second logic values; The random data are written into the plurality of storage cells respectively using the write pulse.

15. The operating method according to claim 14, characterized in that: The memory further comprises a common source line coupled to a plurality of storage strings in the storage cell array, wherein the storage strings comprise a plurality of the storage cells connected in series, and the storage strings in the same column are coupled to a bit line; the peripheral circuit comprises a counting circuit and a modulation circuit, wherein the counting circuit is coupled to the common source line, and the modulation circuit is coupled to the counting circuit; The step of determining the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the first logic values ​​or the number of the second logic values ​​comprises: The counting circuit determines the number of the bit lines selected within the preset time according to the current of the common source line; wherein the number of the bit lines selected is equal to the number of the first logic values ​​or the number of the second logic values; The modulation circuit determines the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the bit lines selected within the preset time.

16. The operating method according to claim 15, characterized in that: The counting circuit comprises a conversion circuit and a follower circuit, wherein the conversion circuit is coupled to the common source line, and the follower circuit is coupled to the conversion circuit; The counting circuit determines the number of the bit lines selected within the preset time according to the current of the common source line, including: The conversion circuit generates a first voltage according to the current of the common source line; The follower circuit generates a counting voltage according to the first voltage; wherein the counting voltage is used to indicate the number of the selected bit lines.

17. The operating method according to claim 16, characterized in that: The modulation circuit comprises a charging circuit, a discharging circuit and a regulating circuit, wherein the charging circuit is respectively coupled to the counting circuit and the first node, the discharging circuit is coupled to the first node, and the regulating circuit is coupled to the first node; The modulation circuit determines the pulse width of the write pulse and / or the peak value of the write pulse according to the number of the bit lines selected within the preset time, including: the charging circuit charges the voltage of the first node to the counting voltage; The discharge circuit discharges the first node from the counting voltage to a second voltage; The regulating circuit adjusts the pulse width of the write pulse and / or the peak value of the write pulse according to the discharge time of the first node from the count voltage to the second voltage.

18. The operating method according to claim 11, characterized in that: The at least one set of random data includes N sets of random data, where N is an integer greater than 1; wherein the N sets of random data are used to indicate the current states of the plurality of random events at N preset times; and the operation method further includes: Generate an i-th group of the random data according to the current states of the plurality of random events at the i-th preset time, where i is an integer greater than or equal to 1 and less than or equal to N; Determine the pulse width of the i-th write pulse and / or the peak value of the i-th write pulse according to the number of the first logic values ​​or the number of the second logic values ​​in the i-th group of random data; The i-th group of random data is written into the plurality of storage cells respectively using the i-th write pulse.

19. The operating method according to claim 11, characterized in that: The operation method also includes: According to the number of the random events, the number of the storage units in the memory for writing the random data and the storage capacity in the memory for writing the random data are determined.

20. A memory system, characterized in that: include: One or more memories as claimed in any one of claims 1 to 10; A memory controller is coupled to the memory and is configured to control the memory.

Images