Memory device and operation method thereof

Abstract

A memory device is provided and includes a memory array, first to second latch circuits, and a gating circuit. The read operation and the write operation are respectively triggered by a first edge and a second edge of the internal clock signal. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal being generated based on a first edge of an internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latched clock signal, the first edge of the second latched clock signal being between the first edge and the second edge of the first latched clock signal. The gating circuit generates a third output signal to the memory array in response to the second output signal and the generated gating clock.

Description

Technical Field

[0001] The present disclosure relates to a memory structure and an operating method thereof, and more particularly to a memory structure with an optimized latch clock design and an operating method thereof. Background Art

[0002] Static random access memory (SRAM) is widely used in integrated circuits. SRAM cells store data in latches. SRAM can be called dual / dual-port SRAM, indicating that the SRAM can be a dual-port SRAM or a dual-port SRAM.

[0003] In some designs, the SRAM may contain at least six transistors, and data is written or read by two pass-gate transistors that are turned on in response to a word line signal. Due to architectural constraints, 6T SRAM uses a clock signal for both read and write operations. The rising edge of the clock signal is used for read operations, and the falling edge of the clock signal is used for write operations, or vice versa.

[0004] However, the performance of pseudo dual / dual port 6T SRAM is limited by the operation that takes a longer time in the same clock cycle. Specifically, this is because the read and write operations are tied together, and the clock cycle time must be long enough to accommodate one of the read and write operations that takes a longer time to complete. In some applications, the write operation is the bottleneck of the cycle time. Summary of the invention

[0005] According to one embodiment of the present disclosure, a memory device is provided. The memory device includes a memory array, and a first latch circuit to a second latch circuit. The read operation of the memory array is triggered by a first edge of an internal clock signal, and the write operation of the memory array is triggered by a second edge of the internal clock signal. The read operation and the write operation of the memory array are performed within the same clock cycle of the internal clock signal. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal. The first edge of the first latch clock signal is generated based on the first edge of the internal clock signal. The second latch circuit is coupled to the output end of the first latch circuit and generates a second output signal in response to the first output signal and the second latch clock signal. The first edge of the second latch clock signal is between the first edge of the first latch clock signal and the second edge of the first latch clock signal. The memory device further includes a gating circuit for generating a third output signal to the memory array for a write operation in response to the second output signal and a gating clock generated based on the second edge of the internal clock signal.

[0006] According to one embodiment of the present disclosure, a memory device is provided. The memory device includes a plurality of latch circuits and a gating circuit. Each of the latch circuits is used to latch data associated with an input signal in response to a corresponding latch clock signal in a plurality of latch clock signals. A plurality of pulses in the latch clock signal partially and continuously overlap in a clock cycle of an internal clock signal. The gating circuit is coupled to the Nth latch circuit in the latch circuit and is used to generate a gated output signal to a memory array in response to an Nth output signal of the Nth latch circuit and a gating clock signal for a write operation of the memory array. N is the number of latch circuits. The read operation of the memory array is triggered by a first pulse of the internal clock signal, and the write operation of the memory array is triggered by a second pulse of the internal clock signal. The read operation and the write operation of the memory array are performed within the same clock cycle of the internal clock signal.

[0007] According to an embodiment of the present disclosure, a method for operating a memory device is provided, the following operations: triggering a read operation of a memory array by a first rising edge of an internal clock signal; generating a first rising edge of a first latch clock signal based on the first rising edge of the internal clock signal to latch data of a first output signal; triggering a write operation of the memory array by a second rising edge of the internal clock signal; and generating a rising edge of a second latch clock signal based on the second rising edge of the internal clock signal to latch data of a second output signal for a write operation of the memory array, wherein the rising edge of the second latch clock signal is before the falling edge of the first latch clock signal. The read operation and the write operation of the memory array are performed within the same clock cycle of the internal clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] An aspect of an embodiment of the present disclosure is described in the accompanying Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 illustrates an exemplary block diagram of a memory device including a memory array and circuits for performing read and write operations on the memory array according to some embodiments of the present disclosure;

[0010] Figure 2 is a schematic diagram of a write port input latch circuit according to some embodiments of the present disclosure;

[0011] Figure 3 According to some embodiments of the present disclosure, Figure 2 A detailed schematic diagram of a latch circuit of a write port input latch circuit;

[0012] Figure 4 FIG. 1 shows a schematic diagram of ... Figure 5 The method operates Figure 1 The waveform of the signal in the memory device in;

[0013] Figure 5 For operation according to some embodiments of the present disclosure Figure 1 A flowchart of a method for a memory device in;

[0014] Figure 6 is a schematic diagram of a clock generator according to some embodiments of the present disclosure;

[0015] Figure 7 FIG. 1 shows a schematic diagram of some embodiments of the present disclosure. Figure 6 The waveform of the signal in the clock generator;

[0016] Figure 8 is a schematic diagram of a write port input latch circuit according to some embodiments of the present disclosure;

[0017] Fig. 9 FIG. 1 shows a schematic diagram of some embodiments of the present disclosure. Figure 1 The waveform of the signal in the memory device in;

[0018] Fig.10 FIG. 1 is a schematic diagram of a write port input latch circuit according to some embodiments of the present disclosure.

[0019]

Explanation of symbols

[0020] 10: Memory Device

[0021] 110:Memory Array

[0022] 111:Memory unit

[0023] 120: Clock generator

[0024] 130: Control circuit

[0025] 131: Write address latch

[0026] 140: Column decoder

[0027] 150: Input / output circuit

[0028] 151: Input Data

[0029] 161: dummy bit line

[0030] 200: Write port input latch circuit

[0031] 211: Latch circuit

[0032] 212: Latch circuit

[0033] 213: Latch circuit

[0034] 21n: Latch circuit

[0035] 220:Gate control circuit

[0036] 221:NAND Gate

[0037] 311~312: Latch circuit

[0038] 500:Method

[0039] 501: Operation

[0040] 502: Operation

[0041] 503: Operation

[0042] 504: Operation

[0043] 601~603: Delay chain

[0044] 604: Tracing character lines

[0045] 605: P-type transistor

[0046] 606: Delay circuit

[0047] 607: Tracking Unit

[0048] 608: Virtual pull-down device

[0049] 800: Write port input latch circuit

[0050] 1000: Write port input latch circuit

[0051] 1201:NAND Gate / Logic Circuit

[0052] 1202:SR latch / logic circuit

[0053] 1203: Inverter / Logic Circuit

[0054] 1204~1205: NOR gate / logic circuit

[0055] 1206: Inverter / Logic Circuit

[0056] 1207:NOR Gate / Logic Circuit

[0057] 1208~1209: Inverter / Logic Circuit

[0058] 1210:NAND Gate / Logic Circuit

[0059] 1211~1213: Inverter / Logic Circuit

[0060] 1214:NOR Gate / Logic Circuit

[0061] 1215:Inverter / Logic Circuit

[0062] 1216:NAND Gate / Logic Circuit

[0063] 1217~1221: Inverter / Logic Circuit

[0064] AA: write address

[0065] BL: Bit Line

[0066] BLB: Bit Line

[0067] Cbl:Capacitor

[0068] CKEN2:Signal

[0069] CKP1_AWS:Signal

[0070] CKP2_UNBUF: signal

[0071] CKP2D: gated clock signal

[0072] CKP2:Signaling

[0073] CKP3:Signaling

[0074] CKP: internal clock signal

[0075] D_Lat_1~D_Lat_3: Output signal

[0076] D_Lat_n: Nth output signal

[0077] D_OUT: gate output signal

[0078] DIN: Input signal

[0079] D: Terminal

[0080] EF1~EF5: Falling edge

[0081] ER1~ER7: rising edge

[0082] IN1: Inverter

[0083] IN2: Inverter

[0084] IO1: internal output signal

[0085] IO2: internal output signal

[0086] Lat_ck_1~Lat_ck_3: latch clock signal

[0087] Lat_ck_n: latch clock signal

[0088] N1~N8: Transistor

[0089] NP2AL:Signal

[0090] P1~P8: Transistor

[0091] Q:Terminal

[0092] Rbl: Resistor

[0093] RSC2: Reset signal

[0094] RSTCK2B: latch clock signal

[0095] RSTCK2D: latch clock signal

[0096] RSTCK2: Signal

[0097] T1~T7: Time

[0098] tcyc: clock cycle

[0099] TIN1: Three-state inverter

[0100] TIN2: Three-state inverter

[0101] VDDHD: voltage

[0102] VDDM: voltage

[0103] VSSI: voltage

[0104] WCKC: latch clock signal

[0105] WCKT: latch clock signal

[0106] WEB: Write enable signal

[0107] WL: Character Line DETAILED DESCRIPTION

[0108] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify an embodiment of the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, an embodiment of the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0109] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any term discussed herein, is illustrative only and in no way limits the scope and meaning of an embodiment of the present disclosure or the scope and meaning of any exemplified term. Likewise, an embodiment of the present disclosure is not limited to the various embodiments given in this specification.

[0110] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly a second element may be referred to as a first element without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0111] As used herein, the terms "comprising," "including," "having," "containing," "involving," and the like should be construed as open ended, ie, meaning including, but not limited to, including.

[0112] As used herein, "approximately," "about," "roughly," or "substantially" shall generally refer to any approximation or range of a given value, wherein the value or range varies according to the various technologies to which the value is related, and its range should be interpreted in the broadest sense as understood by a person familiar with an embodiment of the present disclosure to cover all such modifications and similar structures. In some embodiments, "approximately," "about," "roughly," or "substantially" shall generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The quantities given herein are approximate, thereby meaning that the terms "roughly," "about," "approximately," or "substantially" may be inferred without explicit statement, or mean other approximate values.

[0113] Throughout the description, the symbol “ / ” means “and” or “or”, and the symbol “ / ” means “and”, or “or” is related to the case where the symbol “ / ” is used.

[0114] A clock generation scheme and an exemplary clock generation circuit for reading and writing memory cells in a memory array are provided according to various exemplary embodiments. Variations and operation of the embodiments are discussed. Throughout the various views and illustrative embodiments, similar reference numbers are used to designate similar elements. Throughout, for example, Figure 4 , Figure 7 and Fig. 9 , the rising edge of some clock signals is used to trigger actions, such as the example of generating an internal clock signal edge. In alternative embodiments, the falling edge can also be used to trigger actions. It should be understood that the concepts "row" and "column" can be interchangeable, and the concepts "row address" and "column address" can be interchangeable, and the address can therefore be referred to as a "row / column" address, indicating that the address can be a row address or a column address.

[0115] View now Figure 1 . Figure 1 An exemplary block diagram of a memory device 10 including a memory array 110 and circuits according to some embodiments of the present disclosure is shown. For illustration, the memory device 10 further includes a clock generator 120, a control circuit 130, a row decoder 140, and an input / output circuit 150 for performing read and write operations on the memory array 110. The memory array 110 includes a plurality of memory cells 111 arranged in rows and columns of the memory array 110 and coupled to bit lines BL and BLB to receive data of the memory cells 111 or output data from the memory cells 111 in response to word lines WL. For illustrative purposes, only one column of the memory cells 111 is depicted. In some embodiments, the memory cell 111 includes a six-transistor (6T) static random access memory (SRAM) cell, wherein an exemplary circuit diagram of the 6T SRAM cell is depicted and operates as a pseudo dual port (PDP) memory cell. Although the external operation of the pseudo dual-port memory is similar to that of a real dual-port memory, the pseudo dual-port memory does not have a single-port core unit. The pseudo dual-port memory should perform multiple read and / or write operations within the same clock cycle of the internal clock signal CKP ( Figure 4 and Fig. 9 ). The timing is achieved by using an internal clock signal CKP.

[0116] The clock generator 120, the control circuit 130, the row decoder 140, and the input / output circuit 150 operate as support circuits for performing read and write operations on the memory array 110. For example, in some embodiments, the clock generator 120 is configured to receive an internal clock signal CKP to generate a corresponding clock signal, wherein the internal clock signal CKP includes two parts for a read operation and a write operation of the memory cell 111, respectively.

[0117] The control circuit 130 is used to control the peripheral circuits to perform read and write operations on the memory array 110. For example, in a write operation, the write address latch 131 and the pre-decoder (not shown) in the control circuit 130 are used to receive and latch the write address AA (row address) and pre-decode the write address AA. The pre-decoded address is provided to the row decoder 140, which selects one of the word lines WL and drives the word line WL. The selected word line WL is the word line of the memory cell 111 where the write operation is performed. The control circuit 130 is further used to receive a write enable signal WEB to trigger the write operation.

[0118] The input / output circuit 150 is used to decode the selected row of memory cells 111 to perform write operations and read operations. For example, in some embodiments, the input / output circuit 150 includes a row decoder, a read row decoder, and a sense amplifier, which are used to read and amplify signals from the bit lines BL and BLB of the memory array 110. In some embodiments, the input / output circuit 150 is further configured to drive input data 151 to be written to the bit lines BL and BLB of the memory array 110.

[0119] View now Figure 2 . Figure 2Schematic diagram of a write port input latch circuit 200 according to some embodiments of the present disclosure. The write port input latch circuit 200 is used to receive an input signal DIN and output a gated output signal D_OUT associated with the input signal DIN in response to latch clock signals Lat_ck_1-Lat_ck_2 and a gated clock signal CKP2D. In some embodiments, the write port input latch circuit 200 is coupled to an input terminal of the memory device 10 to receive an operation signal, such as a signal indicating a write address AA, a write enable signal WEB, or input data 151. In some embodiments, the write port input latch circuit 200 is implemented as a write address latch 131, and receives a signal indicating the write address AA as an input signal. In another embodiment, the write port input latch circuit 200 is included in the control circuit 130 to latch data associated with the write enable signal WEB, and further generate a corresponding signal as a gated output signal D_OUT to trigger a write operation. In yet another embodiment, the write port input latch circuit 200 is included in the input / output circuit 150 to receive the input data 151 as the input signal DIN and generate a corresponding signal as the gated output signal D_OUT to the bit lines BL and BLB of the memory array 110 .

[0120] For illustration, the write port input latch circuit 200 includes latch circuits 211 to 212 serially coupled to a gating circuit 220. In some embodiments, the gating circuit 220 includes a NAND gate 221. In operation, each of the latch circuits 211 to 212 is used to latch data associated with the input signal DIN in response to one of the latch clock signals Lat_ck_1 to Lat_ck_2. Specifically, as shown in FIG. Figure 2 In the embodiment shown in FIG. 1 , the latch circuit 211 is used to generate an output signal D_Lat_1 at a terminal Q in response to an input signal DIN received at a terminal D and a latch clock signal Lat_ck_1. The latch circuit 212 is used to generate an output signal D_Lat_2 at a terminal Q in response to an output signal D_Lat_1 received at a terminal D and a latch clock signal Lat_ck_2. The gating circuit 220 is used to generate a gated output signal D_OUT to the memory array 110 for a write operation in response to the output signal D_Lat_2 and the gating clock signal CKP2D.

[0121] Figure 2The configuration is given for illustrative purposes. Various implementations are within the contemplated scope of an embodiment of the present disclosure. For example, in some embodiments, the write port input latch circuit 200 is included in the input / output circuit 150 to latch data associated with the write enable signal BWEB representing a bit-write-enable-bar function, which performs a logical flip of the enable bit write signal; and further generates a corresponding signal as a gated output signal D_OUT of a write operation.

[0122] View now Figure 3 . Figure 3 According to some embodiments of the present disclosure, Figure 2 Detailed schematic diagram of latch circuits 311 to 312 of the write port input latch circuit 200. In some embodiments, latch circuit 311 is related to, for example, Figure 2 The latch circuit 211 is configured, and the latch circuit 312 is configured with respect to, for example Figure 2 The latch circuit 212 is configured.

[0123] Specifically, the latch circuit 311 includes a three-state inverter TIN1 composed of transistors P1 to P2 and N1 to N2, an inverter IN1, and transistors P3 to P4 and N3 to N4. The transistors P1 to P2 and N1 to N2 are serially coupled between voltage terminals to provide voltages VDDHD and VSSI. The gates of the transistors P1 and N1 receive latch clock signals WCKT and WCKC, respectively, wherein the latch clock signal WCKT is related to, for example, Figure 2 The latch clock signal Lat_ck_1 of the three-state inverter TIN1 is configured, and the latch clock signal WCKC is inverted from the latch clock signal WCKT. The gates of transistors P2 and N2 receive the input signal DIN. The inverter IN1 is used to generate the output signal D_Lat_1 based on the internal output signal IO1 from the three-state inverter TIN1. Transistors P3 to P4 and N3 to N4 are coupled in series between voltage terminals to provide voltages VDDHD and VSSI. The gates of transistors P3 and N3 are coupled to the output of the inverter IN1. The gates of transistors P4 and N4 receive the latch clock signals WCKC and WCKT, respectively. The sources of transistors P4 and N4 are coupled to transistors P3 and N3, respectively. The drains of transistors P4 and N4 are coupled to the input of the inverter IN1. The output of the inverter IN1 transmits the output signal D_Lat_1 to the latch circuit 312. The input signal DIN and the output signal D_Lat_1 have the same logic state which is different from the logic state of the internal output signal IO1 .

[0124] Similarly, the latch circuit 312 includes a tri-state inverter TIN2 composed of transistors P5 to P6 and N5 to N6, an inverter IN2, and transistors P7 to P8 and N7 to N8. The transistors P5 to P6 and N5 to N6 are coupled in series between voltage terminals to provide voltages VDDHD and VSSI. The gates of the transistors P5 and N5 receive latch clock signals RSTCK2D and RSTCK2B, respectively, wherein the latch clock signal RSTCK2D is related to, for example, Figure 2 The latch clock signal Lat_ck_2 is configured, and the latch clock signal RSTCK2D is inverted from the latch clock signal RSTCK2B. The gates of transistors P6 and N6 receive the output signal D_Lat_1. Inverter IN2 is used to generate the output signal D_Lat_2 based on the internal output signal IO2 from the three-state inverter TIN2. Transistors P7 to P8 and N7 to N8 are coupled in series between voltage terminals to provide voltages VDDHD and VSSI. The gates of transistors P7 and N7 are coupled to the output of inverter IN2. The gates of transistors P8 and N8 receive the latch clock signals RSTCK2B and RSTCK2D, respectively. The sources of transistors P8 and N8 are coupled to transistors P7 and N7, respectively. The drains of transistors P8 and N8 are coupled to the input of inverter IN2. The output of inverter IN2 transmits the output signal D_Lat_2 to Figure 2 The gate control circuit 220 of FIG. 31 shows that the input signal DIN, the output signal D_Lat_2 and the output signal D_Lat_1 have the same logic state which is different from the logic state of the internal output signal IO2. In other words, the data of the input signal DIN is output through the latch circuits 311 to 312.

[0125] In some embodiments, Figure 3 As shown in FIG. 1 , the bases of transistors P1 to P8 receive voltage VDDM, and the bases of transistors N1 to N8 receive voltage VSSI.

[0126] In various embodiments, inverters IN1 and IN2 are configured to be operated by voltages VDDHD, VDDM, and VSSI.

[0127] Figure 3 The configuration is given for illustrative purposes. Various implementations are within the contemplated scope of an embodiment of the present disclosure. For example, in some embodiments, other latch circuits are suitable for implementing the present application.

[0128] View now Figures 4 to 5 and Figures 1 to 3 configuration. Figure 4 FIG. 1 shows a schematic diagram of ... Figure 5 Method 500 of operation Figure 1 The waveform of the signal of the memory device 10 in FIG. Figure 5 For operation according to some embodiments of the present disclosure Figure 1 Flowchart of method 500 of memory device 10 in FIG. 1 . It should be understood that additional operations / stages may be performed by Figure 5 The depicted process is provided before, during, and after, and some of the operations / stages described below may be replaced or eliminated for additional embodiments of method 600. Method 500 includes operations 501 to 504, and will be referred to in detail in detail. Figures 1 to 5 Discussed in the following paragraphs.

[0129] For illustration purposes, Figure 4 As shown in FIG. 1 , the latch clock signal WCKT and the latch clock signal RSTCK2D partially and continuously overlap in the clock cycle tcyc of the internal clock signal DKP from time T1 to time T7. In some embodiments, in the clock cycle tcyc, the read operation of the memory array 110 is triggered by the read pulse of the internal clock signal CKP, and the write operation thereof is triggered by the write pulse of the internal clock signal CKP. In other words, the read operation and the write operation of the memory array 110 are performed in the same clock cycle of the internal clock signal CKP.

[0130] Specifically, in Figure 5 In operation 501, the read operation of the memory array 110 is triggered by the rising edge ER1 of the read pulse of the internal clock signal CKP at time T1. Figure 4 shown in.

[0131] At operation 502, as Figure 4 As shown in FIG. 1 , the clock generator 120 generates a rising edge ER2 of the latch clock signal WCKT based on a rising edge ER1 of the internal clock signal CKP to latch the data of the output signal D_Lat_1. Specifically, at time T2, the latch circuit 311 operates in a latch mode to latch the data of the output signal D_Lat_1 having a high logic state in response to the latch clock signals WCKT and WCKC. The latch circuit 312 operates in a transparent mode to read data from the output signal D_Lat_1. Therefore, after time T2, the latch circuit 312 generates an output signal D_Lat_2 having a high logic state in response to the output signal D_Lat_1.

[0132] In operation 503, Figure 4, the read operation of the memory array 110 is triggered by the rising edge ER3 of the write pulse of the internal clock signal CKP at time T3. In some embodiments, the clock generator 120 further generates a rising edge ER4 of the gated clock signal CKP2D in response to the rising edge ER3. Therefore, the gating circuit 220 generates a gated output signal D_OUT having a high logic state based on the output signal D_Lat_2. In other words, the data of the input signal DIN is "clocked out" from the write port input latch circuit 200 to the memory array 110 for the write operation.

[0133] In operation 504, the clock generator 120 generates a rising edge ER5 of the latch clock signal RSTCK2D based on the rising edge ER3 of the internal clock signal CKP to latch the data of the output signal D_Lat_2. Specifically, at time T4, both latch circuits 311 to 312 operate in a latching mode to latch the data of the output signals D_Lat_1 and D_Lat_2 for the write operation of the memory array 110, respectively.

[0134] In some embodiments, the time difference between the rising edge ER2 of the latch clock signal WCKT and the rising edge ER5 of the latch clock signal RSTCK2D is greater than the delay time between the input terminal of the latch circuit 312 receiving the input signal D_Lat_1 and the output terminal outputting the output signal D_Lat_2. In other words, the time difference between the rising edges ER2 and ER5 ensures that the logic states of the output signals D_Lat_1 to D_Lat_2 are the same before the latch circuit 312 switches to the latch mode to ensure that the data of the output signal D_Lat_2 is accurate. In some embodiments, the delay time between the input terminal and the output terminal of the latch circuit 312 is generated by the tri-state inverter TIN2 and the inverter IN2. Since the rising edges of the pulses in the latch clock signal WCKT and the latch clock signal RSTCK2D are associated with the time delay generated by the tri-state inverter and the inverter in the latch circuit 312, the pulse width of the latch clock signal is associated with the time delay generated by the tri-state inverter and the inverter in the latch circuit.

[0135] In some embodiments, at time T5, the clock generator 120 generates a falling edge EF1 of the latch clock signal WCKT. Figure 4As shown in , the falling edge EF1 of the latch clock signal WCKT is after the rising edge ER5 of the latch clock signal RSTCK2D. In other words, the rising edge ER5 of the latch clock signal RSTCK2D is between the rising edge ER2 of the latch clock signal WCKT and the falling edge EF1 of the latch clock signal WCKT. In response to the falling edge EF1 of the latch clock signal WCKT, the latch circuit 311 switches to operate in a transparent mode to read the data of the input signal DIN, while the latch circuit 312 still operates in a latch mode to latch the data of the output signal D_Lat_2. Therefore, the logic state of the output signal D_Lat_1 changes, for example, from a high logic state to a low logic state associated with the input signal DIN, and the logic state of the output signal D_Lat_2 remains at a high logic state, as shown in FIG. Figure 4 As shown in the embodiment of .

[0136] In some embodiments, the clock generator 120 further generates a falling edge EF2 of the gated clock signal CKP2D based on a falling edge EF3 of a write pulse in the internal clock signal CKP in response to termination of a write operation to the memory array 110. Figure 4 As shown schematically in the figure, the falling edge EF2 of the gate clock signal CKP2D is after the falling edge EF1 of the latch clock signal WCKT and the falling edge EF3 of the internal clock signal CKP.

[0137] In addition, at time T6, the clock generator 120 generates a falling edge EF4 of the latch clock signal RSTCK2D based on the falling edge EF3 of the internal clock signal CKP. In response to the falling edge EF4 of the latch clock signal RSTCK2D, the latch circuit 312 changes from the latch mode to the transparent mode, while the latch circuit 311 operates in the transparent mode. Therefore, the logic state of the output signal D_Lat_2 changes from a high logic state to a low logic state, for example.

[0138] In some embodiments, Figure 4 In the embodiment shown in FIG. 1 , the falling edge EF4 of the latch clock signal RSTCK2D is after the falling edge EF2 of the gate clock signal CKP2D. The falling edge EF4 of the latch clock signal RSTCK2D is further before the rising edge ER6 of the latch clock signal WCKT in the next cycle.

[0139] View now Figure 6 . Figure 6 is a schematic diagram of a clock generator 120 according to some embodiments of the present disclosure. In some embodiments, the clock generator 120 is used to generate a signal used in the memory device 10, such as Figures 1 to 5 shown in.

[0140] For illustration, the clock generator 120 includes a plurality of logic circuits (e.g., NOR gates, NAND gates, inverters and / or buffers) 1201 to 1221, delay chains 601 to 603 and a delay circuit 606 to generate signals for operating the memory device 10, which has a clock source 1201 to 1221. Figures 2 to 3 The write port input latch circuit 200 in FIG. 1 is a clock source of the clock generator 120. In some embodiments, the clock generator 120 is implemented as a self-timing clock generator by the reset signal RSC2 associated with the write operation. The design of the reset signal RSC2 ensures that the pulses in the latch clock signal WCKT and the latch clock signals RSTCK2D partially overlap each other and thus the falling edge EF4 of the latch clock signal RSTCK2D is after the falling edge EF2 of the gate clock signal CKP2D to ensure that the internal holding time of the data of the output signal D_Lat_2 from the gate circuit 220 is sufficient. In other words, the latch circuit 312 latches the data of the output signal D_Lat_2 until the gate circuit 220 fully outputs the data to the memory array 110 for the write operation.

[0141] In operation, according to some embodiments, NAND gate 1201 receives signals CKP1_AWS, CKEN2, and reset signal RSC2, and outputs a corresponding output to SR latch 1202. In some embodiments, the pulse in signal CKP1_AWS corresponds to the read pulse of internal clock signal CKP. SR latch 1202 generates signal NP2AL to inverter 1203 based on the output of NAND gate 1201 and reset signal RSC2. NOR gate 1204 receives the output from inverter 1203 and signal CKP1_AWS to generate signal CKP2_UNBUF to delay chain 601 and NOR gate 1205.

[0142] To generate the latch clock signals WCKT and WCKC, the NOR gate 1205 generates corresponding outputs to the inverter 1206 based on the signals NP2AL, CKP2_UNBUF, and CKP1_AWS. The inverter 1206 generates the signal CKP3 to the NOR gate 1207. The NOR gate 1207 generates corresponding outputs to the inverter 1208 based on the signals CKP1_AWS and CKP3. The inverter 1208 generates the latch clock signal WCKT by inverting the output of the NOR gate 1207. The inverter 1209 generates the latch clock signal WCKC by inverting the latch clock signal WCKT.

[0143] In some embodiments, the delay chain 601 includes a certain number of buffers to delay the signal CKP2_UNBUF to further generate the signal CKP2 via the NAND gate 1210 and the inverters 1211 to 1213. In some embodiments, the number of buffers in the delay chain 601 is associated with and determined by the time difference between the read operation and the write operation of the memory array 110. In some embodiments, the signal CKP2 corresponds to the write pulse of the internal clock signal CKP.

[0144] To generate the gated clock signal CKP2D, the signal CKP2 is transmitted to the NOR gate 1214, and the delay chain 602 generates a delayed signal based on the CKP2 to the NOR gate 1214. The NOR gate 1214 generates a corresponding output to the inverter 1215 based on the delayed signal and the signal CKP2, thereby generating the gated clock signal CKP2D. In some embodiments, the delay chain 602 includes a certain number of buffers to delay the signal CKP2, and the number of buffers in the delay chain 602 is associated with the write operation of the memory array 110.

[0145] The delay chain 603 including a certain number of buffers delays the signal CKP2 and generates a corresponding delayed signal to the NAND gate 1216. The NAND gate 1216 receives the delayed signal and the signal CKP2 to generate an output to the inverter 1217. The output of the inverter 1217 is coupled to the delay circuit in the clock generator 120 and the gate of the P-type transistor 605 via the tracking word line 604. The transistor 605 has a source coupled to a voltage terminal to provide, for example, the voltage VDDHD, and a drain coupled to the delay circuit 606 and the inverter 1218 via the dummy bit line 161 in the delay circuit 606.

[0146] The delay circuit 606 further includes a tracking unit 607 having a plurality of dummy pull-down devices 608. Figure 6 As shown, the gate of the dummy pull-down device 608 is coupled to the tracking word line 604, the source / drain of the dummy pull-down device 608 is coupled to the dummy bit line 161, and the drain / source of the dummy pull-down device 608 is coupled to ground or a voltage corresponding to a low logic state.

[0147] In some embodiments, the delay circuit 606 is used to delay a portion of a write pulse of the internal clock signal CKP, such as the signal CKP2, to generate a latched clock signal RSTCK2D. The dummy bit line 161 has a length that is close to the length of a bit line coupled to the memory array 110, such as the bit line BL or BLB. The dummy pull-down device 608 is used to track the execution of the bit line to precharge the memory array 110. For example, the dummy pull-down device 608 tracks the execution of a device (not shown) in the bit line precharging circuit of the input / output circuit 150 (for example, by matching the size). The capacitor Cbl of the dummy pull-down device 608 is designed to have a tracking capacity of the regular bit lines BL and BLB ( Figure 1 ) of the capacitor. This can be achieved by forming a dummy bit line 161 ( Figure 1 ) is achieved, the dummy bit line 161 may have the same length as the regular bit lines BL and BLB ( Figure 1 ). The capacitance of dummy bit line 161 is used as the capacitance of Cbl. Similarly, resistor Rbl of dummy pull-down device 608 is designed to have a tracking capacitance of regular bit lines BL and BLB ( Figure 1 ). This can also be achieved by forming a dummy bit line 161, which can have the same length and the same width as the regular bit lines BL and BLB, where the dummy bit line 161 acts as the resistor Rbl. In some embodiments, the delay circuit 606 also has an increased delay when the bit line precharge takes a long time due to, for example, the long bit lines BL and BLB, and vice versa. The resulting clock generator 120 thus has an optimized bit line precharge time, and the frequency of write operations can be increased.

[0148] Continue to view Figure 6 , inverter 1218 generates signal RSTCK2 according to the output of delay circuit 606 to inverters 1219 to 1220. Inverter 1219 generates reset signal RSC2 based on RSTCK2 to NAND gate 1201 and SR latch 1202. Inverter 1220 generates latch clock signal RSTCK2B to inverter 1221, thereby generating latch clock signal RSTCK2D.

[0149] View now Figure 7 . Figure 7 FIG. 1 shows a schematic diagram of some embodiments of the present disclosure. Figure 6 The waveform of the signal in the clock generator 120.

[0150] In some embodiments, the rising edge of the signal CKP1_AWS triggers the rising edge of the latch clock signal WCKT, and the falling edge of the signal CKP1_AWS triggers the rising edge of the signal CKP2_UNBUF. The falling edge of the signal CKP2_UNBUF triggers the falling edge of the signal CKP2 and the falling edge of the latch clock signal WCKT. In some embodiments, the rising edge of the signal RSTCK2 triggers the falling edge of the latch clock signal WCKT. The rising edge of the signal CKP2 triggers the rising edge of the gated clock signal CKP2D. The falling edge of the signal CKP2 triggers the falling edge of the signal RSTCK2 and the falling edge of the gated clock signal CKP2D. The rising edge of the signal RSTCK2 triggers the rising edge of the latch clock signal RSTCK2D, and the falling edge of the signal RSTCK2 triggers the falling edge of the latch clock signal RSTCK2D.

[0151] View now Figure 8 . Figure 8 FIG. 8 is a schematic diagram of a write port input latch circuit 800 according to some embodiments of the present disclosure. In some embodiments, the write port input latch circuit 800 is related to, for example, Figure 2 The write port input latch circuit 200 is configured. Figures 1 to 7 An embodiment of Figure 8 Similar elements in the embodiment are designated by the same reference numerals for ease of understanding. Specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted herein for brevity.

[0152] and Figure 2 Compared with the embodiment of the present invention, the write port input latch circuit 800 further includes a latch circuit 213 coupled between the latch circuit 212 and the gating circuit 220. In some embodiments, the latch circuit 213 is configured with respect to the latch circuit 212, for example, and is used to generate an output signal D_Lat_3 based on the output signal D_Lat_2 in response to the latch clock signal Lat_ck_3, and the gating circuit 220 generates a gated output signal D_OUT based on the output signal D_Lat_3.

[0153] View now Fig. 9 . Fig. 9 FIG. 1 shows a schematic diagram of some embodiments of the present disclosure. Figure 1 In Figure 8 The waveform of the signal in the memory device 10 of the write port input latch circuit 800.

[0154] For illustration, pulses in the latch clock signals Lat_ck_1 to Lat_ck_3 partially and continuously overlap with each other, and the pulse widths of the latch clock signals Lat_ck_1 to Lat_ck_3 are associated with time delays generated by the serially coupled tri-state inverters and inverters in the latch circuits 211 to 213 .

[0155] Specifically, regarding e.g. Figure 4 The falling edge EF1 of the latch clock signal Lat_ck_1 configured by the latch clock signal WCKT is between the rising edge ER5 of the latch clock signal Lat_ck_2 and the falling edge EF5 of the latch clock signal Lat_ck_2. Similarly, the rising edge ER7 of the latch clock signal Lat_ck_3 is before the falling edge EF5 of the latch clock signal Lat_ck_2. The falling edge EF6 of the latch clock signal Lat_ck_3 is after the falling edge EF2 of the gated clock signal CKP2D.

[0156] like Figures 8 to 9 As shown in FIG. 2 , at time T2 , latch circuit 211 latches data of output signal D_Lat_1 in latch mode, while latch circuits 212 to 213 operate in transparent mode to sequentially read output signals D_Lat_1 and D_Lat_2 . Latch circuit 213 further generates output signal D_Lat_3 having the same logic state as input signal DIN.

[0157] At time T3 , the latch circuit 212 switches to the latch mode in response to the rising edge ER5 of the latch clock signal Lat_ck_2 .

[0158] In some embodiments, after time T3, latch circuit 211 switches to transparent mode to read data of input signal DIN in response to falling edge EF1 of latch clock signal Lat_ck_1 and thus the logic state of output signal D_Lat_1 changes. However, the logic state does not change due to latch circuit 212 operating in latch mode.

[0159] At time T4 , the latch circuit 213 switches to the latch mode in response to the rising edge ER7 of the latch clock signal Lat_ck_3 .

[0160] In some embodiments, after time T4, latch circuit 212 switches to transparent mode to read data of output signal D_Lat_1 in response to falling edge EF5 of latch clock signal Lat_ck_2 and thus the logic state of output signal D_Lat_2 changes. However, the logic state does not change due to latch circuit 213 operating in latch mode.

[0161] At time T5 , the latch circuit 213 switches to the transparent mode to read the data of the output signal D_Lat_2 in response to the falling edge EF6 of the latch clock signal Lat_ck_3 , and thus the logic state of the output signal D_Lat_3 changes.

[0162] View now Fig.10 . Fig.10 FIG. 1 is a schematic diagram of a write port input latch circuit 1000 according to some embodiments of the present disclosure. Figures 1 to 9 An embodiment of Fig.10 Similar elements in the drawings are designated by the same reference numerals for ease of understanding.

[0163] In some embodiments, the write port input latch circuit 1000 is related to, for example, Figure 2 The write port input latch circuit 200 and Figure 8 The write port input latch circuit 800 is configured. Figure 8 Compared with the embodiment of the present invention, the write port input latch circuit 1000 further includes a number N of latch circuits 211 to 21n, where N is a positive integer. In some embodiments, N is equal to or greater than 3. For illustration, the gating circuit 220 is coupled to the Nth latch circuit 21n of the latch circuits 211 to 21n, and is used to generate a gated output signal D_OUT to the memory array 110 in response to the Nth output signal D_Lat_n and the gating clock signal CKP2D for a write operation of the memory array 110.

[0164] In some embodiments, the latch clock signals Lat_ck_1 to Lat_ck_n partially and continuously overlap each other, wherein the rising edge of the pulse in the Mth latch clock signal of the latch clock signals Lat_ck_1 to Lat_ck_n is between the rising edge and the falling edge of the (M-1)th latch clock signal of the latch clock signals Lat_ck_1 to Lat_ck_n. M is a positive integer less than N. For example, when N is equal to 3 and M is equal to 2, Fig. 9 As shown in FIG. 2 , the rising edge ER5 of the latch clock signal Lat_ck_2 is between the rising edge ER2 of the latch clock signal Lat_ck_1 and the falling edge EF1 of the latch clock signal Lat_ck_1 .

[0165] Furthermore, according to some embodiments, the falling edge of the latch clock signal Lat_ck_n is after the falling edge of the gate clock signal CKP2D.

[0166] Generally speaking, the operation time of the write operation is the bottleneck of the cycle time of the pseudo dual-port SRAM, which is because the faster possible frequency (Fmax) is the main concern of the SRAM design for high performance computing (HPC) applications. For example, in some methods with a latch circuit and a gating circuit for latching and outputting data associated with a write port (e.g., a write enable pin, a write address pin, and / or a data pin), the faster possible frequency Fmax is limited by the write port interface setting time. In other words, the long cycle time for latching data in a write operation constrains the increase of the faster possible frequency Fmax. In a certain architecture of the method, the falling edge of the latch clock signal of the latch circuit of the write port is designed to be triggered after the write operation is completed. In other words, according to some methods, the falling edge of the latch clock signal is after the falling edge of the clock signal of the gating circuit, which outputs data to the memory array. Therefore, sufficient pulse width is necessary for the latch clock signal and is not reduced, which increases the total cycle time.

[0167] As described above, in the configuration of one embodiment of the present disclosure, at least two latch circuits are configured in the write port input latch circuit, and the corresponding latch clock signals partially and sequentially overlap each other, which causes the latch circuits to latch the input data sequentially. Therefore, the last latch circuit and the gating circuit cooperate to output the data of the write operation in response to the corresponding latch clock signal during the internal hold time, which is relative to the data hold time of the first latch circuit in the write port input latch circuit. In other words, the data hold time of the first latch circuit can be shortened with respect to the last latch circuit latching the data. Correspondingly, an increased faster possible frequency Fmax is achieved.

[0168] In some embodiments, the first edge and the second edge of the internal clock signal are a plurality of rising edges.

[0169] In some embodiments, a falling edge of the gated clock is after a falling edge after the second edge of the internal clock signal.

[0170] In some embodiments, a second edge of the second latch clock signal is after the falling edge of the gating clock.

[0171] In some embodiments, the second latch circuit is used to latch a data of the second output signal when the first latch circuit is used to be in a transparent mode to read a data of the input signal.

[0172] In some embodiments, a time difference between a first edge of the first latch clock signal and a first edge of the second latch clock signal is greater than a delay time between an input terminal and an output terminal of the second latch circuit.

[0173] In some embodiments, the memory device further comprises a clock generator comprising a delay circuit, wherein the delay circuit is used to delay a portion of the internal clock signal to generate the second latch clock signal.

[0174] In some embodiments, the delay circuit includes a dummy bit line having a length that approximates a length of a bit line coupled to the memory array; and a plurality of dummy pull-down devices for tracking an execution of precharging of a bit line of the memory array.

[0175] In some embodiments, the first latch circuit includes a first tri-state inverter and a first inverter coupled to the first tri-state inverter, the first tri-state inverter is used to generate a first internal output signal to the first inverter based on the input signal, and the first inverter is used to generate a first output signal based on the first internal output signal. The second latch circuit includes a second tri-state inverter and a second inverter coupled to the second tri-state inverter, the second tri-state inverter is used to generate a second internal output signal to the second inverter based on the first output signal, and the second inverter is used to generate a second output signal based on the second internal output signal.

[0176] In some embodiments, a memory device is disclosed. The memory device includes a memory array, and first to second latch circuits. A read operation is triggered by a first edge of an internal clock signal, and a write operation is triggered by a second edge of the internal clock signal. The read operation and the write operation of the memory array are performed within a same clock cycle of the internal clock signal. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal. A first edge of the first latch clock signal is generated based on the first edge of the internal clock signal. The second latch circuit is coupled to an output end of the first latch circuit and generates a second output signal in response to the first output signal and a second latch clock signal. A first edge of the second latch clock signal is between a first edge of the first latch clock signal and a second edge of the first latch clock signal. The memory device further includes a gating circuit for generating a third output signal of the memory array for a write operation in response to the second output signal and a gating clock generated based on the second edge of the internal clock signal.

[0177] A memory device is also disclosed, which includes a plurality of latch circuits and a gating circuit. Each of the plurality of latch circuits is used to latch data associated with an input signal in response to a corresponding latch clock signal among a plurality of latch clock signals. A plurality of pulses among the plurality of latch clock signals partially and continuously overlap in a clock cycle of an internal clock signal. The gating circuit is coupled to an Nth latch circuit among the latch circuits and is used to generate a gated output signal to a memory array in response to an Nth output signal of the Nth latch circuit and a gating clock signal for a write operation of the memory array. N is a number of latch circuits. A read operation of the memory array is triggered by a first pulse of the internal clock signal, and a write operation of the memory array is triggered by a second pulse of the internal clock signal. The read operation and the write operation of the memory array are performed within the same clock cycle of the internal clock signal.

[0178] In some embodiments, the latch circuit is serially coupled between an input terminal of the memory device for transmitting an input signal and the gate circuit.

[0179] In some embodiments, a falling edge of a pulse in a first one of the latch clock signals is before a falling edge of the gating clock signal.

[0180] In some embodiments, a falling edge of a pulse in an Nth latch clock signal in the latch clock signal is after a falling edge of the gating clock signal.

[0181] In some embodiments, a rising edge of a pulse in an Mth latch clock signal in the latch clock signal is between a rising edge and a falling edge of an (M-1)th latch clock signal in the latch clock, where M is a positive integer less than N.

[0182] In some embodiments, a falling edge of a pulse in a first latch clock signal of the latch clock signal is after a rising edge of a second latch clock signal of the latch clock signal.

[0183] In some embodiments, each of the latch circuits includes a tri-state inverter and an inverter, the tri-state inverter and the inverter are serially coupled to receive an output signal from a previous latch circuit in the latch circuits and output the output signal to a next latch circuit in the latch circuits. Multiple pulse widths of pulses in the latch clock signal are associated with a time delay generated by the tri-state inverter and the inverter.

[0184] A method of a memory device is also disclosed, the method comprising the following operations: triggering a read operation of a memory array by a first rising edge of an internal clock signal; generating a first rising edge of a first latch clock signal based on the first rising edge of the internal clock signal to latch a data of a first output signal; triggering a write operation of the memory array by a second rising edge of the internal clock signal; and generating a rising edge of a second latch clock signal based on the second rising edge of the internal clock signal to latch a data of a second output signal for the write operation of the memory array, wherein the rising edge of the second latch clock signal is before a falling edge of the first latch clock signal. The read operation and the write operation of the memory array are performed within a same clock cycle of the internal clock signal.

[0185] In some embodiments, the method of the memory device further comprises the following steps: generating a rising edge of a gating clock signal based on a first falling edge of the internal clock signal to generate a gated output signal to the memory array based on the second output signal.

[0186] In some embodiments, the method of the memory device further comprises the following steps: generating a falling edge of the gated clock signal based on a second falling edge of the internal clock signal, wherein the falling edge of the gated clock signal is after the falling edge of the first latched clock signal.

[0187] In some embodiments, the method of the memory device further comprises the following steps: generating a falling edge of the second latch clock signal based on a first falling edge of the internal clock signal to change a logic state of the second output signal. The falling edge of the second latch clock signal is before a second rising edge of the first latch clock signal.

[0188] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of an embodiment of the present disclosure. Those skilled in the art will appreciate that they may readily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. A memory device, characterized in that: Include: A memory array, wherein a read operation of the memory array is triggered by a first edge of an internal clock signal, and a write operation of the memory array is triggered by a second edge of the internal clock signal, wherein the read operation and the write operation of the memory array are performed within a same clock cycle of the internal clock signal; a first latch circuit for generating a first output signal in response to an input signal and a first latch clock signal, wherein a first edge of the first latch clock signal is generated based on the first edge of the internal clock signal; a second latch circuit coupled to an output terminal of the first latch circuit and configured to generate a second output signal in response to the first output signal and a second latch clock signal, wherein a first edge of the second latch clock signal is between the first edge of the first latch clock signal and a second edge of the first latch clock signal; and A gating circuit is used for generating a third output signal to the memory array for the write operation in response to the second output signal and a gating clock generated based on the second edge of the internal clock signal.

2. The memory device as claimed in claim 1, wherein the first edge and the second edge of the internal clock signal are a plurality of rising edges.

3. The memory device of claim 1 , wherein a falling edge of the gating clock is after a falling edge after the second edge of the internal clock signal, and a second edge of the second latch clock signal is after the falling edge of the gating clock.

4. The memory device as claimed in claim 1, wherein a time difference between the first edge of the first latch clock signal and the first edge of the second latch clock signal is greater than a delay time between an input terminal and an output terminal of the second latch circuit.

5. The memory device of claim 1, further comprising: A clock generator includes a delay circuit, wherein the delay circuit is used to delay a portion of the internal clock signal to generate the second latch clock signal. The delay circuit comprises: a dummy bit line having a length that is close to a length of a bit line coupled to the memory array; and A plurality of dummy pull-down devices are used to track an execution of a bit line precharge of the memory array.

6. The memory device as claimed in claim 1 , wherein the first latch circuit comprises a first tri-state inverter and a first inverter coupled to the first tri-state inverter, the first tri-state inverter is used to generate a first internal output signal to the first inverter based on the input signal, and the first inverter is used to generate the first output signal based on the first internal output signal; The second latch circuit includes a second tri-state inverter and a second inverter coupled to the second tri-state inverter, the second tri-state inverter is used to generate a second internal output signal to the second inverter based on the first output signal, and the second inverter is used to generate the second output signal based on the second internal output signal.

7. A memory device, characterized in that: Include: a plurality of latch circuits, each for latching data associated with an input signal in response to a corresponding latch clock signal among a plurality of latch clock signals, wherein a plurality of pulses among the plurality of latch clock signals partially and continuously overlap in a clock cycle of an internal clock signal; and a gating circuit coupled to an Nth latch circuit among the plurality of latch circuits and configured to generate a gating output signal to a memory array in response to an Nth output signal of the Nth latch circuit and a gating clock signal for a write operation of the memory array, wherein N is a number of the plurality of latch circuits, A read operation of the memory array is triggered by a first pulse of the internal clock signal, and a write operation of the memory array is triggered by a second pulse of the internal clock signal, wherein the read operation and the write operation of the memory array are performed within a same clock cycle of the internal clock signal.

8. The memory device of claim 7, wherein a falling edge of a pulse in a first latch clock signal among the plurality of latch clock signals is before a falling edge of the gating clock signal, and A falling edge of a pulse in an Nth latch clock signal among the plurality of latch clock signals is after the falling edge of the gating clock signal, A rising edge of a pulse in an Mth latch clock signal among the multiple latch clock signals is between a rising edge and a falling edge of an (M-1)th latch clock signal among the multiple latch clocks, and M is a positive integer less than N.

9. A method for operating a memory device, characterized in that: The following steps are involved: A read operation of a memory array is triggered by a first rising edge of an internal clock signal; Generate a first rising edge of a first latch clock signal based on the first rising edge of the internal clock signal to latch data of a first output signal; triggering a write operation of the memory array by a second rising edge of the internal clock signal; and A rising edge of a second latch clock signal is generated based on the second rising edge of the internal clock signal to latch data of a second output signal for the write operation of the memory array, wherein the rising edge of the second latch clock signal is before a falling edge of the first latch clock signal, The read operation and the write operation of the memory array are executed within a same clock cycle of the internal clock signal.

10. The method of claim 9, further comprising the steps of: Generating a rising edge of a gated clock signal based on a first falling edge of the internal clock signal to generate a gated output signal to the memory array based on the second output signal; and A falling edge of the gated clock signal is generated based on a second falling edge of the internal clock signal, The falling edge of the gating clock signal is after the falling edge of the first latching clock signal.

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