Manufacturing method of semiconductor structure
In the manufacturing process of semiconductor structures, the frequency and duty cycle of the radio frequency signal are adjusted by using plasma dry etching technology, and the problem of micro-trench phenomenon at the bottom of the trench is solved and the reliability of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202311050641.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-18
- Publication Date
- 2025-02-21
AI Technical Summary
During the etching of the semiconductor material layer to form trenches, micro-trench phenomena are prone to occur at the bottom of the trench, resulting in holes appearing during subsequent filling, affecting the reliability of the semiconductor structure.
By performing plasma dry etching in the first groove, the frequency and duty cycle of the radio frequency signal are adjusted to make the bottom of the second groove flat, and the occurrence of micro groove phenomena are avoided.
The bottom of the second groove is flattened, the reliability of the semiconductor structure is improved, and the occurrence of holes is avoided.
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Figure CN119495565A_ABST
Abstract
Description
Technical Field
[0001] The disclosed embodiments relate to the field of semiconductor technology, and more particularly to a method for manufacturing a semiconductor structure. Background Art
[0002] At present, in the process of etching the semiconductor material layer to form a groove, a micro-trenches phenomenon is likely to occur at the bottom of the groove. In the subsequent process of filling the groove, holes are likely to appear at the micro-trenches at the bottom of the groove, thereby affecting the reliability of the semiconductor structure.
[0003] Therefore, there is an urgent need to improve the manufacturing method of the semiconductor structure to enhance the reliability of the semiconductor structure. Summary of the invention
[0004] In view of this, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:
[0006] The present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:
[0007] A stacking structure is provided; the stacking structure comprises a first semiconductor layer, a first dielectric layer, a second semiconductor layer and a second dielectric layer stacked in sequence; a first groove penetrating the second dielectric layer and the second semiconductor layer and exposing a surface of the first dielectric layer is formed in the stacking structure;
[0008] In the first etching process, a portion of the first dielectric layer is etched through the first groove to form a second groove; wherein the height of the second groove along the stacking direction is less than the height of the first dielectric layer along the stacking direction; the first etching process is a plasma dry etching process, and the bottom of the second groove is flat by adjusting the frequency and duty cycle of the radio frequency signal in the first etching process.
[0009] In some embodiments, the frequency range of the radio frequency signal in the first etching process is 150 Hz to 500 Hz;
[0010] The duty cycle of the radio frequency signal in the first etching process ranges from 20% to 70%.
[0011] In some embodiments, the etching gas in the first etching process includes carbon tetrafluoride;
[0012] In the first etching process, the RF power ranges from 200W to 700W, and the bias voltage ranges from 120V to 220V.
[0013] In some embodiments, a ratio between a height of the second groove along the stacking direction and a height of the first dielectric layer along the stacking direction is greater than a preset value.
[0014] In some embodiments, the stacked structure further includes an anti-reflective coating and a photoresist layer sequentially disposed on the second dielectric layer;
[0015] Before providing the stacking structure, the manufacturing method further includes:
[0016] Performing patterning on the photoresist layer to form a patterned photoresist layer;
[0017] In the second etching process, the anti-reflective coating is etched using the patterned photoresist layer as a mask to form an opening.
[0018] In some embodiments, providing a stacking structure includes:
[0019] In a third etching process, the patterned photoresist layer is used as a mask to etch and form a first sub-groove that penetrates the second dielectric layer and extends into the second semiconductor layer; wherein the bottom of the first sub-groove is flattened by adjusting the process parameters of the third etching process;
[0020] In the fourth etching process, the patterned photoresist layer is used as a mask to etch and form a second sub-groove that penetrates the second semiconductor layer and exposes the surface of the first dielectric layer; wherein the first sub-groove and the second sub-groove are connected, and the first sub-groove and the second sub-groove together form the first groove.
[0021] In some embodiments, in the third etching process, the second dielectric layer has a first etching selectivity ratio to the second semiconductor layer;
[0022] In the fourth etching process, the second semiconductor layer has a second etching selectivity ratio to the first dielectric layer; wherein the first etching selectivity ratio is smaller than the second etching selectivity ratio.
[0023] In some embodiments, the etching gas used in the second etching process includes carbon oxysulfide, oxygen and an inert gas; wherein the ratio between carbon oxysulfide and oxygen ranges from 0.5 to 1.2;
[0024] The etching gas used in the third etching process includes carbon tetrafluoride, oxygen and an inert gas; wherein the ratio between carbon tetrafluoride and oxygen is in the range of 4.5 to 5.5;
[0025] The etching gas used in the fourth etching process includes hydrogen bromide, oxygen and an inert gas; wherein the ratio between hydrogen bromide and oxygen is in the range of 30 to 40.
[0026] In some embodiments, in the first etching process, after etching the first dielectric layer through the first groove to form a second groove, the manufacturing method further includes:
[0027] The patterned photoresist layer and the anti-reflective coating layer having the opening are removed.
[0028] In some embodiments, in the second etching process, the RF power ranges from 700W to 1000W, and the bias voltage ranges from 50V to 200V;
[0029] In the third etching process, the RF power ranges from 300W to 400W, and the bias voltage ranges from 50V to 150V;
[0030] In the fourth etching process, the RF power ranges from 300W to 450W, and the bias voltage ranges from 30V to 100V.
[0031] The embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes: providing a stacking structure; the stacking structure includes a first semiconductor layer, a first dielectric layer, a second semiconductor layer, and a second dielectric layer stacked in sequence; a first groove penetrating the second dielectric layer and the second semiconductor layer and exposing the surface of the first dielectric layer is formed in the stacking structure; in a first etching process, a portion of the first dielectric layer is etched through the first groove to form a second groove; wherein the height of the second groove along the stacking direction is less than the height of the first dielectric layer along the stacking direction; the first etching process is a plasma dry etching process, and the bottom of the second groove is made flat by adjusting the frequency and duty cycle of the radio frequency signal in the first etching process. In the embodiment of the present disclosure, the frequency and duty cycle of the radio frequency signal in the first etching process for etching the second groove are adjusted to avoid the occurrence of micro-grooves at the bottom of the second groove, so that the bottom of the second groove is flat, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figures 1A to 1C A cross-sectional view of a semiconductor structure during manufacturing is provided as an example;
[0033] Figure 2 The remaining amount of the first oxide layer provided for an example;
[0034] Figure 3 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;
[0035] FIG. 4A to FIG. 4E A cross-sectional view of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;
[0036] Figure 5 The remaining amount of the first dielectric layer provided in the embodiment of the present disclosure. DETAILED DESCRIPTION
[0037] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0038] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0039] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0040] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.
[0041] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0043] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.
[0044] During the etching process of semiconductor integrated circuits, an oxide layer (Oxide) can be deposited on the substrate, a polysilicon layer (Poly) can be deposited on the oxide layer, and a semiconductor structure can be formed in the polysilicon layer. This semiconductor structure can solve the leakage and latch-up effects of traditional complementary metal oxide semiconductors (CMOS). The top polysilicon layer and the bottom oxide layer are opened in specific areas of this semiconductor structure, and applying voltage to the bottom of the substrate can change the turn-on voltage of the MOS transistor, thereby improving the performance of the chip.
[0045] Before introducing the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure, various directions that may be used in the embodiment of the present disclosure are first defined. The direction perpendicular to the substrate (or the first semiconductor layer) is defined as the Z direction, and the X direction and the Y direction are defined in a plane perpendicular to the Z direction, and the X direction and the Y direction intersect. In some embodiments, the X direction and the Y direction may be perpendicular to each other, so that the X direction, the Y direction, and the Z direction are perpendicular to each other.
[0046] refer to Figures 1A to 1C , Figures 1A to 1C A cross-sectional view of a semiconductor structure during the manufacturing process is provided as an example. Figures 1A to 1C The cross-sectional view of the XZ plane is shown below. Figures 1A to 1C , which describes in detail the manufacturing process of the semiconductor structure.
[0047] like Figure 1A As shown, the stacked structure includes a substrate 101, a first oxide layer 102, a first polysilicon layer 103, a second oxide layer 104, an anti-reflective coating 105 and a photoresist layer 106 which are stacked in sequence; a first groove 107 penetrating the photoresist layer 106, the anti-reflective coating 105 and the second oxide layer 104 and extending into the first polysilicon layer 103 is formed by etching in sequence along the Z direction.
[0048] Figure 1A The two dotted circles in the figure indicate the micro-grooves at the bottom of the first trench 107, that is, the micro-grooves appear at the part of the first trench 107 located in the first polysilicon layer 103. In other words, the bottom of the first trench 107 is uneven, that is, the height of the bottom of the first trench 107 along the Z direction is different.
[0049] like Figure 1B As shown, along the Z direction, a second trench 108 penetrating the first polysilicon layer 103 and extending into the first oxide layer 102 is formed by etching the first trench 107; wherein the first trench 107 (as shown in FIG. Figure 1B The second groove 108 (shown in the dashed box) Figure 1B The etching depth of the first oxide layer 102 is less than the height of the first oxide layer 102 along the Z direction, that is, the first oxide layer 102 is not etched through during the etching process.
[0050] Figure 1B The two dotted circles in the figure indicate the micro grooves at the bottom of the second groove 108, that is, the micro grooves appear at the part of the second groove 108 located in the first oxide layer 102. In other words, the bottom of the second groove 108 is uneven, that is, the height of the bottom of the second groove 108 along the Z direction is different.
[0051] like Figure 1CAs shown, the photoresist layer 106 and the anti-reflective coating layer 105 are removed to expose the surface of the second oxide layer 104 .
[0052] Figure 1C The two dotted circles in the figure indicate the micro grooves appearing at the bottom of the second groove 108 . Figures 1A to 1C During the manufacturing process of the semiconductor structure shown in the diagram, micro-grooves may appear at the bottom of the second trench 108 , thereby affecting the reliability of the semiconductor structure.
[0053] refer to Figure 2 , Figure 2 The remaining amount of the first oxide layer provided as an example. Figure 1C and Figure 2 As shown, the height of the remaining amount of the first oxide layer 102 at the bottom of the second trench 108 formed by etching the stacked structure along the Z direction is a. Figure 2 The diagram shows that the stacked structure is etched using the same etching process, and the residual amounts of the first oxide layer 102 at the bottom of the second trench 108 are different. Numbers 1, 2, and 3 are the stacked structure etched using the same etching process, and the residual amounts of the first oxide layer obtained are respectively and
[0054] That is to say, the process of repeatedly etching the stacked structure causes the remaining amount of the first oxide layer at the bottom of the second trench formed in different batches to fluctuate greatly, which will affect the subsequent ion implantation process (Implant), resulting in unstable energy entry depth, thereby affecting the performance and reliability of the chip.
[0055] In view of this, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
[0056] refer to Figure 3 , Figure 3 Schematic diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Figure 3 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the manufacturing method comprising:
[0057] Step S301: providing a stacking structure; the stacking structure comprises a first semiconductor layer, a first dielectric layer, a second semiconductor layer and a second dielectric layer stacked in sequence; a first groove penetrating the second dielectric layer and the second semiconductor layer and exposing the surface of the first dielectric layer is formed in the stacking structure;
[0058] Step S302: In the first etching process, a portion of the first dielectric layer is etched through the first groove to form a second groove; wherein the height of the second groove along the stacking direction is less than the height of the first dielectric layer along the stacking direction; the first etching process is a plasma dry etching process, and the frequency and duty cycle of the radio frequency signal in the first etching process are adjusted to make the bottom of the second groove flat.
[0059] In the embodiment of the present disclosure, a portion of the first dielectric layer is etched through the first groove to form a second groove; by adjusting the frequency and duty cycle of the radio frequency signal in the first etching process for etching the second groove, the occurrence of micro-grooves at the bottom of the second groove is avoided, so that the bottom of the second groove is flat, thereby improving the reliability of the semiconductor structure.
[0060] refer to FIG. 4A to FIG. 4E , FIG. 4A to FIG. 4E A cross-sectional view of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure. FIG. 4A to FIG. 4E The cross-sectional view of the XZ plane is shown below. FIG. 4A to FIG. 4E , which describes in detail the manufacturing process of the semiconductor structure.
[0061] In the embodiment of the present disclosure, in step S301, a stacking structure is provided; the stacking structure includes a first semiconductor layer 201, a first dielectric layer 202, a second semiconductor layer 203 and a second dielectric layer 204 stacked in sequence; a first groove 210 is formed in the stacking structure, penetrating the second dielectric layer 204 and the second semiconductor layer 203 and exposing the surface of the first dielectric layer 202.
[0062] like Figure 4A As shown, the stacked structure includes a first semiconductor layer 201, a first dielectric layer 202, a second semiconductor layer 203, a second dielectric layer 204, an anti-reflective coating 205 and a photoresist layer which are stacked in sequence.
[0063] Here, the first semiconductor layer 201 can be a substrate, specifically including at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art.
[0064] Here, the materials of the first dielectric layer 202 and the second dielectric layer 204 may include but are not limited to insulating materials, such as silicon oxide.
[0065] Here, the material of the second semiconductor layer 203 may be, for example, polysilicon.
[0066] In a specific embodiment, the materials of the first semiconductor layer 201 and the second semiconductor layer 203 may both be polysilicon, and the materials of the first dielectric layer 202 and the second dielectric layer 204 may both be silicon oxide.
[0067] Here, the anti-reflection coating 205 may be, for example, a bottom anti-reflection coating (BARC), which is located between the second dielectric layer 204 and the photoresist layer. For example, a layer of anti-reflection coating material may be coated on the second dielectric layer 204, and the anti-reflection coating material may be cured by a baking step to form the anti-reflection coating 205.
[0068] Here, the photoresist layer may be formed by spin coating, for example, a photoresist solution may be sprayed, the photoresist solution may be evenly distributed by spinning, and a baking step may be used to volatilize the solvent in the photoresist solution to form the photoresist layer.
[0069] In some embodiments, the process of forming the first dielectric layer 202, the second semiconductor layer 203, and the second dielectric layer 204 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The disclosed embodiment has no special limitation on the process of forming the first dielectric layer 202, the second semiconductor layer 203, and the second dielectric layer 204, and can be flexibly selected according to actual conditions.
[0070] In some embodiments, before step S301, the manufacturing method further includes:
[0071] Performing patterning on the photoresist layer to form a patterned photoresist layer 206;
[0072] In the second etching process, the anti-reflective coating 205 is etched using the patterned photoresist layer 206 as a mask to form an opening 207 .
[0073] like Figure 4A As shown, the photoresist layer may be patterned to form a patterned photoresist layer 206 ; in a second etching process, the patterned photoresist layer 206 is used to etch through the anti-reflective coating layer 205 along the Z direction to form an opening 207 . Figure 4A A patterned photoresist layer 206 and an anti-reflective coating 205 having openings 207 are illustrated.
[0074] Exemplarily, patterning the photoresist layer may include the following steps: the mask and the stack structure may be aligned; after alignment, the mask and the stack structure are exposed to light, thereby transferring the pattern on the mask to the photoresist layer; after exposure, baking is performed to further remove the solvent in the photoresist layer; and a developing solution is used to dissolve the soluble area of the photoresist layer to obtain a patterned photoresist layer, that is, the photoresist layer is patterned so that the photoresist layer has openings.
[0075] Illustratively, the anti-reflective coating is etched using the patterned photoresist layer as a mask to form an opening.
[0076] In some embodiments, the second etching process is a plasma dry etching process.
[0077] In some embodiments, the etching gas used in the second etching process includes carbon oxysulfide (COS), oxygen (Q2) and an inert gas, wherein the ratio between carbon oxysulfide and oxygen ranges from 0.5 to 1.2. Here, the inert gas may include but is not limited to helium.
[0078] In some embodiments, in the second etching process, the RF power ranges from 700W to 1000W, and the bias voltage ranges from 50V to 200V.
[0079] In some embodiments, step S301 includes:
[0080] In the third etching process, the patterned photoresist layer 206 is used as a mask to form a first sub-recess 208 penetrating the second dielectric layer 204 and extending into the second semiconductor layer 203 by etching; wherein, by adjusting the process parameters of the third etching process, the bottom of the first sub-recess 208 is flat;
[0081] In the fourth etching process, the patterned photoresist layer 206 is used as a mask to etch and form a second sub-recess 209 that penetrates the second semiconductor layer 203 and exposes the surface of the first dielectric layer 202; wherein the first sub-recess 208 and the second sub-recess 209 are connected, and the first sub-recess 208 and the second sub-recess 209 together form a first recess 210.
[0082] like Figure 4B As shown, in the third etching process, the patterned photoresist layer 206 is used as a mask to etch along the Z direction to form a first sub-groove 208 (as shown in FIG. 1 ) penetrating the second dielectric layer 204 and extending into the second semiconductor layer 203. Figure 4B wherein, by adjusting the process parameters of the third etching process, the bottom of the first sub-recess 208 is made flat.
[0083] Figure 4BThe bottom of the first sub-recess 208 indicated by the dashed box is flat, that is, the surface of the first sub-recess 208 located in the second semiconductor layer 203 is flat. More specifically, the height of the bottom of the first sub-recess 208 along the Z direction is substantially the same. In other words, there is no micro-groove phenomenon at the bottom of the first sub-recess 208.
[0084] In some embodiments, the third etching process is a plasma dry etching process.
[0085] In some embodiments, the etching gas used in the third etching process includes carbon tetrafluoride (CF4), oxygen and an inert gas, wherein the ratio between carbon tetrafluoride and oxygen is in a range of 4.5 to 5.5. Here, the inert gas may include but is not limited to argon.
[0086] In some embodiments, in the third etching process, the RF power ranges from 300W to 400W, and the bias voltage ranges from 50V to 150V.
[0087] In the embodiment of the present disclosure, the bottom of the first sub-groove can be made flat by adjusting the process parameters of the second etching process, such as the type of etching gas, the ratio range between the etching gases, the RF power range, and the bias voltage range, etc.
[0088] like Figure 4C As shown, in the fourth etching process, the patterned photoresist layer is used as a mask to etch along the Z direction to form a second sub-groove 209 (as shown in FIG. 1 ) penetrating the second semiconductor layer 203 and exposing the surface of the first dielectric layer 202. Figure 4C The first sub-groove 208 and the second sub-groove 209 are connected, and the first sub-groove 208 and the second sub-groove 209 together form a first groove 210.
[0089] Figure 4C The dotted line box indicates that the bottom of the second sub-groove 209 is flat, that is, the bottom of the second sub-groove 209 exposes the surface of the first dielectric layer 202. More specifically, the height of the bottom of the second sub-groove 209 along the Z direction is substantially the same. In other words, there is no micro-groove phenomenon at the bottom of the second sub-groove 209.
[0090] In some embodiments, the fourth etching process is a plasma dry etching process.
[0091] In some embodiments, the etching gas used in the fourth etching process includes hydrogen bromide (HBr), oxygen and an inert gas, wherein the ratio between hydrogen bromide and oxygen is in a range of 30 to 40. Here, the inert gas may include but is not limited to helium.
[0092] In some embodiments, in the fourth etching process, the RF power ranges from 300W to 450W, and the bias voltage ranges from 30V to 100V.
[0093] In the disclosed embodiment, the bottom of the second sub-groove can be made flat by adjusting the process parameters of the third etching process, such as the type of etching gas, the ratio range between the etching gases, the RF power range, the bias voltage range, etc.
[0094] In some embodiments, in the third etching process, the second dielectric layer 204 has a first etching selectivity ratio to the second semiconductor layer 203;
[0095] In the fourth etching process, the second semiconductor layer 203 has a second etching selectivity to the first dielectric layer 202 , wherein the first etching selectivity is smaller than the second etching selectivity.
[0096] Here, the first etching selectivity refers to the ratio between the etching rate of the second dielectric layer 204 and the etching rate of the second semiconductor layer 203 in the same etching process; the second etching selectivity refers to the ratio between the etching rate of the second semiconductor layer 203 and the etching rate of the first dielectric layer 202 in the same etching process. In the third etching process, part of the second semiconductor layer 203 will also be etched during the etching of the second dielectric layer 204; in the fourth etching process, the first dielectric layer 202 will basically not be etched during the etching of the second semiconductor layer 203; therefore, the first etching selectivity is less than the second etching selectivity.
[0097] In some embodiments, the second etch selectivity ratio may be greater than 100.
[0098] In the embodiment of the present disclosure, in step S302, in a first etching process, a portion of the first dielectric layer 202 is etched through the first groove 210 to form a second groove 211; wherein the height of the second groove 211 along the stacking direction is less than the height of the first dielectric layer 202 along the stacking direction; the first etching process is a plasma dry etching process, and the bottom of the second groove 211 is flattened by adjusting the frequency and duty cycle of the radio frequency signal in the first etching process.
[0099] like Figure 4D As shown, in the first etching process, a portion of the first dielectric layer 202 is etched along the Z direction through the first groove 210 to form a second groove 211 (eg, Figure 4D At this time, in the first etching process, the patterned photoresist layer 206 is still used as a mask for etching.
[0100] Figure 4DThe dotted circle in the middle indicates that the bottom of the second groove 211 is flat, that is, the surface of the second groove 211 located in the first dielectric layer 202 is flat. More specifically, the height of the bottom of the second groove 211 along the Z direction is substantially the same. In other words, there is no micro-groove phenomenon at the bottom of the second groove 211.
[0101] In some embodiments, the frequency range of the radio frequency signal in the first etching process is 150 Hz to 500 Hz;
[0102] The duty cycle of the radio frequency signal in the first etching process ranges from 20% to 70%.
[0103] In a specific embodiment, the frequency of the radio frequency signal in the first etching process is 200 Hz, and the duty cycle of the radio frequency signal in the first etching process is 50%.
[0104] In the disclosed embodiment, the bottom of the second groove can be made flat by adjusting the process parameters of the first etching process, for example, the frequency range of the RF signal and the duty cycle range of the RF signal. At this time, the process parameters of the first etching process are set to the pulse mode (Pulsing Mode), more specifically, the frequency range of the RF signal is 150HZ to 500HZ, and the duty cycle range of the RF signal is 20% to 70%. By setting the frequency and duty cycle of the RF signal within the above range, the accumulation of reaction by-products and polymers can be reduced, the distribution of polymers can be improved, and the influence of polymer accumulation on the etching program (Profile) can be reduced. In this way, it is possible to avoid the etching rate being reduced or even the etching being stopped due to the low frequency of the RF signal and the large duty cycle, and it is also possible to avoid the etching rate being low due to the high frequency of the RF signal and the small duty cycle, and the improvement effect is weakened.
[0105] In some embodiments, the etching gas in the first etching process includes carbon tetrafluoride;
[0106] In the first etching process, the RF power ranges from 200W to 700W, and the bias voltage ranges from 120V to 220V.
[0107] In some embodiments, the first etching process, the second etching process, the third etching process, and the fourth etching process may all use transformer coupled plasma (TCP).
[0108] In some embodiments, after step S302, the manufacturing method further includes:
[0109] The patterned photoresist layer 206 and the anti-reflective coating layer 205 having the openings are removed.
[0110] like Figure 4D and Figure 4E As shown, the patterned photoresist layer 206 and the anti-reflection coating 205 with the opening can be removed to expose the surface of the second dielectric layer 204. At this time, the first groove 210 includes a first sub-groove 208 and a second sub-groove 209 connected to each other, and the first groove 210 and the second groove 211 are connected to each other.
[0111] In some embodiments, the patterned photoresist layer 206 can be removed by solvent dissolution or etching. The disclosed embodiment has no particular limitation on the process of removing the patterned photoresist layer 206 and the anti-reflective coating 205 with openings, and can be flexibly selected according to actual conditions.
[0112] It should be noted that, combined with Figure 4A and Figure 4B As shown, during the process of etching to form the first sub-groove 208, a portion of the patterned photoresist layer 206 is also etched away. In other words, Figure 4A The height of the patterned photoresist layer 206 in the Z direction is greater than Figure 4B The height of the patterned photoresist layer 206 along the Z direction is shown. Figure 4B and Figure 4C As shown, during the process of etching to form the second sub-groove 209 , a portion of the patterned photoresist layer 206 is also etched away. Figure 4B The height of the patterned photoresist layer 206 in the Z direction is greater than Figure 4C The height of the patterned photoresist layer 206 along the Z direction is shown. Figure 4C and Figure 4D As shown, during the process of etching to form the second groove 211 , a portion of the patterned photoresist layer 206 is also etched away. Figure 4C The height of the patterned photoresist layer 206 in the Z direction is greater than Figure 4D The height of the patterned photoresist layer 206 along the Z direction is shown. During the process of sequentially performing the third etching process, the fourth etching process and the first etching process, the height of the patterned photoresist layer 206 along the Z direction gradually decreases.
[0113] In some embodiments, a ratio between a height of the second groove 211 along the stacking direction and a height of the first dielectric layer 202 along the stacking direction is greater than a preset value.
[0114] Here, the etching depth of the first dielectric layer 202 is less than the height of the first dielectric layer 202 along the Z direction, that is, the first dielectric layer 202 is not etched through during the etching process.
[0115] In some embodiments, the ratio between the remaining height of the first dielectric layer 202 and the height of the first dielectric layer 202 ranges from 0.1 to 0.8.
[0116] In the embodiment of the present disclosure, by adjusting the etching process steps, for example, performing the second etching process, the third etching process, the fourth etching process and the first etching process in sequence, and adjusting the process parameters of each etching process, the remaining amount of the first dielectric layer at the bottom of the second groove is stabilized, avoiding affecting the subsequent ion implantation process, thereby improving the reliability and stability of the chip.
[0117] refer to Figure 5 , Figure 5 The remaining amount of the first dielectric layer provided in the embodiment of the present disclosure. Figure 4E and Figure 5 As shown, the height of the remaining amount of the first dielectric layer 202 at the bottom of the second groove 211 formed by etching the stacked structure along the Z direction is b. Figure 5 The diagram shows that the stacked structure is etched using the same etching process, and the residual amounts of the first dielectric layer 202 at the bottom of the second groove 211 are different. Numbers 1, 2, and 3 are the stacked structure etched using the same etching process, and the residual amounts of the first oxide layer obtained are respectively and
[0118] That is to say, by repeatedly performing the stacked structure etching process, the remaining amount of the first dielectric layer at the bottom of the second groove formed in different batches is relatively stable, and the energy penetration depth in the subsequent ion implantation process is stable, thereby improving the performance and reliability of the chip.
[0119] In some embodiments, the remaining amount of the first dielectric layer at the bottom of the second groove can be controlled within 6%, that is, the ratio between the difference between the maximum value of the remaining amount of the first dielectric layer and the minimum value of the remaining amount of the first dielectric layer and the average value of the remaining amount of the first dielectric layer is less than 6%. In other words, the remaining amount of the first dielectric layer at the bottom of the second groove is relatively stable, and the etching process for the semiconductor structure is relatively stable.
[0120] It should be noted that, by using the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure, the first etching process is used as the main etching step, so that the remaining amount of the first dielectric layer at the bottom of the second groove can be better controlled, and the bottom of the second groove is flat, and no micro-groove phenomenon occurs at the bottom of the second groove. In this way, the reliability and stability of the semiconductor structure can be improved.
[0121] The embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes: providing a stacking structure; the stacking structure includes a first semiconductor layer, a first dielectric layer, a second semiconductor layer, and a second dielectric layer stacked in sequence; a first groove penetrating the second dielectric layer and the second semiconductor layer and exposing the surface of the first dielectric layer is formed in the stacking structure; in a first etching process, a portion of the first dielectric layer is etched through the first groove to form a second groove; wherein the height of the second groove along the stacking direction is less than the height of the first dielectric layer along the stacking direction; the first etching process is a plasma dry etching process, and the bottom of the second groove is made flat by adjusting the frequency and duty cycle of the radio frequency signal in the first etching process. In the embodiment of the present disclosure, the frequency and duty cycle of the radio frequency signal in the first etching process for etching the second groove are adjusted to avoid the occurrence of micro-grooves at the bottom of the second groove, so that the bottom of the second groove is flat, thereby improving the reliability of the semiconductor structure.
[0122] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.
[0123] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: A stacking structure is provided; the stacking structure comprises a first semiconductor layer, a first dielectric layer, a second semiconductor layer and a second dielectric layer stacked in sequence; a first groove penetrating the second dielectric layer and the second semiconductor layer and exposing a surface of the first dielectric layer is formed in the stacking structure; In the first etching process, a portion of the first dielectric layer is etched through the first groove to form a second groove; wherein the height of the second groove along the stacking direction is less than the height of the first dielectric layer along the stacking direction; the first etching process is a plasma dry etching process, and the bottom of the second groove is flattened by adjusting the frequency and duty cycle of the radio frequency signal in the first etching process.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The frequency range of the radio frequency signal in the first etching process is 150 Hz to 500 Hz; The duty cycle of the radio frequency signal in the first etching process ranges from 20% to 70%.
3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: In the first etching process, the etching gas includes carbon tetrafluoride; In the first etching process, the RF power ranges from 200W to 700W, and the bias voltage ranges from 120V to 220V.
4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: A ratio between a height of the second groove along the stacking direction and a height of the first dielectric layer along the stacking direction is greater than a preset value.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The stacked structure further comprises an anti-reflective coating and a photoresist layer sequentially disposed on the second dielectric layer; Before providing the stacking structure, the manufacturing method further includes: Performing patterning on the photoresist layer to form a patterned photoresist layer; In the second etching process, the anti-reflective coating is etched using the patterned photoresist layer as a mask to form an opening.
6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The stacking structure provided comprises: In a third etching process, the patterned photoresist layer is used as a mask to etch and form a first sub-groove that penetrates the second dielectric layer and extends into the second semiconductor layer; wherein the bottom of the first sub-groove is flattened by adjusting the process parameters of the third etching process; In the fourth etching process, the patterned photoresist layer is used as a mask to etch and form a second sub-groove that penetrates the second semiconductor layer and exposes the surface of the first dielectric layer; wherein the first sub-groove and the second sub-groove are connected, and the first sub-groove and the second sub-groove together form the first groove.
7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: In the third etching process, the second dielectric layer has a first etching selectivity ratio to the second semiconductor layer; In the fourth etching process, the second semiconductor layer has a second etching selectivity ratio to the first dielectric layer; wherein the first etching selectivity ratio is smaller than the second etching selectivity ratio.
8. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The etching gas used in the second etching process includes carbon oxysulfide, oxygen and an inert gas; wherein the ratio between carbon oxysulfide and oxygen is in the range of 0.5 to 1.2; The etching gas used in the third etching process includes carbon tetrafluoride, oxygen and an inert gas; wherein the ratio between carbon tetrafluoride and oxygen is in the range of 4.5 to 5.5; The etching gas used in the fourth etching process includes hydrogen bromide, oxygen and an inert gas; wherein the ratio between hydrogen bromide and oxygen is in the range of 30 to 40.
9. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: In the first etching process, after the first dielectric layer is etched through the first groove to form a second groove, the manufacturing method further includes: The patterned photoresist layer and the anti-reflective coating layer having the opening are removed.
10. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: In the second etching process, the RF power ranges from 700W to 1000W, and the bias voltage ranges from 50V to 200V; In the third etching process, the RF power ranges from 300W to 400W, and the bias voltage ranges from 50V to 150V; In the fourth etching process, the RF power ranges from 300W to 450W, and the bias voltage ranges from 30V to 100V.