Semiconductor structure and forming method thereof

Abstract

The method includes depositing a first metal layer on a package assembly, the package assembly including a first device die; forming a dielectric layer on the package assembly; and plating a metal thermal interface material on the first metal layer. The dielectric layer includes portions on opposite sides of the metal thermal interface material. A heat sink is bonded to the metallic thermal interface material. The heat sink includes a second metal layer physically bonded to the metal thermal interface material. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] With the increasing density and driving current of integrated circuit devices, heat dissipation becomes a more stringent requirement. Conventional solid TIM has relatively low thermal conductivity and may not meet the high heat dissipation requirements. On the other hand, indium TIM has a low melting point, which is also lower than the melting point of solder. This causes the indium TIM to melt again in the subsequent packaging process when the solder melts. The remelting of the indium TIM may cause voids and low coverage. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: depositing a first metal layer on a packaging component, wherein the packaging component includes a first device die; forming a first dielectric layer on the packaging component; forming a metal thermal interface material on the first metal layer, wherein the first dielectric layer includes portions located on opposite sides of the metal thermal interface material; and bonding a heat sink to the metal thermal interface material, wherein the heat sink includes a second metal layer bonded to the metal thermal interface material by direct metal-to-metal bonding.

[0004] Other embodiments of the present application provide a semiconductor structure, comprising: a packaging component including a first device die; a metal layer located above the packaging component and in physical contact with the packaging component; a metal thermal interface material located on the metal layer; and a heat sink bonded to the metal thermal interface material, wherein the heat sink comprises a metal layer physically bonded to the metal thermal interface material.

[0005] Still other embodiments of the present application provide a semiconductor structure, comprising: an interposer including a first edge; a first device die and a second device die located above the interposer and bonded to the interposer; a metal component located above the first device die and the second device die and contacting the first device die and the second device die, wherein the metal component comprises: a lower portion including a second edge vertically aligned with the corresponding first edge; and an upper portion, wherein the upper portion is laterally recessed from the second edge; and a metal cover located above the upper portion and bonded to the upper portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 , Figure 2A , Figure 2B , Figure 3 to Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Figure 7 , Fig. 8A and Figure 8B A diagram illustrating an intermediate stage in the formation of a built-in metal thermal interface material (TIM) package including a TIM built-in package according to some embodiments.

[0008] Fig. 9 A package including a TIM built-in package according to some embodiments is shown.

[0009] Figures 10 to 13 A view showing an intermediate stage in the formation of a package including a TIM built-in package and a skylight metal cover according to some embodiments.

[0010] Figures 14 to 16 A diagram illustrating an intermediate stage in the formation of a package including a TIM built-in package and a metal lid, according to some embodiments.

[0011] Fig.17 A package including a TIM built-in package and a metal lid is shown according to some embodiments.

[0012] Figures 18 to 22 A view showing an intermediate stage in the formation of a TIM embedded package according to an alternative embodiment.

[0013] Fig.23 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] A package including a built-in thermal interface material (TIM) and a method for forming the same are provided. According to some embodiments, a first metal TIM is plated on a package including a device die. The first metal TIM may be plated and may include copper. A dielectric layer (which may be a polymer region) may be formed on opposite sides of the first metal TIM. A metal cover including a second metal TIM may be bonded to the first metal TIM. In the case where the metal TIM is formed of a metal such as copper, better thermal conductivity is achieved. In addition, the metal TIM has a high melting point so that they do not melt in a subsequent reflow process for reflowing the solder region.

[0017] The embodiments discussed herein are intended to provide examples of the subject matter of the disclosed embodiments that can be manufactured or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the contemplation of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0018] Figure 1 , Figure 2A , Figure 2B , Figure 3 to Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Figure 7 , Fig. 8A and Figure 8B 1 shows a view of an intermediate stage in the formation of a TIM built-in package including a built-in metal TIM according to some embodiments. The corresponding process is also schematically reflected in Fig.23 In the process flow shown in .

[0019] refer to Figure 1 , a carrier 10 is provided. According to some embodiments, the carrier 10 is a glass carrier, an organic carrier, etc. A release film 12 is formed on the carrier 10 for attaching the package component to the carrier 10. The release film 12 may be formed of a light-to-heat conversion (LTHC) material that can be decomposed when exposed to a light beam such as a laser beam.

[0020] Further references Figure 1 , forming package assembly 22. According to some embodiments, package assembly 22 may be a reconstituted wafer having a device wafer, and a device die bonded to the device wafer, an interposer, a die stack, a package, etc. According to some embodiments, package assembly 22 includes package assemblies 24, 36A, and 36B.

[0021] According to some embodiments, package assembly 24 is an interposer wafer including an interposer therein, which includes substrate 26 and corresponding dielectric layer 28. Therefore, package assembly 24 may be referred to as interposer wafer 24, while package assembly 24 may also be of other types. The structure of interposer wafer 24 is schematically shown, and details such as multiple dielectric layers on the top and bottom sides of substrate 26, metal lines and vias, metal pads, etc. are not shown.

[0022] Through substrate vias 30 (sometimes referred to as through silicon vias 30 when substrate 26 is a silicon substrate) penetrate substrate 26. Through substrate vias 30 are used to interconnect conductive features on the top side of substrate 26 to conductive features on the bottom side of substrate 26. Electrical connectors 32 (which may include solder areas) may be located below and bonded to the interposer and used to bond interposer wafer 24 to package assembly 22.

[0023] According to some embodiments, package assemblies 36A and 36B are bonded to respective underlying interposer wafers 24 . Figure 1 A cross section is shown in which one package assembly 36A and two package assemblies 36B are visible and bonded to the same interposer wafer 24. Package assemblies 36A and 36B are different types of package assemblies and are collectively referred to as package assemblies 36.

[0024] Each of the package components 36 may be a device die, a package in which a device die is packaged, a system-on-chip (SoC) die including a plurality of integrated circuits (or device dies) integrated as a system, etc. The device die in the package component 36 may be or may include a logic die, a memory die, an input-output die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die in the package component 36 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die in the package component 36 may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. The device die in the package component 36 may include a semiconductor substrate and an interconnect structure.

[0025] In the subsequent discussion according to some exemplary embodiments, package assembly 36A is referred to as a device die, which may be a SoC die according to some embodiments. Package assembly 36B may be a memory stack, such as a high performance memory (HBM) stack. Package assembly 36B may include a memory die forming a die stack and an encapsulant (such as a molding compound) encapsulating the memory die therein. According to some embodiments, package assembly 36A may generate more heat during operation and may therefore be hotter than package assembly 36B.

[0026] Further references Figure 1 , package component 36 may be bonded to underlying interposer wafer 24, for example, via solder regions 40. Underfill 44 is dispensed between package component 36 and underlying interposer wafer 24. According to some embodiments, package component 22 is formed by a chip-on-wafer (CoW) bonding process, wherein package component 36 (which is a discrete chip / package) is bonded to a package component (such as a die) located in an unsawn wafer 24 to form a reconstructed wafer. After dispensing underfill 44, an encapsulant such as molding compound 48 may be applied to seal package component 36.

[0027] Next, refer to Figure 2A , Figure 2A A cross-sectional view is shown, and a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to make the top surface of molding compound 48 flush with the top surface of package assembly 36. Package assembly 22 is thus formed, which is optionally referred to as a reconstituted wafer.

[0028] Figure 2B It shows that Figure 2A 2. An exemplary top view of some of the components shown in FIG. 22 may include one or more device dies 36A and a plurality of memory stacks 36B. Each of the memory stacks 36B may include stacked memory dies and a molding compound that molds (and surrounds) the memory dies. An encapsulant (e.g., molding compound) 48 fills the spaces between adjacent package assemblies 36.

[0029] refer to Figure 3, the metal layer 50 is formed by a deposition process. According to some embodiments, the metal layer 50 may be formed by physical vapor deposition (PVD). The metal layer 50 may include a single metal layer, or may be a composite layer including a plurality of metal layers formed by or containing different metals. Each of the single metal layer or the plurality of metal layers may be formed by a homogeneous metal material, a metal alloy, etc. According to some embodiments, the metal layer in the metal layer 50 may include a titanium layer, a copper layer, an aluminum layer, etc., their alloys, and / or their multilayers. For example, the metal layer 50 may include a metal seed layer, which may include a titanium layer and a copper layer above the titanium layer. Optionally, the metal layer 50 may be a copper layer. According to some embodiments, the thickness T1 of the metal layer 50 may be in a range between about 0.01 μm and about 0.1 μm.

[0030] Metal layer 50 may contact the silicon substrate of the device die in package assemblies 36A and 36B. Because metal layer 50 has a higher thermal conductivity than the silicon substrate of the device die in package assemblies 36A and 36B, forming metal layer 50 to contact the silicon substrate of package assemblies 36 may help dissipate the heat generated by package assemblies 36A and 36B.

[0031] A dielectric layer 52 is formed over the metal layer 50. According to some embodiments, the dielectric layer 52 is a polymer layer, which may also be formed of a photosensitive dielectric material, such as benzocyclobutene (BCB), polyimide, polybenzoxazole (PBO), etc. According to alternative embodiments, the dielectric layer 52 is formed of or includes a non-photosensitive polymer, an inorganic dielectric material (such as silicon oxide), etc.

[0032] refer to Figure 4 , patterning dielectric layer 52 to remove portions of dielectric layer 52 that overlap package component 36A (which can dissipate more heat than package component 36B). According to some embodiments where dielectric layer 52 includes a photosensitive material, patterning includes: placing a photolithography mask (not shown) over dielectric layer 52; performing an exposure process to expose dielectric layer 52; and developing dielectric layer 52. According to alternative embodiments, dielectric layer 52 is patterned by an etching process, during which a patterned photoresist (not shown) is formed over dielectric layer 52 to define portions of dielectric layer 52 to be etched. Reference Figures 18 to 22 Discuss the corresponding process in detail.

[0033] Figure 5A 5 shows the formation of a metal TIM 54, which is a metal plate. According to some embodiments, the metal TIM 54 is formed by a plating process that is performed using the metal layer 50 as a metal seed layer. The metal TIM 54 may include any suitable metal having a high melting point and high thermal conductivity. For example, the melting point of the metal TIM 54 may be higher than that of solder (such as Fig. 9 The melting point of the solder regions 32 and 68 shown in FIG. 5 is preferably greater than about 100 W / m·K (watts per meter Kelvin), greater than about 200 W / m·K, or greater. For example, the metal TIM 54 may be formed of or include copper, which has a thermal conductivity equal to about 401 W / m·K.

[0034] Metal TIM 54 and portions of underlying metal layer 50 together form a metal feature and may or may not have a distinguishable interface therebetween. Metal TIM 54 and metal layer 50 also together form upper and lower portions of the metal feature, respectively.

[0035] According to some embodiments, after plating, a planarization process is performed to make the top surface of TIM 54 flush with the top surface of dielectric layer 52. In the resulting structure, the thickness T2 of metal TIM 54 may be in a range between about 20 μm and about 50 μm.

[0036] Figure 5B It shows that Figure 5A In accordance with some embodiments, metal TIM 54 covers package component 36A, and dielectric layer 52 covers package component 36B and portions of metal layer 50 thereover.

[0037] Fig. 6A The patterning of dielectric layer 52 according to some embodiments is shown. According to some embodiments, dielectric layer 52 is patterned by an etching process, during which a patterned photoresist is formed over dielectric layer 52 to define the portion of dielectric layer 52 to be etched. After the etching process, the remaining portion of dielectric layer 52 has its edge in contact with the edge of metal TIM 54, while some portions of dielectric layer 52 located over package component 36B are removed. As a result, portions of the underlying metal layer 50 are exposed.

[0038] According to alternative embodiments, instead of patterning dielectric layer 52, where some portions of dielectric layer 52 remain, dielectric layer 52 may be completely removed. Thus, dielectric layer 52 defines where metal TIM 54 is formed. According to still other alternative embodiments, dielectric layer 52 is not patterned and remains as a blanket layer over package component 22. Therefore, a dashed box is shown to indicate portions of dielectric layer 52 that may remain or may be removed.

[0039] Figure 6B It shows that Fig. 6A According to some embodiments, metal TIM 54 covers package component 36A, and the remaining portion of dielectric layer 52 includes portions located on opposite sides of metal TIM 54. The remaining portion of dielectric layer 52 may also form a ring surrounding metal TIM 54.

[0040] Next, refer to Figure 7 , package component 22 (which includes metal TIM 54) is peeled off from carrier 10. According to some embodiments, a light beam such as a laser beam is projected onto release film 12, and release film 12 is decomposed under the heat of the light beam. As a result, package component 22 and the structure thereon are released from carrier 10.

[0041] In subsequent processes, such as Fig. 8A As shown in , the package assembly 22 is placed on a dicing tape 58, which is fixed on a frame 60. A singulation process may be implemented to saw the package assembly 22 so that the package assembly 22 (which may be a reconstructed wafer) is separated into discrete and identical packages 22' (also referred to as package assembly 22'). The die 24' in the wafer 24 is also separated and may be an interposer. The package 22' is optionally referred to as a TIM built-in package hereinafter, and the metal TIM 54 is referred to as a built-in metal TIM 54. The sawing process may be implemented using, for example, a blade 62.

[0042] Figure 8B The resulting TIM built-in package 22' is also shown in FIG. The TIM built-in package 22' includes a metal layer 50. Due to the separation process of sawing the metal layer 50, the edge of the metal layer 50 is vertically aligned with the corresponding edge of the underlying molding compound 48 and is vertically aligned with the edge of the interposer 24'. According to some embodiments in which the dielectric layer 52 is not patterned, as shown by the dashed box, the edge of the metal layer 50 is vertically aligned with the corresponding edge of the dielectric layer 52.

[0043] Fig. 9 , Fig.13 , Fig.16 and Fig.17 According to various embodiments, Figure 8B Some packages 64 are formed by TIM built-in packages 22' shown in FIG. Fig. 9 , the TIM built-in package 22' is bonded to the package component 66. The bottom filler 74 is also dispensed into the gap between the package component 66 and the TIM built-in package 22'. According to some embodiments, the TIM built-in package 22' is bonded to the package component 66 through the electrical connector 32 (optionally referred to as the solder area 32 when it is a solder area) that can be reflowed. The metal TIM 54 has a high melting point, and when the metal TIM 54 is formed of copper, the melting point may be about 1084°C. On the other hand, the solder area 32 has a low melting point, and the melting point may be around 200°C and about 220°C. The reflow may be performed at a temperature ranging between about 230°C and about 250°C. Therefore, the metal TIM 54 does not melt.

[0044] Package assembly 66 may also include electrical connector 68, which may be a solder area. Electrical connector 68 is electrically connected to electrical connector 32 via a conductive path (not shown) inside package assembly 66. Support ring 72 (fastening ring) may be attached to package assembly 66 via adhesive 70 so that support ring 72 may provide mechanical support for package assembly 66 and reduce warpage. According to some embodiments, in package 64, metal TIM 54 may be used as a heat sink. Optionally, another metal cap (which acts as a heat sink) may be attached to metal TIM 54. The resulting structure is similar to Fig.16 The structure shown in Fig. 9 The support ring 72 in the Fig.16 The skirt portion 80S of the metal cover 80 in FIG.

[0045] Figures 10 to 13 The formation of a package 64 including a built-in metal TIM 54 is shown in accordance with some embodiments. Fig.10 , the skylight metal cover 80 is attached to the package assembly 66 by the adhesive 70. According to some embodiments, the skylight metal cover 80 includes a skirt portion 80S and a top portion 80T combined with the skirt portion 80S. When viewed from the top of the structure, the skirt portion 80S can form a complete ring. The top portion 80T can also form a complete ring surrounding the opening 82, which is directly above the metal TIM 54. According to some embodiments, the dielectric layer 52 can also be directly below the opening 82. Optionally, the dielectric layer 52 can overlap the top portion 80T.

[0046] According to some embodiments, the buffer material 84 is dispensed between the top portion 80T and the metal layer 50. Optionally, when the dielectric layer 52 is not patterned and extends to the edge of the sealant 48, the buffer material 84 can be dispensed on the dielectric layer 52. According to some embodiments, the buffer material 84 can be formed by an adhesive. Optionally, the buffer material 84 can be formed by or include a solid TIM, a flowable TIM (including a polymer and thermally conductive particles), etc. The flowable TIM has a thermal conductivity value higher than 1w / m·K, 4w / m·K, 10w / m·K or higher. The buffer material 84 is dispensed and cured (when it is a flowable TIM).

[0047] refer to Fig.11, a metal cap 86 is placed over the metal TIM 54. According to some embodiments, the metal cap 86 includes a metal body 88, which may be formed of or include copper, aluminum, etc. The metal cap 86 also includes a metal layer 50', a dielectric layer 52', and a metal TIM 54' formed on the metal body 88. According to some embodiments, the materials, structures, and formation methods of the metal layer 50', the dielectric layer 52', and the metal TIM 54' may be substantially the same as the materials, structures, and formation methods of the metal layer 50, the dielectric layer 52, and the metal TIM 54, respectively, as described in reference to Figures 2A to 4 , Figure 5A and Fig. 6A For example, the formation process may include: depositing a metal layer 50' on the metal body 88; forming and patterning a dielectric layer 52'; plating a metal TIM 54'; planarizing the dielectric layer 52' ​​and the metal TIM 54'; and patterning the dielectric layer 52'. The remaining details may be referred to Figures 2A to 4 , Figure 5A and Fig. 6A The discussion can be found in , and will not be repeated here.

[0048] According to some embodiments, metal TIM 54' is vertically aligned with and in physical contact with metal TIM 54. Dielectric layer 52' ​​is vertically aligned with and in physical contact with dielectric layer 52. A thermal compression process 92 is then performed, for example, using a compression head 90 to push metal cap 86 against metal TIM 54 and dielectric layer 52. Compression head 90 is heated. Thus, during thermal compression process 92, metal cap 54, dielectric layer 52, metal cap 54', and dielectric layer 52' ​​are heated, for example, to a temperature in a range between about 250° C. and about 350° C. After thermal compression process 92, an annealing process 94 is performed, for example, Fig.12 as shown in .

[0049] Due to the thermal compression process 92 and the annealing process 94, the metals in the metal TIM 54 and the metal TIM 54' are bonded by metal-to-metal direct bonding due to the mutual diffusion of the metals. The dielectric layer 52 and the dielectric layer 52' ​​may also be bonded to each other. For example, when the dielectric layer 52 and the dielectric layer 52' ​​are inorganic dielectric materials, the bonding may be performed by melt bonding. When the dielectric layer 52 and the dielectric layer 52' ​​are polymers, the polymer chains in the dielectric layer 52 may be combined with the chains in the dielectric layer 52' ​​to form longer chains extending into the dielectric layer 52 and the dielectric layer 52'. Alternatively, the dielectric layer 52 is in contact with the dielectric layer 52', but is not bonded to the dielectric layer 52'. Therefore, the dielectric layers 52 and 52' are separable at the location where they are in contact.

[0050] The interface between TIM 54 and metal TIM 54' may or may not be distinguishable. TIM 54 and metal TIM 54' may be slightly offset relative to each other so that their bonding positions may be determined. For example, TIM 54 may be slightly offset to the left so that TIM 54 extends laterally beyond the left edge of TIM 54' and TIM 54' extends laterally beyond the right edge of TIM 54. Dielectric layer 52 may also be slightly offset to the left relative to dielectric layer 52'.

[0051] refer to Fig.13 , electrical connectors 68 are formed on package component 66 to complete the formation of package 64. According to some embodiments, the formation of electrical connectors 68 includes: placing solder balls on package component 66; and reflowing the solder balls to form solder areas.

[0052] According to some embodiments, the thermally conductive material 96 may be dispensed into the gap between the skylight metal cover 80 and the metal cover 86. The thermally conductive material 96 may also be dispensed into the remaining gap below the skylight metal cover 80 and the metal cover 86. The thermally conductive material 96 solidifies into a solid after being dispensed. The thermal conductivity of the thermally conductive material 96 may be higher than 1 w / m·K, 4 w / m·K, 10 w / m·K or higher. The thermally conductive material 96 may be thermal grease, thermal gel, phase change material, thermally conductive adhesive, metal with a low melting point (such as In, Sn, Ga, etc.), a material including a graphite film and an adhesive therein, etc.

[0053] When using a material with a low melting point, thermally conductive material 96 may be dispensed after forming electrical connector 68 to avoid remelting during reflow of electrical connector 68. Otherwise, thermally conductive material 96 may be dispensed before or after forming electrical connector 68.

[0054] Figures 14 to 16 The formation of a package 64 including a metal lid with a blanket-type top portion according to some embodiments is shown. Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments are substantially the same as the same components represented by the same reference numerals in the previous embodiments. The details on materials, structures, and formation processes provided in each of the embodiments throughout the specification can be applied to any other embodiment whenever applicable.

[0055] refer to Fig.14, the package 22' is bonded to the package component 66. The bottom filler 74 is distributed between the package 22' and the package component 66. The metal cover 80 is attached to the package component 66 by the adhesive 70, wherein the buffer material 84 is distributed between the top portion 80T and the metal layer 50. The buffer material 84 can also be formed of an adhesive, a TIM, etc. The buffer material 84 can also be formed of thermal grease, thermal gel, phase change material, thermal conductive adhesive, metal with a low melting point (such as In, Sn, Ga, etc.), a material including a graphite film and an adhesive therein, etc.

[0056] The metal cap 80 may include a skirt portion 80S and a top portion 80T bonded to the skirt portion 80S. The top portion 80T may include a metal body 88, a metal layer 50', a dielectric layer 52', and a metal TIM 54'. The formation of the top portion 80T may be similar to the following. Fig.11 The formation of the metal cap 86 shown in is substantially the same. For example, the formation process of the top portion 80T may include: depositing the metal layer 50' on the metal body 88; forming and patterning the dielectric layer 52'; plating the metal TIM 54'; planarizing the dielectric layer 52' ​​and the metal-plated TIM 54'; and patterning the dielectric layer 52'. The top portion 80T may be formed at a wafer level, where the metal body 88 is part of a metal wafer.

[0057] After forming the dielectric layer 52' ​​and the metal TIM 54', the metal layer 50' may be patterned to remove unwanted portions. Alternatively, the metal layer 50' may be left without patterning. The wafer level top portion 80T may then be sawn to form a plurality of portions, each comprising Fig.14 The part shown in .

[0058] Then, skirt portion 80S may be joined to top portion 80T to form metal cap 80. According to an embodiment, where metal layer 50' is left without patterning, metal layer 50' will overlap and bond with skirt portion 80S to form a horizontal interface.

[0059] Further references Fig.14 , a thermal compression process 92 is performed, for example, using a compression head 90 to push the metal cap 80 against the metal TIM 54 and the dielectric layer 52. The compression head 90 is heated. Therefore, during the thermal compression process 92, the metal cap 54, the dielectric layer 52, the metal cap 54' and the dielectric layer 52' ​​are also heated. The temperature and duration of the thermal compression process 92 can be substantially the same as discussed with reference to the previous embodiments.

[0060] After the thermal compression process 92, an annealing process 94 is performed. Fig.15. The temperature and duration of the annealing process 94 may be substantially the same as discussed with reference to the previous embodiment. Due to the thermal compression process 92 and the annealing process 94, the metals in the metal TIM 54 and the metal TIM 54' are bonded by metal-to-metal direct bonding due to the interdiffusion of the metals. The dielectric layer 52 and the dielectric layer 52' ​​may also be bonded to each other, or may be in contact with each other but not bonded to each other.

[0061] refer to Fig.16 , electrical connectors 68 are formed on package component 66 to complete the formation of package 64. According to some embodiments, the formation of electrical connectors 68 includes: placing solder balls on package component 66; and reflowing the solder balls to form solder areas. Thus, package 64 is formed.

[0062] Fig.17 A package 64 is shown formed in accordance with alternative embodiments. Fig.16 The package 64 in FIG. 1 is substantially the same except that the dielectric layer 52 is not patterned. In other words, in FIG. Figure 5A After the process shown in Fig. 6A The process shown in . Dielectric layer 52 ′ may also be unpatterned. The lateral dimensions of dielectric layer 52 ′ may also match the dimensions of dielectric layer 52 . Dielectric layers 52 and 52 ′ may extend to a position aligned with the edge of encapsulant 48 .

[0063] Figures 18 to 22 The formation of the package 22' according to alternative embodiments is shown. These embodiments are similar to Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B The embodiment shown in , differs in that, instead of using the same dielectric layer 52 as both the plating mask and the dielectric layer in the final structure, a photoresist is formed as the plating mask and then removed, followed by the formation of the dielectric layer 52 .

[0064] refer to Fig.18 , a package component 22 is formed on the carrier 10. Details of the package component 22 and reference Figure 1 and Figure 2A The discussion is basically the same. Next, Fig.18 As shown in , metal layer 50 is deposited as the top portion of package component 22. A plating mask 51 is then formed and then patterned over metal layer 50. The openings in plating mask 51 may overlap package component 36A, which generates more heat than package component 36B during its operation. According to some embodiments, plating mask 51 may be formed of photoresist.

[0065] Next, if Fig.19As shown in , an electroplating process is performed to form a metal TIM 54. During plating, the metal layer 50 can be used as a metal seed layer. The metal TIM 54 is plated to a thickness greater than the thickness in the final package. Then, the plating mask 51 is removed, for example, in an ashing process, an etching process, etc.

[0066] refer to Fig. 20 , forming the dielectric layer 52. The formation process may include spin coating, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc., depending on the material of the dielectric layer 52. For example, when the dielectric layer 52 includes polyimide, BCB, PBO, etc., the formation process may include spin coating and curing. When the dielectric layer 52 includes an inorganic dielectric material such as silicon oxide, the formation process may include ALD, CVD, etc.

[0067] Fig.21 A planarization process is shown to planarize the top surfaces of metal TIM 54 and dielectric layer 52. The planarization process may be performed by a CMP process or a mechanical grinding process. Fig. 22 A patterning process is shown for patterning dielectric layer 52 according to some embodiments. According to an alternative embodiment, dielectric layer 52 is not patterned. Therefore, a dashed box is shown to indicate portions of dielectric layer 52 that may remain or may be removed.

[0068] In the above embodiments, some processes and components are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be implemented on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of a known good die to increase yield and reduce costs.

[0069] Embodiments of the present disclosure have some advantageous features. By using a metal with a high melting point (such as copper) to form a metal TIM, the metal TIM will not be reflowed in a subsequent reflow process, and voids will not be generated in the metal TIM to reduce its thermal conductivity. The metal TIM also has a higher thermal conductivity than a conventional TIM including a polymer / epoxy resin / resin and thermally conductive particles. Forming a dielectric layer on the metal TIM also improves the bonding of the corresponding structure to the metal cover, and can also be used to define the position and size of the metal TIM.

[0070] According to some embodiments of the present disclosure, a method includes: depositing a first metal layer on a package assembly, wherein the package assembly includes a first device die; forming a first dielectric layer on the package assembly; plating a metal thermal interface material on the first metal layer, wherein the first dielectric layer includes portions located on opposite sides of the metal thermal interface material; and bonding a heat sink to the metal thermal interface material, wherein the heat sink includes a second metal layer physically bonded to the metal thermal interface material.

[0071] In an embodiment, the heat sink further comprises a second dielectric layer on an opposite side of the second metal layer, and wherein the second dielectric layer further contacts the first dielectric layer. In an embodiment, the method further comprises: after plating the metal thermal interface material, patterning the first dielectric layer to expose a portion of the first metal layer. In an embodiment, the package assembly further comprises a second device die, wherein the first device die is configured to generate more heat than the second device die, and wherein the metal thermal interface material overlaps the first device die, and the portion of the first dielectric layer overlapping the second device die is removed by patterning the first dielectric layer.

[0072] In an embodiment, the method further comprises: performing a planarization process to level the top surfaces of the first dielectric layer and the metal thermal interface material. In an embodiment, forming the first dielectric layer comprises dispensing a polymer. In an embodiment, dispensing the polymer comprises dispensing BCB. In an embodiment, the heat sink comprises a top metal cover, and the method further comprises attaching a skylight metal cover by an adhesive, wherein the adhesive comprises a bottom surface contacting the first metal layer and a top surface contacting an additional bottom surface of the skylight metal cover.

[0073] In an embodiment, the method further comprises: forming a patterned plating mask over the first metal layer, wherein the metal thermal interface material is plated using the patterned plating mask to define a pattern; removing the patterned plating mask; forming a blanket dielectric layer to cover the metal thermal interface material and the first metal layer; and performing a planarization process on the blanket dielectric layer to expose the metal thermal interface material, wherein the remaining portion of the blanket dielectric layer comprises the first dielectric layer. In an embodiment, bonding the heat sink to the metal thermal interface material comprises: a compression bonding process; and an annealing process, performed after the compression bonding process. In an embodiment, the metal thermal interface material comprises copper.

[0074] According to some embodiments of the present disclosure, a structure includes: a package assembly including a first device die; a metal layer located above the package assembly and in physical contact with the package assembly; a metal thermal interface material located on the metal layer; and a heat sink bonded to the metal thermal interface material, wherein the heat sink includes a metal layer physically bonded to the metal thermal interface material. In an embodiment, the metal layer extends laterally beyond an edge of the metal thermal interface material.

[0075] In an embodiment, the structure further comprises a first dielectric layer located above and contacting the metal layer, wherein a first sidewall of the first dielectric layer contacts a second sidewall of the metal thermal interface material to form an interface. In an embodiment, the metal layer further extends laterally beyond an additional edge of the first dielectric layer. In an embodiment, the first dielectric layer comprises a polymer. In an embodiment, the heat sink further comprises a second dielectric layer bonded to the first dielectric layer.

[0076] According to some embodiments of the present disclosure, a structure includes: an interposer including a first edge; a first device die and a second device die located above the interposer and bonded to the interposer; a metal component located above and contacting the first device die and the second device die, wherein the metal component includes: a lower portion including a second edge vertically aligned with the corresponding first edge; and an upper portion, wherein the upper portion is laterally recessed from the second edge; and a metal cap located above and bonded to the upper portion. In an embodiment, the upper portion includes copper, and the upper portion is physically bonded to an additional copper component in the metal cap.

[0077] In an embodiment, the structure further includes: a first dielectric layer located above and contacting the lower portion, wherein the first dielectric layer and the upper portion form a first vertical interface therebetween; and a second dielectric layer located above and bonded to the first dielectric layer, wherein the second dielectric layer and an additional portion of the metal cap form a second vertical interface therebetween.

[0078] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: depositing a first metal layer on a packaging component, wherein the packaging component includes a first device die; forming a first dielectric layer on the packaging component; forming a metal thermal interface material on the first metal layer, wherein the first dielectric layer includes portions located on opposite sides of the metal thermal interface material; and bonding a heat sink to the metal thermal interface material, wherein the heat sink includes a second metal layer bonded to the metal thermal interface material by direct metal-to-metal bonding.

[0079] In some embodiments, the heat sink further comprises a second dielectric layer on an opposite side of the second metal layer, and wherein the second dielectric layer further contacts the first dielectric layer. In some embodiments, the method further comprises: after plating the metal thermal interface material, patterning the first dielectric layer to expose a portion of the first metal layer. In some embodiments, the package assembly further comprises a second device die, wherein the first device die is configured to generate more heat than the second device die, and wherein the metal thermal interface material overlaps the first device die, and the portion of the first dielectric layer overlapping the second device die is removed by patterning the first dielectric layer. In some embodiments, the method further comprises: performing a planarization process to make the first dielectric layer and the top surface of the metal thermal interface material flush. In some embodiments, forming the first dielectric layer comprises dispensing a polymer. In some embodiments, dispensing the polymer comprises dispensing benzocyclobutene (BCB). In some embodiments, the heat sink comprises a top metal cover, and the method further comprises attaching a skylight metal cover by an adhesive, wherein the adhesive comprises a bottom surface contacting the first metal layer and a top surface contacting an additional bottom surface of the skylight metal cover. In some embodiments, the method further comprises: forming a patterned plating mask over the first metal layer, wherein the metal thermal interface material is plated using the patterned plating mask to define a pattern; removing the patterned plating mask; forming a blanket dielectric layer to cover the metal thermal interface material and the first metal layer; and performing a planarization process on the blanket dielectric layer to expose the metal thermal interface material, wherein the remaining portion of the blanket dielectric layer includes the first dielectric layer. In some embodiments, bonding the heat sink to the metal thermal interface material comprises: a compression bonding process; and an annealing process, performed after the compression bonding process. In some embodiments, the metal thermal interface material comprises copper.

[0080] Other embodiments of the present application provide a semiconductor structure, comprising: a packaging component including a first device die; a metal layer located above the packaging component and in physical contact with the packaging component; a metal thermal interface material located on the metal layer; and a heat sink bonded to the metal thermal interface material, wherein the heat sink comprises a metal layer physically bonded to the metal thermal interface material.

[0081] In some embodiments, the metal layer extends laterally beyond an edge of the metal thermal interface material. In some embodiments, the semiconductor structure further comprises a first dielectric layer located above and contacting the metal layer, wherein a first sidewall of the first dielectric layer contacts a second sidewall of the metal thermal interface material to form an interface.

[0082] In some embodiments, the metal layer further extends laterally beyond an additional edge of the first dielectric layer. In some embodiments, the first dielectric layer comprises a polymer. In some embodiments, the heat sink further comprises a second dielectric layer bonded to the first dielectric layer.

[0083] Still other embodiments of the present application provide a semiconductor structure, comprising: an interposer including a first edge; a first device die and a second device die located above the interposer and bonded to the interposer; a metal component located above the first device die and the second device die and contacting the first device die and the second device die, wherein the metal component comprises: a lower portion including a second edge vertically aligned with the corresponding first edge; and an upper portion, wherein the upper portion is laterally recessed from the second edge; and a metal cover located above the upper portion and bonded to the upper portion.

[0084] In some embodiments, the upper portion includes copper, and the upper portion is physically bonded to an additional copper feature in the metal cap. In some embodiments, the semiconductor structure further includes: a first dielectric layer located above and contacting the lower portion, wherein the first dielectric layer and the upper portion form a first vertical interface therebetween; and a second dielectric layer located above and bonded to the first dielectric layer, wherein the second dielectric layer and the additional portion of the metal cap form a second vertical interface therebetween.

[0085] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Depositing a first metal layer on a package assembly, wherein the package assembly includes a first device die; forming a first dielectric layer on the package assembly; forming a metal thermal interface material on the first metal layer, wherein the first dielectric layer includes portions on opposite sides of the metal thermal interface material; and A heat sink is bonded to the metal thermal interface material, wherein the heat sink includes a second metal layer bonded to the metal thermal interface material by direct metal-to-metal bonding.

2. The method according to claim 1, wherein: The heat sink further includes a second dielectric layer on an opposite side of the second metal layer, and wherein the second dielectric layer further contacts the first dielectric layer.

3. The method according to claim 1, further comprising: After the metal thermal interface material is plated, the first dielectric layer is patterned to expose a portion of the first metal layer.

4. The method according to claim 3, wherein: The package assembly also includes a second device die, wherein the first device die is configured to generate more heat than the second device die, and wherein the metal thermal interface material overlaps the first device die, and wherein the portion of the first dielectric layer overlapping the second device die is removed by patterning the first dielectric layer.

5. The method according to claim 1, further comprising: A planarization process is performed to make the top surfaces of the first dielectric layer and the metal thermal interface material flush.

6. The method according to claim 1, wherein: Forming the first dielectric layer includes dispensing a polymer.

7. The method according to claim 6, wherein: Dispensing the polymer includes dispensing benzocyclobutene (BCB).

8. The method according to claim 1, wherein: The heat sink includes a top metal cover, and the method further includes attaching a sunroof metal cover via an adhesive, wherein the adhesive includes a bottom surface contacting the first metal layer and a top surface contacting an additional bottom surface of the sunroof metal cover.

9. A semiconductor structure comprising: A package assembly including a first device die; a metal layer located above the package component and in physical contact with the package component; A metal thermal interface material is located on the metal layer; as well as A heat sink is coupled to the metal thermal interface material, wherein the heat sink includes a metal layer physically bonded to the metal thermal interface material.

10. A semiconductor structure comprising: an interposer layer including a first edge; a first device die and a second device die located above and bonded to the interposer; A metal component is located above the first device die and the second device die and contacts the first device die and the second device die, wherein the metal component comprises: a lower portion comprising a second edge vertically aligned with a corresponding first edge; and an upper portion, wherein the upper portion is laterally recessed from the second edge; and A metal cover is located over the upper portion and is joined to the upper portion.

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