Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a substrate and an active device formed on the substrate, and the active device comprises an interconnection region; a first dielectric layer and a first mask layer located on the first dielectric layer are formed on the active device, the first mask layer is provided with a first opening, and the projection of the first opening on the substrate is at least partially overlapped with the interconnection area of the active device; a second dielectric layer is formed on the first mask layer, and the second dielectric layer is connected with the first dielectric layer through the first opening; removing the second dielectric layer in a partial region and the first dielectric layer connected with the second dielectric layer to form an interconnection groove exposing an interconnection region of the active device; and forming a metal interconnection structure in the interconnection groove. According to the scheme, the forming process of the metal interconnection structure can be simplified, and the process cost of forming the metal interconnection structure is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] As semiconductor manufacturing technology becomes more sophisticated, integrated circuits are also undergoing major changes. The number of components integrated on the same chip has increased from dozens or hundreds to millions today. In order to meet the requirements of complexity and circuit density, the manufacturing process of semiconductor integrated circuit chips uses batch processing technology to form various types of complex devices on the substrate and connect them to each other to have complete electronic functions.

[0003] However, as the size of semiconductor devices continues to shrink, the process flow of semiconductor devices formed by the prior art is too complicated. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor structure and a method for forming the same, so as to simplify the formation process of a metal interconnection structure and reduce the process cost of forming the metal interconnection structure.

[0005] To solve the above problems, an embodiment of the present application provides a method for forming a semiconductor structure, comprising:

[0006] Providing a substrate, the substrate comprising a substrate, an active device formed on the substrate, wherein the active device comprises an interconnection region;

[0007] Forming a first dielectric layer and a first mask layer located on the first dielectric layer on the active device, wherein the first mask layer has a first opening, and a projection of the first opening on the substrate at least partially overlaps with an interconnection region of the active device;

[0008] forming a second dielectric layer on the first mask layer, wherein the second dielectric layer is connected to the first dielectric layer through the first opening;

[0009] Removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnection trench exposing the interconnection region of the active device;

[0010] A metal interconnect structure is formed in the interconnect trench.

[0011] Optionally, the removing of a portion of the second dielectric layer and the first dielectric layer in contact with the second dielectric layer to form an interconnection trench exposing the interconnection region of the active device comprises:

[0012] forming a second mask layer on the second dielectric layer, wherein the second mask layer has a second opening exposing a partial area of ​​the second dielectric layer, and a projection of the second opening on the substrate at least covers a projection of the first opening on the substrate;

[0013] Using the second mask layer as a mask, the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer are etched to form interconnection grooves exposing the interconnection region of the active device.

[0014] Optionally, the etching of the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer comprises etching the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer by pulse plasma etching.

[0015] Optionally, the substrate further comprises a dielectric barrier layer covering the active device;

[0016] The forming of the first dielectric layer on the active device is specifically, forming the first dielectric layer on the dielectric barrier layer;

[0017] The step of removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnection trench exposing the interconnection region of the active device further includes removing the dielectric barrier layer exposed by the first dielectric layer.

[0018] Optionally, forming a first dielectric layer on the active device and a first mask layer on the first dielectric layer includes:

[0019] forming a first dielectric layer on the active device;

[0020] forming a first mask material layer on the first dielectric layer;

[0021] The first mask material layer is patterned to remove the first mask material layer in a preset area to form the first opening, and the remaining first mask material layer is used as the first mask layer.

[0022] Optionally, forming a metal interconnect structure in the interconnect trench includes:

[0023] forming a metal interconnect material layer in the interconnect trench, wherein the metal interconnect material layer completely covers the interconnect trench;

[0024] The metal interconnect material layer on the top of the second dielectric layer is removed, and the metal interconnect material layer in the interconnect trench is retained as a metal interconnect structure.

[0025] Optionally, the interconnection region of the active device is an interconnection metal layer of the active device.

[0026] Optionally, the second dielectric layer and the first dielectric layer are made of the same material.

[0027] Optionally, in the etching process, the etching gas used is a combination of one or more of C4F6, C4F8, SF6, NF3, O2, CH2F2, CH3F, CHF3, CH4, Ar, Kr, and N2; the flow rate of the etching gas is 10 sccm to 250 sccm, the etching source power is 50 W to 6000 W, the bias power is 100 W to 1600 W, the pressure of the etching chamber is 0 mtorr to 50 mtorr, the etching frequency is 100 Hz to 8000 Hz, and the duty cycle is 10% to 80%.

[0028] An embodiment of the present invention further provides a semiconductor structure, which is formed by the above-mentioned method for forming a semiconductor structure.

[0029] Compared with the prior art, the technical solution of the embodiment of the present application has the following advantages:

[0030] An embodiment of the present invention provides a semiconductor structure and a method for forming the same. The method comprises: providing a substrate, wherein the substrate comprises a substrate and an active device formed on the substrate, wherein the active device comprises an interconnection region; forming a first dielectric layer and a first mask layer located on the first dielectric layer on the active device, wherein the first mask layer has a first opening, and a projection of the first opening on the substrate at least partially overlaps with the interconnection region of the active device; forming a second dielectric layer on the first mask layer, wherein the second dielectric layer is connected to the first dielectric layer through the first opening; removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnection groove exposing the interconnection region of the active device; wherein the interconnection groove exposes the interconnection region of the active device based on the first opening; and forming a metal interconnection structure in the interconnection groove.

[0031] It can be seen that the formation method provided by the embodiment of the present invention forms a first mask layer located on the first dielectric layer, and makes the second dielectric layer connected to the first dielectric layer through the first opening of the first mask layer, so that the second dielectric layer in a partial area and the first dielectric layer connected to the second dielectric layer can be removed at the same time, thereby forming an interconnection groove exposing the interconnection area of ​​the active device, and further forming an interconnection structure for electrical connection with the active device through a one-time interconnection structure formation process. Compared with forming corresponding sub-interconnection structures in the first dielectric layer and the second dielectric layer respectively, the embodiment of the present invention greatly simplifies the formation process of the metal interconnection structure, thereby reducing the process cost of forming the metal interconnection structure.

[0032] In addition, it can be understood that when multiple sub-interconnect structures are connected, contact resistance will be generated, and using multiple sub-interconnect structures as the interconnect structure of the device will form a larger interconnect resistance. In comparison, the embodiment of the present invention forms a metal interconnect structure at one time, which can greatly reduce the interconnect resistance of the interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0034] Figures 1 to 7 is a schematic structural diagram of a semiconductor structure;

[0035] Figures 8 to 16 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] As described in the background art, the process flow of semiconductor devices formed by the prior art is too complicated.

[0037] Next, the cause of this problem is analyzed in conjunction with an existing method for forming a semiconductor structure.

[0038] refer to Figures 1 to 7 , Figures 1 to 7 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0039] refer to Figure 1 , providing a substrate, the substrate comprising a substrate 1 and an active device (not shown in the figure) formed on the substrate 1, wherein the active device comprises an interconnection region 2.

[0040] refer to Figure 2 , forming a first dielectric layer 3 on the active device;

[0041] refer to Figure 3 , patterning the first dielectric layer to form a first interconnection trench 4, wherein the first interconnection trench 4 exposes the interconnection region 2 of the active device;

[0042] refer to Figure 4 , forming a first sub-interconnect structure 5 in the first interconnect trench;

[0043] refer to Figure 5, forming an isolation layer 6 and a second dielectric layer 7 covering the first sub-interconnect structure; wherein the isolation layer 6 is used to protect the first sub-interconnect structure 5 from being damaged by the etching process when the second dielectric layer 7 is subsequently patterned.

[0044] refer to Figure 6 , patterning the second dielectric layer 7 and the isolation layer 6 to form a second interconnection trench 8, wherein the second interconnection trench 8 exposes the first sub-interconnection structure 5;

[0045] refer to Figure 7 A second sub-interconnect structure 9 connected to the first sub-interconnect structure 5 is formed in the second interconnect trench.

[0046] It can be understood that the first sub-interconnection structure 5 and the second sub-interconnection structure 9 together serve as the interconnection structure of the active device to achieve electrical connection with the active device.

[0047] It should be noted that in Figure 4 In the process of forming the first sub-interconnection structure 5, it is necessary to form an interconnection material layer that completely covers the first interconnection groove and the top of the first dielectric layer, and to grind and remove the interconnection material layer above the top of the first dielectric layer by a planarization process, leaving only the interconnection material layer in the first interconnection groove as the first sub-interconnection structure 5; and Figure 7 In the process of forming the second sub-interconnection structure 9, the same process needs to be performed to form the first sub-interconnection structure 5 and the second sub-interconnection structure 9 one by one. Accordingly, in order to form the first sub-interconnection structure 5 and the second sub-interconnection structure 9 one by one, two patterning processes need to be performed to form corresponding grooves. At the same time, in order to prevent the second patterning process from damaging the first sub-interconnection structure 5, an isolation layer 6 needs to be formed at the same time to protect the first sub-interconnection structure 5.

[0048] The inventor believes that the process of forming the metal interconnect structure in this way is too complicated.

[0049] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a substrate and an active device formed on the substrate, wherein the active device comprises an interconnection region; forming a first dielectric layer and a first mask layer located on the first dielectric layer on the active device, the first mask layer having a first opening, the projection of the first opening on the substrate at least partially overlapping with the interconnection region of the active device; forming a second dielectric layer on the first mask layer, wherein the second dielectric layer is connected to the first dielectric layer through the first opening; removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnection groove exposing the interconnection region of the active device; wherein the interconnection groove exposes the interconnection region of the active device based on the first opening; and forming a metal interconnection structure in the interconnection groove.

[0050] It can be seen that the formation method provided by the embodiment of the present invention forms a first mask layer located on the first dielectric layer, and makes the second dielectric layer connected to the first dielectric layer through the first opening of the first mask layer, so that the second dielectric layer in a partial area and the first dielectric layer connected to the second dielectric layer can be removed at the same time, thereby forming an interconnection groove exposing the interconnection area of ​​the active device, and further forming an interconnection structure for electrical connection with the active device through a one-time interconnection structure formation process. Compared with forming corresponding sub-interconnection structures in the first dielectric layer and the second dielectric layer respectively, the embodiment of the present invention greatly simplifies the formation process of the metal interconnection structure, thereby reducing the process cost of forming the metal interconnection structure.

[0051] In addition, it can be understood that when multiple sub-interconnect structures are connected, contact resistance will be generated, and using multiple sub-interconnect structures as the interconnect structure of the device will form a larger interconnect resistance. In comparison, the embodiment of the present invention forms a metal interconnect structure at one time, which can greatly reduce the interconnect resistance of the interconnect structure.

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] Figures 8 to 16 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0054] refer to Figure 8 , providing a substrate, the substrate comprising a substrate 100 and an active device (not shown in the figure) formed on the substrate 100 , wherein the active device comprises an interconnection region 101 .

[0055] The substrate 100 provides a process basis for forming a semiconductor structure.

[0056] In this embodiment, the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may also be other semiconductor materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0057] In this embodiment, the substrate further includes active devices formed on the substrate, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors or inductors, etc. The active devices include interconnect regions for achieving electrical connection with the interconnect structures, thereby controlling the operation of the active devices.

[0058] In a specific example, the interconnection region 101 of the active device may be an interconnection metal layer of the active device, and the interconnection metal layer may be located in a device dielectric layer 102 surrounding the active device, and the interconnection metal layer is used to electrically connect specific structures of the active device, such as a source / drain structure, a gate structure, etc. The material of the interconnection metal layer includes Cu, and in a further example, the interconnection metal layer may include one or more of W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0059] In a further embodiment of the present invention, the substrate further comprises a dielectric barrier layer 103 covering the active device, and the dielectric barrier layer 103 is used to isolate and protect the interconnection region 101 during the subsequent process of forming interconnection trenches corresponding to the metal interconnection structure.

[0060] Among them, the dielectric barrier layer 103 can be silicon nitride. In some optional examples, the dielectric barrier layer can be one or more of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN).

[0061] refer to Fig. 9 and Fig.10 , forming a first dielectric layer 104 and a first mask layer 105 located on the first dielectric layer 104 on the active device;

[0062] The first dielectric layer 104 can be understood as a partial interlayer dielectric layer of the device, which is used to isolate and protect the active device while providing a process basis for forming a metal interconnection structure.

[0063] The first dielectric layer may be an oxide, such as silicon oxide. In some specific examples, the first dielectric layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride and silicon boron nitride carbon.

[0064] Specifically, the first dielectric layer can be formed by a deposition process. When a dielectric barrier layer is formed on the active device, the first dielectric layer can be specifically formed on the dielectric barrier layer.

[0065] The first mask layer 105 can be used for patterning the first dielectric layer 104. Specifically, the first mask layer 105 has a first opening 106, and the projection of the first opening 106 on the substrate at least partially overlaps with the interconnection area 101 of the active device, so that in the subsequent process, the first dielectric layer 104 exposed by the first opening 106 can be removed based on the first mask layer 105, thereby exposing the interconnection area 102 corresponding to the first opening 106.

[0066] The first mask layer may be silicon nitride. In some specific examples, the first mask layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron nitride carbon. It should be noted that the first mask layer is made of a different material from the first dielectric layer side material to isolate and protect the first dielectric layer.

[0067] In an optional example, the first dielectric layer 104 (see Fig. 9 ), then, a first mask layer 105 is formed on the first dielectric layer 104 (refer to Fig.10 ) to perform this step process.

[0068] The first mask layer may be formed on the first dielectric layer by a deposition and etching process. Fig.10 The process of forming the first mask layer may include: forming a first mask material layer on the first dielectric layer; patterning the first mask material layer, removing the first mask material layer in a preset area, forming the first opening, and using the remaining first mask material layer as the first mask layer.

[0069] Specifically, the first mask material layer can be formed by a deposition process, and the patterning can be achieved by photolithography and etching processes, by forming a photolithography pattern on the first mask material layer to expose a preset area of ​​the first mask material layer, and removing the first mask material layer exposed by the photolithography pattern by an etching process to form a first opening, thereby forming the first mask layer. The etching process can be a wet etching process, a dry etching process, or a process combining wet etching and dry etching.

[0070] refer to Fig.11 , forming a second dielectric layer 107 on the first mask layer 105, wherein the second dielectric layer 107 is connected to the first dielectric layer 104 through the first opening 106;

[0071] The second dielectric layer 107 can be understood as another part of the interlayer dielectric layer of the device.

[0072] In the embodiment of the present invention, after forming the first mask layer, the first dielectric layer is not patterned immediately. Instead, the second dielectric layer is further formed, and during the patterning process of the second dielectric layer, the first dielectric layer is patterned at the same time, thereby forming interconnection grooves that expose the interconnection area of ​​the active device through a single patterning process, thereby simplifying the process flow and reducing the process cost.

[0073] It should be noted that, since the first mask layer has a first opening for exposing the first dielectric layer, correspondingly, the second dielectric layer can be connected to the first dielectric layer through the first opening.

[0074] The material of the second dielectric layer can be an oxide, such as silicon oxide. In some specific examples, the first dielectric layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride and silicon boron nitride carbon. In a preferred example, the second dielectric layer and the first dielectric layer are made of the same material.

[0075] Specifically, the second dielectric layer can be formed by a deposition process.

[0076] refer to Figure 12 to Figure 14 , removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnection trench exposing the interconnection region of the active device;

[0077] It can be understood that, based on the aforementioned steps, a first mask layer capable of patterning the first dielectric layer has been formed. In this step, during the process of removing a portion of the second dielectric layer, the first dielectric layer connected to the second dielectric layer through the first opening of the first mask layer can be removed simultaneously, thereby simplifying the process flow and reducing the process cost.

[0078] In addition, by removing the second dielectric layer in a partial area and the first dielectric layer connected to the second dielectric layer, an interconnection groove exposing the interconnection area of ​​the active device is formed, and then an interconnection structure for electrical connection with the active device can be formed through a one-time interconnection structure formation process. Compared with forming corresponding sub-interconnection structures in the first dielectric layer and the second dielectric layer respectively, the embodiment of the present invention greatly simplifies the formation process of the metal interconnection structure, thereby reducing the process cost of forming the metal interconnection structure.

[0079] In an optional example, the process of forming the interconnection trench may include the following process:

[0080] refer to Fig.12, forming a second mask layer 108 on the second dielectric layer, wherein the second mask layer 108 has a second opening 109 exposing a portion of the second dielectric layer 107, and a projection of the second opening 109 on the substrate at least covers a projection of the first opening 106 on the substrate;

[0081] The second mask layer is used to realize the patterning of the second dielectric layer. Accordingly, a second opening for realizing the patterning of the second dielectric layer is formed on the second mask layer, and the projection of the second opening on the substrate at least covers the projection of the first opening on the substrate, so that the patterning process based on the second opening can expose the first opening of the first mask layer.

[0082] It should be noted that one second opening may correspond to one first opening, or, in an optional example, one second opening may correspond to multiple first openings, and the present invention does not make any specific limitation here.

[0083] The second mask layer may be silicon oxynitride. In some specific examples, the second mask layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron nitride carbon. It should be noted that the material of the second mask layer may be the same as or different from the material of the first mask layer. Compared with the solution in which the corresponding sub-interconnection structures are formed in the first dielectric layer and the second dielectric layer respectively, the material of the second mask layer is different from the material of the first mask layer to avoid the second mask layer being etched at the same time during the patterning of the first mask layer, the material selection in the embodiment of the present invention is wider and the process is simpler.

[0084] It can be understood that the formation process of the second mask layer can refer to the formation process of the first mask layer, and the present invention will not be repeated here.

[0085] refer to Fig.13 Using the second mask layer 108 as a mask, the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer are etched to form an interconnection trench 110 exposing the interconnection region of the active device.

[0086] After forming the second mask layer, the second dielectric layer can be patterned based on the second opening of the second mask layer. At the same time, based on the connection between the second dielectric layer and the first dielectric layer based on the first opening, while patterning the second dielectric layer, the first dielectric layer can also be patterned based on the first opening.

[0087] In a specific example, the etching of the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer is specifically to etch the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer by pulsed plasma etching. The pulsed plasma etching method can make the etching device output power in a pulsed manner, thereby making the etching device excite the etching gas in an intermittent and discontinuous manner for etching.

[0088] The inventors believe that, under normal circumstances, the size of the etching area will affect the etching rate of plasma etching. The reason is that during the plasma etching process, the etching gas reacts with the etched material to form deposits that hinder the etching process. The etching device in the embodiment of the present invention generates a pulsed output power, so that the etching process is carried out in an intermittent and non-continuous manner. The etching will be stopped after a certain period of time. At this time, the etching device temporarily stops exciting the etching gas, so that the polymer that has been produced on the etching surface has time to leave the etching surface, thereby reducing the degree of aggregation of the polymer, reducing the hindrance to the etching rate, and improving the process effect of the etching process.

[0089] In an optional example, in the etching process, the etching gas used can be a combination of one or more of C4F6, C4F8, SF6, NF3, O2, CH2F2, CH3F, CHF3, CH4, Ar, Kr, and N2. The flow rate of the etching gas can be 10sccm to 250sccm, the etching source power can be 50W to 6000W, the bias power can be 100W to 1600W, the pressure of the etching chamber can be 0mtorr to 50mtorr, the etching frequency (Frequency) can be 100Hz to 8000Hz, and the duty cycle can be 10% to 80%.

[0090] In other examples, when the substrate further includes a dielectric barrier layer 103 covering the active device, Fig.14 In the process of removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnection groove exposing the interconnection area of ​​the active device, after removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer in the above steps, the dielectric barrier layer exposed by the first dielectric layer can be further removed to form an interconnection groove exposing the interconnection area of ​​the active device.

[0091] Next, refer to Figure 15 to Figure 16 , forming a metal interconnect structure 112 in the interconnect trench.

[0092] Based on the interconnection trench that exposes the interconnection area of ​​the active device formed in the previous step, this step can directly form a metal interconnection structure in the interconnection trench. Compared with forming corresponding sub-interconnection structures in the first dielectric layer and the second dielectric layer respectively, the embodiment of the present invention greatly simplifies the formation process of the metal interconnection structure and reduces the process cost of forming the metal interconnection structure.

[0093] Specifically, the formation process of the metal interconnect structure may be as follows:

[0094] refer to Fig.15 , a metal interconnect material layer 111 is formed in the interconnect trench, and the metal interconnect material layer 111 completely covers the interconnect trench.

[0095] The metal interconnection material is used to provide a process basis for forming a metal interconnection structure.

[0096] It can be understood that the interconnection trench penetrates the first dielectric layer and the second dielectric layer, and accordingly, the metal interconnection material layer completely covers the interconnection trench, thereby forming a metal interconnection structure that penetrates both the first dielectric layer and the second dielectric layer.

[0097] The material of the metal interconnect material layer is determined based on the material of the metal interconnect structure. In an optional example, the material of the metal interconnect structure may be one or more of W, Al, Cu, Ag, Au, Pt, Ni or Ti. In this example, the material of the metal interconnect structure may be Cu. Accordingly, the material of the metal interconnect material layer may be one or more of W, Al, Cu, Ag, Au, Pt, Ni or Ti. In this example, the material of the metal interconnect material layer corresponds to Cu.

[0098] The metal interconnect material layer may be formed by deposition, sputtering, electroplating or other processes, and the present invention does not make any specific limitation here.

[0099] refer to Fig.16 , remove the metal interconnect material layer on the top of the second dielectric layer, and retain the metal interconnect material layer in the interconnect trench as the metal interconnect structure 112.

[0100] The second mask layer can be used as a stop layer, and the metal interconnection layer above the second dielectric layer can be removed by grinding using a planarization process, thereby retaining the metal interconnection material layer in the interconnection trench as a metal interconnection structure.

[0101] It is understandable that the embodiments of the present invention can be applied to large-sized top-level vias (eg, 55nm UTV) and ultra-thick metal (UTM) interconnection processes that use deep trenches to form metal interconnections, thereby simplifying the process flow and reducing process costs.

[0102] Among them, the loss of oxide layer in the non-copper layer stop area of ​​large-size structure should be strictly controlled during UTM etching.

[0103] In addition, it can be understood that when multiple sub-interconnect structures are connected, contact resistance will be generated, and using multiple sub-interconnect structures as the interconnect structure of the device will form a larger interconnect resistance. In comparison, the embodiment of the present invention forms a metal interconnect structure at one time, which can greatly reduce the interconnect resistance of the interconnect structure.

[0104] In another embodiment of the present invention, a semiconductor structure is further provided. The semiconductor structure is formed based on the method for forming the semiconductor structure provided in the above embodiment, wherein the semiconductor structure is formed based on the method for forming the semiconductor structure provided in the above embodiment. Fig.16 , the semiconductor structure comprises:

[0105] The substrate comprises a substrate 100 and an active device (not shown in the figure) arranged on the substrate 100 , wherein the active device comprises an interconnection region 101 .

[0106] In this embodiment, the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may also be other semiconductor materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0107] In this embodiment, the substrate further includes active devices formed on the substrate, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors or inductors, etc. The active devices include interconnect regions for achieving electrical connection with the interconnect structures, thereby controlling the operation of the active devices.

[0108] In a specific example, the interconnection region 101 of the active device may be an interconnection metal layer of the active device, and the interconnection metal layer may be located in a device dielectric layer 102 surrounding the active device, and the interconnection metal layer is used to electrically connect specific structures of the active device, such as a source / drain structure, a gate structure, etc. The material of the interconnection metal layer includes Cu, and in a further example, the interconnection metal layer may include one or more of W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0109] In a further embodiment of the present invention, the substrate further comprises a dielectric barrier layer 103 covering the active device, and the dielectric barrier layer 103 is used to isolate and protect the interconnection region 101 during the subsequent process of forming interconnection trenches corresponding to the metal interconnection structure.

[0110] Among them, the dielectric barrier layer 103 can be silicon nitride. In some optional examples, the dielectric barrier layer can be one or more of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN).

[0111] The first dielectric layer 104 located on the active device and the first mask layer 105 located on the first dielectric layer 104, the first dielectric layer 104 can be understood as a partial interlayer dielectric layer of the device, which is used to isolate and protect the active device while providing a process basis for forming a metal interconnection structure.

[0112] The first dielectric layer may be an oxide, such as silicon oxide. In some specific examples, the first dielectric layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride and silicon boron nitride carbon.

[0113] The first mask layer 105 has a first opening, and a projection of the first opening on the substrate at least partially overlaps with an interconnection region of the active device.

[0114] The first mask layer may be silicon nitride. In some specific examples, the first mask layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron nitride carbon. It should be noted that the first mask layer is made of a different material from the first dielectric layer side material to isolate and protect the first dielectric layer.

[0115] The second dielectric layer 107 located on the first mask layer 105 , the second dielectric layer 107 can be understood as another part of the interlayer dielectric layer of the device.

[0116] The material of the second dielectric layer can be an oxide, such as silicon oxide. In some specific examples, the first dielectric layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride and silicon boron nitride carbon. In a preferred example, the second dielectric layer and the first dielectric layer are made of the same material.

[0117] An interconnection trench that penetrates the second dielectric layer and penetrates the first dielectric layer through the first opening, and a metal interconnection structure 112 located in the interconnection trench. The material of the metal interconnection structure can be one or more of W, Al, Cu, Ag, Au, Pt, Ni or Ti. In this example, the material of the metal interconnection structure can be Cu.

[0118] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0119] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate, an active device formed on the substrate, wherein the active device comprises an interconnection region; Forming a first dielectric layer and a first mask layer located on the first dielectric layer on the active device, wherein the first mask layer has a first opening, and a projection of the first opening on the substrate at least partially overlaps with an interconnection region of the active device; forming a second dielectric layer on the first mask layer, wherein the second dielectric layer is connected to the first dielectric layer through the first opening; Removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnection trench exposing the interconnection region of the active device; A metal interconnect structure is formed in the interconnect trench.

2. The method for forming a semiconductor structure according to claim 1, wherein: The second dielectric layer with a partial area removed and the first dielectric layer connected to the second dielectric layer to form an interconnection trench exposing the interconnection area of ​​the active device include: forming a second mask layer on the second dielectric layer, wherein the second mask layer has a second opening exposing a partial area of ​​the second dielectric layer, and a projection of the second opening on the substrate at least covers a projection of the first opening on the substrate; Using the second mask layer as a mask, the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer are etched to form interconnection grooves exposing the interconnection region of the active device.

3. The method for forming a semiconductor structure according to claim 2, wherein: The etching of the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer is specifically to etch the second dielectric layer exposed by the second opening and the first dielectric layer connected to the second dielectric layer by pulse plasma etching.

4. The method for forming a semiconductor structure according to claim 1, wherein: The substrate further includes a dielectric barrier layer covering the active device; The forming of the first dielectric layer on the active device is specifically, forming the first dielectric layer on the dielectric barrier layer; The step of removing a portion of the second dielectric layer and the first dielectric layer connected to the second dielectric layer to form an interconnection trench exposing the interconnection region of the active device further includes removing the dielectric barrier layer exposed by the first dielectric layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a first dielectric layer on the active device and a first mask layer on the first dielectric layer comprises: forming a first dielectric layer on the active device; forming a first mask material layer on the first dielectric layer; The first mask material layer is patterned to remove the first mask material layer in a preset area to form the first opening, and the remaining first mask material layer is used as the first mask layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The forming of a metal interconnect structure in the interconnect trench comprises: forming a metal interconnect material layer in the interconnect trench, wherein the metal interconnect material layer completely covers the interconnect trench; The metal interconnect material layer on the top of the second dielectric layer is removed, and the metal interconnect material layer in the interconnect trench is retained as a metal interconnect structure.

7. The method for forming a semiconductor structure according to claim 1, wherein: The interconnection region of the active device is an interconnection metal layer of the active device.

8. The method for forming a semiconductor structure according to claim 1, wherein: The second dielectric layer is made of the same material as the first dielectric layer.

9. The method for forming a semiconductor structure according to claim 2, wherein: In the etching process, the etching gas used is a combination of one or more of C4F6, C4F8, SF6, NF3, O2, CH2F2, CH3F, CHF3, CH4, Ar, Kr, and N2. The flow rate of the etching gas is 10 sccm to 250 sccm, the etching source power is 50 W to 6000 W, the bias power is 100 W to 1600 W, the pressure of the etching chamber is 0 mtorr to 50 mtorr, the etching frequency is 100 Hz to 8000 Hz, and the duty cycle is 10% to 80%.

10. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 9.

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