Semiconductor structure and forming method thereof

Abstract

The method includes forming an integrated circuit device on a semiconductor substrate, forming a via through the semiconductor substrate, and forming a dummy pattern surrounding the via. The dummy patterns include a first plurality of dummy patterns and a second plurality of dummy patterns having a first pattern density. The first plurality of dummy patterns is between the via and the second plurality of dummy patterns. The second plurality of dummy patterns has a second pattern density different from the first pattern density. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Through silicon vias (TSVs) are used as electrical paths in a device die so that conductive features on opposite sides of the device die can be interconnected. The formation process of TSVs may include etching a semiconductor substrate to form an opening, filling the opening with a conductive material to form the TSV, performing a backside grinding process to remove a portion of the semiconductor substrate from the backside and expose the TSV, and forming electrical connectors on the backside of the semiconductor substrate to connect the TSVs. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming an integrated circuit device on a semiconductor substrate; forming a first through hole penetrating the semiconductor substrate; and forming a dummy pattern around the first through hole, wherein the dummy pattern comprises: a first plurality of dummy patterns having a first pattern density; and a second plurality of dummy patterns, wherein the first plurality of dummy patterns are located between the first through hole and the second plurality of dummy patterns, and wherein the second plurality of dummy patterns have a second pattern density different from the first pattern density.

[0004] Some other embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; a first interconnect structure covering the semiconductor substrate; a second interconnect structure located below the semiconductor substrate; a through hole passing through the semiconductor substrate, wherein the through hole electrically connects a first metal pad in the first interconnect structure to a second metal pad in the second interconnect structure; a first dummy pad region surrounding the through hole, wherein the first dummy pad region includes a first dummy pattern having a first pattern density; and a second dummy pad region surrounding the first dummy pad region, wherein the second dummy pad region includes a second dummy pattern having a second pattern density different from the first pattern density.

[0005] Some other embodiments of the present application provide a semiconductor structure, comprising: a semiconductor substrate; a first through-hole and a second through-hole penetrating the semiconductor substrate; a redistribution structure, comprising: a plurality of dielectric layers located above the semiconductor substrate; and a plurality of metal lines located in the plurality of dielectric layers; and a plurality of dummy patterns located in the plurality of dielectric layers, wherein, in a top view of the structure, the plurality of dummy patterns are located between the first through-hole and the second through-hole, and wherein a pattern density of the plurality of dummy patterns increases from an area close to the first through-hole or the second through-hole to an intermediate area between the first through-hole and the second through-hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1-Figure 10 A cross-sectional view illustrates an intermediate stage in forming a die including through silicon vias (TSVs) using an intermediate through via process in accordance with some embodiments.

[0008] Figure 11-Figure 14 A cross-sectional view illustrates an intermediate stage in forming a die including TSVs using a via last process in accordance with some embodiments.

[0009] Fig.15 A TSV and a dummy pattern area around the TSV are shown according to some embodiments.

[0010] Fig.16 and Fig.17 The distribution of dummy patterns around a TSV according to some embodiments is shown.

[0011] Figure 18-Figure 20 Possible dummy patterns according to some embodiments are shown.

[0012] Fig.21 A staggered dummy pattern in multiple metal layers is shown in accordance with some embodiments.

[0013] Fig. 22 Dummy patterns in two metal layers having longitudinal directions perpendicular to each other are shown in accordance with some embodiments.

[0014] Fig.23 A process flow for designing a dummy pattern according to some embodiments is shown.

[0015] Fig.24 A process flow for forming a device die including TSVs is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides a variety of different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the subsequent description, forming a first component above or on a second component may include an embodiment in which the formed first component is in direct contact with the second component, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, but does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to facilitate description in describing the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] A through silicon via (TSV, also referred to as a through hole), a dummy pattern around the TSV, and a method for forming the same are provided. According to some embodiments, the dummy pattern around the TSV has different pattern densities, and the area close to the TSV has a lower pattern density than the area far from the TSV. Using different pattern densities, the warping of the corresponding device die and wafer can be reduced. The embodiments discussed herein will provide examples to enable the subject matter of the present disclosure to be performed or used, and a person of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and exemplary embodiments, the same reference numerals are used to designate the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may also be implemented in any reasonable order.

[0019] Figure 1-Figure 10 1 shows a cross-sectional view of an intermediate stage in the formation of a die including a through hole according to some embodiments. The corresponding process is also schematically reflected in Fig.24 In the process flow 200 shown.

[0020] Figure 1 A cross-sectional view of wafer 20 is shown. According to some embodiments, wafer 20 is or includes a device wafer, which includes active devices and possibly passive devices, represented as integrated circuit devices 26. Wafer 20 may include a plurality of chips / dies 20' therein, of which one of chips 20' is shown. According to alternative embodiments of the present disclosure, wafer 20 is an interposer wafer, which has no active devices and may or may not include passive devices.

[0021] According to some embodiments, wafer 20 includes a semiconductor substrate 24 and components formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be made of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. A shallow trench isolation (STI) region (not shown) may be formed in semiconductor substrate 24 to isolate active regions in semiconductor substrate 24.

[0022] According to some embodiments, an integrated circuit device 26 is formed, and is collectively referred to as a front-end structure. The corresponding process is shown as Fig.24 202 in the process flow 200 shown in FIG. According to some embodiments, the integrated circuit device 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit device 26 are not shown here. According to an alternative embodiment, the wafer 20 is used to form an interposer without active devices and passive devices.

[0023] An interlayer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the spaces between the gate stacks of transistors (not shown) in the integrated circuit device 26. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments, the ILD 28 may also be formed using a deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0024] Contact plug 30 is formed in ILD 28 and is used to electrically connect integrated circuit device 26 to the metal lines and vias above. According to some embodiments, contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of contact plug 30 may include forming a contact opening in ILD 28, filling the conductive material into the contact opening, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of contact plug 30 flush with the top surface of ILD 28.

[0025] According to some embodiments, some silicide regions 29 are formed below some contact regions 30. The illustrated silicide regions 29 and the upper contact regions 30 form a ring when viewed from the top. According to some embodiments, the silicide regions 29 and the upper contact plugs 30 may be used to electrically connect a subsequently formed TSV's guard ring to the semiconductor substrate 24. According to some embodiments, the subsequently formed guard ring may also be electrically connected to electrical ground.

[0026] refer to Figure 2, forming an etching mask 32 and patterning it. According to some embodiments, the etching mask 32 includes a photoresist and may or may not include a hard mask formed of TiN, BN, etc. An anisotropic etching process is then performed to form an opening 34 that penetrates the ILD 28. The semiconductor substrate 24 is further etched so that the opening 34 extends to a middle plane of the semiconductor substrate 24, wherein the middle plane is located between the top surface and the bottom surface of the semiconductor substrate 24. The opening 34 is used to form a TSV, and is therefore referred to as a TSV opening 34 hereinafter. The corresponding process is shown as Fig.24 The process 204 in the process flow 200 is shown in FIG. The etch mask 32 is then removed.

[0027] refer to Figure 3 , for example, by a deposition process to form a dielectric liner 36. The corresponding process is shown as Fig.24 206 in the process flow 200 shown in FIG. The dielectric liner 36 may include a horizontal portion outside the TSV opening 34 and a vertical portion extending into the TSV opening 34. According to some embodiments, the dielectric liner 36 is formed of or includes a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, etc. or a combination thereof. The deposition method may include plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.

[0028] Figure 3 Further shown is the deposition of conductive material 38 on dielectric liner 36. The corresponding process is shown as Fig.24 208 in the process flow 200 shown in FIG. According to some embodiments, the conductive material 38 includes a metal seed layer and a metal material above the metal seed layer. According to some embodiments, the metal seed layer is formed by physical vapor deposition (PVD). The metal seed layer can be a single layer, such as formed of copper, or can include multiple layers, such as including a conductive barrier layer and a copper layer on the conductive barrier layer. The conductive barrier layer can be formed of or include TiN, Ti, TaN, Ta, etc.

[0029] The metal material may include copper, copper alloy, tungsten, etc. The deposition process may be performed using electrochemical plating (ECP), chemical plating, etc. The electroplating is performed until the top surface of the plated metal material is higher than the top surface of the dielectric liner 36 .

[0030] Figure 4 A planarization process is shown for planarizing the top surface of the metal material 38 and the dielectric liner 36, which may be a CMP process or a mechanical grinding process. The corresponding process is shown as process 210 in process flow 200, as shown in FIG. Fig.24According to some embodiments, the planarization process is performed using the ILD 28 as a stop layer. The metal seed layer and the remaining portion of the metal material are collectively referred to as TSV 40 hereinafter.

[0031] refer to Figure 5 , forming an interconnect structure 42. The corresponding process is shown as Fig.24 212 in the process flow 200 shown in FIG. The interconnect structure 42 includes metal lines 44 and vias 46 formed in a dielectric layer 48 (also referred to as an intermetallic dielectric (IMD)) and an etch stop layer 47. Metal lines at the same level may be collectively referred to as metal layers hereinafter. According to some embodiments, the interconnect structure 42 includes a plurality of metal layers, including metal lines 44 interconnected by vias 46.

[0032] Metal lines 44 and vias 46 may be formed of copper or copper alloys, and they may also be formed of other metals. According to some embodiments, dielectric layer 48 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than 3.5. Dielectric layer 48 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. Etch stop layer 47 may be formed of or include aluminum oxide, aluminum nitride, SiOC, SiON, etc., or a multilayer thereof.

[0033] Forming metal lines 44 and vias 46 in dielectric layers 48 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or vias, a trench or via opening is first formed in one of dielectric layers 48, and then the trench or via opening is filled with a conductive material. A planarization process (such as a CMP process) is then performed to remove excess conductive material above the top surface of the dielectric layer, leaving metal lines or vias in the corresponding trench or via openings.

[0034] In the dual damascene process, trenches and via openings are formed in the dielectric layer, and the via openings are located below and connected to the trenches. Then conductive materials are filled into the trenches and via openings to form metal lines and vias, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0035] In the same process of forming the metal layer in the interconnect structure 42, dummy patterns 44-D1, 44-D2 and 44-D3 (hereinafter collectively referred to as dummy patterns 44-D) are also formed. The dummy pattern 44-D can be electrically floating. A guard ring 49 is also formed to surround the area just above the TSV 40. The dummy patterns 44-D1, 44-D2 and 44-D3 are formed in dummy pattern regions R1, R2 and R3, respectively, and can extend into the top metal layer of the interconnect structure 42, and can include portions in multiple metal layers. The details of the dummy patterns 44-D1, 44-D2 and 44-D3 are discussed later.

[0036] According to some embodiments, there may be integrated circuit devices 26 formed in the dummy pattern regions R1, R2, and / or R3 and directly below the dummy patterns 44-D1, 44-D2, and 44-D3. According to alternative embodiments, integrated circuit devices 26 are not formed in the dummy pattern regions R1, R2, and R3. Therefore, integrated circuit devices 26 in the dummy pattern regions R1, R2, and R3 are shown as dotted lines to indicate that they may or may not be formed.

[0037] Figure 6 The formation of the upper structure of the wafer 20 is shown. The corresponding process is shown as Fig.24 214 in the process flow 200 shown in FIG. 214. The etch stop layer 50 may be formed over the interconnect structure 42. The passivation layer 52 (sometimes referred to as passivation-1 or pass-1) is formed over the etch stop layer 50. According to some embodiments, the passivation layer 52 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than the dielectric constant of silicon oxide. The passivation layer 52 may be formed of or include an inorganic dielectric material, which may include a material selected from, but not limited to, undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide (SiC), etc., combinations thereof, and / or multilayers thereof. According to some embodiments, the top dielectric layer 48 and the top surfaces of the metal lines 44 of the interconnect structure 42 are flush with each other. Therefore, the passivation layer 52 may be a planar layer.

[0038] According to some embodiments, via 54 is formed in passivation layer 52 and etch stop layer 50 to electrically connect to the top metal feature 44 below. Metal pad 56 is further formed over via 54. According to some embodiments, metal pad 56 includes aluminum, aluminum copper, etc. Passivation layer 58 (sometimes referred to as passivation-2 or pass-2) is also formed and may extend over the sidewalls and top surface of metal pad 56. Passivation layer 58 may be formed of or include silicon oxide, silicon nitride, etc. or multiple layers thereof.

[0039] According to some embodiments, dielectric layer 60 is formed, for example, by dispensing a polymer in a flowable form and then curing polymer layer 60. Dielectric layer 60 is patterned to expose metal pad 56. Dielectric layer 60, when formed of a polymer, may be formed of or include polyimide, polybenzoxazole (PBO), etc. Alternatively, dielectric layer 60 may be formed of or include an organic dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0040] Under bump metal (UBM) 62 and bonding pad 64 may be formed to electrically connect to underlying metal pad 56. The formation process of UBM 62 and bonding pad 64 may include forming openings in passivation layer 58 and polymer layer 60, depositing a blanket metal seed layer extending into the openings, forming a patterned plating mask on the metal seed layer, plating bonding pad 64, removing the plating mask, and etching portions of the blanket metal seed layer previously covered by the plating mask. According to some embodiments, dielectric layer 66 is formed to have a top surface coplanar with the top surface of bonding pad 64 and may be used for hybrid bonding. Other electrical connections for other bonding schemes such as solder bonding may also be formed.

[0041] Figures 7 to 10 A process for forming backside features on the backside of semiconductor substrate 24 is shown. Figure 7 , a carrier 68 (which may be a glass carrier) is attached to the front side of the wafer 20. The attachment may be performed by an adhesive such as a light-to-heat conversion (LTHC) material 70 that is configured to decompose under the heat of light (such as a laser beam). The corresponding process is shown as Fig.24 Process 216 in process flow 200 is shown in FIG.

[0042] refer to Figure 8 , a backside grinding process is performed to remove a portion of the substrate 24 until the TSV 40 is exposed. The corresponding process is shown as Fig.24 200. Next, the semiconductor substrate 24 is slightly grooved (e.g., by etching) so that the ends of the TSVs 40 protrude beyond the back side of the semiconductor substrate 24. Next, a dielectric layer 72 is deposited, followed by a CMP process or a mechanical grinding process to re-expose the TSVs 40. Therefore, the TSVs 40 also penetrate the dielectric layer 72. According to some embodiments, the dielectric layer 72 is formed of silicon oxide, silicon nitride, etc.

[0043] refer to Fig. 9 , forming a backside interconnect structure 80. The corresponding process is shown as Fig.24200. The backside interconnect structure 80 includes one or more dielectric layers 76 and RDL 74 in the dielectric layer 76. The RDL 74 may include a pad portion that contacts the TSV 40. According to some embodiments, the RDL 74 may be formed of aluminum, copper, nickel, titanium, etc. The formation of the RDL 74 layer may include forming a dielectric layer, etching the corresponding dielectric layer to form an opening, electroplating a metal seed layer extending into the opening, forming a patterned plating mask (in which some portions of the metal seed layer are exposed), and electroplating to form the RDL 74.

[0044] According to some embodiments, when forming RDL 74, dummy patterns 74-D1, 74-D2, and 74-D3 (hereinafter collectively referred to as dummy patterns 74-D) are formed. Dummy patterns 74-D1, 74-D2, and 74-D3 are formed in dummy pattern regions R1, R2, and R3, respectively, and may include portions of multiple RDL layers. Details of dummy patterns 74-D1, 74-D2, and 74-D3 are discussed later. Dummy pattern 74-D may be electrically floating.

[0045] According to some embodiments, both dummy patterns 74-D and 44-D are formed. According to an alternative embodiment, dummy pattern 44-D is formed without forming dummy pattern 74-D. According to yet another alternative embodiment, dummy pattern 74-D is formed without forming dummy pattern 44-D. Dummy patterns 74-D and 44-D may have the effect of correcting the same type of warpage or the opposite type of warpage. Therefore, whether to form dummy pattern 74-D, dummy pattern 44-D, or both dummy patterns 74-D and 44-D is determined by the possible warpage profiles of device die 20' and wafer 20. The design of dummy patterns 74-D and 44-D may include measuring (when manufacturing wafer 20) and / or simulating the warpage profiles of device die 20' and wafer 20, adding dummy patterns 74-D and / or 44-D, and measuring and / or simulating the warpage profiles of device die and wafer to select the best design of dummy pattern from multiple designs.

[0046] Electrical connector 78 is also formed. According to some embodiments, electrical connector 78 includes a soldering area, which can be formed by electroplating solder balls on pads of RDL 74 and reflowing the solder balls. According to alternative embodiments, electrical connector 78 is formed of a non-reflowable (non-solderable) metal material. For example, electrical connector 78 can be formed as a copper pad or copper pillar, and may or may not include a nickel capping layer.

[0047] The carrier 68 is then peeled off the underlying wafer 20. The resulting structure is shown in FIG. Fig.10 The corresponding process is shown as Fig.24 The process 222 in the process flow 200 shown in FIG. Then, the wafer 20 can be segmented. The corresponding process is shown as Fig.24Process 224 in process flow 200 is shown in FIG.

[0048] The above TSV formation process is called an intermediate TSV process because the TSV is formed after the integrated circuit device (FEOL structure) is formed and before the interconnect structure (BEOL structure) is formed. According to alternative embodiments, the TSV can be formed using a first TSV process (which is performed before the FEOL structure is formed) or a last TSV process (which is performed after the BEOL structure is formed). These processes can also be implemented through the discussion of the previous embodiments.

[0049] For example, Figures 11 to 14 The post-TSV process is shown as an example. Unless otherwise stated, the materials, structures, and formation processes of the components in these embodiments are substantially the same as the same components, which are represented by the same reference characters in the previous embodiments. The details on materials, structures, and formation processes provided in each embodiment throughout the description can be applied to any other embodiment as long as it is applicable.

[0050] The initial steps of these embodiments are basically the same as Figure 1-Figure 7 The same as shown in , and the resulting structure is essentially the same as Figure 7 , except that the TSV 40 and the corresponding dielectric liner 36 have not yet been formed. The corresponding structure is shown in Fig.11 Next, Fig.12 As shown, a backside thinning process is performed to thin the semiconductor substrate 24 .

[0051] In the subsequent process, Fig.13 As shown, TSV 40 and dielectric liner 36 are formed from the backside of semiconductor substrate 24. The formation process may include etching semiconductor substrate 24 and frontside dielectric layers (such as ILD 28) to expose metal lines / pads 44, filling the openings with dielectric liner and conductive material, and performing a planarization process. Fig.14 The formation of the backside interconnect structure 80 and the electrical connections 78 is shown. A singulation process may then be performed to saw the wafer 20 into discrete device die 20'.

[0052] Fig.15 A top view of the TSV 40 and surrounding dummy pattern regions R1, R2, and R3 is shown, in which dummy patterns (44-D and 74-D, as shown in FIG. Fig.10 and 14). Throughout the description, reference numeral "44-D / 74-D" refers to a dummy pattern 44-D and / or a dummy pattern 74-D. TSV 40 may be surrounded by a plurality of dummy pattern regions such as R1, R2, and R3 or more, wherein an outer region surrounds an inner region. Each of the dummy pattern regions R1, R2, and R3 has a pattern density PD that may be uniform or substantially uniform (e.g., with a variation of less than 20%) throughout the corresponding dummy pattern region. The dummy pattern regions R1, R2, and R3 have pattern density values ​​PD1, PD2, and PD3, respectively.

[0053] Throughout the description, the pattern density of the metal layer refers to the ratio of the total area of ​​all dummy patterns in the unit chip area (area) and in the same metal layer to the total area of ​​the unit chip area. Moreover, since the pattern density has a large fluctuation when the unit chip area is too small, the unit chip area is defined as having a width and length greater than about 50×W40, where the value W40 is the length and width of TSV 40 (or the diameter when the TSV is circular). According to some embodiments, the width W1 of the dummy pattern area R1 may be in the range between about 100×W40 and about 500×W40. The width W2 of the dummy pattern area R2 may be in the range between about 200×W40 and about 1,000×W40. The width W3 of the dummy pattern area R3 may be in the range between about 100×W40 and about 1,000×W40.

[0054] According to some embodiments, a pattern density value of the outer dummy pattern region is greater than a pattern density value of the corresponding inner dummy pattern region. Fig.15 The arrows shown indicate the direction in which the pattern density of the dummy pattern 44 -D / 74 -D increases. For example, the pattern density PD3 of the dummy pattern region R3 is greater than the pattern density PD2 of the dummy pattern region R2 , which is further greater than the pattern density PD1 of the dummy pattern region R1 .

[0055] According to some embodiments, the pattern density PD1 of the dummy pattern region R1 may be in a range between about 10% and about 30%. The pattern density PD2 of the dummy pattern region R2 may be in a range between about 30% and about 50%. The pattern density PD3 of the dummy pattern region R3 may be in a range between about 50% and about 70%. The differences (PD2-PD1) and (PD3-PD2) may be greater than about 10% or greater than about 20%.

[0056] According to some embodiments, Fig.10 , Fig.14 , Fig.16 and Fig.17As shown, each of the dummy pattern regions R1, R2 and R3 has a uniform pattern density or a substantially uniform pattern density, for example, with a fluctuation of less than about 20%. The dummy pattern shape and its size therein may be uniform or substantially uniform. According to an alternative embodiment, there is no clear boundary between the dummy pattern regions R1, R2 and R3. On the contrary, in the direction from the first TSV to the center line between the first TSV and the second TSV adjacent to the first TSV, the pattern density gradually increases. The dummy pattern 44-D / 74-D may also gradually increase, and / or the interval between adjacent dummy patterns 44-D / 74-D may gradually decrease.

[0057] According to some embodiments, Fig.15 As shown, TSV 40 can be arranged in an array. Therefore, the dummy pattern area R3 surrounding the plurality of TSVs 40 can be combined to form a grid pattern including a plurality of horizontal bands and a plurality of vertical bands, wherein the vertical bands and the horizontal bands have overlapping areas. In addition, the combined area of ​​dummy patterns R2 and R3 can form a grid pattern including a plurality of horizontal bands and a plurality of vertical bands, wherein the vertical bands and the horizontal bands have overlapping areas. According to alternative embodiments, the plurality of TSVs 40 can form other patterns, such as a hexagonal pattern, and the shapes of the areas R1, R2, and R3 will change accordingly.

[0058] like Fig.10 and Fig.14 The TSV 40 and dummy patterns 44-D and 74-D shown may be obtained from Fig.15 The cross section AA shown is obtained. Fig.10 and Fig.14 Not shown, but can also be obtained from Fig.15 It is found that the region R3 of one TSV 40 can be joined with the region R3 of its adjacent TSV 40 .

[0059] refer to Fig.10 or Fig.14 The difference in pattern density values ​​PD1, PD2, and PD3 can be achieved by making the intervals S1, S2, and S3 of the dummy patterns 44-D1, 44-D2, and 44-D3 different from each other, and / or the lateral dimensions LD1, LD2, and LD3 of the dummy patterns 44-D1, 44-D2, and 44-D3 different from each other. For example, the interval S3 can be smaller than the interval S2, and / or the interval S2 can be smaller than the interval S1. The lateral dimension L3 can be larger than the lateral dimension L2, and / or the dimension L2 can be larger than the lateral dimension L1. Moreover, some patterns can be hollow (e.g. Fig.16 The dummy pattern 44-D1 in the dummy pattern region R2 in the embodiment of the present invention is used to reduce the pattern density. The difference between the dummy patterns 74-D1, 74-D2 and 74-D4 can also be achieved similarly to the dummy pattern 44-D.

[0060] According to some embodiments, the dummy pattern close to the TSV has a lower pattern density than the dummy pattern far from the TSV. According to alternative embodiments, to meet different warpage conditions, the dummy pattern far from the TSV may have a lower pattern density than the dummy pattern close to the TSV.

[0061] Fig.16 A top view of an example TSV 40 and surrounding dummy pattern regions R1, R2, and R3 according to some embodiments is shown. It should be understood that the pattern, shape, and relative size of the dummy patterns shown are examples and may not be to scale. The areas shown may be Fig.15 According to some embodiments, the TSV 40 is surrounded by the dummy region R1 (eg, Fig.15 dummy pattern 44-D1 / 74-D1 is located therein. Dummy pattern 44D1 / 74-D1 may have the smallest size and / or the largest spacing among the dummy patterns in dummy regions R1, R2, and R3. Dummy pattern 44-D3 / 74-D3 may have the largest size and / or the smallest spacing among the dummy patterns in dummy regions R1, R2, and R3. Dummy pattern 74-D2 / 44-D2 may be designed to be hollow to reduce the pattern density in dummy pattern region R2, or may be solid.

[0062] Fig.17 A top view of an example TSV 40 and its surrounding area according to an alternative embodiment is shown. According to some embodiments, the dummy pattern region R2 has patterns of different shapes. The inner portion has a U-shaped dummy pattern (which is a semi-annular pattern), and the outer portion has an annular pattern (which is hollow). According to some embodiments, the dummy pattern region R3 has different types of patterns. The inner portion has a square and smaller solid dummy pattern, and the outer portion has an elongated and larger solid pattern. Fig.17 The embodiment in can be considered to have 5 dummy pattern regions, or alternatively, the dummy pattern regions R2 and R3 are gradient.

[0063] Fig.18 , Fig.19 and Fig. 20 Different types of dummy patterns according to some embodiments are shown. Fig.18 Some solid candidate pseudo patterns are shown. These pseudo patterns 44-D / 74-D include small rectangles, large rectangles, vertical elongated bars, horizontal elongated bars, etc. Fig.19 Ring-shaped dummy patterns 44 -D / 74 -D having different sizes and shapes are shown. Fig. 20 U-shaped or L-shaped dummy patterns 44 -D / 74 -D having different sizes and shapes are shown.

[0064] According to some embodiments, the dummy patterns in different metal layers (e.g., the top metal layer and the metal layer directly below) can be different, for example, have different shapes and / or sizes. According to alternative embodiments, the dummy patterns in different metal layers (e.g., the top metal layer and the metal layer immediately below) can be the same, for example, have the same shape and the same size.

[0065] Fig.21 Some embodiments are shown in which dummy patterns in different metal layers (e.g., a top metal layer and a metal layer directly below) can be staggered (offset and vertically misaligned), and the offset dummy patterns in different metal layers can have the same shape or different shapes and / or sizes.

[0066] Fig. 22 Some embodiments are shown in which the dummy patterns in different metal layers (e.g., the top metal layer and the immediately lower metal layer) are elongated and their length directions are perpendicular to each other. The dummy pattern 44D-A / 74D-A in the upper metal layer and the dummy pattern 44D-B / 74D-B in the lower metal layer are shown as examples.

[0067] Fig.23 A design flow 84 for designing a layout of a dummy pattern is shown according to some embodiments. Fig.23 The process shown is performed before fabricating dummy patterns and TSVs on the wafer. Referring to process 86, a layout design is provided. The designed layout includes the layout of components of different layers of the wafer 20 ( Fig.10 and Fig.14 ), and the layout of the TSVs. The dummy patterns 44-D and 74-D are then inserted in process 88 according to the rules already discussed. Next, as shown in process 90, a design rule check is performed to ensure that the inserted dummy patterns do not violate the design rules.

[0068] If the inserted dummy pattern passes the design rule check, the layout can be taped out (process 92). Then, a photolithography mask for manufacturing a wafer is made, which includes a mask for forming the dummy pattern and the TSV (process 94). If the inserted dummy pattern does not pass the design rule check, the process loops back to process 88 to redesign the dummy pattern, and then perform the design rule check again, repeating the cycle until the dummy pattern can pass the design rule check.

[0069] Optionally, after mask making, a sample wafer including the inserted dummy pattern can be made and the warpage can be measured to determine whether the warpage profile meets the design specifications. If not, the process loops back to process 88 to repeat the above process. Alternatively, after the design rule check and before tape-out, a simulation is performed to determine whether the warpage profile meets the design specifications. If not, the process loops back to process 88 to repeat the above process.

[0070] Embodiments of the present disclosure have some advantageous features. By forming dummy patterns with different pattern densities, the warpage of corresponding device dies and wafers can be reduced. The reduction of warpage does not involve additional manufacturing costs.

[0071] According to some embodiments, a method includes: forming an integrated circuit device on a semiconductor substrate; forming a first through hole penetrating the semiconductor substrate; forming a dummy pattern surrounding the first through hole, wherein the dummy pattern includes a first plurality of dummy patterns having a first pattern density; and a second plurality of dummy patterns, wherein the first plurality of dummy patterns are located between the first through hole and the second plurality of dummy patterns, and wherein the second plurality of dummy patterns have a second pattern density different from the first pattern density.

[0072] In an embodiment, the dummy pattern further comprises a third plurality of dummy patterns, wherein the first plurality of dummy patterns and the second plurality of dummy patterns are located between the first through hole and the third plurality of dummy patterns, wherein the third plurality of dummy patterns have a third pattern density different from the first pattern density and the second pattern density. In an embodiment, the third pattern density is greater than the second pattern density, and the second pattern density is greater than the first pattern density. In an embodiment, forming the first through hole comprises: forming a first through hole extending into the semiconductor substrate; performing a backside grinding process to expose the first through hole from the back side of the semiconductor substrate; and forming a backside interconnect structure on the back side of the semiconductor substrate.

[0073] In an embodiment, the method further comprises: forming an additional dummy pattern on the back side of the semiconductor substrate, wherein the additional dummy pattern has a lower pattern density in an area close to the first through hole and a higher pattern density in an area away from the first through hole. In an embodiment, each of the first pattern density and the second pattern density is measured in a chip area having a length and a width greater than about 50 μm. In an embodiment, the first through hole is formed by an intermediate through hole process and is formed after forming the integrated circuit device and before forming the dummy pattern.

[0074] In an embodiment, the first through hole is formed by a via last process and is formed after forming both the integrated circuit device and the dummy pattern. In an embodiment, the method further comprises: when forming the first through hole, forming a second through hole, wherein the dummy pattern further comprises a fourth plurality of dummy patterns having a fourth pattern density; a fifth plurality of dummy patterns having a fifth pattern density between the second through hole and the fourth plurality of dummy patterns; and a sixth plurality of dummy patterns having a sixth pattern density between the fifth plurality of dummy patterns and the second plurality of dummy patterns, wherein the fifth pattern density is greater than the fourth pattern density, and the sixth pattern density is greater than the fifth pattern density.

[0075] In an embodiment, the dummy patterns are electrically floating. In an embodiment, the first plurality of dummy patterns have a different shape than the second plurality of dummy patterns. In an embodiment, the first plurality of dummy patterns have a different pitch than the second plurality of dummy patterns.

[0076] According to some embodiments, a structure includes: a semiconductor substrate; a first interconnect structure covering the semiconductor substrate; a second interconnect structure located below the semiconductor substrate; a through-hole penetrating the semiconductor substrate, wherein the through-hole electrically connects a first metal pad in the first interconnect structure to a second metal pad in the second interconnect structure; a first dummy pad region surrounding the through-hole, wherein the first dummy pad region includes a first dummy pattern having a first pattern density; and a second dummy pad region surrounding the first dummy pad region, wherein the second dummy pad region includes a second dummy pattern having a second pattern density different from the first pattern density.

[0077] In an embodiment, the first dummy pad region has a substantially uniform pattern density of the first dummy pattern, and the second dummy pad region has a substantially uniform pattern density of the second dummy pattern. In an embodiment, the structure further includes a third dummy pad region surrounding the second dummy pad region, wherein the third dummy pad region includes a third dummy pattern having a third pattern density different from the first pattern density and the second pattern density.

[0078] In an embodiment, the structure further comprises a device located at a top surface of the semiconductor substrate, wherein the first dummy pattern and the second dummy pattern are located above the semiconductor substrate. In an embodiment, the structure further comprises an active device located at a top surface of the semiconductor substrate, wherein the first dummy pattern and the second dummy pattern are located below the semiconductor substrate.

[0079] According to some embodiments, a structure includes: a semiconductor substrate; a first through hole and a second through hole extending through the semiconductor substrate; a redistribution structure including a plurality of dielectric layers located above the semiconductor substrate; and a plurality of metal lines located in the plurality of dielectric layers; and a plurality of dummy patterns located in the plurality of dielectric layers, wherein, in a top view of the structure, the plurality of dummy patterns are located between the first through hole and the second through hole, wherein the pattern density of the plurality of dummy patterns increases from an area close to the first through hole or the second through hole to an intermediate area between the first through hole and the second through hole. In an embodiment, the intermediate area between the first through hole and the second through hole has the highest pattern density of the dummy patterns. In an embodiment, the pattern density of the plurality of dummy patterns is measured from a device area having a length and a width greater than about 50 μm.

[0080] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming an integrated circuit device on a semiconductor substrate; forming a first through hole penetrating the semiconductor substrate; and forming a dummy pattern around the first through hole, wherein the dummy pattern comprises: a first plurality of dummy patterns having a first pattern density; and a second plurality of dummy patterns, wherein the first plurality of dummy patterns are located between the first through hole and the second plurality of dummy patterns, and wherein the second plurality of dummy patterns have a second pattern density different from the first pattern density. In some embodiments, the dummy pattern further comprises a third plurality of dummy patterns, wherein the first plurality of dummy patterns and the second plurality of dummy patterns are located between the first through hole and the third plurality of dummy patterns, wherein the third plurality of dummy patterns have a third pattern density different from the first pattern density and the second pattern density. In some embodiments, the third pattern density is greater than the second pattern density, and the second pattern density is greater than the first pattern density. In some embodiments, forming the first through hole comprises: forming a first through hole extending into the semiconductor substrate; performing a backside grinding process to expose the first through hole from the back side of the semiconductor substrate; and forming a backside interconnect structure on the back side of the semiconductor substrate. In some embodiments, the method further comprises: forming an additional dummy pattern on the back side of the semiconductor substrate, wherein the additional dummy pattern has a lower pattern density in an area close to the first via and a higher pattern density in an area away from the first via. In some embodiments, each of the first pattern density and the second pattern density is measured in a chip area having a length and a width greater than about 50 μm. In some embodiments, the first via is formed by an intermediate via process and is formed after forming the integrated circuit device and before forming the dummy pattern. In some embodiments, the first via is formed by a post-via process and is formed after forming both the integrated circuit device and the dummy pattern. In some embodiments, the method further comprises: forming a second via when forming the first via, wherein the dummy pattern further comprises: a fourth plurality of dummy patterns having a fourth pattern density; a fifth plurality of dummy patterns having a fifth pattern density between the second via and the fourth plurality of dummy patterns; and a sixth plurality of dummy patterns having a sixth pattern density between the fifth plurality of dummy patterns and the second plurality of dummy patterns, wherein the fifth pattern density is greater than the fourth pattern density, and the sixth pattern density is greater than the fifth pattern density. In some embodiments, the dummy pattern is electrically floating. In some embodiments, the first plurality of dummy patterns have different shapes than the second plurality of dummy patterns. In some embodiments, the first plurality of dummy patterns have different pitches than the second plurality of dummy patterns.

[0081] Some other embodiments of the present application provide a semiconductor structure, comprising: a semiconductor substrate; a first interconnect structure covering the semiconductor substrate; a second interconnect structure located below the semiconductor substrate; a through hole penetrating the semiconductor substrate, wherein the through hole electrically connects a first metal pad in the first interconnect structure to a second metal pad in the second interconnect structure; a first dummy pad region surrounding the through hole, wherein the first dummy pad region includes a first dummy pattern having a first pattern density; and a second dummy pad region surrounding the first dummy pad region, wherein the second dummy pad region includes a second dummy pattern having a second pattern density different from the first pattern density. In some embodiments, the first dummy pad region has a substantially uniform pattern density of the first dummy pattern, and the second dummy pad region has a substantially uniform pattern density of the second dummy pattern. In some embodiments, the semiconductor structure further includes a third dummy pad region surrounding the second dummy pad region, wherein the third dummy pad region includes a third dummy pattern having a third pattern density different from the first pattern density and the second pattern density. In some embodiments, the semiconductor structure further includes an active device located at the top surface of the semiconductor substrate, wherein the first dummy pattern and the second dummy pattern are located above the semiconductor substrate. In some embodiments, the semiconductor structure further includes an active device located at a top surface of the semiconductor substrate, wherein the first dummy pattern and the second dummy pattern are located below the semiconductor substrate.

[0082] Some other embodiments of the present application provide a semiconductor structure, comprising: a semiconductor substrate; a first through hole and a second through hole, extending through the semiconductor substrate; a redistribution structure, comprising: a plurality of dielectric layers, located above the semiconductor substrate; and a plurality of metal lines, located in the plurality of dielectric layers; and a plurality of dummy patterns, located in the plurality of dielectric layers, wherein, in a top view of the structure, the plurality of dummy patterns are located between the first through hole and the second through hole, wherein the pattern density of the plurality of dummy patterns increases from an area close to the first through hole or the second through hole to an intermediate area between the first through hole and the second through hole. In some embodiments, the intermediate area between the first through hole and the second through hole has the highest pattern density of dummy patterns. In some embodiments, the pattern density of the plurality of dummy patterns is measured from a device area having a length and a width greater than about 50 μm.

[0083] The components of several embodiments are discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It should be understood by those skilled in the art that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. It should also be appreciated by those skilled in the art that these equivalent structures do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: forming an integrated circuit device on a semiconductor substrate; forming a first through hole penetrating the semiconductor substrate; as well as forming a dummy pattern surrounding the first through hole, wherein the dummy pattern comprises: a first plurality of dummy patterns having a first pattern density; and A second plurality of dummy patterns, wherein the first plurality of dummy patterns are located between the first through-holes and the second plurality of dummy patterns, and wherein the second plurality of dummy patterns have a second pattern density different from the first pattern density.

2. The method according to claim 1, wherein: The dummy patterns further include a third plurality of dummy patterns, wherein the first plurality of dummy patterns and the second plurality of dummy patterns are located between the first through-holes and the third plurality of dummy patterns, wherein the third plurality of dummy patterns have a third pattern density different from the first pattern density and the second pattern density.

3. The method according to claim 2, wherein: The third pattern density is greater than the second pattern density, and the second pattern density is greater than the first pattern density.

4. The method according to claim 1, wherein: Forming the first through hole includes: forming a first through hole extending into the semiconductor substrate; performing a backside grinding process to expose a first through hole from a backside of the semiconductor substrate; and A backside interconnect structure is formed on the backside of the semiconductor substrate.

5. The method according to claim 4, further comprising: An additional dummy pattern is formed on the back side of the semiconductor substrate, wherein the additional dummy pattern has a lower pattern density in a region close to the first through hole and has a higher pattern density in a region far from the first through hole.

6. The method according to claim 1, wherein: Each of the first pattern density and the second pattern density is measured in a chip area having a length and a width greater than about 50 μm.

7. The method according to claim 1, wherein: The first via is formed by an intermediate via process and is formed after forming the integrated circuit device and before forming the dummy pattern.

8. The method according to claim 1, wherein: The first via is formed by a via last process and is formed after both the integrated circuit device and the dummy pattern are formed.

9. A semiconductor structure comprising: Semiconductor substrate; a first interconnect structure covering the semiconductor substrate; a second interconnect structure located below the semiconductor substrate; a through hole extending through the semiconductor substrate, wherein the through hole electrically connects a first metal pad in the first interconnect structure to a second metal pad in the second interconnect structure; a first dummy pad region surrounding the through hole, wherein the first dummy pad region includes a first dummy pattern having a first pattern density; and A second dummy pad region surrounds the first dummy pad region, wherein the second dummy pad region includes a second dummy pattern having a second pattern density different from the first pattern density.

10. A semiconductor structure comprising: Semiconductor substrate; A first through hole and a second through hole penetrate the semiconductor substrate; Redistribution structure, including: a plurality of dielectric layers disposed above the semiconductor substrate; and a plurality of metal lines disposed in the plurality of dielectric layers; and A plurality of dummy patterns are located in the plurality of dielectric layers, wherein, in a top view of the structure, the plurality of dummy patterns are located between the first through hole and the second through hole, and wherein a pattern density of the plurality of dummy patterns increases from an area close to the first through hole or the second through hole to an intermediate area between the first through hole and the second through hole.

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