Power semiconductor module device and manufacturing method thereof

Abstract

The present application provides a power semiconductor module device (100) comprising: a substrate (10) arranged in a housing (7) or forming a ground surface of the housing (7), the housing (7) comprising a side wall; at least one semiconductor body (20) arranged on the substrate (10); a first layer (50) partially filling the housing (7) and completely covering the substrate (10) and the at least one semiconductor body (20) arranged on the substrate (10); and a second layer (52) arranged adjacent to the first layer (50), where the first layer (50) is a liquid or gel-like layer, the second layer (52) is a solid layer, the first layer (50) is arranged between the substrate (10) and the second layer (52), and the second layer (52) is arranged away from the top of the housing (7).

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor module arrangement and a method for producing such a power semiconductor module arrangement. Background Art

[0002] A power semiconductor module device generally includes at least one substrate. A semiconductor device including a plurality of controllable semiconductor elements (e.g., two or more IGBTs) is arranged on each substrate of at least one substrate. Each substrate generally includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted on, for example, the first metallization layer. Most power semiconductor module devices also include an encapsulant that at least partially fills the interior of the housing, thereby covering any components and electrical connections arranged on at least one substrate. The encapsulant is generally configured to electrically insulate regions with different electrical potentials within the housing and to protect the components and electrical connections of the power semiconductor module from certain environmental conditions and mechanical damage. During the use of the power semiconductor module device, heat may be generated. This is because the regulation of high current density generally produces a heating effect, such as Joule heating. In addition, at least some of the controllable semiconductor elements of the power semiconductor module device perform multiple switching operations during the operation of the power semiconductor module device. For example, when multiple switching operations are performed in a short period of time, the controllable semiconductor elements generate heat. The heat generated during operation of the power semiconductor module arrangement is mostly dissipated from the controllable semiconductor element to the substrate and further via the optional substrate to the heat sink. However, the encapsulant in direct contact with the controllable semiconductor element may also be heated and local hot spots may occur. Due to the heat, the material of the encapsulant may become brittle over time and the interface between the encapsulant and the semiconductor element or between the encapsulant and the substrate metallization may be damaged due to thermal degradation. This may lead to a degradation of the insulation properties of the encapsulant and thus to failure of the power semiconductor module arrangement.

[0003] There is a need for a power semiconductor module arrangement that reduces or even avoids the above-mentioned and other drawbacks, and a method that allows the fabrication of a power semiconductor module arrangement with improved performance and reliability. Summary of the invention

[0004] A power semiconductor module device comprises: a substrate, which is arranged in a shell or forms a ground surface of the shell, the shell comprising side walls and an optional top; at least one semiconductor body, which is arranged on the substrate; a first layer, which partially fills the shell and completely covers the substrate and the at least one semiconductor body arranged on the substrate; and a second layer, which is arranged adjacent to the first layer, wherein the first layer is a liquid or gel-like layer, the second layer is a gel-like or solid layer, the first layer is arranged between the substrate and the second layer, and the second layer is arranged away from the top of the shell.

[0005] A method comprises: filling a first material having a first density in a shell, wherein the shell comprises side walls and an optional top, and a substrate on which at least one semiconductor body is arranged is arranged in the shell or forms a ground surface of the shell; filling the shell with a second material having a second density, wherein the first density is higher than the second density, thereby forming a first liquid layer composed of the first material and a liquid or gel-like pre-layer composed of the second material; and performing a curing step to cure the second material and form a gel-like or solid second layer, wherein the first layer remains liquid or gel-like during and after the curing step; wherein the first layer partially fills the shell and completely covers the substrate and at least one semiconductor body arranged thereon, the first layer is formed between the substrate and the second layer due to its higher density, and the second layer is arranged away from the top of the shell.

[0006] The present invention may be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily drawn to scale, but are intended to illustrate the principles of the present invention. In addition, in the drawings, the same reference numerals represent corresponding components in different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional view of a power semiconductor module device.

[0008] Figure 2 is a cross-sectional view of a defective power semiconductor module arrangement.

[0009] Figure 3 A cross-sectional view of a power semiconductor module arrangement according to an embodiment of the present disclosure is schematically shown.

[0010] Figure 4 and Figure 5 A method for forming a power semiconductor module arrangement according to an embodiment of the present disclosure is schematically illustrated.

[0011] Figure 6 A cross-sectional view schematically shows another power semiconductor module arrangement according to an embodiment of the present disclosure.

[0012] Figures 7A-7CA method for forming a power semiconductor module arrangement according to a further embodiment of the description is schematically illustrated.

[0013] Figure 8 The chemical formula of the functionalized polydiorganosilicon used as the encapsulant in the module assembly is schematically shown. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings show specific examples in which the present invention can be practiced. It should be understood that the features and principles described for various examples can be combined with each other unless otherwise explicitly stated. In the specification and in the claims, certain elements are designated as "first element", "second element", "third element", etc., which should not be understood as enumerative. On the contrary, these designations are only used to refer to different "elements". That is, for example, the presence of a "third element" does not necessarily require the presence of a "first element" and a "second element". The wires or electrical connections described herein may be a single conductive element, or may include at least two individual conductive elements connected in series and / or in parallel. The wires and electrical connections may include metal and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). The semiconductor body described herein may be made of (doped) semiconductor material and may be a semiconductor chip or contained in a semiconductor chip. The semiconductor body has an electrically connectable pad and includes at least one semiconductor element with an electrode.

[0015] refer to Figure 1 , shows a cross-sectional view of a power semiconductor module device 100. The power semiconductor module device 100 includes a housing 7 and a substrate 10. The substrate 10 includes a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to the dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is arranged between the first metallization layer 111 and the second metallization layer 112.

[0016] Each of the first metallization layer 111 and the second metallization layer 112 may be composed of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The substrate 10 may be a ceramic substrate, that is, a substrate in which the dielectric insulating layer 11 is a ceramic (e.g., a thin ceramic layer). The ceramic may be composed of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. Alternatively, the dielectric insulating layer 11 may be composed of an organic compound and include one or more of the following materials: Al2O3, AlN, SiC, BeO, BN, or Si3N4. For example, the substrate 10 may be a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. In addition, the substrate 10 may be an insulated metal substrate (IMS). The insulated metal substrate typically includes a dielectric insulating layer 11, which includes (filling) material, such as epoxy resin or polyimide. The material of the dielectric insulating layer 11 can be filled with, for example, ceramic particles. Such particles can include, for example, SiO2, Al2O3, AlN, SiN or BN, and can have a diameter between about 1 μm and about 50 μm. The substrate 10 can also be a conventional printed circuit board (PCB) with a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 can be composed of or include a cured resin.

[0017] The substrate 10 is arranged in the housing 7. Figure 1 In the example shown, the substrate 10 is arranged on a base plate 64 forming the base surface of the housing 7, while the housing 7 itself only includes side walls and a top or lid. In some power semiconductor module devices 100, more than one substrate 10 is arranged on the same base plate 64 and in the same housing 7. The base plate 64 may include a layer of metal material, such as copper or AlSiC. However, other materials are also possible.

[0018] One or more semiconductor bodies 20 may be arranged on at least one substrate 10. Each semiconductor body 20 arranged on at least one substrate 10 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable semiconductor element.

[0019] One or more semiconductor bodies 20 may form a semiconductor device on the substrate 10. Figure 1 In FIG. 2 , only two semiconductor bodies 20 are shown by way of example. Figure 1The second metallization layer 112 of the substrate 10 in the embodiment is a continuous layer. According to another example, the second metallization layer 112 may be a structured layer. According to other examples, the second metallization layer 112 may be completely omitted. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. In this context, "structured layer" means that the corresponding metallization layer is not a continuous layer, but includes recesses between different parts of the layer. These recesses are Figure 1 Schematically shown in . The first metallization layer 111 in this example includes three different parts. Different semiconductor bodies 20 can be mounted to the same or different parts of the first metallization layer 111. Different parts of the first metallization layer 111 may not be electrically connected, or may be electrically connected to one or more other parts using electrical connections 3 (e.g., bonding wires). The semiconductor bodies 20 can be electrically connected to each other or to the first metallization layer 111 using, for example, electrical connections 3. Instead of bonding wires, the electrical connection 3 can also include, for example, bonding ribbons, connecting plates, or conductor tracks, just to name a few examples. One or more semiconductor bodies 20 can be electrically and mechanically connected to the substrate 10 via a conductive connection layer 60. Such a conductive connection layer 60 can be a solder layer, a conductive adhesive layer, or a sintered metal powder layer, such as sintered silver (Ag) powder. One or more substrates 10 can be mechanically and thermally connected to the base plate 64 via a connection layer 62. The connection layer 62 can be an electrically insulating adhesive layer, a solder layer, a conductive adhesive layer, or a sintered metal powder layer, such as sintered silver (Ag) powder.

[0020] Figure 1 The power semiconductor module device 100 shown in FIG. 1 further includes a terminal element 4. The terminal element 4 provides an electrical connection between the interior and the exterior of the housing 7. The terminal element 4 can be electrically connected to the first metallization layer 111 with a second end 42, while a first end 41 of the terminal element 4 protrudes out of the housing 7. The terminal element 4 can be electrically contacted from the outside at its first end 41.

[0021] Arranging the terminal element 4 in the center of the substrate 10 is only an example. According to other examples, the terminal element 4 can be arranged closer to or adjacent to the side wall of the housing 7. The terminal element 4 can also be inserted into the housing material by manual insertion or by injection molding into the housing 7. The second end 42 of the terminal element 4 can be connected by the conductive connecting layer ( Figure 1 The terminal element 4 is electrically and mechanically connected to the substrate 10 (not specifically shown). Such a conductive connection layer can be a solder layer, a conductive adhesive layer or a sintered metal powder layer, such as sintered silver (Ag) powder. Alternatively, the terminal element 4 can also be coupled to the substrate by ultrasonic welding.

[0022] The power semiconductor module device 100 also includes an encapsulant 5. The encapsulant 5 may be composed of or include a cured silicone gel, or may be a rigid molding compound. The encapsulant 5 may at least partially fill the interior of the housing 7, thereby covering the components and electrical connections arranged on the substrate 10. The terminal element 4 may be partially embedded in the encapsulant 5. However, at least its first end 41 is not covered by the encapsulant 5, and protrudes from the encapsulant 5 through the housing 7 to the outside of the housing 7. The encapsulant 5 is configured to electrically insulate regions with different electrical potentials (e.g., different portions of the first metallization layer 111) from each other, and to protect the components and electrical connections of the power semiconductor module 100, particularly the components arranged in the housing 7, from certain environmental conditions and mechanical damage. The silicone material used to form the encapsulant 5 can generally insulate up to 23.000 V / mm. Therefore, compared to, for example, air, the silicone material provides better insulation performance, and air can provide electrical insulation of up to about 3.000 V / mm.

[0023] During the use of the power semiconductor module device 100, the encapsulant 5 may be heated to a certain extent. This is because high current densities of up to 1000A are regulated and controlled in the housing (especially in areas with relatively high resistance), resulting in Joule heating. In addition, at least some of the semiconductor bodies 20 of the power semiconductor module device 100 typically perform multiple switching operations during the operation of the power semiconductor module device 100. When multiple switching operations are performed in a short period of time, or by controlling high current densities in a long period of time, for example, the semiconductor body 20 generates heat, which may rise to a temperature above a certain maximum threshold in the worst case. The heat generated during the use of the power semiconductor module device 100 is usually mostly dissipated from the semiconductor body 20 to the substrate 10, and further dissipated through the base plate 64 to, for example, a heat sink (not specifically shown). However, a certain amount of heat is always transferred to the encapsulant 5 that is in direct contact with the semiconductor body 20. The encapsulant 5 is typically a cured silicone layer or epoxy resin molding compound. When (repeatedly) exposed to heat over a long period of time (e.g., within the expected service life of the power semiconductor module device), the encapsulant 5 may thermally degrade and may become brittle. In some gel-like materials, the liquid components within the loose network may become mobile, thereby also causing short-term liquefaction of the encapsulant 5. That is, cracks or bubbles filled with air due to evaporation of water or partially liquefied encapsulant may form in the encapsulant 5, resulting in mechanical instability of the encapsulant 5. In addition, partial thermal degradation of the interface between the encapsulant 5 and the housing 7, between the encapsulant 5 and the semiconductor body 20, or between the encapsulant 5 and the substrate 10 may reduce adhesion, resulting in delamination. Due to these air-filled cracks, bubbles, and delamination, the encapsulant 5 may no longer be able to insulate different potentials in the region, or protect the components and electrical connections of the power semiconductor module 100 from environmental conditions and mechanical damage.

[0024] Figure 2Schematically, this process is shown in FIG for an encapsulant 5 comprising a cured silicone gel or a rigid molding compound. A local hot spot 500 may occur in an area of ​​the encapsulant 5 directly adjacent to the semiconductor body 20. Due to continued overheating in such a hot spot area 500, an area of ​​delaminated material 504 may begin to form in the interface of the encapsulant 5 with the semiconductor body 20, the substrate 10, or the bonding wire 3. The delaminated material may also be thermally degraded, resulting in unspecified and possibly corrosive degradation products 504. In addition, the thermal oxidative degradation of silicone causes the silicone to harden until the entire encapsulant 5 eventually becomes brittle and has low mechanical stability, and forms low-volatility degradation products when thermally degraded. Taken together, the loss of mechanical stability and the formation of degradation products lead to cracks, bubbles, and delamination inside the encapsulant 5 or at the interface with surrounding components. Typically, delaminated material 504 and bubbles 502 may also form in the material of the encapsulant 5 due to heat. Such bubbles 502 typically appear in an area (hot spot area 500) close to the semiconductor body 20. Since the encapsulant 5 is a cured silicone layer or a rigid molding compound, the air bubbles 502 and the degradation products 504 cannot move to other areas of the encapsulant 5 .

[0025] Reference now Figure 3 , schematically shows a power semiconductor module device 100 according to an embodiment of the present disclosure. The power semiconductor module device 100 generally corresponds to the above Figure 1 The power semiconductor module device 100 described above. Figure 3 In the example shown, the encapsulant comprises two layers, namely a first layer 50 and a second layer 52. The first layer 50 partially fills the housing 7 and completely covers the substrate 10 and the at least one semiconductor body 20 arranged thereon. The second layer 52 is arranged adjacent to the first layer 50, so that the first layer 50 is arranged between the second layer 52 and the substrate 10. The second layer 52 is arranged away from the top of the housing 7. That is, the area arranged between the first layer 50 and the top of the housing 7 is only partially filled with the material of the second layer 52, and a cavity 54 remains between the second layer 52 and the top of the housing 7. For example, the cavity 54 can be filled with air.

[0026] The first layer 50 is a liquid layer. In this way, the above-mentioned Figure 2 When the semiconductor body 20 heats up during use of the power semiconductor module arrangement 100, the material of the liquid first layer 50 will also heat up to a certain extent in the area directly adjacent to the semiconductor body 20. However, the liquid layer allows convection, such as Figure 3. That is, when the material of the first layer 50 is heated in the region near the semiconductor body 20, it rises and carries the heat from the semiconductor body 20 to the second layer 52. As the material rises, it cools again and sinks again toward the substrate 10. Therefore, any heat transferred from the semiconductor body 20 to the first layer 50 will not be concentrated in the region near the semiconductor body 20, so no or only insignificant local hot spots 500 will appear. Instead, the heat is distributed to other regions of the first layer 50. In addition, any bubbles 502 and degraded materials 504 will not accumulate in the region near the semiconductor body 20, but will be distributed throughout the first layer 50. In addition, the liquid itself will not be affected by the delamination area because it always tends to wet the surface of the semiconductor body 20 or substrate 11, and the bubbles or delaminations will be filled with liquid encapsulant.

[0027] Liquids expand to a certain extent when heated and contract when cooled again. This can be problematic in hermetically sealed enclosures, because pressure builds up inside the enclosure as the liquid layer expands. Figure 3 The power semiconductor module device 100 shown in includes a second layer 52 arranged above the first layer 50. The second layer 52 is a gel-like or solid layer (e.g., a cured (silicone) layer). However, the second layer 52 is flexible to a certain extent. That is, the second layer 52 can be configured to deform when the first layer 50 expands or contracts. The second layer 52 prevents the material of the first layer 50 from flowing out of the housing 7. That is, the second layer 52 seals the lower part of the housing 7 where the first layer 50 is arranged. The housing 7 may include an opening (not specifically shown) that is arranged to allow air to flow into the cavity 54 from the outside of the housing 7 or flow out of the cavity 54 to the outside of the housing 7. That is, as the first layer 50 expands, the second layer 52 can deform toward the top of the housing 7. Therefore, the volume of the cavity 54 can be reduced. In order to prevent pressure from accumulating inside the housing 7, since the housing 7 is not hermetically sealed, air can escape from the housing 7 through the opening or gap.

[0028] The first layer 50 may have a thickness d50, for example, between 4 mm and 20 mm (millimeters) in the vertical direction y. According to one example, the thickness d50 of the first layer 50 is between 5 mm and 18 mm, for example, the thickness d50 of the first layer 50 may be 15 mm. In this way, the amount of the first material is sufficient to effectively insulate the areas that generate the most heat in the operating mode (such as the areas adjacent to the semiconductor body 20 and the electrical connection 3) and to carry the heated material away from the semiconductor body 20. That is, the first layer 50 with a certain thickness d50 allows sufficient convection. The second layer 52 may have a thickness d52, for example, between 3 mm and 20 mm. According to one example, the thickness d52 of the second layer 52 may be between 5 mm and 7 mm, for example, the thickness d52 of the second layer 52 may be 6 mm. The second layer 52 with such a thickness d52 is strong enough to prevent leakage of the first material without breaking itself, while still being able to flexibly deform when the first layer 50 expands or contracts. If the second layer 52 is too thick, it may no longer be able to deform when the first layer 50 expands or contracts.

[0029] The first and second materials may both include (different) silicone materials. Typically, the silicone insulating encapsulant 5 can be formed by filling the module with liquid silicone and then undergoing a hardening (also referred to as curing) reaction in the process of forming a solid elastic network. They are usually composed of a base polymer such as polydimethylsiloxane (PDMS) or polymethylphenylsiloxane. In order to cure, these base polymers are usually attached to chemically reactive groups and combined with a chemically reactive networking agent in the final mixture. Then, the curing reaction can be started or accelerated by irradiating the material with ultraviolet light, heat, or activating or adding a certain catalyst. The platinum-catalyzed hydrosilation reaction of silane (Si-H) with vinyl represents the most common curing reaction in the assembly of power modules. The second layer 52 is composed of this material designated for curing. In contrast, the first layer is composed of a base polymer without a chemically reactive group or an additive designated for curing. For example, this can include a pure PDMS base polymer or polymethylphenylsiloxane. It also includes silicone derivatives in which other non-reactive chemical groups are attached to the base polymer, such as silicones with ethyl or partially fluorinated alkyl groups. The silicone of the first layer 50 may also contain additives, such as heat stabilizers or mineral fillers, as long as they do not accelerate or enable the curing reaction.

[0030] The second layer 52 may have certain adhesive properties and help to adhere to the side wall of the housing 7. In this way, it remains in place during the use of the power semiconductor module device 100 and can be sealed to prevent leakage of the first layer 50. According to an embodiment of the present disclosure, the housing 7 may include a protrusion 72 extending from the side wall of the housing 7 into the second layer 52. The protrusion 72 may be completely surrounded by the material of the second layer 52. In this way, the mechanical stability of the second layer 52 can be improved while the second layer 52 is still flexible. The additional protrusion increases the surface of the housing, thereby improving the adhesion of the second layer 52 through the extended adhesive surface. By extending from the side wall of the housing 7 into the second layer 52, the second layer 52 will be firmly held in its desired position. The protrusion 72 may be integrally formed with the housing 7, or may be attached to the housing 7 in any suitable manner. For example, the protrusion 72 may be glued to the housing 7. The protrusion 72 may have any suitable form. The protrusion 72 may extend in a horizontal direction, or may be inclined to a certain degree relative to the horizontal direction. The protrusion 72 expands the contact area between the housing 7 and the second layer 52. That is, the protrusions 72 provide a high bonding area. Figure 6 Schematically shown in FIG. 5 is a shell 7 including a protrusion 72 extending into the second layer 52. The shell 7 may include a single protrusion 72, such as a protrusion extending circumferentially along the side wall of the shell 7. However, the shell 7 may also include one or more separate protrusions 72 located at different positions along the side wall of the shell 7.

[0031] Reference now Figure 4 and Figure 5 , schematically illustrates a method for forming a power semiconductor module device 100 according to an embodiment of the present disclosure. The method includes filling a first material having a first density in a housing 7, wherein the housing 7 includes side walls and an optional top. A substrate 10 on which at least one semiconductor body 20 is arranged is arranged in the housing 7 or forms a grounding surface of the housing 7. The method also includes filling the housing 7 with a second material having a second density, wherein the first density is higher than the second density, thereby forming a first liquid or gel-like layer 50 composed of the first material and a liquid or gel-like pre-layer 56 composed of the second material. According to an example, the density ρ1 of the first material is greater than 0.98 g / cm 3 (ρ1>0.98g / cm 3 ), and the density ρ2 of the second material is less than 0.98 g / cm 3 (ρ2<0.98g / cm 3 ). The difference between the first density ρ1 and the second density ρ2 can be large enough to ensure that the first and second materials are completely separated to form two separate layers. For example, the difference between the first density ρ1 and the second density ρ2 can be at least 0.005 g / cm 3 , or at least 0.1g / cm 3 .

[0032] The density of the materials used for the first layer 50 and the second layer 52 may be affected by the use of different base polymers and fillers or co-solvents that increase or decrease the density. According to an embodiment, the following material combinations may be used to obtain two materials with sufficiently different densities. The first and second materials may both include a silicone encapsulant. Pure silicone encapsulants are typically composed of base polymers in an amount of >99 vol%. Silicones may also include fillers in an amount of >80 vol%. Silicone encapsulants may include base polymers containing methyl, phenyl, vinyl, hydride, and partially fluorinated alkyl side groups, such as Figure 8 The average chain length of the polymer n is variable, and low molecular weight silicones with an average molecular weight of 200 g / mol and long chain silicone polymers with an average molecular weight of 500.000 g / mol and above are commercially available. The density of the silicone base polymer depends on the substitution pattern and the chain length. For example, short chain vinylated polymethylsiloxane (PDMS) shows a density of 0.90 g / cm 3 Increasing the molecular weight of polymethylsiloxane also results in an increase in density to 0.98 g / cm 3 The partial substitution of methyl groups with phenyl groups results in a base silicone polymer with a density between 0.95 g / cm 3 and 1.11 g / cm 3 Fluorination of the organic substituents allows the density of the silicone base polymer to be further increased to 1.22 g / cm 3 . In addition to these typical properties of silicone encapsulant materials, the branching of the silicone polymer also affects the density. Silicone base polymers can also be copolymerized. For example, copolymerization with polyacrylates produces UV-curable silicone encapsulants. The density of copolymers is typically between the densities of the pure polymers. The given densities of typical silicone base polymers are only examples, and there may be more variations of substitution patterns for higher or lower densities. All given densities are typical values ​​at room temperature. If elevated temperatures are applied, the density may decrease.

[0033] According to another embodiment of the present disclosure, the first material may include or consist of a first base polymer mixed with a filler, and the second material may include or consist of a second base polymer. The filler increases the density of the first base polymer to the desired first density ρ1 of the final silicone encapsulant mixture. In general, the density of the final silicone encapsulant mixture material can be increased by adding a filler (e.g., SiO2, TiO2, Cu, or CaCO3) having a density higher than that of the silicone base polymer.

[0034] According to an embodiment of the present disclosure, the silicone base polymer can be combined with a density of less than 0.90 g / cm 3Solvents (e.g., with a density of 0.79 g / cm 3 The first and second materials may be mixed with isopropyl alcohol (isopropyl alcohol) to affect the density of the first and second materials. According to one example, the pre-layer 56 may include between 10 vol% and 30 vol% isopropyl alcohol, such as 20 vol% isopropyl alcohol. However, the isopropyl alcohol typically evaporates during the curing step and is no longer present in the cured second layer 52, because the boiling point of isopropyl alcohol is only 82°C.

[0035] According to an embodiment of the present disclosure, a first layer 50 having a first density ρ1 and a second layer 52 having a second, lower density ρ2 are formed inside the shell. The densities of the first layer 50 and the second layer 52 can be selected by their silicone base polymer chain lengths, the substitution pattern of each silicone base polymer, and the amount and density of fillers, or by mixing the silicone base polymer with a low-density solvent. Each combination of these effects can be used to build the two layers within the module. It includes but is not limited to: 1. The first layer 50 includes a first silicone base polymer having a high average molecular weight and therefore a high density ρ1, and the second layer 52 includes the same silicone base polymer substitution but with a lower average molecular weight and a lower density ρ2. 2. The first layer 50 includes a first silicone base polymer with a variable average molecular weight and a specific density ρ1, and the second layer 52 includes different silicone base polymers with a variable average molecular weight and a density ρ2, wherein the density ρ1 is higher than the density ρ2. 3. The first layer 50 includes a first silicone base polymer with a variable substitution pattern and a variable average molecular weight and has High-density filler, and the mixture has a defined density ρ1, and the second layer 52 includes a second silicone base polymer with a variable substitution pattern and a variable average molecular weight and no filler, and has a defined density ρ2, wherein the density ρ1 is higher than the density ρ2. 4. The first layer 50 includes a first silicone base polymer with a variable substitution pattern and a variable average molecular weight, which has a defined density ρ1, and the second layer 52 includes a second silicone base polymer with a variable substitution pattern and a variable average molecular weight, which is mixed with a low-density volatile solvent, and the mixture has a defined density ρ2, wherein the density ρ1 is higher than the density ρ2. The embodiments are also not limited to silicone base polymers, and are also applicable to non-silicone polymers, such as epoxy molding compounds. Therefore, the first layer 50 with a defined density ρ1 or the second layer 52 with a defined density ρ2 can be exchanged with a polymer solution or liquid epoxy molding compound having a density ρ1 higher than the density ρ2.

[0036] The method further comprises performing a curing step, thereby curing the second material and forming a solid or gel-like second layer 52, wherein the first layer 50 remains liquid during and after the curing step. The first layer 50 partially fills the housing 7 and completely covers the substrate 10 and the at least one semiconductor body 20 arranged thereon. The first layer 50 is formed between the substrate 10 and the liquid or gel-like pre-layer 56 due to its higher density. The second layer 52 is arranged away from the top of the housing 7.

[0037] The first material and the second material can be filled into the housing 7 simultaneously or successively. The first material and the second material will not mix when they are filled into the housing 7. Due to the different densities, the first material will fall and form a first layer 50 adjacent to the substrate 10, while the second material rises and forms a liquid or gel-like pre-layer 56 on top of the first layer 50. This effect occurs automatically without any further support measures. In order to ensure the separation of the two miscible phases, the material of the first layer and / or the second layer can have a certain viscosity to reduce diffusion and convection during the filling process and storage time to subsequent curing and fixing steps. The viscosity of the first layer and / or the second layer can be at least 450mPa·s or 2000mPa·s to limit convection or diffusion to a local interface area of ​​1mm for 5 minutes or 10 minutes, etc. This can also include encapsulant materials with lower viscosity, which require a more accurate dispensing process and a fast curing / fixing step. A single curing step can then be performed. For example, the curing step can include heating the power semiconductor module device 100 and / or irradiating the power semiconductor module device 100 with ultraviolet light. A certain amount of pressure may also be applied during the curing step.

[0038] After curing, the second layer 52 adheres to the sidewalls of the housing 7. As described above, this adhesion may be sufficient to hold the second layer 52 in a desired position above the first layer 50. If the housing 7 includes protrusions 72 (see, e.g. Figure 6 ), the adhesion can be significantly improved. Therefore, the second layer 52 seals the area of ​​the housing 7 in which the first layer 50 is arranged and prevents the first material from leaking.

[0039] exist Figure 4 and Figure 5 In FIG. 1 , all layers are schematically shown as flat layers. However, Figure 4 and Figure 5 It is intended only to describe the basic principles in general terms. Fig. 7A , schematically shows a power semiconductor module device 100 before performing a curing step. As described above, the power semiconductor module device 100 may be heated during the curing step. For example, the power semiconductor module device 100 may be heated to a temperature of up to 150° C. When exposed to heat, the first layer 50 expands to a certain extent. This Figure 7B. When the power semiconductor module device 100 is subsequently cooled again, for example to room temperature (e.g., 25° C.), the first layer 50 shrinks. The second layer 52 hardened during the curing step can deform when the power semiconductor module device 100 cools. That is, the second layer 52 can deform at room temperature, which is Figure 7C Schematically shown in FIG. When the first layer 50 heats up and expands during operation of the power semiconductor module device 100, the deformation can be reduced. This expansion of the flexible solid or gel-like second layer 52 allows the first liquid layer 50 to thermally expand during operation of the module. Compared to a hermetically sealed housing, the expansion of the flexible second layer 52 can prevent the formation of high pressure inside the module, which would normally shorten the module service life.

[0040] The method described requires only a few steps to be performed and is therefore very cost-effective, since it can be implemented quickly and easily. The resulting power semiconductor module arrangement avoids the formation of hot spots near the semiconductor body 20. The first layer 50 does not become brittle during the service life of the power semiconductor module arrangement. In this way, the service life of the power semiconductor module arrangement can be significantly increased.

Claims

1. A power semiconductor module device (100), comprising: a substrate (10) arranged in a housing (7) or forming a ground surface of the housing (7), the housing (7) comprising a side wall; at least one semiconductor body (20) arranged on the substrate (10); a first layer (50) which partially fills the housing (7) and completely covers the substrate (10) and the at least one semiconductor body (20) arranged on the substrate (10); and a second layer (52) disposed adjacent to said first layer (50), wherein The first layer (50) is a liquid or gel-like layer, The second layer (52) is a solid or gel-like layer, The first layer (50) is arranged between the substrate (10) and the second layer (52), and The second layer (52) is arranged away from the top of the housing (7).

2. The power semiconductor module device according to claim 1, wherein: The second layer (52) is configured to deform when the first layer (50) expands or contracts during operation of the power semiconductor module device (100).

3. The power semiconductor module device according to claim 2, wherein: A cavity (54) inside the shell (7) between the second layer (52) and the top of the shell (7) is filled with air, and the shell (7) includes an opening arranged to allow air to flow between the cavity (54) and the outside of the shell (7).

4. The power semiconductor module device according to any one of claims 1 to 3, wherein: The first layer (50) and the second layer (52) both include silicone material.

5. The power semiconductor module device according to claim 4, wherein: The second layer (52) is a cured silicone layer.

6. The power semiconductor module device according to claim 4 or 5, wherein: The first layer (50) also includes a defined amount of a thermal stabilizer.

7. The power semiconductor module arrangement according to any one of the preceding claims, wherein: The housing (7) comprises one or more protrusions (72) attached to one or more side walls of the housing (7) and extending from the corresponding side wall to the second layer (52).

8. A method comprising: A first material having a first density (ρ1) is filled in a housing (7), wherein the housing (7) comprises side walls and a substrate (10) on which at least one semiconductor body (20) is arranged is arranged in the housing (7) or forms a ground surface of the housing (7), A second material having a second density (ρ2) is filled in the housing (7), wherein the first density (ρ1) is higher than the second density (ρ2), thereby forming a first liquid layer (50) composed of the first material and a liquid or gel-like pre-layer (56) composed of the second material, and performing a curing step, thereby curing the second material and forming a second layer (52) in a solid or gel state, wherein the first layer (50) remains liquid during and after the curing step, wherein The first layer (50) partially fills the housing (7) and completely covers the substrate (10) and the at least one semiconductor body (20) arranged on the substrate (10), The first layer (50) is formed between the substrate (10) and the second layer (52) due to its higher density (ρ1), and The second layer (52) is arranged away from the top of the housing (7).

9. The method according to claim 8, wherein Filling the shell (7) with the first material having the first density (ρ1) comprises filling the shell (7) with a first silicone material, and Filling the shell (7) with the second material having the second density (ρ2) includes filling the shell (7) with a second silicone material.

10. The method according to claim 8 or 9, wherein: Filling the second material in the shell (7) includes filling the second material including at least one of a networking agent, a catalyst, and an adhesion promoter in the shell (7).

11. The method according to any one of claims 8 to 10, wherein: Filling the first material in the shell (7) includes filling the first material including a defined amount of a thermal stabilizer in the shell (7).

12. The method according to any one of claims 8 to 11, wherein: The step of filling the first material in the shell (7) and the step of filling the second material in the shell (7) are performed sequentially.

13. The method according to any one of claims 8 to 12, wherein: The curing step includes at least one of the following: heating the liquid or gel-like pre-layer (56), and The liquid or gel-like pre-layer (56) is irradiated with ultraviolet light.

14. The method according to any one of claims 8 to 13, wherein: The first material has a first viscosity and the second material has a second viscosity, and wherein the first viscosity and / or the second viscosity is greater than a defined viscosity to minimize convection and diffusion at the interface between the liquid first layer (50) and the liquid or gel-like pre-layer (56).

15. The method according to claim 8, wherein: The first material has a first viscosity of at least 450 mPa·s or at least 2000 mPa·s, and / or the second material has a second viscosity of at least 450 mPa·s or at least 2000 mPa·s.

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