Semiconductor structure and forming method thereof

Abstract

The method includes bonding a bottom die to a carrier; and bonding the top die to the bottom die. The top die includes a semiconductor substrate, and the semiconductor substrate has a first thermal conductivity. The method further includes sealing the top die in the gap fill region; bonding a support substrate to the top die and the gap-fill region to form a reconstituted wafer, where the support substrate has a second thermal conductivity higher than the first thermal conductivity; stripping the reconstructed wafer from the carrier; and forming an electrical connection on the bottom die. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Integrated circuit packages may have multiple package components (such as device dies) and package substrates bonded together to increase functionality and integration levels. Warping may occur due to differences between different materials of multiple package components. Warping may cause non-bonding problems, and some conductive components intended to bond to each other are not bonded, resulting in circuit failure. In addition, heat dissipation also becomes a more serious problem. These problems need to be solved. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: bonding a bottom die to a carrier; bonding a top die to the bottom die, wherein the top die includes a semiconductor substrate and the semiconductor substrate has a first thermal conductivity; sealing the top die in a first gap-filling region; bonding a supporting substrate to the top die and the first gap-filling region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity; peeling the reconstructed wafer from the carrier; and forming electrical connectors on the bottom die.

[0004] Other embodiments of the present application provide a semiconductor structure, comprising: a bottom die; a top die located above the bottom die and bonded to the bottom die, wherein the top die comprises a semiconductor substrate having a first thermal conductivity; a first gap-filling region sealing the top die; a supporting substrate bonded to the top die, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity; a bonding film located between the supporting substrate and the top die; and an electrical connector located on the front side of the bottom die.

[0005] Still other embodiments of the present application provide a semiconductor structure, comprising: a top die comprising a semiconductor substrate, wherein the semiconductor substrate has a first Young's modulus; a gap-filling region, sealing the top die therein; a supporting substrate, located above the top die and bonded to the top die, wherein the supporting substrate has a second Young's modulus higher than the first Young's modulus; a thermal interface material, located above the supporting substrate and contacting the supporting substrate; and a heat sink, located above the thermal interface material and attached to the thermal interface material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1 to 12 A diagram illustrating a process for forming a package with a support substrate having improved heat dissipation capabilities in accordance with some embodiments.

[0008] Figures 13 to 16 A heat sink is shown attached to a package with a supporting substrate in accordance with some embodiments.

[0009] Fig.17 A top view of a package is shown in accordance with some embodiments.

[0010] Fig.18 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] A method and resulting structure for forming a package having a support substrate (with improved heat dissipation capabilities) are provided. According to some embodiments, the support substrate is bonded above the device die and is used to provide mechanical support in the formation of the package. The heat generated by the device die can be effectively dissipated by the support substrate. Due to the characteristics of the dummy die and the support substrate, the stress and warping in the resulting package can also be reduced. The embodiments discussed herein are intended to provide examples of the subject matter of the embodiments of the present disclosure that can be manufactured or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of consideration of different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0014] Figures 1 to 12 1 shows a cross-sectional view of an intermediate stage in the formation of a package according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.18 In the process flow shown in .

[0015] Figure 1 2 shows a cross-sectional view of the formation of the package assembly 20. The corresponding process is shown as follows Fig.18 202 in the process flow 200 shown in . According to some embodiments, the package assembly 20 is a device wafer including a device die 20'. The device die 20' may include active devices and possible passive devices, represented as integrated circuit devices 24. According to alternative embodiments, the package assembly 20 is an interposer die, which has no active devices and may or may not include passive devices. According to yet other alternative embodiments, the package assembly 20 is or includes a package such as an integrated fan-out (InFO) package, a redistribution structure including redistribution lines, and the like.

[0016] According to some embodiments, the package assembly 20 includes a semiconductor substrate 22 and a component formed at a top surface of the semiconductor substrate 22. The semiconductor substrate 22 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, etc. The semiconductor substrate 22 may also be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate.

[0017] According to some embodiments, package assembly 20 includes an integrated circuit device formed at the top surface of the semiconductor substrate. According to some embodiments, the integrated circuit device may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit device are not shown herein.

[0018] According to some embodiments, the package assembly 20 includes through-vias (also referred to as through-silicon vias (TSVs)) 26. The TSVs 26 may be electrically connected to the integrated circuit device 24. According to some embodiments, the TSVs 26 extend from a top surface of the semiconductor substrate 22 (or a level higher than the top surface of the semiconductor substrate 22) to a middle level of the semiconductor substrate 22. The middle level of the semiconductor substrate 22 is located between the top surface and the bottom surface of the semiconductor substrate 22. Each of the TSVs 26 is surrounded by a dielectric isolation layer (not shown) for electrically insulating the corresponding TSV 26 from the semiconductor substrate 22.

[0019] An interconnect structure 32 is formed over the semiconductor substrate 22 and the integrated circuit device 24. The interconnect structure 32 may include an interlayer dielectric (ILD, not separately labeled) that fills the spaces between the gate stacks (not shown) of the transistors in the integrated circuit device 24. According to some embodiments, the ILD is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present disclosure, the ILD may also be formed using deposition methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0020] Contact plugs (not shown) are formed in the ILD for electrically connecting the integrated circuit device 24 to the metal lines and vias above. According to some embodiments of the present disclosure, the contact plugs are formed of or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of the contact plugs may include: forming a contact opening in the ILD; filling the conductive material into the contact opening; and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of the contact plug flush with the top surface of the ILD.

[0021] According to some embodiments, interconnect structure 32 further includes a plurality of dielectric layers 34 and a plurality of conductive features, such as metal lines / pads 36 and vias 38 in dielectric layers 34. According to some embodiments, dielectric layers 34 may include low-k dielectric layers (also referred to as intermetallic dielectrics (IMDs)). For example, the dielectric constant (k value) of the low-k dielectric layers may be lower than about 3.5 or 3.0. The low-k dielectric layers may include carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.

[0022] The formation of metal lines 36 and vias 38 in dielectric layer 34 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or vias, a trench or via opening is first formed in one of dielectric layers 34, and then the trench or via opening is filled with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portion of the conductive material above the top surface of the dielectric layer, leaving a metal line or via in the corresponding trench or via opening. In a dual damascene process, trenches and via openings are both formed in the dielectric layer, wherein the via opening is located below the trench and connected to the trench. Conductive material is then filled into the trench and via opening to form metal lines and vias, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0023] Metal lines 36 include top conductive (metal) features, such as metal lines, metal pads, or vias in a top dielectric layer (denoted as dielectric layer 34T), which is the top layer of dielectric layer 34. According to some embodiments, top dielectric layer 34T is formed of a low-k dielectric material similar to the material of lower dielectric layer 34. According to some embodiments, top dielectric layer 34T is formed of a non-low-k dielectric material, such as silicon oxide, silicon nitride, undoped silicate glass, etc. The top metal features in the top dielectric layer may also be formed of copper or copper alloys, and may have a dual damascene structure or a single damascene structure.

[0024] Interconnect structure 32 may also include a passivation layer (not shown) that is located above and may contact underlying dielectric layer 34 (such as top dielectric layer 34T). The passivation layer may be formed of a non-low-k dielectric material that may include silicon and another element including oxygen, nitrogen, carbon, etc. For example, the passivation layer may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, etc.

[0025] A bonding layer 42 is formed over the redistribution structure 32. The bonding layer 42 may be formed of a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof. The bonding layer 42 is planarized using a chemical mechanical polishing (CMP) process or a mechanical grinding process so that its top surface is coplanar.

[0026] A probing process may be performed, wherein defective dies are found. A probing process may be performed on the top conductive feature 36. A singulation process is then performed to saw the package assembly 20 into a plurality of device dies 20'. Known good dies of the device dies 20' are used in subsequent processes.

[0027] According to an optional embodiment, instead of sawing the packaging assembly 20 into device dies 20' and packaging the discrete device dies 20' at the die level, a subsequent packaging process can be performed with the packaging assembly 20 packaged at the wafer level, and wafer-on-wafer bonding is performed to bond the device dies 20' to the wafer-level packaging assembly 20.

[0028] refer to Figure 2 , the front side of the device die 20 ′ (hereinafter also referred to as the bottom die) is attached to the carrier 48. The corresponding process is shown as follows Fig.18 204 in the process flow 200 shown in . It should be understood that although one device die 20' is shown, there are multiple device dies 20' attached, and the multiple device dies 20' can be arranged in an array. According to some embodiments, carrier 48 is a semiconductor carrier, such as a silicon carrier, and layer 50 is a bonding layer. Layer 50 can also be formed of a silicon-containing dielectric material selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. According to some embodiments, device die 20' is attached to carrier 48, wherein bonding layer 42 is bonded to layer 50 by fusion bonding.

[0029] According to an alternative embodiment, carrier 48 includes a transparent substrate such as a glass substrate, and layer 50 may be formed of a binder such as a light-to-heat conversion (LTHC) material configured to decompose under the heat of light such as a laser beam.

[0030] Next, if Figure 3 As shown in , a gap filling process is performed to fill the gaps between adjacent device dies 20' and seal the device dies 20' in a gap filling layer 52 (also referred to as a sealant). The corresponding process is shown as Fig.18 . According to some embodiments, the gap fill layer 52 includes a dielectric liner and a dielectric gap fill layer above the dielectric liner. The dielectric liner and the dielectric gap fill layer are not shown separately. The dielectric liner can be formed of a material that has good adhesion to the device die 20'. According to some embodiments, the dielectric liner is formed of or includes silicon nitride. The dielectric liner is formed in a conformal deposition process and is therefore a conformal layer. The dielectric gap fill layer can be formed of an oxide-based dielectric material, such as silicon oxide, silicon oxynitride, silicate glass, etc. The dielectric liner and the dielectric gap fill layer can be formed by a deposition process.

[0031] According to alternative embodiments, the gap-fill layer 52 is formed of or includes a molding compound, a molded underfill, etc. A corresponding process may include: dispensing a dielectric material in a flowable form; and curing the dielectric material.

[0032] refer to Figure 4 After the gap filling layer 52 is deposited, a planarization process is performed to make the top surface of the device die 20' flush with the top surface of the gap filling layer 52. The corresponding process is shown as follows Fig.18 The remaining portion of gap-fill layer 52 is hereinafter referred to as gap-fill region 52. According to some embodiments, a planarization process is performed until TSV 26 is exposed.

[0033] The semiconductor substrate 22 in the device die 20' may be recessed so that the top portion of the TSV 26 protrudes above the semiconductor substrate 22. At the same time, the gap fill region 52 may or may not be recessed. The dielectric isolation layer 54 may then be filled into the recess, such as Figure 5 The formation of the isolation layer 54 may include performing a deposition process to deposit a dielectric layer into the recess such that the protruding portion of the TSV 26 is located in the dielectric layer, followed by a planarization process. The corresponding process is shown as Fig.18 Process 210 in process flow 200 is shown in FIG. The portion of the dielectric layer located above TSV 26 is removed, and the remaining portion of the dielectric layer forms dielectric isolation layer 54, which becomes part of device die 20'.

[0034] refer to Figure 6 , a bonding layer 56 is deposited over the device die 20' and the gap-filling region 52. The corresponding process is shown as follows Fig.18 The process 212 in the process flow 200 is shown in FIG. The bonding layer 56 may be formed of a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof.

[0035] refer to Figure 7 , a bonding pad 58 is formed in the bonding layer 56. The corresponding process is shown as follows Fig.18 214 in the process flow 200 shown in . According to some embodiments, the bonding pads 58 are formed by: etching the bonding layer 56 to expose the through hole 26; filling the conductive layer into the resulting opening; and performing a planarization process such as a CMP process or a mechanical polishing process. Therefore, the top surfaces of the bonding pads 58 and the bonding layer 56 are coplanar with each other. The bonding pads 58 may include a material selected from copper, titanium, titanium nitride, tantalum, tantalum nitride, etc. For example, each bonding pad 58 may include a titanium nitride barrier layer and a copper region on the titanium nitride barrier layer.

[0036] refer to Figure 8 , device die 60 (also referred to as top die) is bonded to device die 20'. The corresponding process is shown as Fig.18216 in the process flow 200 shown in . Although one device die 60 is shown, the device die 60 shown represents a plurality of device dies 60, each of which is located above and bonded to one of the underlying device dies 20'. The bonding may be performed by a face-to-back bonding process, in which the front side of the device die 60 is bonded to the back side of the device die 20'. According to some embodiments, each of the device dies 60 may be a logic die, which may be a central processing unit (CPU) die, a microcontroller (MCU) die, an input-output (IO) die, a baseband die, etc. The device die 60 may also include a memory die.

[0037] Device die 60 may include a semiconductor substrate 62, which may be a silicon substrate. Device die 60 includes an interconnect structure 70 for connecting to active and passive devices in device die 60. Interconnect structure 70 includes metal lines and vias, as schematically shown.

[0038] Each of the device dies 60 includes a bonding pad 66 and a bonding layer 68 (also referred to as a bonding film) located at the bottom surface of the device die 60. The bottom surface of the bonding pad 66 can be coplanar with the bottom surface of the bonding layer 68. According to some embodiments, the bonding layer 68 can be formed of a silicon-containing dielectric material, which can be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. The bonding pad 66 may include copper and may be formed by a damascene process. The bonding layer 68 and the bonding pad 66 are planarized so that their surfaces are coplanar, which may be caused by CMP in the formation of the bonding pad 66.

[0039] The bonding may be achieved by hybrid bonding. For example, the bonding pad 66 is bonded to the bonding pad 58 by metal-to-metal direct bonding. According to some embodiments, the metal-to-metal direct bonding is copper-to-copper direct bonding. In addition, the bonding layer 68 of the device die 60 is bonded to the bonding layer 56 of the underlying device die 20' by fusion bonding, for example, where Si-O-Si bonds are generated. Figure 8 The structure shown in FIG. 1 is hereinafter referred to as a reconstructed wafer 100 , and more components will be formed to further expand the reconstructed wafer 100 in subsequent processes.

[0040] According to some embodiments, Figure 8As shown in , multiple dummy dies 74 are also attached to the underlying structure. According to some embodiments, each of the dummy dies 74 is attached by a layer 76. Layer 76 can be a bonding layer including a silicon-containing dielectric material, which can be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. Attachment can be performed by fusion bonding by bonding the bonding layer 76 to the bonding layer 56. According to these embodiments, the same annealing process can be used to bond the dummy dies 74 and the device die 60 to the underlying structure.

[0041] According to alternative embodiments, dummy die 74 is attached to underlying bonding layer 56 by an adhesive, also represented by layer 76. According to these embodiments, dummy die 74 may be attached to the underlying structure after device die 60 is bonded.

[0042] According to some embodiments, the entire dummy die 74 is formed of a homogeneous material, with no other materials and structures therein. The dummy die 74 may have a thermal conductivity value that is higher than the thermal conductivity of silicon and higher than the thermal conductivity of the semiconductor substrate 62 (which may also be formed of silicon). For example, the thermal conductivity of silicon may be about 150 watts / mk, and thus the thermal conductivity of the dummy die 74 is higher than 150 watts / mk, and may be in a range between about 160 watts / mk and about 500 watts / mk, or higher. Therefore, the resulting package (in which the dummy die 74 has a thermal conductivity value higher than the thermal conductivity of silicon) has better heat dissipation capabilities than a structure using silicon as the dummy die.

[0043] The dummy die 74 may be formed of a dielectric material, a semiconductor material, a conductive material (such as a metal), etc. For example, the dummy die 74 may be formed of or include SiC (wherein the thermal conductivity is about 160 W / mK), AlN (wherein the thermal conductivity is about 180 W / mK), Ag (wherein the thermal conductivity is about 429 W / mK), etc., while other materials such as Al, BeO, Cu, Au, SiCN, etc. may also be used.

[0044] Because the main function of the dummy die 74 is to fill and reduce the volume of the gap fill area, the Young's modulus of the dummy die 74 can be higher, equal to, or lower than the Young's modulus of silicon, and higher, equal to, or lower than the Young's modulus of the semiconductor substrate 62. For example, the Young's modulus of silicon (and the semiconductor substrate 62) can be in the range between about 130 GPa and about 190 GPa. Therefore, the Young's modulus of the dummy die 74 can be less than about 150 GPa, or higher than about 150 GPa, such as in the range between about 150 GPa and about 500 GPa. For example, the Young's modulus of AlN (which can be used to form the dummy die 74) is about 300 GPa.

[0045] According to some embodiments where dummy die 74 can be directly bonded to bonding layer 56, dummy die 74 (which is homogenous) is directly bonded to and in physical contact with bonding layer 56. For example, when dummy die 74 is formed of SiC, SiCN, etc., dummy die 74 can be in physical contact with bonding layer 56 without layer 76 therebetween. A fusion bond including Si-O-Si bonds can be generated to bond dummy die 74 to bonding layer 56.

[0046] refer to Fig. 9 , forming a gap filling region 80 (also referred to as a sealant). The corresponding process is shown as follows Fig.18 218 in the process flow 200 shown in FIG. The formation process, structure, and material of the gap fill region 80 can be selected from the candidate formation process, candidate structure, and candidate material of the gap fill region 52. For example, the gap fill region 80 can include a dielectric liner and a dielectric gap fill layer above the dielectric liner. Alternatively, the gap fill region 80 can include a molding compound, a molded underfill, etc. A planarization process is performed to make the top surfaces of the semiconductor substrate 62 of the device die 60, the dummy die 74, and the gap fill region 80 flush.

[0047] Further references Fig. 9 , a bonding layer 84 is deposited on the semiconductor substrate 62 of the device die 60, the dummy die 74 and the gap-filling region 80. The corresponding process is shown as follows Fig.18 The process 220 in the process flow 200 shown in FIG. The bonding layer 84 may also be formed of or include a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. Then, a planarization process may be performed to make the top surface of the bonding layer 84 flush.

[0048] In subsequent processes, such as Fig.10 As shown in FIG. 1 , a support substrate 88 is bonded to a reconstructed wafer 100. The corresponding process is shown as follows. Fig.18 A bonding layer 86 may also be formed on the support substrate 88, wherein the bonding layer 86 is formed of a silicon-containing dielectric material selected from the same candidate material group as the bonding layer 86. The materials of the bonding layers 84 and 86 may be the same as or different from each other.

[0049] According to some embodiments, the entire support substrate 88 is formed of a homogeneous material, without other materials and structures. The material of the support substrate 88 may have a thermal conductivity value that is higher than the thermal conductivity of silicon and higher than the thermal conductivity of the semiconductor substrate 62. For example, the thermal conductivity of the support substrate 88 may be higher than 150 watts / mk. Therefore, the resulting package (in which the support substrate 88 has a thermal conductivity higher than the thermal conductivity of silicon) has a better heat dissipation capability than a structure using silicon as a support substrate. According to some embodiments, the thermal conductivity of the support substrate 88 may be higher than about 160 watts / mk, and may be in a range between about 160 watts / mk and about 500 watts / mk, or higher.

[0050] The support substrate 88 may be formed of a dielectric material, a semiconductor material, a conductive material such as a metal, etc. For example, the support substrate 88 may be formed of or include SiC, AlN, Al, BeO, Cu, Au, Ag, SiCN, etc. Other materials may also be used.

[0051] In accordance with some embodiments, for example, when dummy die 74 is formed of a silicon-containing dielectric material such as SiC, SiCN, etc., bonding layer 84 may be skipped and dummy die 74 is directly bonded to and in physical contact with supporting substrate 88 or bonding layer 86 .

[0052] According to some embodiments, for example, when the support substrate 88 is formed of a silicon-containing dielectric material such as SiC, SiCN, etc., the bonding layer 86 can be skipped and the support substrate 88 is directly bonded to the dummy die 74 (and the semiconductor substrate 62) or the bonding layer 84 and is in physical contact with the dummy die 74 (and the semiconductor substrate 62) or the bonding layer 84.

[0053] The bonding may be performed by fusion bonding, for example, where the bonding layer 86 is bonded to the bonding layer 84 by fusion bonding. In addition, fusion bonding may also occur when the bonding layer 84 and / or the bonding layer 86 are skipped. According to some embodiments, the support substrate 88 has a thickness large enough to support subsequent processes, such as Fig.11 and Fig.12 The thickness of the support substrate 88 may be greater than about 100 μm, and may be in a range between about 100 μm and about 1000 μm.

[0054] Because the support substrate 88 provides mechanical support for supporting the reconstructed wafer 100 in subsequent processes and can be used to reduce warpage, the Young's modulus of the support substrate 88 is high so that it does not warp in subsequent processes. The Young's modulus of the support substrate 88 is higher than the Young's modulus of silicon and the semiconductor substrate 62, so that it can provide more mechanical support than other silicon support substrates. For example, the Young's modulus of silicon can be in the range between about 130 GPa and about 190 GPa, and the Young's modulus of the support substrate 88 can be higher than about 150 GPa or 200 GPa, in the range between about 150 GPa and about 500 GPa, or higher. For example, the Young's modulus of AlN is about 300 GPa.

[0055] Although the materials of support substrate 88 and dummy die 74 may be selected from the same candidate material group, as discussed, the material of support substrate 88 may be the same as or different from the material of dummy die 74. Furthermore, each of support substrate 88 and dummy die 74 may be formed of dielectrics, semiconductors, and metals in any combination.

[0056] According to some embodiments, the Young's modulus of the support substrate 88 is higher than the Young's modulus of the dummy die 74. For example, the Young's modulus of the dummy die 74 may be lower than the Young's modulus of the silicon substrate 62, so that the dummy die 74 may be used to absorb stress, while the function of mechanically supporting the underlying structure is provided by the support substrate 88, which has a higher Young's modulus and may be able to prevent warping of the reconstructed wafer 100. Therefore, combining the dummy die 74 having a lower Young's modulus and the support substrate 88 having a higher Young's modulus may provide good warping prevention capability and good heat dissipation capability.

[0057] The carrier 48 is then peeled off and the resulting structure is Fig.11 The corresponding process is shown as Fig.18 224 in the process flow 200 shown in FIG. According to some embodiments where carrier 48 includes a silicon wafer, carrier 48 can be removed by a smart cutting process, which includes, for example, implanting carrier 48 with hydrogen to generate a stress concentration layer, and annealing carrier 48 so that carrier 48 can be separated at the stress concentration layer. The remaining portion of carrier 48 can be removed, for example, by etching, a CMP process, or a mechanical grinding process. Layer 50 ( Fig.10 ), according to these embodiments, layer 50 is a bonding layer.

[0058] According to an alternative embodiment where carrier 48 is a glass carrier, reconstructed wafer 100 may be peeled from carrier 48 by projecting a laser beam onto layer 50 (which may be an LTHC coating material) such that the LTHC coating material decomposes, releasing reconstructed wafer 100 from carrier 48 .

[0059] Next, if Fig.12 As shown in FIG. 1 , an electrical connector 90 is formed. The corresponding process is shown as follows Fig.18 200. The process 226 in the process flow 200 shown in FIG. 226 may or may not be formed. The dielectric layer 92 (when formed) may be formed of or include silicon oxide, silicon nitride, silicon oxynitride, etc. A via 94 is formed to connect the electrical connector 90 to the redistribution structure 32. The electrical connector 90 may include a solder region, a metal pillar, etc. The reconstructed wafer 100 is thus formed.

[0060] In the subsequent process, the same Fig.12 As shown in FIG. 1 , the reconstructed wafer 100 is divided in a sawing process to form individual packages 100 ′. The corresponding process is shown as follows: Fig.18 The discrete package 100 ′ includes the device dies 20 ′ and 60 , and also includes the dummy die 74 and the support substrate 88 ′ cut from the support substrate 88 .

[0061] Fig.13 A package 102 including a package 100' is shown. According to some embodiments, the package 100' is bonded to a package component 104, which may be or may include a package substrate, a silicon interposer, an organic interposer, another package, etc. A heat sink 106 (which may alternatively be referred to as a heat dissipater) is attached to the package 100' via a thermal interface material (TIM) 110, which may include an adhesive and thermally conductive particles. The heat sink 106 may be formed of copper, aluminum, or other metals. The heat sink 106 is also attached to the package component 104 via an adhesive 108. An underfill 112 may be dispensed in the gap between the package 100' and the package component 104. Thus, the package 102 is formed.

[0062] exist Fig.13 In the structure shown in FIG. 1 , the heat generated in the device die 20 ′ can be dissipated to the heat sink 106 through several paths. The heat can be dissipated from the device die 20 ′ to the device die 60, through the support substrate 88 ′, and to the heat sink 106. The heat generated in the device dies 20 ′ and 60 is also dissipated through the gap-fill regions 52 and 80, and to the dummy die 74. Because the dummy die 74 is formed of a material having a high thermal conductivity, a low thermal resistance heat dissipation path is formed, which includes the gap-fill region 52, the dummy die 74, the support substrate 88 ′, and the heat sink 106. In this structure, the dummy die 74 and the support substrate 88 ′ (which have high thermal conductivity values) can improve heat dissipation.

[0063] According to an alternative embodiment, the heat sink may be attached to Fig.12. Thus, in the case where dummy die 74 has a higher thermal conductivity, the heat generated in device die 60 can be dissipated to dummy die 74, and from dummy die 74 into device die 20' and to the heat sink. Therefore, in addition to the heat path from device die 60 directly into device die 20' and to the heat sink, another heat dissipation path through dummy die 74 also has reduced thermal resistance.

[0064] Fig.14 A package 102 including a plurality of packages 100' is shown according to an alternative embodiment. According to some embodiments, there are two or more packages 100' bonded to a package assembly 104, which may be or may include a package substrate, a silicon interposer, an organic interposer, another package, etc. The packages 100' may have the same structure or different structures. An underfill 112 may be dispensed in the gap between the package 100' and the package assembly 104. An encapsulant 116 (which may include a molding compound, a molded underfill, etc.) may seal the package 100'.

[0065] Heat sink 106 is attached to package 100' via TIM 110, which may include adhesive and thermally conductive particles. Heat sink 106 may be formed of copper, aluminum, or other metals. Fig.14 The heat sink 106 is shown not attached to the package assembly 104, but the heat sink 106 may also be attached to the package assembly 104, similar to Fig.13 The structure shown in .

[0066] Fig.15 A package 102 including a plurality of stacked packages 100' (including packages 100'A and 100'B) is shown. Each of the packages 100'A and 100'B may have a configuration similar to that shown in FIG. Fig.12 The packages 100' in the embodiment of the present invention may have the same or similar structure as the packages 100' in the embodiment of the present invention. According to some embodiments, there are two or more packages 100' stacked, wherein the upper package 100'A overlaps with and is bonded to the lower package 100'B. The packages 100' may have the same structure or different structures. The bottom filler 112 may be dispensed in the gap between the packages 100'A and 100'B.

[0067] The heat sink 106 may be attached to the top package 100'A via a TIM 110, which may include an adhesive and thermally conductive particles. The heat sink 106 may be formed of copper, aluminum, or other metals. The TIM 110 may be attached to the support substrate 88' ( Fig.12 ) physical contact. The bottom filler 112 may be in contact with the supporting substrate 88' ( Fig.12 )Physical contact.

[0068] Fig.16 A package 102 is shown that includes a package 100' and a plurality of package components 120 interconnected by a bridge die 122 (also referred to as a local interconnect die). In accordance with some embodiments, the bridge die 122 is encapsulated in an encapsulant 124 to form an interconnect structure 126, which may be a molding compound. Adjacent packages 100' and package components 120 are bonded to the bridge die 122 and interconnected by the bridge die 122. An independent passive device (IPD) 128 is also encapsulated in the encapsulant 124. The interconnect structure 126 may be further bonded to the package component 104.

[0069] Heat sink 106 may be attached to package 100' and package assembly 120 via TIM 110, which may include adhesive and thermally conductive particles. Heat sink 106 may be formed of copper, aluminum, or other metals. TIM 110 may be attached to support substrate 88' ( Fig.12 )Physical contact.

[0070] Fig.17 According to some embodiments, Fig.12 A top view of package 100 ′ is shown in . Device die 20 ′ may extend laterally beyond all sides of device die 60 . Device die 60 may be surrounded by dummy die 74 and gap-fill region 80 . Fig.17 Two possible locations for the edges of device die 20 ′ are shown. Some possible edges are vertically aligned with corresponding outer edges of dummy die 74 , and some other possible edges may extend beyond corresponding edges of dummy die 74 .

[0071] In the embodiments shown above, some processes and components are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be implemented on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in combination with a test method for intermediate verification of a known good die to increase yield and reduce costs.

[0072] Embodiments of the present disclosure have some advantageous features. By forming a support substrate with increased thermal conductivity and increased Young's modulus, the support substrate can effectively conduct heat and can provide better mechanical support for the underlying structure. The dummy die can also have increased thermal conductivity and can also effectively conduct heat.

[0073] According to some embodiments of the present disclosure, a method includes: bonding a bottom die to a carrier; bonding a top die to the bottom die, wherein the top die includes a semiconductor substrate and the semiconductor substrate has a first thermal conductivity; sealing the top die in a first gap-filling region; bonding a support substrate to the top die and the first gap-filling region to form a reconstructed wafer, wherein the support substrate has a second thermal conductivity higher than the first thermal conductivity; peeling the reconstructed wafer from the carrier; and forming an electrical connector on the bottom die. In an embodiment, the support substrate includes a metal substrate. In an embodiment, the support substrate includes a dielectric substrate.

[0074] In an embodiment, the dielectric substrate of the support substrate is in physical contact with the additional semiconductor substrate of the top die. In an embodiment, the method further comprises: sawing the reconstituted wafer into a plurality of packages, wherein each of the packages comprises a portion of the support substrate. In an embodiment, the method further comprises: attaching a heat sink to one of the plurality of packages, wherein a thermal interface material (TIM) is located between and contacts the heat sink and the support substrate in one of the plurality of packages.

[0075] In an embodiment, the method further comprises: sealing the bottom die in the second gap-filling region before bonding the top die to the bottom die. In an embodiment, the support substrate also has a Young's modulus higher than a Young's modulus of the semiconductor substrate of the top die. In an embodiment, the method further comprises: bonding a dummy die to the bottom die, wherein the dummy die is sealed in the first gap-filling region, and wherein the dummy die has a third thermal conductivity higher than the first thermal conductivity.

[0076] In an embodiment, the dummy die has a Young's modulus lower than a Young's modulus of the semiconductor substrate of the top die. In an embodiment, the first bottom surface of the top die and the second bottom surface of the dummy die are bonded to and in physical contact with the same bonding layer of the bottom die, and wherein the entire dummy die is formed of a homogenous material.

[0077] According to some embodiments of the present disclosure, a structure includes: a bottom die; a top die located above the bottom die and bonded to the bottom die, wherein the top die includes a semiconductor substrate having a first thermal conductivity; a first gap-filling region sealing the top die; a supporting substrate bonded to the top die, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity; a bonding film located between the supporting substrate and the top die; and an electrical connector located on a front side of the bottom die.

[0078] In an embodiment, the structure further comprises: a thermal interface material located above and in contact with the support substrate; and a heat sink located above and in contact with the thermal interface material. In an embodiment, the structure further comprises: an underfill located above and in contact with the support substrate. In an embodiment, the support substrate comprises a metal. In an embodiment, the support substrate comprises a dielectric material.

[0079] According to some embodiments of the present disclosure, a structure includes: a top die including a semiconductor substrate, wherein the semiconductor substrate has a first Young's modulus; a gap-filling region, sealing the top die therein; a support substrate located above the top die and bonded to the top die, wherein the support substrate has a second Young's modulus higher than the first Young's modulus; a thermal interface material located above and contacting the support substrate; and a heat sink located above the thermal interface material and attached to the thermal interface material.

[0080] In an embodiment, the structure further comprises: a dummy die located in the gap-fill region, wherein the dummy die comprises a first material different from a second material of the semiconductor substrate. In an embodiment, the dummy die has a third Young's modulus different from the first Young's modulus. In an embodiment, the dummy die comprises a dielectric material or a metal.

[0081] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: bonding a bottom die to a carrier; bonding a top die to the bottom die, wherein the top die includes a semiconductor substrate and the semiconductor substrate has a first thermal conductivity; sealing the top die in a first gap-filling region; bonding a supporting substrate to the top die and the first gap-filling region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity; peeling the reconstructed wafer from the carrier; and forming electrical connectors on the bottom die.

[0082] In some embodiments, the support substrate comprises a metal substrate. In some embodiments, the support substrate comprises a dielectric substrate. In some embodiments, the dielectric substrate of the support substrate is in physical contact with the additional semiconductor substrate of the top die. In some embodiments, the method further comprises: sawing the reconstructed wafer into a plurality of packages, wherein each of the packages comprises a portion of the support substrate. In some embodiments, the method further comprises: attaching a heat sink to one of the plurality of packages, wherein a thermal interface material (TIM) is located between the heat sink and the support substrate in the one of the plurality of packages and contacts the heat sink and the support substrate in the one of the plurality of packages. In some embodiments, the method further comprises: sealing the bottom die in a second gap-filling region before the top die is bonded to the bottom die. In some embodiments, the support substrate also has a Young's modulus higher than the Young's modulus of the semiconductor substrate of the top die. In some embodiments, the method further comprises: bonding a dummy die to the bottom die, wherein the dummy die is sealed in the first gap-filling region, and wherein the dummy die has a third thermal conductivity higher than the first thermal conductivity. In some embodiments, the dummy die has a Young's modulus lower than the Young's modulus of the semiconductor substrate of the top die. In some embodiments, the first bottom surface of the top die and the second bottom surface of the dummy die are bonded to and in physical contact with the same bonding layer of the bottom die, and wherein the entire dummy die is formed of a homogenous material.

[0083] Other embodiments of the present application provide a semiconductor structure, comprising: a bottom die; a top die located above the bottom die and bonded to the bottom die, wherein the top die comprises a semiconductor substrate having a first thermal conductivity; a first gap-filling region sealing the top die; a supporting substrate bonded to the top die, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity; a bonding film located between the supporting substrate and the top die; and an electrical connector located on the front side of the bottom die.

[0084] In some embodiments, the semiconductor structure further comprises: a thermal interface material located above and in contact with the support substrate; and a heat sink located above and in contact with the thermal interface material. In some embodiments, the semiconductor structure further comprises: an underfill located above and in contact with the support substrate. In some embodiments, the support substrate comprises a metal. In some embodiments, the support substrate comprises a dielectric material.

[0085] Still other embodiments of the present application provide a semiconductor structure, comprising: a top die comprising a semiconductor substrate, wherein the semiconductor substrate has a first Young's modulus; a gap-filling region, sealing the top die therein; a supporting substrate, located above the top die and bonded to the top die, wherein the supporting substrate has a second Young's modulus higher than the first Young's modulus; a thermal interface material, located above the supporting substrate and contacting the supporting substrate; and a heat sink, located above the thermal interface material and attached to the thermal interface material.

[0086] In some embodiments, the semiconductor structure further comprises: a dummy die located in the gap-filling region, wherein the dummy die comprises a first material different from a second material of the semiconductor substrate. In some embodiments, the dummy die has a third Young's modulus different from the first Young's modulus. In some embodiments, the dummy die comprises a dielectric material or a metal.

[0087] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: bonding the bottom die to the carrier; bonding a top die to the bottom die, wherein the top die comprises a semiconductor substrate and the semiconductor substrate has a first thermal conductivity; sealing the top die in a first gap-fill region; bonding a support substrate to the top die and the first gap-fill region to form a reconstituted wafer, wherein the support substrate has a second thermal conductivity higher than the first thermal conductivity; peeling the reconstituted wafer from the carrier; and Electrical connections are formed on the bottom die.

2. The method according to claim 1, wherein: The support substrate includes a metal substrate.

3. The method according to claim 1, wherein: The support substrate includes a dielectric substrate.

4. The method according to claim 3, wherein: The dielectric substrate of the support substrate is in physical contact with the additional semiconductor substrate of the top die.

5. The method according to claim 1, further comprising: The reconstituted wafer is sawn into a plurality of packages, wherein each of the packages includes a portion of the support substrate.

6. The method according to claim 5, further comprising: A heat sink is attached to one of the plurality of packages, wherein a thermal interface material (TIM) is located between and contacts the heat sink and the support substrate in the one of the plurality of packages. 7 . The method of claim 1 , further comprising: sealing the bottom die in a second gap-fill region before the top die is bonded to the bottom die.

8. The method according to claim 1, wherein: The support substrate also has a Young's modulus that is higher than the Young's modulus of the semiconductor substrate of the top die.

9. A semiconductor structure comprising: bottom die; a top die over and bonded to the bottom die, wherein the top die comprises a semiconductor substrate having a first thermal conductivity; a first gap-fill region encapsulating the top die; a support substrate bonded to the top die, wherein the support substrate has a second thermal conductivity higher than the first thermal conductivity; a bonding film between the support substrate and the top die; and Electrical connections are located on the front side of the bottom die.

10. A semiconductor structure comprising: a top die comprising a semiconductor substrate, wherein the semiconductor substrate has a first Young's modulus; a gap-fill region in which the top die is sealed; a support substrate over the top die and bonded to the top die, wherein the support substrate has a second Young's modulus higher than the first Young's modulus; a thermal interface material located above and contacting the support substrate; and A heat sink is located above the thermal interface material and attached to the thermal interface material.

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