Semiconductor package

Abstract

The semiconductor package includes: a lower semiconductor die stack in which lower semiconductor dies are vertically stacked in a stepped manner to extend in a first horizontal direction; an upper semiconductor die stack, wherein the upper semiconductor dies are vertically stacked on the lower semiconductor die stack in a stepped manner to extend in a first reverse horizontal direction; a wiring structure over the upper semiconductor die stack; and a bonding wire group connecting the lower semiconductor die and the upper semiconductor die to the wiring structure. The bond wire group includes a first bond wire group including bond wires connecting a first plurality of semiconductor dies of the upper and lower semiconductor dies to the wiring structure. The bonding wire group includes a first curved wire connecting a second plurality of semiconductor dies of the first plurality of semiconductor dies, a first upward wire connected to the first curved wire, a first inclined wire connected to the first upward wire, and a second upward wire connecting the first inclined wire to the wiring structure.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a semiconductor die stack. Background Art

[0002] Electronic products are becoming smaller and smaller while meeting the requirements of high performance and high capacity. Semiconductor packages used in electronic products also need to become smaller. Therefore, it is necessary to stack semiconductor dies included in semiconductor packages and to easily connect semiconductor dies with bonding wires. Summary of the invention

[0003] The inventive concept relates to a semiconductor package including a plurality of semiconductor die stacks and a bonding wire group capable of easily connecting the semiconductor die stacks to a wiring structure.

[0004] According to one aspect of the present invention, a semiconductor package is provided, comprising: a lower semiconductor die stack, in which a plurality of lower semiconductor die are vertically stacked in a step-wise manner to extend in a first horizontal direction; an upper semiconductor die stack, in which a plurality of upper semiconductor die are vertically stacked in a step-wise manner on the lower semiconductor die stack to extend in a first reverse horizontal direction (-X direction) opposite to the first horizontal direction; a wiring structure, the wiring structure being located above the upper semiconductor die stack; and a bonding lead group, the bonding lead group connecting the lower semiconductor die and the upper semiconductor die to the wiring structure.

[0005] The bonding wire group includes a first bonding wire group, the first bonding wire group connecting a first plurality of semiconductor dies selected from the lower semiconductor die and the upper semiconductor die to the wiring structure. The first bonding wire group includes a first bonding portion, the first bonding portion includes a first bent lead, a first upward lead, a first inclined lead, and a second upward lead, the first bent lead connecting a second plurality of semiconductor dies among the first plurality of semiconductor dies, the first upward lead connected to the first bent lead and extending toward the wiring structure, the first inclined lead connected to the first upward lead, and the second upward lead extending toward the wiring structure to connect the first inclined lead to the wiring structure.

[0006] According to another aspect of the present invention, a semiconductor package is provided, comprising: a lower semiconductor die stack, in which a plurality of lower semiconductor die are vertically stacked in a stepped manner to extend in a first horizontal direction; an upper semiconductor die stack, in which a plurality of upper semiconductor die are vertically stacked in a stepped manner on the lower semiconductor die stack to extend in a first reverse horizontal direction (-X direction) opposite to the first horizontal direction; a wiring structure, the wiring structure being located above the upper semiconductor die stack; and a bonding lead group, the bonding lead group connecting the lower semiconductor die and the upper semiconductor die to the wiring structure.

[0007] The bonding wire group includes a first bonding wire group and a second bonding wire group, wherein the first bonding wire group connects a first plurality of semiconductor dies selected from the lower semiconductor die and the upper semiconductor die to the wiring structure, and the second bonding wire group includes bonding wires each connecting a single semiconductor die from the upper semiconductor die and the lower semiconductor die to the wiring structure.

[0008] The first bonding lead group includes a first bonding portion, the first bonding portion includes a first bent lead, a first upward lead, a first inclined lead, and a second upward lead, the first bent lead connecting a second plurality of semiconductor dies among the first plurality of semiconductor dies, the first upward lead connected to the first bent lead and extending toward the wiring structure, the first inclined lead connected to the first upward lead, and the second upward lead extending toward the wiring structure to connect the first inclined lead to the wiring structure. The bonding leads of the second bonding lead group each include a fifth upward lead extending toward the wiring structure to connect a single semiconductor die among the upper semiconductor die or the lower semiconductor die to the wiring structure.

[0009] According to another aspect of the present invention, a semiconductor package is provided, comprising: a lower semiconductor die stack, in which a plurality of lower semiconductor die are vertically stacked in a stepped manner to extend in a first horizontal direction (X direction); an upper semiconductor die stack, in which a plurality of upper semiconductor die are vertically stacked in a stepped manner on the lower semiconductor die stack to extend in a first reverse horizontal direction (-X direction) opposite to the first horizontal direction; and a wiring structure, the wiring structure being located above the upper semiconductor die stack.

[0010] The semiconductor package includes a lower bonding lead group, which connects the lower semiconductor die to the wiring structure, wherein the lower bonding lead group includes a first lower bonding portion, the first lower bonding portion includes a first lower bent lead, a first lower upward lead, a first lower inclined lead and a second lower upward lead, the first lower bent lead connects at least two of the lower semiconductor dies, the first lower upward lead is connected to the first lower bent lead and extends toward the wiring structure, the first lower inclined lead is connected to the first lower upward lead, and the second lower upward lead extends toward the wiring structure to connect the first lower inclined lead to the wiring structure.

[0011] The semiconductor package includes an upper bonding lead group, which electrically connects the upper semiconductor die to the wiring structure, wherein the upper bonding lead group includes a first upper bonding portion, the first upper bonding portion includes a first upper bent lead and a first upper upward lead, the first upper bent lead connects at least two of the upper semiconductor dies, and the first upper upward lead extends toward the wiring structure to connect the first upper bent lead to the wiring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment;

[0014] Figure 2 yes Figure 1 An enlarged view of the left part of ;

[0015] Figure 3 yes Figure 1 An enlarged view of the right part of ;

[0016] Figure 4 It's a picture. Figure 1 A top view of a state in which a first semiconductor die and a second semiconductor die are stacked;

[0017] Figure 5 is a cross-sectional view illustrating a semiconductor package according to an embodiment;

[0018] Figure 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment;

[0019] Figure 7 is a cross-sectional view illustrating a semiconductor package according to an embodiment;

[0020] Figure 8 is a cross-sectional view illustrating a semiconductor package according to an embodiment;

[0021] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to an embodiment;

[0022] Fig.10 yes Fig. 9 An enlarged view of the left part of ;

[0023] Fig.11 yes Fig. 9 An enlarged view of the right part of ;

[0024] Fig.12 is a cross-sectional view illustrating a semiconductor package according to an embodiment;

[0025] Figures 13 to 18 It is a diagram showing the manufacturing Figure 1 A cross-sectional view of a method for a semiconductor package;

[0026] Figures 19 to 24 It is a diagram showing the manufacturing Fig. 9 A cross-sectional view of a method for a semiconductor package;

[0027] Figure 25 to Figure 28 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. In addition, embodiments of the present invention may be set forth in separate drawings or in a combination of one or more drawings. It should also be emphasized that the present disclosure provides details of alternative examples, but such enumeration of alternatives is not exhaustive. In addition, any consistency of details between the various examples should not be construed as requiring such details—it is impractical to enumerate every possible variation for every feature described herein. In determining the requirements of the present invention, reference should be made to the language of the claims.

[0029] In the current specification, unless the context clearly indicates otherwise, components described using singular forms such as "a", "an" and "the" are also intended to include plural forms of components. In the current specification, the drawings are exaggerated to more clearly illustrate the inventive concept. In the current specification, ordinals such as "first", "second", "third", etc. can be simply used as labels for certain elements, steps, etc. to distinguish such elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, terms cited with specific ordinals (e.g., "first" in a specific claim) can be described elsewhere with different ordinals (e.g., "second" in the specification or another claim).

[0030] In the current specification, "connection" can mean that the component is physically connected and / or electrically connected. It will be understood that when an element is referred to as "connected" or "coupled" to another element or "on" another element, the element can be directly connected or coupled to another element or "on" another element, or there can be an intermediate element. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element or is referred to as "contacting" another element or "contacting" another element (or using any form of the word "contact"), there is no intermediate element at the contact point. As used herein, the component described as "electrically connected" is configured to enable an electrical signal to be transmitted from one component to another component (but such an electrical signal can be attenuated in strength as it is transmitted and can be selectively transmitted). In addition, the component of "direct electrical connection" is shared by one or more conductors such as leads, pads, internal wires, through-paths, etc. through electrical connections. Therefore, the component of direct electrical connection does not include a component electrically connected by an active element such as a transistor or a diode.

[0031] Figure 1 is a cross-sectional view illustrating a semiconductor package EM1 according to an embodiment, Figure 2 yes Figure 1 An enlarged view of the left part of Figure 3 yes Figure 1 , and Figure 4 It's a picture. Figure 1 A top view of a state in which a first semiconductor die and a second semiconductor die are stacked.

[0032] Specifically, the semiconductor package EM1 may include a lower semiconductor die stack CS1, an upper semiconductor die stack CS2, a wiring structure WR1, a first bonding lead group BG1, a second bonding lead group BG2 (refer to Figure 2 and Figure 3 ) and a molding layer 54.

[0033] In the lower semiconductor die stack CS1, a plurality of, for example, four, lower semiconductor dies (e.g., a first lower semiconductor die 12, a second lower semiconductor die 14, a third lower semiconductor die 16, and a fourth lower semiconductor die 18) may be vertically stacked in a stepped manner to extend in a first horizontal direction (X direction). The first horizontal direction (X direction) may be horizontal with respect to top surfaces of the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18, and may be a first step direction in which the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 are stacked (e.g., the horizontal position of each subsequent die moves in the step direction with respect to the die immediately below).

[0034] An insulating adhesive material such as an adhesive layer (e.g., a die attach film (DAF)) may be formed among the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18. Each of the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 may have a thickness of several tens of micrometers (μm).

[0035] The first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 may include a first lower semiconductor chip, a second lower semiconductor chip, a third lower semiconductor chip, and a fourth lower semiconductor chip, respectively. The first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 may include: a non-volatile memory, such as a flash memory, a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM); a volatile memory, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM); or a non-memory, such as a logic circuit.

[0036] like Figure 2 As shown, the fourth lower semiconductor die 18 may be stacked to be spaced apart from the first lower semiconductor die 12 by a first offset distance OS1 (eg, horizontally offset) in a first horizontal direction (X direction).

[0037] The first lower semiconductor die 12 , the second lower semiconductor die 14 , the third lower semiconductor die 16 , and the fourth lower semiconductor die 18 may each include a first lower die pad cp1 , a second lower die pad cp2 , a third lower die pad cp3 , and a fourth lower die pad cp4 , respectively.

[0038] like Figure 4 As shown, the first lower semiconductor die 12 may include a plurality of first lower die pads cp1, and each of the first lower die pads cp1 may be spaced apart from each other in a second horizontal direction (e.g., Y direction). The second lower semiconductor die 14 may include a plurality of second lower die pads cp2, and each of the second lower die pads cp2 may be spaced apart from each other in the second horizontal direction. The second horizontal direction (Y direction) may be horizontal relative to the top surfaces of the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18, and may be perpendicular to the first horizontal direction (X direction) on the top surfaces of the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18.

[0039] The first lower die pad cp1 of the first lower semiconductor die 12 and the second lower die pad cp2 of the second lower semiconductor die 14 may have edge pads. Figure 4 A first lower semiconductor die 12 and a second lower semiconductor die 14 are illustrated in FIG. 1 , and it is understood that other semiconductor dies may be of similar form.

[0040] In the upper semiconductor die stack CS2, a plurality of, for example, four, upper semiconductor dies (e.g., a first upper semiconductor die 36, a second upper semiconductor die 38, a third upper semiconductor die 40, and a fourth upper semiconductor die 42) may be vertically stacked in a stepped manner to extend in a first reverse horizontal direction (-X direction) that may be opposite to the first horizontal direction.

[0041] The first reverse horizontal direction (-X direction) can be horizontal relative to the top surfaces of the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42, and can be a second step direction in which the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42 are stacked, which is opposite to the first step direction of the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16 and the fourth lower semiconductor die 18.

[0042] An insulating adhesive material such as an adhesive layer (e.g., DAF) may be formed between the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42. Each of the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 may have a thickness of several tens of micrometers (μm).

[0043] The first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 may include first to fourth upper semiconductor chips, respectively. The first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 may include: a non-volatile memory such as a flash memory, a PRAM, or an MRAM; a volatile memory such as a DRAM or an SRAM; or a non-memory such as a logic circuit.

[0044] like Figure 3 As shown, the fourth upper semiconductor die 42 may be stacked to be spaced apart from the first upper semiconductor die 36 by a second offset distance OS2 (eg, horizontally offset) in a first reverse horizontal direction (-X direction). In some embodiments, the second offset distance OS2 may be the same as the first offset distance OS1.

[0045] like Figure 3 As shown, the first upper semiconductor die 36 may protrude a first overhang distance OH1 beyond one end of the fourth lower semiconductor die 18. In some embodiments, the first overhang distance OH1 may be less than the second offset distance OS2. The first overhang distance OH1 may reduce the first bonding portion 34 as will be described later, and therefore, the size of the semiconductor package EM1 in the first horizontal direction (X direction) may also be reduced.

[0046] The first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 may include a first upper die pad cp5, a second upper die pad cp6, a third upper die pad cp7, and a fourth upper die pad cp8, respectively. Each of the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 may have an edge pad, such as Figure 4 Same as those shown.

[0047] The wiring structure WR1 may be positioned above the upper semiconductor die stack CS2. The wiring structure WR1 may include a wiring board 64 and external connection terminals 66. The wiring board 64 may include a substrate body 62, an internal wiring pad 58, and an external wiring pad 60. In some embodiments, the wiring board 64 may include a printed circuit board (PCB). The internal wiring pad 58 and the external wiring pad 60 may be formed of a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), nickel (Ni), or tin (Sn) and / or include a metal such as Cu, Al, W, Ti, Ni, or Sn. The external connection terminals 66 may be connected to the external wiring pads 60, respectively.

[0048] The first bonding lead group BG1 and the second bonding lead group BG2 (refer to Figure 2 and Figure 3 ) can connect the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16 and the fourth lower semiconductor die 18 and the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42 to the wiring structure WR1. The first bonding lead group BG1 and the second bonding lead group BG2 (refer to Figure 2 and Figure 3 ) may include a lower bonding lead group LBG1 and an upper bonding lead group HBG1, the lower bonding lead group LBG1 connects the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16 and the fourth lower semiconductor die 18 to the wiring structure WR1, and the upper bonding lead group HBG1 connects the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42 to the wiring structure WR1.

[0049] The first bonding lead group BG1 and the second bonding lead group BG2 (refer to Figure 2 and Figure 3 ) may include bonding wires. The bonding wires may be formed of and / or include metals such as gold (Au), silver (Ag), Cu, or platinum (Pt), or alloys thereof, which may be welded to the die pads by ultrasonic energy and / or heat. The bonding wires may have a length of hundreds of micrometers (μm).

[0050] The first bonding wire group BG1 connects a plurality of upper semiconductor dies and lower semiconductor dies selected from among the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 and the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 to the wiring structure WR1. Each bonding wire of the first bonding wire group BG1 may be connected to at least two semiconductor dies selected from among the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 or the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42.

[0051] In some embodiments, the first bonding wire group BG1 may connect the first lower semiconductor die 12 and the second lower semiconductor die 14 to the wiring structure WR1. In some embodiments, the bonding wires of the first bonding wire group BG1 may connect the first lower semiconductor die 12 and the second lower semiconductor die 14 to the wiring structure WR1. In some embodiments, the first bonding wire group BG1 may connect the third lower semiconductor die 16 and the fourth lower semiconductor die 18 to the wiring structure WR1. In some embodiments, the bonding wires of the first bonding wire group BG1 may connect the third lower semiconductor die 16 and the fourth lower semiconductor die 18 to the wiring structure WR1.

[0052] like Figure 2 As shown, the first bonding lead group BG1 may include a first bonding portion 34, the first bonding portion 34 includes a first bent lead 26, a first upward lead 28, a first inclined lead 30 and a second upward lead 32, the first bent lead 26 connecting multiple upper semiconductor dies and lower semiconductor dies (for example, the third lower semiconductor die 16 and the fourth lower semiconductor die 18), the first upward lead 28 is connected to the first bent lead 26 and extends toward the wiring structure WR1, the first inclined lead 30 is connected to the first upward lead 28, and the second upward lead 32 extends toward the wiring structure WR1 to connect the first inclined lead 30 to the wiring structure WR1.

[0053] like Figure 2 As shown, the first connection point C1 located between the first upward lead 28 and the first inclined lead 30 may be configured to connect to some of the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 (e.g., Figure 2 A fourth upper semiconductor die 42 is shown vertically overlapping.

[0054] In addition, if Figure 2 As shown, the second connection point C2 between the first inclined lead 30 and the second upward lead 32 may be configured not to vertically overlap the first upper semiconductor die 36 , the second upper semiconductor die 38 , the third upper semiconductor die 40 , and the fourth upper semiconductor die 42 .

[0055] The first bent lead 26 may connect the third lower die pad cp3 to the fourth lower die pad cp4. An end of the second upward lead 32 may include a spherical ball bp. The spherical ball bp may be referred to as a free air ball.

[0056] Because the first bonding portion 34 includes a first bent lead 26, a first upward lead 28, a first inclined lead 30, and a second upward lead 32 to easily connect a plurality of upper semiconductor dies and lower semiconductor dies (for example, a third lower semiconductor die 16 and a fourth lower semiconductor die 18) to the wiring structure WR1, the first overhang distance OH1 of the semiconductor package EM1 can be effectively reduced.

[0057] exist Figure 1 In the semiconductor package EM1 of FIG. 1 , the first inclined lead 30 is shown to be inclined at a single angle relative to the first upward lead 28. However, when the first inclined lead 30 is configured to be relatively long, similar to Fig.12 , the first inclined lead 30 may be configured to be inclined at a plurality of angles relative to the first upward lead, for example, inclined twice from the first upward lead 28 .

[0058] like Figure 2 As shown, the first bonding lead group BG1 may further include a second bonding portion 24, the second bonding portion 24 includes a second bent lead 20 and a third upward lead 22, the second bent lead 20 connects a plurality of upper semiconductor dies and lower semiconductor dies (e.g., the first lower semiconductor die 12 and the second lower semiconductor die 14) that are not connected by the first bonding portion 34, and the third upward lead 22 extends toward the wiring structure WR1 to connect the second bent lead 20 to the wiring structure WR1. The second bent lead 20 may connect the first lower die pad cp1 to the second lower die pad cp2. The end of the third upward lead 22 may include a spherical ball bp.

[0059] In some embodiments, Figure 3 As shown, the first bonding wire group BG1 may connect the first upper semiconductor die 36 and the second upper semiconductor die 38 to the wiring structure WR1 .

[0060] like Figure 3 As shown, the first bonding lead group BG1 may further include a third bonding portion 48, the third bonding portion 48 includes a third bent lead 44 and a fourth upward lead 46, the third bent lead 44 connects a plurality of upper semiconductor dies and a lower semiconductor die (e.g., the first upper semiconductor die 36 and the second upper semiconductor die 38), and the fourth upward lead 46 extends toward the wiring structure WR1 to connect the third bent lead 44 to the wiring structure WR1. The third bent lead 44 may connect the first upper die pad cp5 to the second upper die pad cp6. The end of the fourth upward lead 46 may include a spherical ball bp.

[0061] Each bonding lead of the second bonding lead group BG2 connects a semiconductor die (i.e., a single die) selected from the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16 and the fourth lower semiconductor die 18 and the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42 to the wiring structure WR1.

[0062] In some embodiments, the bonding leads of the second bonding lead group BG2 may include a fifth upward lead 50, which connects one upper semiconductor die or lower semiconductor die (e.g., the third upper semiconductor die 40) to the wiring structure WR1 and extends toward the wiring structure WR1. The bonding leads of the second bonding lead group BG2 may include a sixth upward lead 52, which connects one upper semiconductor die or lower semiconductor die (e.g., the fourth upper semiconductor die 42) to the wiring structure WR1 and extends toward the wiring structure WR1. The ends of the fifth upward lead 50 and the sixth upward lead 52 may include spherical balls bp.

[0063] exist Figure 1 , for convenience, the third lower semiconductor die 16 and the fourth lower semiconductor die 18 and the wiring structure WR1 are depicted as being connected to the lower bonding lead group LBG1 only by using the first inclined wire 30, but the embodiment is not limited thereto. In some embodiments, the first lower semiconductor die and the second lower semiconductor die of the lower bonding lead group LBG1 may also be connected to the wiring structure WR1 by using the inclined wires according to the positions of the internal wiring pads 58 of the wiring board 64.

[0064] In some embodiments, at least one of the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42 of the upper bonding lead group HBG1 can also be connected to the wiring structure WR1 by using inclined leads according to the position of the internal wiring pad 58 of the wiring board 64.

[0065] The molding layer 54 may mold the lower semiconductor die stack CS1, the upper semiconductor die stack CS2, and the first bonding lead group BG1 and the second bonding lead group BG2 (refer to Figure 2 and Figure 3). The molding layer 54 may be formed of and / or include an epoxy molding compound (EMC). The molding layer 54 may mold the lower semiconductor die stack CS1, the upper semiconductor die stack CS2, the lower bonding lead group LBG1, and the upper bonding lead group HBG1. The top surface of the molding layer 54 may be coplanar with the top surfaces of the spherical balls bp at the ends of the second upward leads 32, the third upward leads 22, the fourth upward leads 46, the fifth upward leads 50, and the sixth upward leads 52.

[0066] The wiring structure WR1 may be located on the mold layer 54. The spherical balls bp at the ends of the second upward lead 32, the third upward lead 22, the fourth upward lead 46, the fifth upward lead 50, and the sixth upward lead 52 may be connected to the internal wiring pad 58 of the wiring board 64. Because the ends of the second upward lead 32, the third upward lead 22, the fourth upward lead 46, the fifth upward lead 50, and the sixth upward lead 52 include the spherical balls bp, the ends of the second upward lead 32, the third upward lead 22, the fourth upward lead 46, the fifth upward lead 50, and the sixth upward lead 52 may be easily connected to the internal wiring pad 58 of the wiring board 64.

[0067] For convenience, in Figures 1 to 4 , the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 and the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 are illustrated as being stacked along a first horizontal direction (X direction) and a first reverse horizontal direction (-X direction). However, in the semiconductor package EM1 according to the inventive concept, the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 and the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42 may be stacked along a second horizontal direction (Y direction) and a second reverse horizontal direction (-Y direction) opposite to the second horizontal direction.

[0068] In the semiconductor package EM1 described above, the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16 and the fourth lower semiconductor die 18 and the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42 can be easily connected to the wiring structure WR1 by using the first bonding lead group BG1 and the second bonding lead group BG2.

[0069] In addition, since the semiconductor package EM1 includes the first bonding portion 34 having the first bent lead 26, the first upward lead 28, the first inclined lead 30, and the second upward lead 32, the first overhang distance OH1 of the semiconductor package EM1 can be effectively reduced. Therefore, the size of the semiconductor package EM1 in the first horizontal direction (X direction) can be reduced.

[0070] Figure 5 is a cross-sectional view illustrating a semiconductor package EM2 according to an embodiment.

[0071] Specifically, the semiconductor package EM2 may be similar to the semiconductor package EM2 except that the configurations of the first bonding lead group BG1 and the second bonding lead group BG2 constituting the lower bonding lead group LBG1 are different. Figures 1 to 4 The semiconductor package EM1 is the same as that of FIG. Figure 5 Give previous reference Figures 1 to 4 Description given.

[0072] like Figure 5 As shown, the first bonding lead group BG1 may include a first bonding portion 34-1, the first bonding portion 34-1 includes a first bent lead 26-1, a first upward lead 28, a first inclined lead 30, and a second upward lead 32, the first bent lead 26-1 connects a plurality of upper semiconductor dies and lower semiconductor dies (e.g., the second to fourth lower semiconductor dies 14, 16, and 18), the first upward lead 28 extends toward the wiring structure WR1 and is connected to the first bent lead 26-1, the first inclined lead 30 is connected to the first upward lead 28, and the second upward lead 32 extends toward the wiring structure WR1 to connect the first inclined lead 30 to the wiring structure WR1. The first bent lead 26-1 may connect the second lower die pad cp2, the third lower die pad cp3, and the fourth lower die pad cp4.

[0073] The second bonding lead group BG2 may include a second bonding portion 24 - 1 including one lower semiconductor die not connected by the first bonding portion 34 - 1 (eg, the third upward lead 22 connected to the first lower semiconductor die 12 and extending toward the wiring structure WR1 ).

[0074] Figure 6 is a cross-sectional view illustrating a semiconductor package EM3 according to an embodiment.

[0075] Specifically, the semiconductor package EM3 may be similar to the semiconductor package EM3 except that the ends of the second to sixth upward leads 32, 22, 46, 50, and 52 of the lower bonding lead group LBG1-1 and the upper bonding lead group HBG1-1 include the hemispherical ball bp-1. Figures 1 to 4 The semiconductor package EM1 is the same as that of FIG. Figure 6 Give previous reference Figures 1 to 4 Description given.

[0076] The lower bonding lead group LBG1-1 may include second and third upward leads 32 and 22. End portions of the second and third upward leads 32 and 22 connected to the wiring structure WR1 may include a hemispherical ball bp-1.

[0077] The upper bonding lead group HBG1-1 may include fourth, fifth, and sixth upward leads 46, 50, and 52. Ends of the fourth, fifth, and sixth upward leads 46, 50, and 52 connected to the wiring structure WR1 may include a hemispherical ball bp-1.

[0078] When the ends of the second to sixth upward leads 32 , 22 , 46 , 50 , and 52 include the hemispherical balls bp- 1 , the second to sixth upward leads 32 , 22 , 46 , 50 , and 52 can be easily connected to the internal wiring pads 58 of the wiring board 64 .

[0079] Figure 7 is a cross-sectional view illustrating a semiconductor package EM4 according to an embodiment.

[0080] Specifically, in addition to the wiring structure WR-1 including the redistribution structure 76, the semiconductor package EM4 may be Figures 1 to 4 The semiconductor package EM1 is the same as that of FIG. Figure 7 Give previous reference Figures 1 to 4 Description given.

[0081] The lower bonding lead group LBG2 may include second and third upward leads 32 and 22. End portions of the second and third upward leads 32 and 22 connected to the wiring structure WR1-1 may have a flat surface instead of a spherical shape.

[0082] The upper bonding lead group HBG2 may include fourth, fifth, and sixth upward leads 46, 50, and 52. Ends of the fourth, fifth, and sixth upward leads 46, 50, and 52 connected to the wiring structure WR1-1 may have a flat surface instead of a spherical shape.

[0083] The wiring structure WR1-1 may be disposed on the lower bonding lead group LBG2, the upper bonding lead group HBG2, and the mold layer 54. The wiring structure WR-1 may include a redistribution structure 76. The redistribution structure 76 may include a redistribution body 72, an inner redistribution pad 68, a redistribution layer 74, and an outer redistribution pad 70.

[0084] The redistribution layer 74 may be formed of and / or include a metal such as Cu, Al, W, or Ti. The internal redistribution pads 68 and the external redistribution pads 70 may be formed of and / or include a metal such as Cu, Al, W, Ti, Ni, or Sn. The wiring structure WR1-1 may include external connection terminals 66 connected to the external redistribution pads 70, respectively.

[0085] Figure 8 is a cross-sectional view illustrating a semiconductor package EM5 according to an embodiment.

[0086] Specifically, in addition to further forming connection solder balls 78 on the lower bonding lead group LBG2 and the upper bonding lead group HBG2, the semiconductor package EM5 may be Figures 1 to 4 The semiconductor package EM1 is the same as that of FIG. Figure 8 Give previous reference Figures 1 to 4 Description given.

[0087] The lower bonding lead group LBG2 may include second and third upward leads 32 and 22. End portions of the second and third upward leads 32 and 22 connected to the wiring structure WR1 may have a flat surface instead of a spherical shape.

[0088] The upper bonding lead group HBG2 may include fourth, fifth, and sixth upward leads 46, 50, and 52. Ends of the fourth, fifth, and sixth upward leads 46, 50, and 52 connected to the wiring structure WR1 may have a flat surface instead of a spherical shape.

[0089] The connection solder balls 78 may be formed on the second upward lead 32, the third upward lead 22, the fourth upward lead 46, the fifth upward lead 50, and the sixth upward lead 52. The connection solder balls 78 may be formed of a low-strength solder composition having Sn as a base metal and Ag and Cu as auxiliary metals and / or include a low-strength solder composition having Sn as a base metal and Ag and Cu as auxiliary metals. The connection solder balls 78 may be formed of a high-strength solder composition having Ag as a base metal and Cu and bismuth (Bi) as auxiliary metals and / or include a high-strength solder composition having Ag as a base metal and Cu and Bi as auxiliary metals.

[0090] The wiring structure WR1 may be disposed on the lower bonding lead group LBG2, the upper bonding lead group HBG2, and the connection solder balls 78 on the mold layer 54. The inner wiring pads 58 of the wiring structure WR1 may be easily connected to the second to sixth upward leads 32, 22, 46, 50, and 52.

[0091] Fig. 9 is a cross-sectional view illustrating a semiconductor package EM6 according to an embodiment, Fig.10 yes Fig. 9 , and Fig.11 yes Fig. 9 An enlarged view of the right part of .

[0092] Specifically, the semiconductor package EM6 may include a lower semiconductor die stack CS1-1, an upper semiconductor die stack CS2-1, a wiring structure WR3, and a first bonding lead group BG3 and a second bonding lead group BG3-1 (refer to Fig.10 and Fig.11 ) and a molding layer 182.

[0093] In the lower semiconductor die stack CS1-1, a plurality of, for example, eight lower semiconductor dies (e.g., first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116) may be vertically stacked in a stepped manner to extend in a first horizontal direction (X direction). The first horizontal direction (X direction) may be horizontal with respect to top surfaces of the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116, and may be a first stepped direction in which the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 are stacked.

[0094] An insulating adhesive material such as an adhesive layer (e.g., DAF) may be formed between the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116. Each of the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 may have a thickness of several tens of micrometers (μm).

[0095] The first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 may include first to eighth lower semiconductor chips. The first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 may include: a non-volatile memory such as a flash memory, a PRAM, or an MRAM; a volatile memory such as a DRAM or an SRAM; or a non-memory such as a logic circuit.

[0096] like Fig.10 As shown, the eighth lower semiconductor die 116 may be stacked to be spaced apart from the first lower semiconductor die 102 by a third offset distance OS3 in the first horizontal direction (X direction).

[0097] The first lower semiconductor die 102, the second lower semiconductor die 104, the third lower semiconductor die 106, the fourth lower semiconductor die 108, the fifth lower semiconductor die 110, the sixth lower semiconductor die 112, the seventh lower semiconductor die 114 and the eighth lower semiconductor die 116 may respectively include a first lower die pad cp1, a second lower die pad cp2, a third lower die pad cp3, a fourth lower die pad cp4, a fifth lower die pad cp5, a sixth lower die pad cp6, a seventh lower die pad cp7 and an eighth lower die pad cp8.

[0098] Each of the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 may be similar to the Figure 4 It also has edge pads.

[0099] In the upper semiconductor die stack CS2-1, a plurality of, for example, eight, upper semiconductor dies (e.g., first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160, and 162) may be vertically stacked in a stepped manner to extend in a first reverse horizontal direction (-X direction) opposite to the first horizontal direction.

[0100] The first reverse horizontal direction (-X direction) can be horizontal relative to the top surfaces of the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162, and can be a second step direction in which the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162 are stacked, which is opposite to the first step direction of the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114 and 116.

[0101] An insulating adhesive material such as an adhesive layer (e.g., DAF) may be formed between the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160, and 162. Each of the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160, and 162 may have a thickness of several tens of micrometers (μm).

[0102] The first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162 may include first to eighth upper semiconductor chips. The first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162 may include: a non-volatile memory such as a flash memory, a PRAM or an MRAM; a volatile memory such as a DRAM or an SRAM; or a non-memory such as a logic circuit.

[0103] like Fig.11 As shown, the eighth upper semiconductor die 162 may be stacked to be spaced apart from the first upper semiconductor die 148 by a fourth offset distance OS4 in the first reverse horizontal direction (-X direction). In some embodiments, the fourth offset distance OS4 may be the same as the third offset distance OS3.

[0104] like Fig.11 As shown, the first upper semiconductor die 148 may protrude a second overhang distance OH2 beyond one end of the eighth lower semiconductor die 116. In some embodiments, the second overhang distance OH2 may be less than the fourth offset distance OS4. The second overhang distance OH2 may reduce the first to third lower bonding portions 126, 136, and 146 as will be described later, and therefore, the size of the semiconductor package EM6 in the first horizontal direction (X direction) may also be reduced.

[0105] The first upper semiconductor die 148, the second upper semiconductor die 150, the third upper semiconductor die 152, the fourth upper semiconductor die 154, the fifth upper semiconductor die 156, the sixth upper semiconductor die 158, the seventh upper semiconductor die 160 and the eighth upper semiconductor die 162 may respectively include a first upper die pad cp9, a second upper die pad cp10, a third upper die pad cp11, a fourth upper die pad cp12, a fifth upper die pad cp13, a sixth upper die pad cp14, a seventh upper die pad cp15 and an eighth upper die pad cp16.

[0106] Each of the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160, and 162 may be similar to the Figure 4 It also has edge pads.

[0107] The wiring structure WR3 may be positioned above the upper semiconductor die stack CS2-1. The wiring structure WR3 may include a wiring board 190 and external connection terminals 192. The wiring board 190 may include a substrate body 188, internal wiring pads 184, and external wiring pads 186. In some embodiments, the wiring board 190 may include a PCB. The external connection terminals 192 may be connected to the external wiring pads 186, respectively.

[0108] The first bonding lead group BG3 and the second bonding lead group BG3-1 (refer to Fig.10 and Fig.11 ) may connect the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 and the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160, and 162 to the wiring structure WR3.

[0109] The first bonding lead group BG3 and the second bonding lead group BG3-1 (refer to Fig.10 and Fig.11 ) may include bonding wires. The bonding wires may be formed of and / or include metals such as Au, Ag, Cu, or Pt, or alloys thereof, which may be welded to the die pads by ultrasonic energy and / or heat. The bonding wires may have a length of hundreds of micrometers (μm).

[0110] The first bonding lead group BG3 and the second bonding lead group BG3-1 (refer to Fig.10 and Fig.11 ) may include a lower bonding lead group LBG3 and an upper bonding lead group HBG3, the lower bonding lead group LBG3 connecting the first to the eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114 and 116 to the wiring structure WR3, and the upper bonding lead group HBG3 connecting the first to the eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162 to the wiring structure WR3.

[0111] The first bonding wire group BG3 connects a plurality of lower semiconductor dies selected from the first to eighth lower semiconductor dies 102 , 104 , 106 , 108 , 110 , 112 , 114 , and 116 to the wiring structure WR3 .

[0112] In some embodiments, the first bonding wire group BG3 may connect the first lower semiconductor die 102 and the second lower semiconductor die 104 to the wiring structure WR3. In some embodiments, the first bonding wire group BG3 may connect the third lower semiconductor die 106, the fourth lower semiconductor die 108, and the fifth lower semiconductor die 110 to the wiring structure WR3. In some embodiments, the first bonding wire group BG3 may connect the sixth lower semiconductor die 112, the seventh lower semiconductor die 114, and the eighth lower semiconductor die 116 to the wiring structure WR3.

[0113] like Fig.10As shown, the lower bonding lead group LBG3 may include a first lower bonding portion 126, the first lower bonding portion 126 includes a first lower bent lead 118, a first lower upward lead 120, a first lower inclined lead 122 and a second lower upward lead 124, the first lower bent lead 118 connects a plurality of lower semiconductor die (for example, the first lower semiconductor die 102 and the second lower semiconductor die 104) to each other, the first lower upward lead 120 is connected to the first lower bent lead 118 and extends toward the wiring structure WR3, the first lower inclined lead 122 is connected to the first lower upward lead 120, and the second lower upward lead 124 extends toward the wiring structure WR3 to connect the first lower inclined lead 122 to the wiring structure WR3.

[0114] The first lower bent lead 118 may connect the first lower die pad cp1 to the second lower die pad cp2. An end of the second lower upward lead 124 may have a flat surface. In some embodiments, an end of the second lower upward lead 124 may include a spherical ball.

[0115] like Fig.10 As shown, the lower bonding lead group LBG3 may include a second lower bonding portion 136, the second lower bonding portion 136 includes a second lower bent lead 128, a third lower upward lead 130, a second lower inclined lead 132 and a fourth lower upward lead 134, the second lower bent lead 128 connecting multiple lower semiconductor dies (for example, the third to fifth lower semiconductor dies 106, 108 and 110) that are not connected through the first lower bonding portion 126, the third lower upward lead 130 is connected to the second lower bent lead 128 and extends toward the wiring structure WR3, the second lower inclined lead 132 is connected to the third lower upward lead 130, and the fourth lower upward lead 134 extends toward the wiring structure WR3 to connect the second lower inclined lead 132 to the wiring structure WR3.

[0116] The second lower bent lead 128 may connect the third lower die pad cp3, the fourth lower die pad cp4, and the fifth lower die pad cp5. The end of the fourth lower upward lead 134 may have a flat surface. In some embodiments, the end of the fourth lower upward lead 134 may include a spherical ball.

[0117] like Fig.10As shown, the lower bonding lead group LBG3 may include a third lower bonding portion 146, the third lower bonding portion 146 includes a third lower bent lead 138, a fifth lower upward lead 140, a third lower inclined lead 142 and a sixth lower upward lead 144, the third lower bent lead 138 connecting a plurality of lower semiconductor dies (for example, the sixth to eighth lower semiconductor dies 112, 114 and 116) that are not connected through the first lower bonding portion 126 and the second lower bonding portion 136, the fifth lower upward lead 140 is connected to the third lower bent lead 138 and extends toward the wiring structure WR3, the third lower inclined lead 142 is connected to the fifth lower upward lead 140, and the sixth lower upward lead 144 extends toward the wiring structure WR3 to connect the third lower inclined lead 142 to the wiring structure WR3.

[0118] The third lower bent lead 138 may connect the sixth lower die pad cp6, the seventh lower die pad cp7, and the eighth lower die pad cp8. The end of the sixth lower upward lead 144 may have a flat surface. In some embodiments, the end of the sixth lower upward lead 144 may include a spherical ball.

[0119] Because the first to third lower joining portions 126, 136 and 146 include first to third lower bent leads 118, 128 and 138, first to sixth lower upward leads 120, 124, 130, 134, 140 and 144 and first to third lower inclined leads 122, 132 and 142 to easily connect multiple lower semiconductor dies to the wiring structure WR3, the second overhang distance OH2 of the semiconductor package EM6 can be effectively reduced.

[0120] The second bonding wire group BG3 - 1 connects two upper semiconductor die selected from the first upper semiconductor die 36 , the second upper semiconductor die 38 , the third upper semiconductor die 40 , and the fourth upper semiconductor die 42 to the wiring structure WR3 .

[0121] In some embodiments, the second bonding wire group BG3-1 may connect the first upper semiconductor die 148 and the second upper semiconductor die 150 to the wiring structure WR3. In some embodiments, the second bonding wire group BG3-1 may connect the third upper semiconductor die 152, the fourth upper semiconductor die 154, and the fifth upper semiconductor die 156 to the wiring structure WR3. In some embodiments, the second bonding wire group BG3-1 may connect the sixth upper semiconductor die 158, the seventh upper semiconductor die 160, and the eighth upper semiconductor die 162 to the wiring structure WR3.

[0122] like Fig.11As shown, the upper bonding lead group HBG3 may include a first upper bonding portion 168, the first upper bonding portion 168 includes a first upper bent lead 164 and a first upper upward lead 166, the first upper bent lead 164 connecting multiple upper semiconductor die (for example, the first upper semiconductor die 148 and the second upper semiconductor die 150), and the first upper upward lead 166 extending toward the wiring structure WR3 to connect the first upper bent lead 164 to the wiring structure WR3.

[0123] The first upper bent lead 164 may connect the first upper die pad cp9 to the second upper die pad cp10. The end of the first upper upward lead 166 may have a flat surface. In some embodiments, the end of the first upper upward lead 166 may include a spherical ball.

[0124] like Fig.11 As shown, the upper bonding lead group HBG3 may include a second upper bonding portion 174, the second upper bonding portion 174 includes a second upper bent lead 170 and a second upper upward lead 172, the second upper bent lead 170 connecting multiple upper semiconductor dies (for example, the third to fifth upper semiconductor dies 152, 154 and 156) that are not connected through the first upper bonding portion 168, and the second upper upward lead 172 extending toward the wiring structure WR3 to connect the second upper bent lead 170 to the wiring structure WR3.

[0125] The second upper bent lead 170 may connect the third upper die pad cp11, the fourth upper die pad cp12, and the fifth upper die pad cp13. The end of the second upper upward lead 172 may have a flat surface. In some embodiments, the end of the second upper upward lead 172 may include a spherical ball.

[0126] like Fig.11 As shown, the upper bonding lead group HBG3 may include a third upper bonding portion 180, the third upper bonding portion 180 includes a third upper bent lead 176 and a third upper upward lead 178, the third upper bent lead 176 connecting multiple upper semiconductor dies (for example, the sixth to eighth upper semiconductor dies 158, 160 and 162) that are not connected through the first upper bonding portion 168 and the second upper bonding portion 174, and the third upper upward lead 178 extending toward the wiring structure WR3 to connect the third upper bent lead 176 to the wiring structure WR3.

[0127] The third upper bent lead 176 may connect the sixth upper die pad cp14, the seventh upper die pad cp15, and the eighth upper die pad cp16. The end of the third upper upward lead 178 may have a flat surface. In some embodiments, the end of the third upper upward lead 178 may include a spherical ball.

[0128] Because the first to third upper bonding portions 168 , 174 and 180 include the first to third upper bent leads 164 , 170 and 172 and the first to third upper upward leads 166 , 172 and 178 to easily connect the plurality of upper semiconductor dies to the wiring structure WR3 , the second overhang distance OH2 of the semiconductor package EM6 may be effectively reduced.

[0129] exist Fig. 9 , for convenience, only in the lower bonding lead group LBG3, the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114 and 116 are depicted as being connected to the wiring structure WR3 by using the first to third inclined leads 122, 132 and 142, but the embodiment is not limited thereto. In some embodiments, at least one of the first to eighth upper semiconductor dies 148, 150, 152, 156, 158, 160 and 162 of the upper bonding lead group HBG3 may also be connected to the wiring structure WR3 by using an inclined lead according to the position of the internal wiring pad 184 of the wiring board 190.

[0130] The molding layer 182 may mold the lower semiconductor die stack CS1-1, the upper semiconductor die stack CS2-1, and the first bonding lead group BG3 and the second bonding lead group BG3-1 (refer to Fig.10 and Fig.11 ). The molding layer 182 may include EMC. The molding layer 182 may mold the lower semiconductor die stack CS1-1, the upper semiconductor die stack CS2-1, the lower bonding lead group LBG3, and the upper bonding lead group HBG3. The top surface of the molding layer 182 may be coplanar with the top surfaces of the ends of the second lower upward lead 124, the fourth lower upward lead 134, the sixth lower upward lead 144, the first upper upward lead 166, the second upper upward lead 172, and the third upper upward lead 178.

[0131] The wiring structure WR3 may be located on the mold layer 182. Ends of the second lower upward lead 124, the fourth lower upward lead 134, the sixth lower upward lead 144, the first upper upward lead 166, the second upper upward lead 172, and the third upper upward lead 178 may be connected to the internal wiring pad 184 of the wiring board 190.

[0132] For convenience, in Fig. 9104, 106, 108, 110, 112, 114, and 116 and the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160, and 162 are illustrated as being stacked along a first horizontal direction (X direction) and a first reverse horizontal direction (-X direction). However, in the semiconductor package EM6 according to the inventive concept, the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 and the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160, and 162 may be stacked along a second horizontal direction (Y direction) and a second reverse horizontal direction (-Y direction).

[0133] In the semiconductor package EM6, the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114 and 116 and the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162 can be easily connected to the wiring structure WR3 by using the first bonding wire group BG3 and the second bonding wire group BG3-1. In addition, since the semiconductor package EM6 includes the first to third lower bonding parts 126, 136 and 146, the second overhang distance OH2 of the semiconductor package EM6 can be effectively reduced. Therefore, the size of the semiconductor package EM6 in the first horizontal direction (X direction) can be reduced.

[0134] Fig.12 is a cross-sectional view illustrating a semiconductor package EM7 according to an embodiment.

[0135] Specifically, the semiconductor package EM7 may be different from the semiconductor package EM7 except that the configuration of the first bonding lead group BG3 constituting the lower bonding lead group LBG3-1 is different. Figures 9 to 11 The semiconductor package EM6 is the same as that of FIG. Fig.12 Give previous reference Figures 9 to 11 Description given.

[0136] The first bonding lead group BG3 constituting the lower bonding lead group LBG3-1 may include a first lower bonding portion 126. The first lower bonding portion 126 may include a first lower bent lead 118, a first lower upward lead 120, a first lower inclined lead 122, and a second lower upward lead 124, the first lower upward lead 120 extending toward the wiring structure WR3 and connected to the first lower bent lead 118, the first lower inclined lead 122 connected to the first lower upward lead 120, and the second lower upward lead 124 extending toward the wiring structure WR3 to connect the first lower inclined lead 122 to the wiring structure WR3.

[0137] The first bonding lead group BG3 constituting the lower bonding lead group LBG3-1 may include a second lower bonding portion 136-1. The second lower bonding portion 136-1 may include a second lower bent lead 128 that connects a plurality of lower semiconductor dies (e.g., the third to fifth lower semiconductor dies 106, 108, and 110) that are not connected through the first lower bonding portion 126, a third lower upward lead 130 that is connected to the second lower bent lead 128 and extends toward the wiring structure WR3, second lower inclined leads 132-1 and 132-2 that are connected to the third lower upward lead 130, and a fourth lower upward lead 134 that extends toward the wiring structure WR3 to connect the second lower inclined leads 132-1 and 132-2 to the wiring structure WR3.

[0138] The second lower inclined leads 132-1 and 132-2 may include a first sub-lower inclined lead 132-1 connected to the first lower upward lead 130 and a second sub-lower inclined lead 132-2 connecting the first sub-lower inclined lead 132-1 to the fourth lower upward lead 134. In the current embodiment, the second lower inclined leads 132-1 and 132-2 include two sub-lower inclined leads, but may include more sub-lower inclined leads.

[0139] The first bonding lead group BG3 constituting the lower bonding lead group LBG3 - 1 may include a third lower bonding portion 146 - 1 . The third lower bonding portion 146-1 includes a third lower bent lead 138, a fifth lower upward lead 140, third lower inclined leads 142-1 and 142-2, and a sixth lower upward lead 144, the third lower bent lead 138 connecting multiple lower semiconductor dies (for example, the sixth to eighth lower semiconductor dies 112, 114, and 116) that are not connected through the first lower bonding portion 126 and the second lower bonding portion 136-1, the fifth lower upward lead 140 connected to the third lower bent lead 138 and extending toward the wiring structure WR3, the third lower inclined leads 142-1 and 142-2 connected to the fifth lower upward lead 140, and the sixth lower upward lead 144 extending toward the wiring structure WR3 to connect the third lower inclined leads 142-1 and 142-2 to the wiring structure WR3.

[0140] The third lower inclined leads 142-1 and 142-2 may include a third sub-lower inclined lead 142-1 connected to the third lower upward lead 140 and a third sub-lower inclined lead 142-2 connecting the third sub-lower inclined lead 142-1 to the sixth lower upward lead 144. In the current embodiment, the third lower inclined leads 142-1 and 142-2 include two sub-lower inclined leads, but may include more sub-lower inclined leads.

[0141] Figures 13 to 18 It is a diagram showing the manufacturing Figure 1 A cross-sectional view of a semiconductor package EM1 is shown.

[0142] Specifically, please refer to Figures 13 to 18 Briefly give or do not repeat previous references Figure 1 The description given. Fig.13 , a lower semiconductor die stack CS1 is formed on a carrier substrate 10. The carrier substrate 10 may include a glass carrier substrate, a silicon carrier substrate, or a ceramic carrier substrate. Alternatively, the carrier substrate 10 may include a wafer.

[0143] A plurality of, for example, four lower semiconductor dies (e.g., a first lower semiconductor die 12, a second lower semiconductor die 14, a third lower semiconductor die 16, and a fourth lower semiconductor die 18) are vertically stacked in a stepped manner on the carrier substrate 10 to extend in a first horizontal direction (X direction) to form a lower semiconductor die stack CS1. The first horizontal direction (X direction) may be horizontal with respect to top surfaces of the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18, and may be a first stepped direction in which the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18 are stacked.

[0144] The first lower semiconductor die 12 , the second lower semiconductor die 14 , the third lower semiconductor die 16 , and the fourth lower semiconductor die 18 may include a first lower die pad cp1 , a second lower die pad cp2 , a third lower die pad cp3 , and a fourth lower die pad cp4 , respectively.

[0145] refer to Fig.14 , forming a lower bonding wire group LBG1 connected to the lower semiconductor die stack CS1. The lower bonding wire group LBG1 may include a first bonding wire group BG1 connecting two lower semiconductor dies selected from the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16, and the fourth lower semiconductor die 18.

[0146] The first bonding lead group BG1 may include a first bonding portion 34, the first bonding portion 34 includes a first bent lead 26, a first upward lead 28, a first inclined lead 30, and a second upward lead 32, the first bent lead 26 connecting the lower semiconductor die (for example, the third lower semiconductor die 16 and the fourth lower semiconductor die 18), the first upward lead 28 connected to the first bent lead 26 and extending from the top surface of the third lower semiconductor die 16 in an upward direction (Z direction), the first inclined lead 30 connected to the first upward lead 28, and the second upward lead 32 extending from the top surface of the third lower semiconductor die 16 in an upward direction (Z direction) and connected to the first inclined lead 30.

[0147] The first bent lead 26 connects the third lower die pad cp3 to the fourth lower die pad cp4. The end of the second upward lead 32 may include a spherical ball bp. The spherical ball bp may be referred to as a free air ball.

[0148] The first bonding lead group BG1 may include a second bonding portion 24 including a second bent lead 20 connecting a plurality of lower semiconductor dies (e.g., the first lower semiconductor die 12 and the second lower semiconductor die 14) that are not connected by the first bonding portion 34, and a third upward lead 22 extending in an upward direction (Z direction) from a top surface of the first lower semiconductor die 12 and connected to the second bent lead 20. The second bent lead 20 may connect the first lower die pad cp1 to the second lower die pad cp2. An end of the third upward lead 22 may include a spherical ball bp.

[0149] refer to Fig.15 , the upper semiconductor die stack CS2 is stacked on the lower semiconductor die stack CS1. A plurality of, for example, four, upper semiconductor die (e.g., a first upper semiconductor die 36, a second upper semiconductor die 38, a third upper semiconductor die 40, and a fourth upper semiconductor die 42) are vertically stacked on the fourth lower semiconductor die 18 in a stepped manner to extend in a first reverse horizontal direction (-X direction) opposite to the first horizontal direction (X direction) to form the upper semiconductor die stack CS2.

[0150] The first reverse horizontal direction (-X direction) can be horizontal relative to the top surfaces of the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42, and can be a second step direction in which the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40 and the fourth upper semiconductor die 42 are stacked, which is opposite to the first step direction of the first lower semiconductor die 12, the second lower semiconductor die 14, the third lower semiconductor die 16 and the fourth lower semiconductor die 18.

[0151] The first upper semiconductor die 36 , the second upper semiconductor die 38 , the third upper semiconductor die 40 , and the fourth upper semiconductor die 42 may include a first upper die pad cp5 , a second upper die pad cp6 , a third upper die pad cp7 , and a fourth upper die pad cp8 , respectively.

[0152] refer to Fig.16 , forming an upper bonding wire group HBG1 connected to the upper semiconductor die stack CS2. The upper bonding wire group HBG1 may include a first bonding wire group BG1 connecting two upper semiconductor dies selected from the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42.

[0153] The first bonding lead group BG1 constituting the upper bonding lead group HBG1 may include a third bonding portion 48 including a third bent lead 44 connecting a plurality of upper semiconductor dies (e.g., the first upper semiconductor die 36 and the second upper semiconductor die 38) and a fourth upward lead 46 extending in an upward direction (Z direction) from a surface of the first upper semiconductor die 36 and connected to the third bent lead 44. The third bent lead 44 may connect the first upper die pad cp5 to the second upper die pad cp6. The end of the fourth upward lead 46 may include a spherical ball bp.

[0154] The upper bonding lead group HBG1 may include a second bonding lead group BG2 connecting one upper semiconductor die selected from the first upper semiconductor die 36, the second upper semiconductor die 38, the third upper semiconductor die 40, and the fourth upper semiconductor die 42. The second bonding lead group BG2 may include a fifth upward lead 50 extending from a top surface of one upper semiconductor die or a lower semiconductor die (e.g., the third upper semiconductor die 40) in an upward direction (Z direction).

[0155] In addition, the second bonding lead group BG2 may include a sixth upward lead 52 extending in an upward direction (Z direction) from a top surface of an upper semiconductor die (eg, fourth upper semiconductor die 42). Ends of the fifth and sixth upward leads 50 and 52 may include spherical balls bp.

[0156] refer to Fig.17 A molding material layer 54 r that molds the lower semiconductor die stack CS1 , the upper semiconductor die stack CS2 , the lower bonding lead group LBG1 , and the upper bonding lead group HBG1 is formed on the carrier substrate 10 .

[0157] Subsequently, as indicated by reference numeral 56, a molding layer 54 is formed by polishing the molding material layer 54r using the surfaces of the spherical balls bp of the second upward leads 32, the third upward leads 22, the fourth upward leads 46, the fifth upward leads 50, and the sixth upward leads 52 as etching stops.

[0158] refer to Fig.18 , a wiring structure WR1 is formed on the mold layer 54. The spherical balls bp at the ends of the second upward lead 32, the third upward lead 22, the fourth upward lead 46, the fifth upward lead 50, and the sixth upward lead 52 are attached to the internal wiring pads 58 of the wiring board 64 using a process such as a thermal compression method. The spherical balls bp at the ends of the second upward lead 32, the third upward lead 22, the fourth upward lead 46, the fifth upward lead 50, and the sixth upward lead 52 are attached to the internal wiring pads 58 of the wiring board 64 by a process such as a thermal compression method. The external connection terminals 66 are formed on the external wiring pads 60 of the wiring board 64.

[0159] Subsequently, the carrier substrate 10 may be removed to complete the Figures 1 to 4 The illustrated semiconductor package EM1. In some embodiments, the carrier substrate 10 may be removed immediately after the molding layer 54 is formed. The carrier substrate 10 may be removed by irradiating ultraviolet rays onto the carrier substrate 10.

[0160] Figures 19 to 24 It is a diagram showing the manufacturing Fig. 9 A cross-sectional view of a method for a semiconductor package.

[0161] Specifically, please refer to Figures 19 to 24 Simply give or omit references Fig. 9 A description of the item given previously. Fig.19, a lower semiconductor die stack CS1-1 is formed on the carrier substrate 10. A plurality of, for example, eight lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 are vertically stacked on the carrier substrate 10 in a stepped manner to extend in a first horizontal direction (X direction) to form the lower semiconductor die stack CS1-1.

[0162] The first horizontal direction (X direction) may be horizontal with respect to top surfaces of the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116, and may be a first step direction in which the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116 are stacked.

[0163] The first lower semiconductor die 102, the second lower semiconductor die 104, the third lower semiconductor die 106, the fourth lower semiconductor die 108, the fifth lower semiconductor die 110, the sixth lower semiconductor die 112, the seventh lower semiconductor die 114 and the eighth lower semiconductor die 116 may respectively include a first lower die pad cp1, a second lower die pad cp2, a third lower die pad cp3, a fourth lower die pad cp4, a fifth lower die pad cp5, a sixth lower die pad cp6, a seventh lower die pad cp7 and an eighth lower die pad cp8.

[0164] refer to Fig. 20 , forming a lower bonding wire group LBG3 connected to the lower semiconductor die stack CS1-1. The lower bonding wire group LBG3 may include a first bonding wire group BG3 connected to a plurality of lower semiconductor dies selected from the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114, and 116.

[0165] The lower bonding lead group LBG3 may include a first lower bonding portion 126. The first lower bonding portion 126 may include a first lower bent lead 118 connecting the first lower semiconductor die 102 and the second lower semiconductor die 104, a first lower upward lead 120 connected to the first lower bent lead 118 and extending from the surface of the first lower semiconductor die 102 in an upward direction (Z direction), a first lower inclined lead 122 connected to the first lower upward lead 120, and a second lower upward lead 124 connected to the first lower inclined lead 122 and extending from the surface of the first lower semiconductor die 102 in an upward direction (Z direction).

[0166] The first lower bent lead 118 may connect the first lower die pad cp1 to the second lower die pad cp2. An end of the second lower upward lead 124 may have a flat surface. In some embodiments, an end of the second lower upward lead 124 may include a spherical ball.

[0167] The lower bonding lead group LBG3 may include a second lower bonding portion 136. The second lower bonding portion 136 may include a second lower bent lead 128 connecting the third to fifth lower semiconductor dies 106, 118, and 120 that are not connected through the first lower bonding portion 126, a third lower upward lead 130 connected to the second lower bent lead 128 and extending from the surface of the third lower semiconductor die 106 in an upward direction (Z direction), a second lower inclined lead 132 connected to the third lower upward lead 130, and a fourth lower upward lead 134 extending from the surface of the third lower semiconductor die 106 in an upward direction (Z direction) and connected to the second lower inclined lead 132.

[0168] The second lower bent lead 128 may connect the third lower die pad cp3, the fourth lower die pad cp4, and the fifth lower die pad cp5. The end of the fourth lower upward lead 134 may have a flat surface. In some embodiments, the end of the fourth lower upward lead 134 may include a spherical ball.

[0169] The lower bonding lead group LBG3 may include a third lower bonding portion 146. The third lower bonding portion 146 may include a third lower bent lead 138 connecting the sixth to eighth lower semiconductor dies 112, 114, and 116 that are not connected through the first lower bonding portion 126 and the second lower bonding portion 136, a fifth lower upward lead 140 connected to the third lower bent lead 138 and extending from the surface of the sixth lower semiconductor die 112 in an upward direction (Z direction), a third lower inclined lead 142 connected to the fifth lower upward lead 140, and a sixth lower upward lead 144 connected to the third lower inclined lead 142 and extending from the surface of the sixth lower semiconductor die 112 in an upward direction (Z direction).

[0170] The third lower bent lead 138 may connect the sixth lower die pad cp6, the seventh lower die pad cp7, and the eighth lower die pad cp8. The end of the sixth lower upward lead 144 may have a flat surface. In some embodiments, the end of the sixth lower upward lead 144 may include a spherical ball.

[0171] refer to Fig.21 , the upper semiconductor die stack CS2-1 is stacked on the lower semiconductor die stack CS1-1. The upper semiconductor die stack CS2-1 is formed by vertically stacking a plurality of, for example, eight upper semiconductor dies 148, 150, 152, 154, 156, 158, 160, and 162 in a stepped manner to extend in a first reverse horizontal direction (-X direction) opposite to the first horizontal direction.

[0172] The first reverse horizontal direction (-X direction) can be horizontal relative to the top surfaces of the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162, and can be a second step direction in which the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162 are stacked, which is opposite to the first step direction of the first to eighth lower semiconductor dies 102, 104, 106, 108, 110, 112, 114 and 116.

[0173] The first upper semiconductor die 148, the second upper semiconductor die 150, the third upper semiconductor die 152, the fourth upper semiconductor die 154, the fifth upper semiconductor die 156, the sixth upper semiconductor die 158, the seventh upper semiconductor die 160 and the eighth upper semiconductor die 162 may respectively include a first upper die pad cp9, a second upper die pad cp10, a third upper die pad cp11, a fourth upper die pad cp12, a fifth upper die pad cp13, a sixth upper die pad cp14, a seventh upper die pad cp15 and an eighth upper die pad cp16.

[0174] refer to Fig. 22 , forming an upper bonding wire group HBG3 connected to the upper semiconductor die stack CS2-1. The upper bonding wire group HBG3 may include a second bonding wire group BG3-1 connected to a plurality of upper semiconductor dies selected from the first to eighth upper semiconductor dies 148, 150, 152, 154, 156, 158, 160 and 162.

[0175] The upper bonding lead group HBG3 may include a first upper bonding portion 168. The first upper bonding portion 168 may include a first upper bent lead 164 connecting the first upper semiconductor die 148 and the second upper semiconductor die 150 and a first upper upward lead 166 connected to the first upper bent lead 164 and extending from the surface of the first upper semiconductor die 148 in an upward direction (Z direction).

[0176] The first upper bent lead 164 may connect the first upper die pad cp9 to the second upper die pad cp10. The end of the first upper upward lead 166 may have a flat surface. In some embodiments, the end of the first upper upward lead 166 may include a spherical ball.

[0177] The upper bonding lead group HBG3 may include a second upper bonding portion 174 that is not connected by the first upper bonding portion 168. The second upper bonding portion 174 may include a second upper bent lead 170 connecting the third to fifth upper semiconductor dies 152, 154, and 156, and a second upper upward lead 172 connected to the second upper bent lead 170 and extending from the surface of the third upper semiconductor die 152 in an upward direction (Z direction).

[0178] The second upper bent lead 164 may connect the third upper die pad cp11, the fourth upper die pad cp12, and the fifth upper die pad cp13. The end of the second upper upward lead 172 may have a flat surface. In some embodiments, the end of the second upper upward lead 172 may include a spherical ball.

[0179] The upper bonding lead group HBG3 may include a third upper bonding portion 180 that is not connected by the first upper bonding portion 168 and the second upper bonding portion 174. The third upper bonding portion 180 may include a third upper bent lead 176 that connects the sixth to eighth upper semiconductor dies 158, 160, and 162, and a third upper upward lead 178 that is connected to the third upper bent lead 176 and extends from the surface of the sixth upper semiconductor die 158 in an upward direction (Z direction).

[0180] The third upper bent lead 176 may connect the sixth upper die pad cp14, the seventh upper die pad cp15, and the eighth upper die pad cp16. The end of the third upper upward lead 178 may have a flat surface. In some embodiments, the end of the third upper upward lead 178 may include a spherical ball.

[0181] refer to Fig.23 A molding material layer 182 r is formed on the carrier substrate 10 to mold the lower semiconductor die stack CS1 - 1 , the upper semiconductor die stack CS2 - 1 , the lower bonding lead group LBG3 , and the upper bonding lead group HBG3 .

[0182] Subsequently, as indicated by reference numeral 183, a molding layer 182 is formed by polishing the molding material layer 182r using the surfaces of the second lower upward lead 124, the fourth lower upward lead 134, the sixth lower upward lead 144, the first upper upward lead 166, the second upper upward lead 172 and the third upper upward lead 178 as etching stop points.

[0183] refer to Fig.24 , a wiring structure WR3 is formed on the mold layer 182. The surfaces of the second lower upward lead 124, the fourth lower upward lead 134, the sixth lower upward lead 144, the first upper upward lead 166, the second upper upward lead 172, and the third upper upward lead 178 are attached to the internal wiring pad 184 of the wiring board 190 by a thermal compression method. The external connection terminal 192 is formed on the external wiring pad 186 of the wiring board 190.

[0184] Subsequently, the carrier substrate 10 may be removed to complete the Figures 9 to 11 The semiconductor package EM6 is shown. In some embodiments, the carrier substrate 10 may be removed immediately after the molding layer 182 is formed. The carrier substrate 10 may be removed by irradiating ultraviolet rays onto the carrier substrate 10 .

[0185] Figure 25 to Figure 28 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0186] Specifically, Figure 25 to Figure 28 It is provided to explain a process of connecting two semiconductor dies 202 and 206 with bonding wires by using a bonding device. The first semiconductor die 202 and the second semiconductor die 206 may include the lower semiconductor die or the upper semiconductor die described above.

[0187] refer to Fig.25 , the second semiconductor die 206 is step-mounted on the first semiconductor die 202. A first die pad 204 may be formed on the first semiconductor die 202. A second die pad 208 may be formed on the second semiconductor die 206. A bonding device 309 may be positioned on the second die pad 208 to form a ball bump 301 on the bonding wire 305.

[0188] The bonding device 309 is positioned on the second die pad 208 of the second semiconductor die 206. The bonding device 309 includes a guide element 307 and a capillary element 306. A through hole 303 is formed in the bonding device 309 (i.e., the guide element 307 and the capillary element 306). After the bonding wire 305 is passed through the through hole 303, a ball bump 301 is formed at one end of the bonding wire 305.

[0189] The ball bump 301 may be formed by generating discharge (eg, spark discharge) at one end of the bonding wire 305. The discharge may be generated at one end of the bonding wire 305 by using a spark electrode included inside or outside the bonding device 309.

[0190] refer to Fig.26 After bonding the ball bump 301 on the second die pad 208 of the second semiconductor die 206 , a bonding device 309 including a bonding wire 305 is moved to the top of the first die pad 204 .

[0191] Specifically, the ball bump 301 is first bonded onto the second die pad 208 of the second semiconductor die 206. That is, the bonding device 309 is lowered to bond the ball bump 301 formed at the end of the bonding wire 305 onto the second die pad 208. The ball bump 301 formed at the end of the bonding wire 305 is bonded to the second die pad 208 in a compression method such as a thermal compression method. The method of forming the ball bump 301 and then bonding the ball bump 301 may be referred to as a ball bonding method.

[0192] If necessary, the bonding wire 305 may be directly bonded to the second die pad 208 without forming a ball bump at the end of the bonding wire 305. The method of not forming a ball bump at the end of the bonding wire 305 may be referred to as a stitch bonding method or a wedge bonding method. Subsequently, the bonding device 309 including the bonding wire 305 is moved to the top of the first die pad 204 of the first semiconductor die 202.

[0193] refer to Fig. 27 , attaching the bonding wire 305 to the first die pad 204 of the first semiconductor die 202. That is, the bonding device 309 is moved and lowered to position the bonding wire 305 on the first die pad 204 of the first semiconductor die 202.

[0194] The bonding wire 305 is moved onto the first die pad 204 and directly attached to the first die pad 204 by using a bonding device 309. The bonding wire 305 may be directly bonded to the first die pad 204 by a compression method (e.g., a thermal compression method) without forming a ball bump at the end of the bonding wire 305. Therefore, the bonding wire 305 may form a ring-shaped bent lead component 310r from the second die pad 208 to the first die pad 204 in a horizontal direction.

[0195] As described above, a method of not forming a ball bump at the end of the bonding wire 305 may be referred to as a stitch bonding method. If necessary, a ball bonding method of forming a ball bump at the end of the bonding wire 305 and then bonding the bonding wire 305 to the first die pad 204 may be used.

[0196] Then, the bonding device 309 including the bonding wire 305 moves upward relative to the top of the first die pad 204 of the first semiconductor die 202. Then, the bonding device 309 including the bonding wire 305 moves continuously in an oblique upward direction relative to the top of the first die pad 204 of the first semiconductor die 202.

[0197] In this case, the bonding lead 305 may include a first upward lead component 311r formed from the surface of the first die pad 204 in an upward direction, an inclined lead component 312r formed from the first upward lead component 311r in an inclined direction, and a second upward lead component 313r formed from the inclined lead component 312r in an upward direction.

[0198] refer to Fig.28 , before cutting the bonding wire 305 (reference Fig. 27 ) can then be bonded to the wire 305 (reference Fig. 27 ) is formed as a bonding lead group BG. The bonding lead group BG may include a ring-shaped bent lead 310 extending from the second die pad 208 to the first die pad 204 in a horizontal direction, a first upward lead 311 extending from the surface of the first die pad 204 in an upward direction, an inclined lead 312 extending from the first upward lead 311 in an inclined direction, and a second upward lead 313 extending from the inclined lead 312 in an upward direction. In some embodiments, a spherical ball BP may be formed by generating a spark at the end of the second upward lead 313 using a spark generating device 401.

[0199] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a lower semiconductor die stack in which a plurality of lower semiconductor die are vertically stacked in a stepped manner to extend in a first horizontal direction; an upper semiconductor die stack in which a plurality of upper semiconductor die are vertically stacked in a stepped manner on the lower semiconductor die stack to extend in a first reverse horizontal direction opposite to the first horizontal direction; a wiring structure located above the upper semiconductor die stack; as well as a set of bonding wires connecting the lower semiconductor die and the upper semiconductor die to the wiring structure, wherein the set of bonding wires includes a first set of bonding wires connecting a first plurality of semiconductor dies selected from the lower semiconductor die and the upper semiconductor die to the wiring structure, and Among them, the first bonding lead group includes a first bonding part, the first bonding part includes a first bent lead, a first upward lead, a first inclined lead and a second upward lead, the first bent lead connects the second plurality of semiconductor dies among the first plurality of semiconductor dies, the first upward lead is connected to the first bent lead and extends toward the wiring structure, the first inclined lead is connected to the first upward lead, and the second upward lead extends toward the wiring structure to connect the first inclined lead to the wiring structure.

2. The semiconductor package according to claim 1, wherein: The first inclined lead includes a first sub-inclined lead connected to the first upward lead and a second sub-inclined lead connecting the first sub-inclined lead to the second upward lead.

3. The semiconductor package according to claim 1, wherein: The first bonding lead group also includes a second bonding portion, the second bonding portion includes a second bent lead and a third upward lead, the second bent lead connects a third plurality of semiconductor dies among the first plurality of semiconductor dies that are not connected by the first bonding portion, and the third upward lead extends toward the wiring structure to connect the second bent lead to the wiring structure.

4. The semiconductor package according to claim 1, wherein: The set of bonding wires also includes a second set of bonding wires connecting a single upper semiconductor die or a single lower semiconductor die selected from the lower semiconductor die and the upper semiconductor die to the wiring structure.

5. The semiconductor package according to claim 4, wherein: The second bonding lead group includes a fourth upward lead extending toward the wiring structure to connect the single upper semiconductor die or the single lower semiconductor die to the wiring structure.

6. The semiconductor package according to claim 1, wherein: The end of the second upward lead connected to the wiring structure has a spherical or hemispherical shape.

7. The semiconductor package according to claim 1, wherein: The wiring structure includes a wiring board or a redistribution structure.

8. The semiconductor package according to claim 1, wherein: A connection solder ball is further formed on the second upward lead, and the connection solder ball is connected to the wiring structure.

9. The semiconductor package according to claim 1, wherein: A first connection point between the first upward lead and the first inclined lead is configured to vertically overlap some of the upper semiconductor dies.

10. A semiconductor package, comprising: a lower semiconductor die stack in which a plurality of lower semiconductor die are vertically stacked in a stepped manner to extend in a first horizontal direction; an upper semiconductor die stack in which a plurality of upper semiconductor die are vertically stacked in a stepped manner on the lower semiconductor die stack to extend in a first reverse horizontal direction opposite to the first horizontal direction; a wiring structure located above the upper semiconductor die stack; as well as a bonding lead group connecting the lower semiconductor die and the upper semiconductor die to the wiring structure, wherein the bonding lead group includes a first bonding lead group and a second bonding lead group, the first bonding lead group including bonding leads connecting a first plurality of semiconductor die selected from the lower semiconductor die and the upper semiconductor die to the wiring structure, the second bonding lead group including bonding leads connecting a single semiconductor die of the upper semiconductor die or the lower semiconductor die to the wiring structure, wherein the first bonding lead group includes a first bonding portion, the first bonding portion includes a first bent lead, a first upward lead, a first inclined lead, and a second upward lead, the first bent lead connecting a second plurality of semiconductor die of the first plurality of semiconductor die, the first upward lead connected to the first bent lead and extending toward the wiring structure, the first inclined lead connected to the first upward lead, the second upward lead extending toward the wiring structure to connect the first inclined lead to the wiring structure, and The bonding wires of the second bonding wire group each include a fifth upward lead extending toward the wiring structure to connect the single semiconductor die of the upper semiconductor die or the lower semiconductor die to the wiring structure.

11. The semiconductor package according to claim 10, wherein: The first bonding lead group also includes a second bonding portion, the second bonding portion includes a second bent lead and a third upward lead, the second bent lead connects a third plurality of semiconductor dies among the first plurality of semiconductor dies that are not connected by the first bonding portion, and the third upward lead extends toward the wiring structure to connect the second bent lead to the wiring structure.

12. The semiconductor package according to claim 10, wherein: The first bonding lead group also includes a third bonding portion, the third bonding portion includes a third bent lead and a fourth upward lead, the third bent lead connects a fourth plurality of semiconductor dies among the first plurality of semiconductor dies that are not connected by the first bonding portion and the second bonding portion, and the fourth upward lead extends toward the wiring structure to connect the third bent lead to the wiring structure.

13. The semiconductor package according to claim 10, wherein: A second connection point between the second upward lead and the first inclined lead is configured not to vertically overlap the upper semiconductor die.

14. The semiconductor package according to claim 10, wherein: The lower semiconductor die stack and the upper semiconductor die stack each include four semiconductor dies.

15. The semiconductor package according to claim 10, wherein: The end of the second upward lead connected to the wiring structure has a spherical or hemispherical shape.

16. A semiconductor package, comprising: a lower semiconductor die stack in which a plurality of lower semiconductor die are vertically stacked in a stepped manner to extend in a first horizontal direction; an upper semiconductor die stack in which a plurality of upper semiconductor die are vertically stacked in a stepped manner on the lower semiconductor die stack to extend in a first reverse horizontal direction opposite to the first horizontal direction; a wiring structure located above the upper semiconductor die stack; a lower bonding lead set connecting the lower semiconductor die to the wiring structure, wherein the lower bonding lead set includes a first lower bonding portion, the first lower bonding portion includes a first lower bent lead, a first lower upward lead, a first lower inclined lead, and a second lower upward lead, the first lower bent lead connecting at least two of the lower semiconductor dies, the first lower upward lead connected to the first lower bent lead and extending toward the wiring structure, the first lower inclined lead connected to the first lower upward lead, and the second lower upward lead extending toward the wiring structure to connect the first lower inclined lead to the wiring structure; and An upper bonding lead group electrically connects the upper semiconductor die to the wiring structure, wherein the upper bonding lead group includes a first upper bonding portion, the first upper bonding portion includes a first upper bent lead and a first upper upward lead, the first upper bent lead connects at least two of the upper semiconductor dies, and the first upper upward lead extends toward the wiring structure to connect the first upper bent lead to the wiring structure.

17. The semiconductor package according to claim 16, wherein: The first lower inclined lead includes a first sub-lower inclined lead connected to the first lower upward lead and a second sub-lower inclined lead connecting the first sub-lower inclined lead to the second lower upward lead.

18. The semiconductor package according to claim 16, wherein: The lower bonding lead group also includes a second lower bonding portion, which includes a second lower bent lead, a second lower upward lead, a second lower inclined lead and a third lower upward lead, the second lower bent lead connecting at least two of the lower semiconductor dies that are not connected by the first lower bonding portion, the second lower upward lead connected to the second lower bent lead and extending toward the wiring structure, the second lower inclined lead connected to the second lower upward lead, and the third lower upward lead extending toward the wiring structure to connect the second lower inclined lead to the wiring structure.

19. The semiconductor package according to claim 16, wherein: The upper bonding lead group includes a second upper bonding portion, the second upper bonding portion includes a second upper bent lead and a second upper upward lead, the second upper bent lead connects at least two of the upper semiconductor dies that are not connected by the first upper bonding portion, and the second upper upward lead extends toward the wiring structure to connect the second upper bent lead to the wiring structure.

20. The semiconductor package according to claim 16, wherein The lower semiconductor die stack and the upper semiconductor die stack each include eight semiconductor dies.

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