Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package may include: a package substrate; a plurality of upper dies on an upper side of the package substrate and arranged so as not to vertically overlap each other; a plurality of electrical connection structures between the plurality of upper dies and the package substrate and electrically connected to the package substrate; a lower die on the package substrate and arranged so as not to vertically overlap the plurality of electrical connection structures; and a plurality of stacked electrical connection structures disposed between the plurality of upper dies and the upper surface of the lower die, and electrically connected to the upper surface of the lower die. Each of the plurality of upper dies may include a plurality of memory dies vertically stacked on one another.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0107139 filed in the Korean Intellectual Property Office on August 16, 2023, and the entire contents of the above application are incorporated herein by reference for all purposes. Technical Field

[0002] The inventive concept relates to a semiconductor package. Background Art

[0003] Recently, there is a demand for improved performance and / or increased capacity of semiconductor packages to be installed in electronic devices. Therefore, semiconductor packages including multiple dies are being developed, and data transmission speeds of signals sent and received between the multiple dies are gradually increasing. For example, semiconductor packages may be implemented with high bandwidth memory (HBM), and it may be desirable that the size (e.g., planar size) of the semiconductor package may be limited or reduced. Summary of the invention

[0004] Certain aspects of the present disclosure provide semiconductor packages that can achieve or exhibit improved performance and / or increased capacity, and can do so in a relatively efficient manner.

[0005] According to some embodiments, a semiconductor package may include: a packaging substrate; a plurality of upper dies, each of which is arranged on the upper side of the packaging substrate so as not to be vertically stacked with other upper dies in the plurality of upper dies, and each upper die includes a plurality of memory dies stacked vertically; a plurality of electrical connection structures, between the plurality of upper dies and the packaging substrate, the plurality of electrical connection structures being electrically connected to the packaging substrate; a lower die, on the packaging substrate, and arranged so as not to be vertically stacked with the plurality of electrical connection structures; and a plurality of stacked electrical connection structures, arranged between the plurality of upper dies and the upper surface of the lower die, the plurality of stacked electrical connection structures being electrically connected to the upper surface of the lower die.

[0006] According to some embodiments, a semiconductor package may include: a packaging substrate; a plurality of upper dies, each of which is arranged not to be vertically overlapped with other upper dies in the plurality of upper dies, above the packaging substrate; a plurality of electrical connection structures, between the plurality of upper dies and the packaging substrate, the plurality of electrical connection structures being electrically connected to the packaging substrate; and a lower die, on the packaging substrate, and arranged not to be vertically overlapped with the plurality of electrical connection structures. Each of the plurality of upper dies may partially vertically overlap with the lower die, and the plurality of electrical connection structures may be arranged asymmetrically with respect to respective centers of the plurality of upper dies.

[0007] According to some embodiments, a semiconductor package may include: a packaging substrate; at least one upper die on the packaging substrate; a plurality of electrical connection structures between the at least one upper die and the packaging substrate, the plurality of electrical connection structures being electrically connected to the packaging substrate; a lower die on the packaging substrate and arranged not to be vertically overlapped with the plurality of electrical connection structures; an encapsulant sealing the plurality of electrical connection structures and the lower die; and at least one buffer die electrically connected between the at least one upper die and the plurality of electrical connection structures and electrically connected to the at least one upper die and the plurality of electrical connection structures. The lower surface of the buffer die may be in direct contact with the encapsulant. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1A is a perspective view illustrating a semiconductor package according to some embodiments.

[0010] Figure 1B is a cross-sectional view illustrating a semiconductor package according to some embodiments.

[0011] FIG. 2A to FIG. 2C is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments.

[0012] FIG. 3A to FIG. 3C is a perspective view illustrating a semiconductor package according to some embodiments.

[0013] Figure 4A and Figure 4B is a perspective view illustrating a semiconductor package according to some embodiments.

[0014] FIG. 5A to FIG. 5D is a plan view showing a semiconductor package according to some embodiments.

[0015] FIG. 6A to FIG. 6D is a cross-sectional view illustrating a semiconductor package according to some embodiments.

[0016] Fig. 7A and Figure 7B is a cross-sectional view illustrating a semiconductor package according to some embodiments.

[0017] Fig. 8A is a block diagram illustrating connections between dies of a semiconductor package according to some embodiments.

[0018] Figure 8B is a block diagram illustrating a memory die of each of a plurality of upper dies of a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0019] Hereinafter, some examples of the embodiments will be described with reference to the accompanying drawings.

[0020] The detailed description of the inventive concept described below refers to the accompanying drawings, which are shown in the form of example specific embodiments that can practice the inventive concept. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments are different from each other, but are not necessarily mutually exclusive. For example, without departing from the spirit and scope of the invention, the specific shapes, structures and characteristics described herein for one embodiment can be implemented in other embodiments. In addition, it should be understood that the position or arrangement of each component within each disclosed embodiment can be changed without departing from the spirit and scope of the invention. Therefore, the following detailed description is not intended to be understood in a limiting sense, and the scope of the inventive concept is limited only by the attached claims and all equivalents claimed in those claims. Similar reference numerals in the drawings represent the same or similar functions throughout various aspects.

[0021] Hereinafter, in order for those skilled in the art to easily practice the inventive concept, embodiments will be described in detail with reference to the accompanying drawings.

[0022] Figure 1A is a perspective view showing a plurality of upper dies 60 connected to upper ends of a plurality of electrical connection structures 130 of a semiconductor package (PKG1) according to some embodiments, and Figure 1B yes Figure 1A A cross-sectional view of the semiconductor package PKG1 when the semiconductor package PKG1 is cut along an XZ plane from a Y-direction perspective. Figure 1A One of the memory dies 61, 62, 63 and 64 is in Figure 1B is omitted, and Figure 1B The encapsulant 140 Figure 1A is omitted.

[0023] Reference Figure 1A and Figure 1B , a semiconductor package (PKG1) according to example embodiments may include a package substrate 110 , a plurality of upper dies 60 , a plurality of electrical connection structures 130 , and a lower die 120 , and may further include a buffer die 70 and / or a plurality of stacked electrical connection structures 127 .

[0024] The package substrate 110 may have a structure in which at least one wiring layer and at least one insulating layer 111 are alternately stacked, and may be a printed circuit board, but the present disclosure is not limited thereto. At least one wiring layer may include a signal line 112SL and / or a power line 112PL, and may include a redistribution line according to the design. In addition, according to the design, at least one wiring layer and its signal line 112SL and / or power line 112PL may protrude on the upper and lower surfaces of the package substrate 110, and may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) and / or titanium (Ti), or an alloy of at least one of them. At least one insulating layer 111 may include a prepreg, but the present disclosure is not limited thereto. For example, the insulating layer 111 may also include at least one of a photosensitive insulating material (such as a photoimageable dielectric (PID) resin), a build-up film (such as Ajinomoto Build-up Film (ABF)), a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), a resin mixed with an inorganic filler, FR-4 (flame retardant), and bismaleimide triazine (BT).

[0025] The lower die 120 may be on the package substrate 110, and the plurality of upper dies 60 and the buffer die 70 may be on the package substrate 110. The lower die 120 may include a semiconductor substrate 120M, circuit layers 120F and 120B, and a pad 120P. Each of the plurality of upper dies 60 may include a semiconductor substrate 60M, circuit layers 60F and 60B, pads 60P and 65P, and through vias 60V, and each of the buffer dies 70 may include a semiconductor substrate 70M, circuit layers 70F and 70B, pads 70P, and through vias 70V.

[0026] For example, each of the semiconductor substrates 60M, 70M, and 120M may include a semiconductor element such as silicon and / or germanium or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP), and each of the semiconductor substrates 60M, 70M, and 120M may be implemented as or based on a wafer. The semiconductor substrates 60M and 70M may have a polygonal structure through which the through vias 60V and 70V pass, and the semiconductor substrate 120M may have a polygonal structure through which the through vias do not penetrate or a polygonal structure in which no through vias are provided. Each of the circuit layers 60F, 60B, 70F, 70B, 120F, and 120B may include an insulating layer (e.g., including silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and / or silicon carbonitride (SiCN), or a combination of two or more thereof) and wiring, and may be implemented as a front-end process (FEOL) or a back-end process (BEOL). For example, the wiring and pads (60P, 65P, 70P, 120P) and through vias (60V, 70V) may include aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof.

[0027] The device layer of each die (e.g., the upper die 60, the buffer die 70, and the lower die 120) may be between the semiconductor substrate (60M, 70M, 120M) and its circuit layer (60F, 70F, 120F), and may include transistors constituting the integrated circuit. For example, the transistors constituting the integrated circuit in each device layer may include a planar metal oxide semiconductor FET (MOSFET), a FinFET in which the active region has a fin structure, a multi-bridge channel FET (MBCFET), and a MOSFET. TM ) or a gate-all-around transistor including a plurality of channels vertically stacked on an active area, or a vertical FET (VFET), but the inventive concept is not limited thereto. The integrated circuit may be a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor (DSP), other digital processors or signal processors, a cryptographic processor, a controller or an application specific integrated circuit (ASIC), etc., and / or may also include a volatile memory device (such as DRAM, static RAM (SRAM), etc.) and / or a non-volatile memory device (such as PRAM, MRAM, ReRAM and flash memory device, etc.).

[0028] The semiconductor substrate 60M, 70M and 120M may support the device layer. The circuit layer 60F, 70F and 120F may provide an electrical connection path between the device layer and the pad 60P, 65P, 70P and 120P, and the circuit layer 60F, 70F and 120F may support the pad 60P, 65P, 70P and 120P. The pad 60P, 65P, 70P and 120P may provide an electrical connection path between the circuit layer 60F, 70F and 120F and a device or component outside the die. The through vias 60V and 70V may provide an electrical connection path upward from the device layer, and the circuit layer 60B and 70B may provide an electrical connection path upward from the through vias 60V and 70V.

[0029] The design of the device layer of each die may be affected by the through vias (60V, 70V) that provide electrical connection paths for the device layer. Therefore, the design of the device layer of a die without through vias (60V, 70V) or with very few through vias (60V, 70V) can be said to be freer or more free than the design of the device layer of a die containing through vias (60V, 70V). The freer the design of the device layer, the higher the design efficiency of the device layer can be. As the design efficiency of the device layer increases, the performance related to the die size can be higher.

[0030] The design freedom / efficiency of the lower die 120 may be improved because the lower die 120 may not include through-vias or may include only limited through-vias near the corners of the lower die 120. However, if the lower die 120 does not include through-vias or almost does not include through-vias, since the lower die 120 may only provide an electrical connection path on one of the upper surface and the lower surface of the lower die 120, the freedom of designing the arrangement / connection relationship between the lower die 120 and the plurality of upper dies 60 may be further reduced.

[0031] The plurality of upper dies 60 may not be stacked vertically with each other, and each of the plurality of upper dies 60 may include a plurality of memory dies 61, 62, 63, and 64 stacked vertically with each other. For example, the integrated circuit of the device layer of the plurality of memory dies 61, 62, 63, and 64 may include a volatile memory device (such as DRAM, SRAM (static RAM), etc.) or a non-volatile memory device (such as PRAM, MRAM, ReRAM, and flash memory device). For example, the plurality of memory dies 61, 62, 63, and 64 include a plurality of channels (CELL_CH or CELL CH) with independent interfaces, and may be a memory device in the form of HBM (high bandwidth memory) with increased bandwidth.

[0032] As the number of memory dies 61, 62, 63, and 64 increases, the performance (e.g., bandwidth, storage capacity) of the memory device can be improved. The higher the degree of design freedom of the arrangement / connection relationship between the lower die 120 and the plurality of upper dies 60, the further the number (and / or total size) of the plurality of memory dies 61, 62, 63, and 64 can be increased compared to the size of the semiconductor package PKG1.

[0033] The plurality of electrical connection structures 130 may not be vertically overlapped with the lower die 120, and at least a portion of the plurality of electrical connection structures 130 may be used as a signal path between the lower die 120 and the plurality of memory dies 61, 62, 63, and 64. Therefore, the degree of freedom in designing the arrangement / connection relationship between the lower die 120 and the plurality of upper dies 60 may be improved. The plurality of electrical connection structures 130 may be arranged to be vertically overlapped with the plurality of upper dies 60 and the package substrate 110, and may be electrically connected between the plurality of upper dies 60 and the package substrate 110. The plurality of electrical connection structures 130 may be electrically connected to the plurality of upper dies 60 through the buffer die 70, and at least a portion of the plurality of electrical connection structures 130 may be electrically connected to the lower die 120 through the package substrate 110.

[0034] Therefore, the semiconductor package PKG1 according to some embodiments can increase (e.g., can effectively increase) the number of multiple memory dies 61, 62, 63, and 64 (e.g., 12, 16), and the performance (e.g., bandwidth, storage capacity) of the memory device can be improved (e.g., can effectively be improved). In addition, the semiconductor package PKG1 can exclude or almost exclude through-vias from the lower die 120, and the design freedom / efficiency of the lower die 120 can be improved, and the performance (e.g., speed) of the lower die 120 can also be improved (e.g., can also be effectively improved).

[0035] The plurality of stacked electrical connection structures 127 may be between the plurality of upper dies 60 and the upper surface of the lower die 120 and electrically connected to the upper surface of the lower die 120, and may be used as a signal path between the plurality of upper dies 60 and the lower die 120. The plurality of stacked electrical connection structures 127 may be vertically stacked with the plurality of upper dies 60, and thus may be disposed adjacent to respective corners of the upper surface of the lower die 120. The vertical length of each of the plurality of stacked electrical connection structures 127 may be shorter than the vertical length of each of the plurality of electrical connection structures 130.

[0036] The signal paths of the plurality of stacked electrical connection structures 127 and the signal paths of the plurality of electrical connection structures 130 may be parallel to each other, and the length of the signal path of each of the plurality of stacked electrical connection structures 127 may be shorter than the length of the signal path of each of the plurality of electrical connection structures 130. Therefore, the signal paths between the plurality of upper dies 60 and the lower die 120 may include both relatively long signal paths (e.g., passing through the plurality of electrical connection structures 130) and relatively short signal paths (e.g., passing through the plurality of stacked electrical connection structures 127), and the interface design flexibility / optimality between the plurality of upper dies 60 and the lower die 120 may be further improved. In addition, due to the presence of the plurality of stacked electrical connection structures 127, it may be advantageous for the plurality of upper dies 60 to be placed in closer contact with each other, and the performance (e.g., storage capacity, interface speed) associated with the unit size of the plurality of upper dies 60 may be further improved.

[0037] For example, the plurality of stacked electrical connection structures 127 may include stacked bumps 127C and stacked pads 127P. A first stacked pad among the stacked pads 127P may be on the upper surface of the lower die 120, and the remaining stacked pads among the stacked pads 127P (e.g., a second stacked pad among the stacked pads 127P) may be above the first stacked pad among the stacked pads 127P. The stacked bumps 127C may be connected and fixed between the first stacked pad among the stacked pads 127P and the remaining stacked pads among the stacked pads 127P. For example, the stacked pads 127P may be implemented in substantially the same manner as the pads 60P, 65P, 70P, and 120P (e.g., the same material, the same shape), and the stacked bumps 127C may be formed of a conductive material having a lower melting point than that of the stacked pads 127P (e.g., lead (Pb), tin (Sn), an alloy thereof (Sn-Ag-Cu)) or solder. The stack bump 127C may be connected and fixed to the stack pad 127P through a thermal compression bonding (TCB) process or a reflow process.

[0038] The plurality of electrical connection structures 130 may be in the form of metal pillars extending up and down (e.g., in the form of Cu pillars), but the present disclosure is not limited thereto. For example, the plurality of electrical connection structures 130 may be implemented as bumps or solder balls. In some embodiments, the plurality of electrical connection structures 130 implemented as bumps or solder balls may be implemented larger in a manner similar to the stacked bumps 127C.

[0039] The bump 125C may be connected and fixed between the pad 120P of the lower die 120 and the pad 112P of the package substrate 110, and the lower die 120 may be mounted on the package substrate 110. The bump 65C may be connected and fixed between the pad 65P of the plurality of upper dies 60 and the pad 70P of the plurality of buffer dies 70, or may be connected and fixed between the pad 60P of the plurality of upper dies 60 and the pad 65P of the plurality of upper dies 60. For example, the bumps 65C and 125C may include a conductive material (e.g., lead (Pb), tin (Sn), an alloy thereof (Sn-Ag-Cu)) or solder having a lower melting point than that of the pads (60P, 65P, 70P, 112P, 120P), and the bumps 65C and 125C may be connected and fixed to the pads (60P, 65P, 70P, 112P, 120P) by a thermal compression bonding (TCB) process or a reflow process.

[0040] The plurality of electrical connection structures 130 may be arranged to surround the lower die 120, and thus may be arranged along one or more edges of the upper surface of the package substrate 110. Therefore, the plurality of upper dies 60 may also be arranged along the one or more edges of the upper surface of the package substrate 110. Since the shape of each of the plurality of upper dies 60 may be close to a rectangular parallelepiped, the plurality of upper dies 60 may include (e.g., may be) at least four upper dies 60 arranged not to be vertically stacked on each other. Therefore, from a three-dimensional perspective, the plurality of memory dies 61, 62, 63, and 64 may be arranged in a balanced manner. The number of memory dies 61, 62, 63, and 64 may be more effectively increased. For example, since the ratio of the upper and lower surface (XY plane) area of ​​the combined structure of the plurality of memory dies 61, 62, 63 and 64 to the length in the Z direction and the ratio of the upper and lower surface (XY plane) area of ​​each of the plurality of memory dies 61, 62, 63 and 64 to the length in the Z direction may be similar to each other, the plurality of memory dies 61, 62, 63 and 64 may be arranged in a balanced manner from a three-dimensional perspective. Due to the balanced arrangement, the secondary effect (or "secondary effect") caused by the increase in the number of memory dies 61, 62, 63 and 64 may also be reduced. Therefore, the number of memory dies 61, 62, 63 and 64 may be increased more effectively.

[0041] The Z-direction length (or vertical direction length) of each of the plurality of electrical connection structures 130 may be greater than or equal to the Z-direction thickness (or vertical direction thickness) of the lower die 120. Therefore, the lower surface of the plurality of buffer dies 70 (or, if there is no buffer die 70, the lower surface of the lowest memory die 61 of each upper die 60) may be located at a level not lower than the upper surface of the lower die 120. The lower surface of each of the plurality of buffer dies 70 may be coplanar with the upper surface of the lower die 120 relative to the upper surface of the package substrate 110 or above the upper surface of the lower die 120. Therefore, each of the at least four upper dies 60 may more easily use the space above the lower die 120, and the overall size of the at least four upper dies 60 may be larger. As the overall size of the at least four upper dies 60 increases, the overall performance (e.g., bandwidth, storage capacity) of the at least four upper dies 60 may be further improved. Optionally, the horizontal size of the semiconductor package PKG1 may be reduced in an effective manner.

[0042] Since each of the plurality of upper dies 60 can use the space above the lower die 120, each of the plurality of upper dies 60 can partially vertically overlap with the lower die 120. For example, since each of the at least four upper dies 60 can use the space above the lower die 120, each of the at least four upper dies 60 can vertically overlap with a corresponding one of the four corners of the lower die 120. Therefore, performance (e.g., bandwidth, storage capacity) compared to the horizontal size of the semiconductor package (PKG1) can be improved in an effective manner.

[0043] Since the plurality of electrical connection structures 130 may extend up and down and may bypass the lower die 120, the plurality of electrical connection structures 130 may be arranged asymmetrically with respect to the center of each of the plurality of upper dies 60. For example, the plurality of electrical connection structures 130 may be connected to a first side (e.g., Figure 1B The plurality of electrical connection structures 130 of the upper die 60 on the left side in the cross-sectional view of the lower die 120 may be arranged to be offset to the first side relative to the center of the upper die 60 located on the first side in the horizontal direction of the lower die 120, and connected to the second side (e.g., Figure 1B The plurality of electrical connection structures 130 of the upper die 60 on the right side in the cross-sectional view of FIG. 1 may be arranged to be offset toward the second side relative to the center of the upper die 60 located on the second side of the lower die 120 in the horizontal direction.

[0044] The conductive material (e.g., metal material, plating material, conductive paste) included in the multiple electrical connection structures 130 for electrical connection may have a relatively strong overall strength. Therefore, the multiple electrical connection structures 130 may provide a force to physically support the multiple upper dies 60. The asymmetric arrangement of the multiple electrical connection structures 130 may result in a force that causes the multiple upper dies 60 to tilt in a horizontal direction. The lower die 120 may offset the tilting force with its force that physically supports the multiple upper dies 60. Therefore, even if the number of memory dies 61, 62, 63, and 64 increases, the semiconductor package PKG1 according to some embodiments may also be conducive to supporting the multiple upper dies 60 (in a stable manner) and improving reliability.

[0045] Some of the plurality of electrical connection structures 130 (e.g., the first electrical connection structure, the first portion) may be connected to the signal line 112SL of the package substrate 110, and may be electrically connected to the lower die 120. Other portions of the plurality of electrical connection structures 130 (e.g., the second electrical connection structure, the second portion) may be connected to the power line 112PL of the package substrate 110, and may be used as a power supply path for the plurality of upper dies 60, the power supply path being connected to an external source or external component that provides power to the semiconductor package PKG1. Therefore, the lower die 120 may not include a power supply path for the plurality of upper dies 60, and the design freedom and efficiency of the lower die 120 may be further improved.

[0046] Reference Figure 1B , the semiconductor package PKG1 according to some example embodiments may further include at least one of upper and lower electrical connection paths 65 and an encapsulant 140 .

[0047] The upper and lower electrical connection paths 65 may be implemented to vertically pass through the plurality of memory dies 61 , 62 , 63 , and 64 , and / or the plurality of buffer dies 70 , and may include at least a portion of the bumps 65C, the pads 60P, 65P, and 70P, and the through vias 60V. Figure 1A The horizontal arrangement positions of the upper and lower electrical connection paths 65 in the embodiment may vary according to the design.

[0048] The encapsulant 140 may include a lower encapsulant 140F and / or an upper encapsulant 140B. The lower encapsulant 140F may seal the plurality of electrical connection structures 130 and the lower die 120, and the upper encapsulant 140B may seal the plurality of upper die 60. For example, the encapsulant 140 may include a molding material such as an epoxy molding compound (EMC), but the present disclosure is not limited thereto, and the encapsulant 140 may also include an insulating material that may have similar protective properties or high ductility as the molding material. For example, the insulating material may be a build-up film such as Ajinomoto Build-up Film (ABF), a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as polyimide. The insulating material of the insulating layer 111 may be an insulating material to which inorganic fillers and / or glass fibers are appropriately added.

[0049] FIG. 2A to FIG. 2C Shown is sequentially manufactured through the first state (PKG1-1), the second state (PKG1-2) and the third state (PKG1-3) Figure 1A and Figure 1B The semiconductor package PKG1, however Figure 1A and Figure 1B The manufacturing method of the semiconductor package PKG1 is not limited to FIG. 2A to FIG. 2C The method shown in .

[0050] Reference Figure 2A , the first state (PKG1-1) of the semiconductor package according to some embodiments may include a structure in which the lower die 120 is mounted on the upper surface of the package substrate 110. Figure 2B According to some embodiments, the second state (PKG1-2) of the semiconductor package may include a structure in which a plurality of electrical connection structures 130 are formed on the upper surface of the package substrate 110, and may include a structure in which a lower encapsulant 140F is filled or disposed in one or more spaces on the upper surface of the package substrate 110 that are not occupied by the plurality of electrical connection structures 130 and the lower die 120.

[0051] A plurality of electrical connection structures 130 may be formed before forming the lower encapsulant 140F. For example, a photosensitive insulating layer having a thickness equal to the Z-direction extension length of each of the plurality of electrical connection structures 130 may be temporarily formed on the upper surface of the package substrate 110, a through hole penetrating or extending through the photosensitive insulating layer may be formed, the plurality of electrical connection structures 130 may be formed by filling the surface or the entire surface of each through hole formed with a conductive material (e.g., a metal material, a plating material, a conductive paste), and then the photosensitive insulating layer may be removed and replaced with the lower encapsulant 140F.

[0052] Reference Figure 2C, the third state (PKG1-3) of the semiconductor package according to some embodiments may include a structure in which a plurality of upper dies 60 and / or a plurality of buffer dies 70 are disposed on the upper surface of the lower encapsulant 140F. Thereafter, Figure 1B The upper encapsulant 140B is filled in spaces on the upper surface of the lower encapsulant 140F that are not occupied by the plurality of upper dies 60 and the plurality of buffer dies 70 .

[0053] The lower surfaces of the plurality of buffer dies 70 may contact (eg, may directly contact) Figure 1B If the plurality of buffer dies 70 are omitted, the lower surfaces of the plurality of upper dies 60 may contact (eg, may directly contact) Figure 1B For example, there may be no bumps between the plurality of buffer dies 70 and the lower encapsulant 140F, and there may be no non-conductive polymer that can be used with the bumps between the plurality of buffer dies 70 and the lower encapsulant 140F. Therefore, the plurality of buffer dies 70 (more specifically, the lower surfaces and side surfaces of the plurality of buffer dies 70) may directly contact the plurality of buffer dies 70. Figure 1B Therefore, the upper surface of the lower encapsulant 140F can support the plurality of buffer dies 70 in a stable manner, and even if the number of the plurality of memory dies 61, 62, 63, and 64 increases, the plurality of upper dies 60 can be supported stably and in a manner that advantageously improves reliability.

[0054] Since it can be formed after forming the lower encapsulant 140F Figure 1B The upper encapsulant 140B is formed so that an interface may be formed between the lower surface of the upper encapsulant 140B and the upper surface of the lower encapsulant 140F. For example, the interface may be confirmed by at least one of a scanning electron microscope (SEM), an atomic force microscope (AFM), a transmission electron microscope (TEM), an optical microscope, and a surface profiler.

[0055] Reference FIG. 3A to FIG. 3C , the semiconductor packages (PKG2, PKG3, and PKG4) according to some embodiments may have Figure 1A The structure in which the plurality of buffer dies 70 are omitted. Figure 3A As shown in FIG. 1 , a single buffer die 70 may be provided in the semiconductor package PKG2, and the buffer die 70 of the semiconductor package PKG2 may be arranged in Figure 1AThe buffer die 70 of the semiconductor package PKG2 may be surrounded by a plurality of electrical connection structures 130 and may be partially vertically overlapped with a plurality of upper dies 60. In some embodiments, as shown in FIG. Figure 3A As shown in FIG. 1 , the lower die 120 may be disposed in the semiconductor package PKG2 in a manner horizontally offset from the plurality of upper dies 60. In some embodiments, the buffer die 70 and the lower die 120 of the semiconductor package PKG2 may be electrically connected to each other through the package substrate 110. Figure 3B As shown in the semiconductor package PKG3, the buffer die 70 can be completely omitted from the semiconductor package PKG3. Figure 3C As seen in the semiconductor package PKG4 thereof, the lower die 120 of the semiconductor package PKG4 may be divided into a plurality of lower dies 120a and 120b. The number of the lower dies 120a and 120b is not limited to one or two.

[0056] Reference Figure 4A and Figure 5A , in the semiconductor package (PKG5) according to some embodiments, Figure 1A The at least four upper dies 60 may have a structure in which the upper dies 60 are integrated into two upper dies 60. Therefore, the plurality of electrical connection structures 130 may be arranged in two substantially U-shaped configurations that may at least partially surround the lower die 120. Figure 4B and Figure 5B , in the semiconductor package (PKG6) according to some embodiments, Figure 1A The at least four upper dies 60 may have a structure in which the upper dies are integrated into one upper die 60. Figure 5B As seen in FIG. 1 , in the semiconductor package PKG6 , the plurality of electrical connection structures 130 may be arranged in two substantially U-shaped configurations that may at least partially surround the lower die 120 .

[0057] Reference Figure 5C , the plurality of electrical connection structures 130 of the semiconductor package (PKG7) according to some embodiments may be arranged in two I-shaped configurations. Figure 5D , the arrangement of the plurality of electrical connection structures 130 of the semiconductor package (PKG8) according to some embodiments may be in a configuration of four L shapes.

[0058] Reference Fig. 6A, a plurality of electrical connection structures 130, 131, and 132 of a semiconductor package (PKG9) according to some embodiments may have a structure in which a first portion 130, a second portion 131, and a third portion 132 are connected in series. A conductive material (eg, nickel) included in the second portion 131 may be different from a conductive material (eg, copper) included in the first portion 130 and the third portion 132.

[0059] The spacing distance (MG1) between the electrical connection structure closest to the lower die 120 among the plurality of electrical connection structures 130, 131, and 132 and the lower die 120 may be longer than the average spacing distance (MG3) between the plurality of electrical connection structures 130, 131, and 132. Therefore, when the plurality of electrical connection structures 130, 131, and 132 are formed, the possibility of the lower die 120 having an indirect effect (e.g., the lower die 120 indirectly affecting the process dispersion factor) may be eliminated or reduced. The spacing distance MG2 between the lower die 120 and the plurality of buffer dies 70 may be formed or not formed according to the design.

[0060] Reference Figure 6B and Figure 6C According to some embodiments, the semiconductor package (PKG10, PKG11) may further include a silicon dummy member 150, which is located above the lower die 120 in the vertical direction and between the plurality of upper dies 60 in the horizontal direction. For example, the silicon dummy member 150 may be formed of silicon and may not include a device layer. For example, the silicon dummy member 150 may be provided to block Figure 1A The space between at least four upper dies 60 of the semiconductor package 10 and the semiconductor package 10 may be formed in the form of a barrier having a +-shaped upper surface and a +-shaped lower surface. The width of the silicon dummy member 150 may be determined based on the horizontal dimensions of the plurality of upper dies 60 and may help the semiconductor package (PKG10, PKG11) to have a shape close to a rectangular parallelepiped. Figure 6C As seen in FIG. 1 , in the semiconductor package ( PKG11 ) according to some embodiments, the plurality of upper dies 60 may not be vertically overlapped with the lower die 120 .

[0061] Reference Fig.6D, the semiconductor package (PKG12) according to some embodiments may have a structure in which bumps are omitted from all of the plurality of upper dies 60 and the plurality of buffer dies 70, and may further include a bonding insulation layer (60D). The bonding insulation layer 60D may surround the pads 60P, 65P, and 70P, and may provide bonding between the plurality of upper dies 60 and the plurality of buffer dies 70 and bonding between the memory dies of the plurality of corresponding upper dies 60. The combined structure of the bonding insulation layer 60D and the pads 60P, 65P, and 70P may be represented as direct bonding, and may include a dielectric-to-dielectric bonding structure and a metal-to-metal (e.g., copper-to-copper) bonding structure. For example, the bonding insulation layer 60D may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN).

[0062] According to the design, Figure 1B Multiple stacked electrical connection structures 127 may also be used Fig.6D Direct bonding structure or dielectric to dielectric bonding structure replacement, and depending on the design, Figure 1B The stacking protrusion 127C may also be omitted.

[0063] Reference Fig. 7A The semiconductor package (PKG13) according to some embodiments includes a plurality of stacked electrical connection structures 127 and may include Figure 1B The structure of only one of the circuit layers 120B and 120F of the lower die 120. The lower die 120 may not include a through via, and may be electrically connected to the plurality of electrical connection structures 130 through the plurality of stacked electrical connection structures 127 and the buffer die 70. Therefore, in some embodiments, the structure of the lower die 120 is not limited to Figure 1B .

[0064] Reference Figure 7B , at least a portion of the lower die 120 of the semiconductor package (PKG14) according to some embodiments may be embedded in the cavity in the package substrate 110. Therefore, the plurality of electrical connection structures 130 may be shortened and may be more efficiently implemented with bumps or solder balls.

[0065] Reference Figure 1A and Fig. 8A , the buffer die 70 may include an internal command generator (ICG) 71, a via region (TSVR) 72, a physical (PHY) region (PHYR) 73, a direct access (DA) region (DAR) 74, and an interface circuit (IFC) 75. The internal command generator 71 may be configured to generate an internal command using a command signal (CMD) received from the lower die 120 or an external host.

[0066] The via region 72 may be a region where upper and lower electrical connection paths 65 for communicating with the plurality of memory dies 61, 62, 63, and 64 are formed. The physical region 73 may be a region where an input / output circuit for communicating with the lower die 120 or an external host is placed. For example, a signal received from the lower die 120 or an external host may be transmitted to the via region 72 through the physical region 73, and may be transmitted to at least one of the plurality of memory dies 61, 62, 63, and 64 through the upper and lower electrical connection paths 65.

[0067] In the test mode for the semiconductor package PKG1, the direct access area 74 can communicate with an external test device through a pad exposed to the outside of the semiconductor package PKG1 (for example, it can directly communicate with an external test device through a pad exposed to the outside of the semiconductor package PKG1). The signal provided from the test device can be provided to the multiple memory dies 61, 62, 63 and 64 through the direct access area 74 and the via area 72. The interface circuit 75 can be configured to provide the address signal and the data signal provided from the lower die 120 or the external host to at least one target memory die among the multiple memory dies 61, 62, 63 and 64, and the data signal output by the target memory die can be output to the lower die 120 or the external host. In addition, the interface circuit 75 can be configured to provide a decision signal related to the test provided from the target memory die to an external device.

[0068] The lower die 120 may be a host or controller in a memory device (or system). The interface of the host may be a universal flash memory (UFS), but the present disclosure is not limited thereto. For example, the host universal flash memory interface may be at least one of peripheral component interconnect express (PCIe), non-volatile memory express (NVMe), serial attached SCSI (SAS), small computer system interface (SCSI), SCSIe, serial advanced technology attachment (SATA), SATAe, compute express link (CXL), and Gen-Z. The lower die 120 may be configured to provide command signals (CMD), address signals (ADDR), etc. used in the operation of the buffer die 70 and / or the plurality of memory dies 61, 62, 63, and 64 to the buffer die 70.

[0069] The buffer die 70 may be configured to buffer a command signal (CMD) and an address signal (ADDR), and transmit the command signal (CMD) and the address signal (ADDR) to at least one of the plurality of memory dies (61, 62, 63, and 64), and each of the plurality of memory dies 61, 62, 63, and 64 may be configured to perform a control operation (such as read, write, erase, and refresh) that may be performed in response to the command signal (CMD) and the address signal (ADDR) received through the buffer die 70. The buffer die 70 and / or each of the plurality of memory dies 61, 62, 63, and 64 may also be configured as a storage queue. Therefore, the buffer die 70 may perform a control operation (example: data processing order determination operation, error and bad sector prevention operation, load control operation, frequency boosting interface (Frequency Boosting Interface, FBI) ​​operation) on the plurality of memory dies 61, 62, 63, and 64.

[0070] The lower die 120 may be configured to receive a data signal DQ output as a result of a control operation of each of the plurality of memory dies 61 , 62 , 63 , and 64 through the buffer die 70 and / or transmit a data signal (DQ) containing data to be stored through the buffer die 70 .

[0071] Figure 8B 1 shows an internal block diagram of a dynamic random access memory (DRAM) based device of one memory die of each upper die of the plurality of upper dies 60, but the present disclosure is not limited thereto. Figure 8B , the memory die may include a plurality of memory banks 410 and a logic circuit 420. Each of the plurality of memory banks 410 may include a bank array 411 having a plurality of memory cells, a row decoder 412, a sense amplifier (SA) 413, and a column decoder 414.

[0072] A plurality of memory banks 410 included in one memory die may share one logic circuit 420. The logic circuit 420 may read data from the memory bank 410 and / or write data to the memory bank 410. In addition, the logic circuit 420 may specify an address for storing data and / or determine an operation mode of the memory die. In addition, the logic circuit 420 may include an input / output circuit for transmitting data to be stored in the plurality of memory banks 410 and / or data output from the plurality of memory banks 410, and a plurality of pads connected to the input / output circuit.

[0073] A plurality of pads included in the logic circuit 420 may be connected to the plurality of via structures described above. A plurality of upper pads and a plurality of lower pads may be connected to both sides of the plurality of via structures, and the input / output circuit may receive signals from the memory die and the buffer die through the plurality of via structures, or may output signals to the buffer die.

[0074] The bank array 411 may include a memory cell array having a plurality of memory cells. The row decoder 412 is connected to the memory cell array through a plurality of word lines, and the sense amplifier 413 may be connected to the memory cell array through a plurality of bit lines. A write operation of writing data into a plurality of memory cells, a read operation of reading data stored in a plurality of memory cells, etc. may be performed based on a command signal, an address signal, etc. received by the logic circuit 420 from the buffer die.

[0075] As described above, the semiconductor package according to some embodiments can achieve improved performance and / or increased capacity in an effective manner. For example, in the semiconductor package, the number (or total volume) of multiple upper dies can be effectively increased, and the design freedom / efficiency of the lower die can be improved. Therefore, high performance and / or large capacity can be achieved relatively effectively.

[0076] While certain embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, comprising: Package substrate; a plurality of upper dies, each of the upper dies being arranged on an upper side of the package substrate so as not to be vertically stacked with other upper dies of the plurality of upper dies, and each of the upper dies comprising a plurality of memory dies stacked vertically; a plurality of electrical connection structures, between the packaging substrate and the plurality of upper dies, the plurality of electrical connection structures being electrically connected to the packaging substrate; a lower die, on the package substrate and arranged not to vertically overlap the plurality of electrical connection structures; as well as A plurality of stacked electrical connection structures are arranged between the upper surface of the lower die and the plurality of upper die, and the plurality of stacked electrical connection structures are electrically connected to the upper surface of the lower die.

2. The semiconductor package according to claim 1, wherein: The plurality of upper dies includes at least four upper dies.

3. The semiconductor package according to claim 2, wherein: The at least four upper dies are vertically stacked with corresponding corners of the lower die.

4. The semiconductor package according to claim 3, further comprising: A plurality of buffer dies are electrically connected between and to the plurality of upper dies and the plurality of electrical connection structures.

5. The semiconductor package according to claim 4, wherein: The plurality of electrical connection structures are arranged to at least partially surround the lower die, and The lower surfaces of the plurality of buffer dies are located at a height coplanar with or above the upper surface of the lower die relative to the upper surface of the package substrate.

6. The semiconductor package according to claim 1, wherein: Each of the plurality of upper dies partially vertically overlaps the lower die, and The plurality of electrical connection structures are arranged asymmetrically with respect to respective centers of the plurality of upper dies.

7. The semiconductor package according to claim 6, wherein: A spacing distance between the lower die and an electrical connection structure closest to the lower die among the plurality of electrical connection structures is greater than an average spacing distance between the plurality of electrical connection structures.

8. The semiconductor package according to claim 1, further comprising: A silicon dummy member is disposed above the lower die in a vertical direction and between the plurality of upper dies in a horizontal direction.

9. The semiconductor package according to claim 1, wherein: At least a portion of the lower die is embedded in the packaging substrate.

10. The semiconductor package according to claim 1, further comprising: A plurality of buffer dies are electrically connected between and to the plurality of upper dies and the plurality of electrical connection structures.

11. The semiconductor package according to claim 10, further comprising: an encapsulant, sealing at least the plurality of electrical connection structures and the lower die, Wherein, the lower surfaces of the plurality of buffer dies are in direct contact with the encapsulant.

12. The semiconductor package according to claim 11, wherein Encapsulating agents include: a lower encapsulant to seal the plurality of electrical connection structures and the lower die; and an upper encapsulant, sealing the plurality of upper dies, Here, the lower surface of the upper encapsulant and the upper surface of the lower encapsulant have an interface therebetween.

13. The semiconductor package according to claim 10, wherein: A first electrical connection structure among the plurality of electrical connection structures is configured as a signal path between the plurality of upper dies and the lower die, and A second electrical connection structure other than the first electrical connection structure among the plurality of electrical connection structures is configured as a power supply path for the plurality of upper dies.

14. A semiconductor package, comprising: Package substrate; a plurality of upper dies, each of the upper dies being arranged not to vertically overlap with other upper dies in the plurality of upper dies above the package substrate; a plurality of electrical connection structures, between the packaging substrate and the plurality of upper dies, the plurality of electrical connection structures being electrically connected to the packaging substrate; as well as a lower die on the package substrate and arranged not to vertically overlap the plurality of electrical connection structures, wherein each of the plurality of upper dies is partially vertically overlapped with the lower die, and The plurality of electrical connection structures are arranged asymmetrically with respect to respective centers of the plurality of upper dies.

15. The semiconductor package according to claim 14, wherein: The plurality of upper dies include at least four upper dies, and The at least four upper dies are vertically stacked with corresponding corners of the lower die.

16. The semiconductor package according to claim 14, further comprising: a plurality of buffer dies electrically connected between and to the plurality of upper dies and the plurality of electrical connection structures, Each of the plurality of upper dies includes a plurality of memory dies vertically stacked on each other.

17. The semiconductor package according to claim 14, wherein: A first electrical connection structure among the plurality of electrical connection structures is used as a signal path between the plurality of upper dies and the lower die, and A second electrical connection structure among the plurality of electrical connection structures is used as a power supply path for the plurality of upper dies.

18. A semiconductor package, comprising: Package substrate; at least one upper die on the package substrate; a plurality of electrical connection structures between the packaging substrate and the at least one upper die, the plurality of electrical connection structures being electrically connected to the packaging substrate; a lower die, on the package substrate and arranged not to vertically overlap the plurality of electrical connection structures; an encapsulant to seal at least the plurality of electrical connection structures and the lower die; as well as at least one buffer die electrically connected between and connected to the at least one upper die and the plurality of electrical connection structures, Wherein, a lower surface of the at least one buffer die is in direct contact with the encapsulant.

19. The semiconductor package according to claim 18, wherein: Encapsulating agents include: a lower encapsulant to seal the plurality of electrical connection structures and the lower die; and an upper encapsulant, sealing the at least one upper die, Here, the lower surface of the upper encapsulant and the upper surface of the lower encapsulant have an interface therebetween.

20. The semiconductor package according to claim 19, wherein The at least one upper die includes at least four upper dies arranged not to vertically overlap each other, The at least four upper dies are vertically stacked with corresponding corners of the lower die.

Images