Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof, and electronic equipment, the semiconductor structure can be a wafer, a bare chip obtained by cutting the wafer, a chip obtained by packaging the bare chip, and the like, and is used for solving the problems of silicon wafer fracture and the like caused by insufficient filling of a conductive material in a substrate and easy expansion. The semiconductor structure includes a substrate, a dielectric layer, a protective layer, and a conductive pillar. Wherein the dielectric layer is stacked on the substrate. A through hole penetrating through the dielectric layer and the substrate is formed in the direction from the dielectric layer to the substrate. The via includes a first portion formed within the substrate. The protection layer covers a part of the inner wall, close to the dielectric layer, of the first part; the conductive pillar is disposed in the through hole and electrically connected to the electronic component on the dielectric layer. Due to the existence of the protective layer, a lower notch is prevented from being generated near one side, close to the dielectric layer, of the first local part, and the problem that a silicon wafer is broken due to the fact that the conductive material is insufficiently filled in the substrate and is easy to expand is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a semiconductor structure manufacturing method and an electronic device. Background Art

[0002] Taking the chip manufacturing scenario using silicon wafers as substrates as an example, the chip manufacturing process involves etching through silicon vias (TSVs) in the silicon wafer, depositing an insulating layer (liner), an adhesion layer (barrier) and a seed (seed) on the inner wall of the TSV, and finally filling it with conductive materials to form conductive columns, which are used to achieve electrical interconnection between electronic components in the chip, and between electronic components and external circuits.

[0003] Figure 1 Schematic diagram of a through silicon via etching process. Figure 1 As shown in the figure, when the aspect ratio of the through silicon via (the ratio of the depth of the through silicon via in the first direction F1 to the width in the second direction F2) is high, it is easy to cause over-etching of the silicon wafer in the second direction F2, and then generate an undercut near the junction between the silicon wafer and the dielectric layer. Specifically, if the through silicon via is divided into a first part located in the substrate and a second part located in the dielectric layer, over-etching occurs in the second direction F2, that is, in the second direction F2, the bottom critical dimension (bottom CD, BCD) of the second part is smaller than the top critical dimension (top CD, TCD) of the first part.

[0004] The existence of the above-mentioned lower gap will, on the one hand, lead to discontinuous deposition of the subsequent insulating layer, adhesion layer and seed, and insufficient filling of the conductive material; on the other hand, during the annealing process after filling the conductive material, the conductive column is prone to expansion, causing the silicon wafer to crack. Summary of the invention

[0005] The present application provides a semiconductor structure, a method for manufacturing a semiconductor structure, and an electronic device. The semiconductor structure may be a wafer, a bare chip obtained by cutting the wafer, a chip obtained by packaging the bare chip, etc., which is used to solve the problem of etching a through hole in a substrate. Figure 1 The lower notch shown in the figure results in discontinuous deposition of the insulating layer, adhesion layer and seed on the inner wall of the through hole, insufficient filling of the conductive material, and easy expansion of the conductive column, resulting in cracks in the silicon wafer.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a semiconductor structure is provided, comprising: a substrate, a dielectric layer, a protective layer and a conductive column. The dielectric layer is stacked on the substrate. A through hole is provided along a first direction (the first direction here is the direction from the dielectric layer to the substrate) that penetrates the dielectric layer and the substrate. The through hole includes a first part formed in the substrate. The protective layer covers a part of the inner wall of the first part close to the dielectric layer; the conductive column is arranged in the through hole and is electrically connected to the electronic component on the dielectric layer.

[0008] The presence of the protective layer avoids the generation of a lower notch in the first part near the side of the first part close to the dielectric layer. This is because, in the process of etching the through hole in the substrate, before the lower notch is generated, a protective layer is formed on the upper inner wall of the first part (at this time, the inner wall of the groove etched in the substrate constitutes the upper inner wall of the first part in the finished chip subsequently obtained) to protect the upper inner wall of the first part by the protective layer. Then, the substrate is further etched to deepen the groove depth. If the process is briefly described as "etching the substrate and depositing the protective layer before generating the lower notch", then the through hole depth required by the process can be achieved by repeatedly cycling the process. In addition, since the protective layer protects the upper inner wall of the first part, when etching the through hole in the substrate, as the etching depth increases, the substrate will not be over-etched in the width direction of the through hole. Therefore, the generation of a lower notch in the first part near the side of the dielectric layer can be avoided.

[0009] In combination with the first aspect, in a possible implementation, the first part includes a first section close to the dielectric layer and a second section away from the dielectric layer and continuous with the first section; the minimum radial dimension of the first section is greater than the maximum radial dimension of the second section. The protective layer covers the inner wall of the first section, and a side surface of the protective layer close to the conductive column is flush with the inner wall surface of the second section, thereby forming a continuous surface with the inner wall surface of the second section.

[0010] In combination with the first aspect, in a possible implementation, the second section has a contact surface facing the dielectric layer at the junction with the first section; the side of the protective layer close to the second section is connected to the contact surface; the thickness of the protective layer at the connection with the contact surface is equal to the size of the contact surface in the second direction; the second direction is a direction perpendicular to the first direction. This means that the surface of the side of the protective layer close to the conductive column is flush with the inner wall surface of the second section, which means that the surface of the side of the protective layer close to the conductive column forms a continuous surface with the inner wall surface of the second section. Accordingly, the radial size of the conductive column decreases continuously.

[0011] In combination with the first aspect, in a possible implementation manner, the dielectric layer further includes an active region, and the active region includes the electronic component. Furthermore, the semiconductor structure constitutes a chip.

[0012] In combination with the first aspect, in a possible implementation, the semiconductor structure further includes an active layer, which is disposed on the dielectric layer and / or on a side of the substrate away from the dielectric layer; the electronic components connected to the conductive pillars are electronic components in the active layer.

[0013] In combination with the first aspect, in a possible implementation, the semiconductor structure further includes a chip, which is disposed on the dielectric layer and / or disposed on a side of the substrate away from the dielectric layer; and the electronic component connected to the conductive pillar is an electronic component in the chip. In this way, the semiconductor structure constitutes a chip packaging structure.

[0014] In combination with the first aspect, in a possible implementation, the through hole also includes a second part formed in the dielectric layer; the inner wall surface of the second part is flush with the side surface of the protective layer close to the conductive column, thereby forming a continuous surface with the side surface of the protective layer close to the conductive column. Alternatively, the inner wall of the second part is covered with a second dielectric layer, and the side surface of the second dielectric layer close to the conductive column is flush with the side surface of the protective layer close to the conductive column, thereby forming a continuous surface with the side surface of the protective layer close to the conductive column. This means that the side surface of the second dielectric layer close to the conductive column, the side surface of the protective layer close to the conductive column, and the inner wall of the second section constitute a continuous surface, that is, there is no lower gap near the junction of the first part and the second part. Among them, the protective layer and the second dielectric layer can be composed of the same material, or they can be composed of different materials. The protective layer and the second dielectric layer can be connected as one, that is, there is no observable interface at the connection between the two, or there can be an observable interface.

[0015] From the above, it can be seen that since there is no lower notch near the junction of the first part and the second part, and the protective layer is located between the conductive column and the inner wall of the through hole, that is, before filling the conductive material used to form the conductive column, the surface of the protective layer on one side close to the conductive column has formed a continuous surface with the inner wall surface of the second section, so it can ensure that the conductive material is fully filled, and then, the quality of the conductive column is guaranteed, and the chip performance is guaranteed.

[0016] In combination with the first aspect, in a possible implementation, the aspect ratio of the through hole is greater than or equal to 10. Since when the aspect ratio of the through hole is high, it is easy to over-etch the substrate in the second direction, thereby generating a lower notch near the junction between the substrate and the dielectric layer, the chip involved in the embodiment of the present application has an aspect ratio of the through hole in the substrate greater than or equal to 10. The chip structure solution involved in the embodiment of the present application is more suitable for application scenarios where the chip size is large and the through hole in the substrate has a high aspect ratio.

[0017] In combination with the first aspect, in a possible implementation, the radial dimension of the through hole at the first position is greater than the radial dimension at the second position, and the first position is closer to the dielectric layer than the second position. Since the radial dimension of the through hole at the first position is greater than or equal to the radial dimension at the second position, it means that the TCD of the first part is less than or equal to the BCD of the second part, indicating that there is no lower notch at the junction of the first part and the second part.

[0018] In combination with the first aspect, in a possible implementation manner, along the first direction, the radial dimension of the first part decreases in a gradient manner.

[0019] In combination with the first aspect, in a possible implementation, along the first direction, the thickness of the protective layer at the third position is greater than the thickness at the fourth position, and the third position is closer to the dielectric layer than the fourth position. This is because, in the process of etching a through hole in the substrate, according to the depth requirement of the through hole, the above-mentioned process of "etching the substrate and depositing the protective layer before generating the lower notch" may be repeated multiple times, that is, the protective layer is deposited on the sidewall of the etched groove multiple times, so that the closer the protective layer is to the dielectric layer, the greater its thickness is, and the farther away from the dielectric layer, the smaller its thickness is.

[0020] In combination with the first aspect, in a possible implementation manner, the semiconductor structure further includes an insulating layer, which covers a continuous surface formed by the protective layer and the inner wall surface of the second segment.

[0021] In combination with the first aspect, in a possible implementation, the semiconductor structure further includes an adhesion layer, which covers the insulating layer and is located between the conductive pillar and the insulating layer. In this way, the adhesion layer is located between the insulating layer and the conductive pillar to bond and fix the conductive pillar.

[0022] In combination with the first aspect, in a possible implementation manner, the protective layer includes SiCN, SiON, OX, SiN, SiOCN, SiC or SiOC.

[0023] In combination with the first aspect, in a possible implementation manner, the insulating layer includes silicon oxide or other organic matter.

[0024] In a second aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, comprising:

[0025] A dielectric layer is formed on a substrate; the dielectric layer includes a conductive pattern, and the conductive pattern indicates a formation position of the conductive column in the substrate;

[0026] According to the formation position of the conductive pillar in the substrate indicated by the conductive pattern, a conductive pillar is prepared in the substrate, and the conductive pillar is electrically connected to the electronic component on the dielectric layer;

[0027] Among them, the conductive column is formed in a through hole that penetrates the dielectric layer and the substrate along a first direction; the through hole includes a first part formed in the substrate; the inner wall of the first part close to the dielectric layer is covered with a protective layer; the first direction is the direction from the dielectric layer to the substrate.

[0028] In combination with the second aspect, in a possible implementation manner, the through hole further includes a second portion formed in the dielectric layer, and the conductive pattern includes the second portion; and preparing the conductive column in the substrate according to a formation position of the conductive column indicated by the conductive pattern in the substrate includes:

[0029] The substrate is etched along a first direction in a region of the substrate exposed to the second local portion to form a first groove in the substrate; the first groove constitutes a first section of the first local portion;

[0030] forming a protection layer on the sidewall of the first groove for protecting the sidewall;

[0031] At the bottom wall of the first groove, the substrate is continuously etched along the first direction to form a second groove in the substrate; the second groove constitutes a second section of the first part;

[0032] A conductive column is formed in a space formed by the first segment and the second segment.

[0033] In combination with the second aspect, in a possible implementation, a protective layer for protecting the sidewalls is formed on the sidewalls of the first groove, including: forming an initial dielectric layer on the inner wall of the first groove; and removing a portion of the initial dielectric layer located on the bottom wall of the first groove.

[0034] In combination with the second aspect, in a possible implementation manner, a side wall surface of the first groove is flush with an inner wall surface of the second part.

[0035] In combination with the second aspect, in a possible implementation, at the junction of the first groove and the second part, the size of the first groove in the second direction is equal to the size of the second part in the second direction; and the second direction is perpendicular to the first direction.

[0036] In combination with the second aspect, in a possible implementation manner, a side surface of the protection layer close to the conductive pillar is flush with an inner wall surface of the second groove.

[0037] In combination with the second aspect, in a possible implementation manner, a minimum radial dimension of the first groove in the second direction is greater than a maximum radial dimension of the second groove in the second direction; and the second direction is perpendicular to the first direction.

[0038] In combination with the second aspect, in a possible implementation, a conductive column is formed in a space formed by a first section and a second section, including: forming an insulating layer on the inner wall surface of the protective layer and the second groove; forming an adhesion layer on the insulating layer; and forming a conductive column in the space after the insulating layer and the adhesive layer are formed.

[0039] In combination with the second aspect, in a possible implementation manner, forming an initial dielectric layer on an inner wall of the first groove includes: forming an initial dielectric layer on an inner wall of the second part and an inner wall of the first groove.

[0040] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a main board; and any one of the above-mentioned semiconductor structures electrically connected to the main board.

[0041] Among them, the technical effects brought about by any design method in the second aspect to the third aspect can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of through silicon via etching;

[0043] Figure 2 A three-dimensional schematic diagram of an electronic device provided in an embodiment of the present application;

[0044] Figure 3 An exploded diagram of an electronic device provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of a chip packaging structure and a mainboard structure of an electronic device provided in an embodiment of the present application

[0046] Figure 5 A schematic diagram of a chip packaging structure in an electronic device provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of a chip provided in an embodiment of the present application;

[0048] Figure 7 A schematic diagram of another chip provided in an embodiment of the present application;

[0049] Figure 8 A schematic diagram of an exploded view of a chip provided in an embodiment of the present application;

[0050] Fig. 9 A schematic diagram of another chip provided in an embodiment of the present application;

[0051] Fig.10 A schematic diagram of a process of manufacturing a semiconductor structure provided in an embodiment of the present application;

[0052] Fig.11 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0053] Fig.12 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0054] Fig.13 A flowchart of a semiconductor structure manufacturing method provided in an embodiment of the present application;

[0055] Fig.14 A flowchart of another semiconductor structure manufacturing method provided in an embodiment of the present application;

[0056] Fig.15 Another process schematic diagram of the semiconductor structure manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0058] In the description of this application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0059] Furthermore, in the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0060] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0061] In addition, the business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0062] In order to solve the problem of lower gaps during the etching of silicon vias pointed out in the background technology, in related technologies, such as the Bosch process, the macro etching process is decomposed into multiple cycles of micro etching processes, each cycle including two steps of "etching the silicon wafer" and "depositing a protective layer on the sidewalls of the etched grooves". Among them, under the condition that the macro etching time remains unchanged, the more cycles there are, the shorter the etching time of each cycle is. In this way, by shortening the etching time of each cycle and at the same time using the protective layer (such as carbon tetrafluoride) to protect the sidewalls of the etched grooves, excessive etching in the width direction of the silicon via is prevented, thereby preventing the generation of lower gaps.

[0063] However, due to the limitation of machine capacity, the above solution is only applicable to the through silicon via etching process with a small depth-to-width ratio, that is, the optimization space is small. When the depth-to-width ratio is large, the generation of the lower gap cannot be completely avoided.

[0064] In view of this, an embodiment of the present application provides a semiconductor structure and an electronic device including the semiconductor structure.

[0065] In some application scenarios, the semiconductor structure mentioned in this article can be a wafer, a bare chip obtained by cutting the wafer, a chip obtained by packaging the bare chip, etc. Since in the semiconductor structure, the through silicon via of the substrate does not exist, such as Figure 1 The lower notch is shown, so the insulating layer, adhesion layer and seed layer deposited on the inner wall of the silicon via are flat and continuous, and the conductive material in the silicon via is fully filled, and the functions of the semiconductor structure and electronic equipment are guaranteed.

[0066] The above-mentioned electronic devices include, but are not limited to, electronic devices in the fields of information technology (IT) and communication technology (CT), such as servers, optical communication equipment, mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), cameras, personal computers, notebook computers, vehicle-mounted devices, wearable devices, augmented reality (AR) glasses, AR helmets, virtual reality (VR) glasses or VR helmets, and other devices that require data processing / storage / transmission. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic devices. For the convenience of explanation below, the electronic devices are all taken as follows: Figure 2 The mobile phone shown is used as an example for illustration.

[0067] Figure 2 A three-dimensional diagram of an electronic device provided in some embodiments of the present application, Figure 3 for Figure 2 Exploded view of the electronic device shown. Figure 2 and Figure 3 , the electronic device 1000 is a mobile phone. The electronic device 1000 may include Figure 2 The screen 100 , the middle frame 200 , the rear cover 300 and the mainboard 400 fixed on the middle frame 200 are shown.

[0068] Understandably, Figure 2 and Figure 3 Some components included in the electronic device 1000 are shown only as examples, and the actual shapes, actual sizes, actual positions, and actual structures of these components are not subject to any restriction. Figure 2 and Figure 3 For example, in some other examples, the electronic device 1000 may not include the screen 100. Alternatively, the electronic device 1000 may also include Figure 2 Camera 500 is shown.

[0069] In the embodiment of the present application, the electronic device 1000 further includes: Figure 4 The chip packaging structure 600 shown in the figure. The chip packaging structure mentioned in the embodiment of the present application can also be referred to as an integrated circuit. Figure 4As shown, the chip package structure 600 is disposed on the mainboard 400 and is electrically connected to the mainboard 400. For example, the chip package structure 600 can be electrically connected to the mainboard 400 through a ball grid array (BGA) or a plurality of copper pillar bumps (CPB) arranged in an array, so that the chip package structure 600 can achieve signal transmission with other devices or device stacking structures on the mainboard 400.

[0070] It should be noted that the mainboard 400 may be a printed circuit board (PCB). The number of chip packaging structures 600 on the mainboard 400 may be one, two, or more than two, which is not limited in the present application.

[0071] For the convenience of the following description, some drawings of the embodiments of the present application show a three-dimensional space coordinate system, namely, an X, Y, and Z coordinate system. Figure 4 , the plane where the main board 400 is located is the XY plane. Figure 4 Taking the main board 400 shown in the figure as a rectangle as an example, the X-axis may be the length direction of the main board 400, the Y-axis may be the width direction of the main board 400, and the Z-axis may be a direction perpendicular to or approximately perpendicular to the main board 400 within a manufacturing tolerance range. It can be understood that the width dimension of the main board 400 is smaller than the length dimension of the main board 400.

[0072] In different application scenarios, the semiconductor structure provided by the embodiment of the present application can be as follows: Figure 4 The chip packaging structure shown in FIG. 1 may also be as follows Figure 4 The chip in the chip packaging structure shown in FIG. The specific implementation of the semiconductor structure as a chip is first introduced below, and then the specific implementation of the semiconductor structure as a chip packaging structure is introduced.

[0073] Please refer to Figure 5 The chip packaging structure 600 includes a substrate 1 and a chip 2 arranged on the substrate 1. The substrate 1 is located between the mainboard 400 and the chip 2. The substrate 1 includes a wiring layer, and the chip 2 is electrically connected to the wiring layer. The chip 2 can be a bare chip (i.e., a single die) or a chip stacking structure (i.e., multiple bare dies are stacked). The present application does not limit the number of chips 2 in the chip packaging structure 600. The number of chips in the chip packaging structure 600 can be one or more.

[0074] The semiconductor structure provided in the embodiment of the present application can be the above-mentioned chip 2, and the chip 2 can specifically be a processing chip with data processing function, such as a central processing unit (CPU), a system on chip (SOC) or a graphics processing unit (GPU) and other chips that can process data. The above-mentioned memory can be a random access memory (RAM) or a read-only memory (ROM).

[0075] Please refer to Figure 6 , the chip 2 includes a substrate 21, a dielectric layer 22, a protective layer 23, a conductive column 24 and an electronic component 25. Among them, the dielectric layer 22 is stacked on the substrate 21. Along the first direction F1 (the first direction here is the direction from the dielectric layer 22 to the substrate 21), there is a through hole that penetrates the dielectric layer 22 and the substrate 21. In some of the following contents, in order to facilitate the description of the structure of the chip 2, the through hole is divided into a first part formed in the substrate and a second part formed in the dielectric layer, and the inner wall of the first part close to the dielectric layer is called the upper inner wall. The protective layer 23 covers the upper inner wall of the first part. The conductive column 24 is arranged in the through hole and is electrically connected to the electronic component 25.

[0076] In such Figure 6 In the chip 2 shown, the presence of the protective layer 23 prevents the TCD of the first part from being greater than the BCD of the second part, that is, prevents the lower notch from being generated near the junction of the first part and the second part. This is because, in the process of etching the through hole in the substrate 21, before the lower notch is generated, the protective layer 23 is formed on the upper inner wall of the first part (at this time, the inner wall of the groove etched in the substrate 21 constitutes the upper inner wall of the first part in the finished chip subsequently obtained) to protect the upper inner wall of the first part by the protective layer 23. Then, the substrate 21 is further etched to deepen the groove depth. In the following contents, the process is briefly described as multiple cycles of "etching the substrate and depositing the protective layer before generating the lower notch" until the through hole depth reaches the process requirements. Since the protective layer 23 protects the upper inner wall of the first part, when etching the through hole in the substrate 21, as the etching depth increases, the substrate 21 will not be over-etched in the width direction of the through hole. Therefore, it is possible to avoid the TCD of the first part being greater than the BCD of the second part, that is, to avoid the lower notch being generated near the boundary between the first part and the second part.

[0077] In a possible implementation, the dielectric layer may further include an active region, and the electronic component 25 is an active device in the active region, for example Figure 6 shown.

[0078] In another possible implementation, the chip 2 further includes an active layer 26, which is disposed on a side of the substrate 21 away from the dielectric layer 22. The electronic component 25 is an active device in the active layer 26, for example Figure 7 In another possible implementation, the active layer 26 may also be disposed on the dielectric layer 22. In another possible implementation, the active layer may be disposed on the side of the substrate 21 away from the dielectric layer 22 and on the dielectric layer 22.

[0079] Of course, in other possible implementations, the electronic component 25 may also be a passive device, or other electronic devices, such as a power module.

[0080] In some embodiments, along the first direction F1, the radial dimension of the first part decreases in a gradient manner. Figure 6 or Figure 7 Taking the chip structure shown as an example, if the first part is divided into a first section close to the dielectric layer 22 and a second section away from the dielectric layer 22 and connected to the first section, the minimum radial dimension of the first section is greater than the maximum radial dimension of the second section. In other words, in the second direction F2 (a direction perpendicular to the first direction F1), the size of the first section is greater than the size of the second section.

[0081] Based on the above embodiment, the upper inner wall of the first part can be the inner wall of the first section, and the protective layer 23 covers the inner wall of the first section. In addition, the surface of the protective layer 23 near the conductive column 24 is flush with the inner wall surface of the second section, thereby forming a continuous surface with the inner wall surface of the second section. Figure 8 for Figure 6 The exploded schematic diagram of the chip shown, as a possible implementation, has a contact surface facing the dielectric layer 22 at the junction of the second section and the first section. The thickness of the protective layer 23 at the connection with the contact surface is equal to the size of the contact surface in the second direction. This means that the side surface of the protective layer close to the conductive column 24 is flush with the inner wall surface of the second section, which means that the side surface of the protective layer 23 close to the conductive column 24 forms a continuous surface with the inner wall surface of the second section. Accordingly, the radial size of the conductive column 24 decreases continuously.

[0082] Based on the above embodiment, the inner wall surface of the second part is flush with the surface of the side of the protective layer 23 close to the conductive column 24, thereby forming a continuous surface with the surface of the side of the protective layer 23 close to the conductive column 24. Fig. 9As shown, the protective layer 23 also covers the inner wall of the second part, which means that the side surface of the protective layer 23 close to the conductive column 24 and the inner wall of the second section form a continuous surface, that is, there is no lower gap near the junction of the first part and the second part. Among them, the protective layer 23 and the dielectric layer 22 can be composed of the same material, or they can be composed of different materials. When the protective layer 23 and the dielectric layer 22 are composed of the same material, the part of the protective layer 23 covering the inner wall of the second part can be connected to the inner wall of the second part, that is, there is no observable interface at the connection between the two, or there can be an observable interface.

[0083] It can be seen from the above embodiments that since there is no lower notch near the junction of the first part and the second part, and the protective layer 23 is located between the conductive column 24 and the inner wall of the through hole, that is, before filling the conductive material used to form the conductive column 24, the side surface of the protective layer 23 close to the conductive column 24 has formed a continuous surface with the inner wall surface of the second section, so that the conductive material can be fully filled, thereby ensuring the quality of the conductive column 24 and the chip performance.

[0084] In some embodiments, the aspect ratio of the through hole is greater than or equal to 10. As described in the background technology, when the aspect ratio of the through hole is high, it is easy to over-etch the substrate 21 in the second direction, thereby generating a lower notch near the junction between the substrate 21 and the dielectric layer 22. Therefore, in the chip involved in the embodiment of the present application, the aspect ratio of the through hole in the substrate 21 is greater than or equal to 10. The chip structure solution involved in the embodiment of the present application is more suitable for application scenarios in which the chip size is large and the through hole in the substrate has a high aspect ratio.

[0085] In some embodiments, the radial dimension of the through hole at the first position is greater than the radial dimension at the second position, and the first position is closer to the dielectric layer relative to the second position. Generally, if a lower notch is generated near the junction of the first part and the second part during the chip manufacturing process, it means that the TCD of the first part is greater than the BCD of the second part. In the embodiment of the present application, since the radial dimension of the through hole at the first position is greater than or equal to the radial dimension at the second position, it means that the TCD of the first part is less than or equal to the BCD of the second part, indicating that there is no lower notch at the junction of the first part and the second part.

[0086] In some embodiments, along the first direction, the thickness of the protective layer 23 at the third position is greater than the thickness at the fourth position, and the third position is closer to the dielectric layer 22 than the fourth position. That is, along the first direction, the thickness of the protective layer 23 tends to decrease. This is because, in the process of etching a through hole in the substrate 21, according to the depth requirement of the through hole, the above-mentioned process of "etching the substrate and depositing the protective layer before generating the lower notch" may be repeated multiple times, that is, it may be repeated as follows. Fig.10 As shown, dielectrics are deposited multiple times on the sidewalls of the etched grooves, so that the closer the protective layer 23 is to the dielectric layer 22, the thicker it is, and the farther away from the dielectric layer 22, the thinner it is.

[0087] In some embodiments, the protective layer 23 also covers the inner wall of the second section, and the thickness of the protective layer 23 at the third position is greater than the thickness at the fourth position along the first direction, and the third position is closer to the dielectric layer 22 relative to the fourth position. This is because, in the chip manufacturing process, before filling the conductive material, an insulating layer and an adhesive layer may be sequentially formed on the "continuous surface formed by the side surface of the protective layer close to the conductive column and the inner wall of the second section". When the insulating layer, the adhesive layer and the protective layer are made of the same material, the structure of the manufactured chip is that the protective layer 23 covers the inner wall of the entire second part, that is, it covers both the inner wall of the first section and the inner wall of the second section, and its thickness tends to decrease along the first direction.

[0088] In some embodiments, the continuous surface formed by the protective layer 23 and the inner wall surface of the second section is covered with an insulating layer, and the insulating layer is further covered with an adhesive layer. In this way, the adhesive layer is located between the insulating layer and the conductive column to bond and fix the conductive column.

[0089] In the above embodiments, the protective layer includes any one of multi-system materials such as silicon carbon nitride SiCN, silicon oxynitride SiON, silicon oxide OX, silicon nitride SiN, silicon oxycarbon nitride SiOCN, silicon carbide SiC and silicon oxycarbon SiOC. The insulating layer includes silicon oxide or other organic substances, such as various resins. The adhesion layer includes metal or metal compound, such as TaN, TiN, etc.

[0090] Please refer to Fig.11 In combination with the above embodiments, the semiconductor structure provided in other embodiments may include: a substrate 21, a dielectric layer 22, a protective layer 23, a conductive column 24 and a chip 27. The specific implementation of the substrate 21, the dielectric layer 22, the protective layer 23 and the conductive column 24 can refer to the above embodiment of the chip 2 and will not be described in detail here. The chip 27 may be the chip 2 provided in the above embodiment of the present application, or may be a chip of other structures. The chip 27 may be as follows: Fig.11 As shown, it is disposed on the dielectric layer 22, and can also be as shown Fig.12 As shown in FIG. 1 , the chips are arranged on the side of the substrate 21 away from the dielectric layer 22. A plurality of chips can also be arranged on the dielectric layer 22 and on the side of the substrate 21 away from the dielectric layer 22. Fig.11In the implementation shown, a wiring layer 28 may be provided on the side of the substrate 21 away from the dielectric layer 22, the chip 27 is provided on the wiring layer 28, and the conductive pillar 24 may be electrically connected to the circuit in the wiring layer 28, and further, electrically connected to the chip 27 through the circuit in the wiring layer 28. Fig.11 and Fig.12 In the illustrated implementation, the semiconductor structure is specifically a chip packaging structure, wherein the substrate 21 , the dielectric layer 22 , the protective layer 23 , the conductive pillars 24 and the wiring layer 28 constitute a base plate for packaging the chip 27 .

[0091] The present application also provides a method for manufacturing a semiconductor structure. Fig.13 As shown, the manufacturing method may include:

[0092] S100, forming a dielectric layer on a substrate, the dielectric layer comprising a conductive pattern, the conductive pattern indicating a formation position of a conductive column in the substrate.

[0093] In some embodiments, a dielectric layer is first formed on a substrate, and then the exposed conductive pattern is transferred to the dielectric layer through a dielectric etching chamber to form a mask for silicon.

[0094] In some embodiments, the dielectric layer also includes an active region, and an electronic device is formed in the active region. In S100, a dielectric layer is first formed on a substrate, and then active devices are prepared in the dielectric layer to form an active region. Then, the exposed conductive pattern is transferred to the active layer through a dielectric etching chamber to form a mask for silicon.

[0095] S200, preparing a conductive pillar in the substrate according to the formation position of the conductive pillar in the substrate indicated by the conductive pattern, and electrically connecting the conductive pillar to the electronic component on the dielectric layer.

[0096] Among them, the conductive column is formed in a through hole that penetrates the dielectric layer and the substrate along a first direction; the through hole includes a first part formed in the substrate; the inner wall of the first part close to the dielectric layer is covered with a protective layer; the first direction is the direction from the dielectric layer to the substrate.

[0097] In some embodiments, the through hole further includes a second portion formed in the dielectric layer, and the conductive pattern includes the second portion.

[0098] like Fig.14 and Fig.15 As shown, the above S200, according to the formation position of the conductive pillar in the substrate indicated by the conductive pattern, prepares the conductive pillar in the substrate, which may specifically include:

[0099] S201, etching the substrate along a first direction in the area of ​​the substrate exposed to the second part to form a first groove in the substrate. The first groove subsequently constitutes the first section of the first part mentioned in the above chip structure embodiment.

[0100] In some embodiments, a sidewall surface of the first groove is flush with an inner wall surface of the second portion.

[0101] In some embodiments, at the junction of the first groove and the second portion, a size of the first groove in the second direction is equal to a size of the second portion in the second direction.

[0102] S202 , forming a protection layer on the sidewall of the first groove for protecting the sidewall.

[0103] Specifically, an initial dielectric layer is first formed on the inner wall of the first groove, and then the portion of the initial dielectric layer located on the bottom wall of the first groove is removed. The initial dielectric layer retained on the side wall of the first groove is the protective layer.

[0104] In some possible implementations, forming an initial dielectric layer on the inner wall of the first groove specifically includes: forming an initial dielectric layer on the inner wall of the second part and the inner wall of the first groove.

[0105] S203, continue etching the substrate along the first direction at the bottom wall of the first groove to form a second groove in the substrate. The first groove subsequently constitutes the second section of the first part mentioned in the above chip structure embodiment.

[0106] In some embodiments, a surface of a side of the protection layer away from the inner wall of the substrate is flush with an inner wall surface of the second groove.

[0107] In some embodiments, a minimum radial dimension of the first groove in the second direction is greater than a maximum radial dimension of the second groove in the second direction.

[0108] It should be noted that the above S202 and S203 are a cycle of "etching the substrate and depositing a protective layer before forming a lower notch" mentioned in the above chip structure embodiment. According to the requirements for the through hole depth, this process may be repeated multiple times until the through hole reaches the expected depth.

[0109] S204, forming a conductive column in the etched inner space of the substrate. The inner space of the substrate here is a space formed by the first section and the second section, or a space formed by the first groove connecting the second groove.

[0110] Specifically, an insulating layer is first formed on the protective layer and the inner wall surface of the second groove; an adhesive layer is then formed on the insulating layer; a conductive material is then filled in the space after the insulating layer and the adhesive layer are formed, and a conductive column is formed after annealing and other treatments. Finally, a side of the substrate away from the dielectric layer is polished so that the size of the conductive column along the first direction meets the process requirements, and one end of the conductive column away from the dielectric layer is exposed to the outside of the substrate.

[0111] Through the above S100 and S200, the above Figure 6 The semiconductor structure shown.

[0112] In some embodiments, the method for manufacturing the semiconductor structure further includes: forming an active layer on a side of the substrate away from the dielectric layer, and electrically connecting the electronic components in the active layer to the conductive pillars.

[0113] Through the above-mentioned manufacturing method, the above-mentioned Figure 7 The semiconductor structure shown.

[0114] In some embodiments, the method for manufacturing the semiconductor structure further includes: mounting a chip on the dielectric layer and / or on a side of the substrate away from the dielectric layer.

[0115] In a possible process implementation, a wiring layer is first formed on the side of the substrate away from the dielectric layer, and the circuit in the wiring layer is electrically connected to the conductive pillar. Then, a chip is mounted on the wiring layer, and the chip is electrically connected to the circuit in the wiring layer. In this way, the chip and the conductive pillar are electrically connected through the wiring layer, and the following is obtained: Fig.12 The chip packaging structure shown.

[0116] It can be seen from the above manufacturing method that in the process of etching a through hole in the substrate, before the lower notch is generated, a protective layer is formed on the upper inner wall of the first part (at this time, the inner wall of the groove etched in the substrate constitutes the upper inner wall of the first part in the finished chip subsequently obtained) to protect the upper inner wall of the first part through the protective layer. Then, the substrate is further etched to deepen the depth of the groove. If the process is briefly described as "etching the substrate and depositing a protective layer before generating the lower notch", then the through hole depth required by the process can be achieved by repeatedly cycling the process. In addition, since the protective layer protects the upper inner wall of the first part, when etching the through hole in the substrate, as the etching depth increases, the substrate will not be over-etched in the width direction of the through hole. Therefore, it can be avoided that the TCD of the first part is greater than the BCD of the second part, that is, it is avoided that the lower notch is generated near the junction of the first part and the second part.

[0117] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0118] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A dielectric layer is stacked on the substrate; along a first direction, there is a through hole penetrating the dielectric layer and the substrate, the through hole includes a first part formed in the substrate; the first direction is the direction from the dielectric layer to the substrate; A protective layer covering a portion of the inner wall of the first part close to the dielectric layer; A conductive column, disposed in the through hole; The electronic component is electrically connected to the conductive column.

2. The semiconductor structure according to claim 1, characterized in that: The first part includes a first segment close to the dielectric layer and a second segment far from the dielectric layer and continuous with the first segment; the minimum radial dimension of the first segment is greater than the maximum radial dimension of the second segment; The protective layer covers the inner wall of the first section; and a surface of one side of the protective layer close to the conductive column is flush with the inner wall surface of the second section.

3. The semiconductor structure according to claim 2, characterized in that: The second section has a contact surface facing the dielectric layer at the junction with the first section; The side of the protective layer close to the second section is connected to the contact surface; the thickness of the protective layer at the connection with the contact surface is equal to the size of the contact surface in the second direction; the second direction is a direction perpendicular to the first direction.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The dielectric layer also includes an active region, and the active region includes the electronic component.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The semiconductor structure further comprises: An active layer is arranged on the dielectric layer and / or on a side of the substrate away from the dielectric layer; the active layer includes the electronic component.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The semiconductor structure further comprises: A chip, arranged on the dielectric layer and / or on a side of the substrate away from the dielectric layer; The chip includes the electronic component.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The aspect ratio of the through hole is greater than or equal to 10:

1.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: A radial dimension of the through hole at a first position is greater than a radial dimension of the through hole at a second position, and the first position is closer to the dielectric layer than the second position.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: Along the first direction, the radial dimension of the conductive column decreases continuously.

10. The semiconductor structure according to any one of claims 1 to 8, characterized in that: Along the first direction, the radial dimension of the first part decreases gradually.

11. The semiconductor structure according to any one of claims 1 to 10, characterized in that: Along the first direction, the thickness of the protection layer at a third position is greater than the thickness at a fourth position, and the third position is closer to the dielectric layer than the fourth position.

12. The semiconductor structure according to any one of claims 1 to 11, characterized in that: The through hole further includes a second portion formed in the dielectric layer; an inner wall surface of the second portion is flush with a surface of one side of the protection layer close to the conductive column.

13. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The through hole further includes a second portion formed in the dielectric layer; the protection layer further covers an inner wall of the second portion.

14. The semiconductor structure according to claim 2 or 3, characterized in that: Also includes: An insulating layer covers a continuous surface formed by the protective layer and the inner wall surface of the second section.

15. The semiconductor structure according to claim 14, characterized in that: Also includes: The adhesion layer covers the insulating layer and is located between the conductive pillar and the insulating layer.

16. The semiconductor structure according to any one of claims 1 to 15, characterized in that: The protective layer includes silicon carbon nitride SiCN, silicon oxynitride SiON, silicon oxide OX, silicon nitride SiN, silicon oxycarbon nitride SiOCN, silicon carbide SiC or silicon oxycarbon SiOC.

17. The semiconductor structure according to any one of claims 14 to 15, characterized in that: The insulating layer includes silicon dioxide or other organic matter.

18. A method for manufacturing a semiconductor structure, characterized in that: include: forming a dielectric layer on the substrate; The dielectric layer includes a conductive pattern, the conductive pattern indicating a formation position of a conductive pillar in the substrate; According to the formation position of the conductive pillar in the substrate indicated by the conductive pattern, the conductive pillar is prepared in the substrate, and the conductive pillar is electrically connected to the electronic component on the dielectric layer; Wherein, the conductive column is formed in a through hole that penetrates the dielectric layer and the substrate along a first direction; the through hole includes a first part formed in the substrate; a portion of the inner wall of the first part close to the dielectric layer is covered with a protective layer; the first direction is the direction from the dielectric layer to the substrate.

19. The method for manufacturing a semiconductor structure according to claim 18, wherein: The through hole further includes a second portion formed in the dielectric layer, and the conductive pattern includes the second portion; The forming position of the conductive pillar in the substrate according to the conductive pattern indicates that the conductive pillar is formed in the substrate, and the conductive pillar is prepared in the substrate, comprising: In the area of ​​the substrate exposed to the second part, the substrate is etched along the first direction to form a first groove in the substrate; the first groove constitutes a first section of the first part; forming a protection layer on the sidewall of the first groove for protecting the sidewall; At the bottom wall of the first groove, the substrate is further etched along the first direction to form a second groove in the substrate; the second groove constitutes a second section of the first part; The conductive column is formed in a space formed by the first segment and the second segment.

20. The method for manufacturing a semiconductor structure according to claim 19, wherein: The step of forming a protection layer on the sidewall of the first groove for protecting the sidewall comprises: forming an initial dielectric layer on an inner wall of the first groove; A portion of the initial dielectric layer located on the bottom wall of the first groove is removed.

21. The method for manufacturing a semiconductor structure according to claim 19, wherein: The side wall surface of the first groove is flush with the inner wall surface of the second portion.

22. The method for manufacturing a semiconductor structure according to claim 19, wherein: At the junction of the first groove and the second part, the size of the first groove in the second direction is equal to the size of the second part in the second direction; the second direction is perpendicular to the first direction.

23. The method for manufacturing a semiconductor structure according to claim 19, wherein: A side surface of the protection layer close to the conductive column is flush with an inner wall surface of the second groove.

24. The method for manufacturing a semiconductor structure according to claim 19, wherein: The minimum radial dimension of the first groove in the second direction is greater than the maximum radial dimension of the second groove in the second direction; and the second direction is perpendicular to the first direction.

25. The method for manufacturing a semiconductor structure according to claim 19, wherein: The forming of the conductive column in the space formed by the first segment and the second segment comprises: forming an insulating layer on the protective layer and the inner wall surface of the second groove; forming an adhesive layer on the insulating layer; The conductive column is formed in the space after the insulating layer and the adhesive layer are formed.

26. The method for manufacturing a semiconductor structure according to claim 20, wherein: The forming of an initial dielectric layer on the inner wall of the first groove comprises: The initial dielectric layer is formed on the inner wall of the second portion and the inner wall of the first groove.

27. An electronic device, characterized in that: include: Motherboard; A semiconductor structure as claimed in any one of claims 1 to 17 electrically connected to the mainboard.

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