Semiconductor structure and forming method thereof

Abstract

A semiconductor structure may include a first feature formed within a first dielectric layer having a first electrical bonding structure, a second feature formed within a second dielectric layer having a second electrical bonding structure, and an organic substrate layer formed between the first dielectric layer and the second dielectric layer. The organic substrate layer includes a carbon chain structure such that the first dielectric layer may be bonded to the second dielectric layer by a bond formed between the first dielectric layer, the organic substrate layer, and the second dielectric layer. The carbon chain structures have a carbon number between 10 and 1000 and a hydrogen / carbon ratio H / C greater than 2, such that the organic substrate layer has a thickness between 0.5 nm and 30 nm. The carbon chain structures also include functional groups that can form bonds between the carbon chain structures.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to a semiconductor structure and a method for forming the same, and more particularly to a semiconductor structure with an improved bonding structure and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically made by sequentially depositing multiple insulating layers or multiple dielectric layers, multiple conductive layers, and multiple layers of semiconductor material on a semiconductor substrate; and patterning the various material layers using lithography techniques to form a number of circuit components and elements thereon. Typically, dozens or hundreds of integrated circuits are manufactured on a single semiconductor wafer, and the individual dies on the semiconductor wafer are separated by cutting the integrated circuits along scribelines. Individual dies are typically packaged separately, such as in multi-chip modules, or in other types of packaging.

[0003] However, as semiconductor packages become more complex, the size of semiconductor packages becomes larger so that each package can accommodate a greater number of integrated circuits and / or dies. These larger and more complex semiconductor packages are challenging to make effective and reliable interconnections between the various components of the semiconductor package. Therefore, there is a need for continuous improvement in semiconductor package design, and attention is paid to shortening the interconnection length, thereby reducing ohmic losses, heat generation, and signal delays. Furthermore, there is also a continuous need for improved die-to-die bonding structures and methods of manufacturing the same. Summary of the invention

[0004] Some embodiments of the present disclosure provide a semiconductor structure, characterized by a first component, including a first electrical bonding structure formed in a first dielectric layer; a second component, including a second electrical bonding structure formed in a second dielectric layer; and an organic base layer, including a carbon chain structure, formed between the aforementioned first dielectric layer and the aforementioned second dielectric layer, so that the aforementioned first dielectric layer can be bonded to the aforementioned second dielectric layer through a bond formed between the aforementioned first dielectric layer, the aforementioned organic base layer and the aforementioned second dielectric layer.

[0005] Some embodiments of the present disclosure further provide a semiconductor structure, characterized by a first component including a first dielectric layer; and a first organic base layer including a first carbon chain structure formed on a first surface of the first dielectric layer, wherein the first carbon chain structure respectively includes a first proximal end bonded to the first dielectric layer by a first carbon-silicon bond, and a first distal end including a first organic functional group.

[0006] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, characterized in that a first component including a first dielectric layer is provided; a second component including a second dielectric layer is provided; a first organic base layer including a first carbon chain structure is deposited on a first surface of the aforementioned first dielectric layer; a second organic base layer including a second carbon chain structure is deposited on a second surface of the aforementioned second dielectric layer; the aforementioned first component and the aforementioned second component are arranged adjacent to each other so that the aforementioned first surface faces the aforementioned second surface; and the aforementioned first component and the aforementioned second component are bonded by a covalent bond formed between the aforementioned first carbon chain structure and the aforementioned second carbon chain structure, thereby forming the aforementioned semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description in conjunction with the accompanying drawings of the specification can better understand the content of the embodiments of the present disclosure. It should be emphasized that, according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a vertical cross-sectional view of a chip assembly structure according to various embodiments, the chip assembly structure including a first semiconductor die and a second semiconductor die to illustrate a first bonding configuration.

[0009] Figure 2 is a vertical cross-sectional view of a chip assembly structure including a first semiconductor die and a second semiconductor die according to various embodiments to illustrate another bonding configuration.

[0010] Figure 3A is a vertical cross-sectional view of an intermediate structure in a pre-bonding configuration prior to forming a direct dielectric-to-dielectric bond, the intermediate structure comprising a first dielectric layer and a second dielectric layer.

[0011] Figure 3B is a vertical cross-sectional view of another intermediate structure in a bonding configuration during formation of a direct dielectric-to-dielectric bond, the intermediate structure comprising Figure 3A A first dielectric layer and a second dielectric layer.

[0012] Figure 3C is a vertical cross-sectional view of a bonded structure after forming a direct dielectric-to-dielectric bond between a first dielectric layer and a second dielectric layer.

[0013] Figure 4 is a vertical cross-sectional view of a semiconductor structure having an improved dielectric-to-dielectric junction structure according to various embodiments.

[0014] Figure 5A A vertical cross-sectional view of an intermediate structure including a first dielectric layer and a second dielectric layer using an organic substrate layer in a pre-bonding configuration prior to forming a direct dielectric-to-dielectric bond according to various embodiments.

[0015] Figure 5B According to various embodiments, Figure 5A A vertical cross-sectional view of a bonding structure after a direct dielectric-to-dielectric bonding is formed between a first dielectric layer and a second dielectric layer.

[0016] Figure 5C FIG. 2 is a diagram showing an exemplary chemical reaction that may occur between an organic functional group and a carbon chain structure according to various embodiments.

[0017] Fig. 6A An exemplary carbon chain structure having a hydrogen / carbon ratio greater than 2 is shown according to various embodiments.

[0018] Figure 6B Comparative example cyclic carbon molecules having a hydrogen / carbon ratio approximately equal to 1 are shown according to various embodiments.

[0019] Figure 7 is a three-dimensional perspective view of a plasma jet device that may be used to deposit an organic base layer on a surface of a dielectric layer according to various embodiments.

[0020] Fig. 8A is a vertical cross-sectional view of an intermediate structure used in the formation of a semiconductor structure according to various embodiments.

[0021] Figure 8B is a vertical cross-sectional view of another intermediate structure used in forming a semiconductor structure according to various embodiments.

[0022] Figure 8C is a vertical cross-sectional view of another intermediate structure used in forming a semiconductor structure according to various embodiments.

[0023] Fig.8D is a vertical cross-sectional view of another intermediate structure used in forming a semiconductor structure according to various embodiments.

[0024] Fig. 9 A flow chart showing steps of a method of forming a semiconductor structure according to various embodiments.

[0025] Description of reference numerals:

[0026] 100a, 100b: Chip assembly structure (semiconductor packaging structure)

[0027] 102: First semiconductor grain

[0028] 104: Second semiconductor grain

[0029] 106a, 106b, 106c, 106d, 106e: Joint configuration

[0030] 108a: First electrical bonding structure

[0031] 108b: Second electrical bonding structure

[0032] 108c: The third electrical bonding structure

[0033] 110a: first bonding level dielectric layer (first dielectric layer)

[0034] 110b: second bonding level dielectric layer (second dielectric layer)

[0035] 112,112a,112b: Through substrate via (TSV) structure

[0036] 114,114a: Solder part

[0037] 116: Substrate

[0038] 300a,300b,500a,800a,800b,800c,800d: Intermediate structure

[0039] 300c,500b: Joint structure

[0040] 302a: First surface

[0041] 302b: Second surface

[0042] 304a: First separation distance

[0043] 304b: Second separation distance

[0044] 304c: The third separation distance

[0045] 400: Semiconductor Structure

[0046] 402a: First component

[0047] 402b: Second component

[0048] 406a: first semiconductor substrate

[0049] 406b: second semiconductor substrate

[0050] 408: Organic base layer

[0051] 408a: first organic base layer

[0052] 408b: Second organic base layer

[0053] 410a: first electrical interconnection structure

[0054] 410b: second electrical interconnection structure

[0055] 412: Carrier substrate

[0056] 502: Carbon chain structure

[0057] 502a: The first carbon chain structure

[0058] 502b: Second carbon chain structure

[0059] 503a1,503b1: Near end

[0060] 503a2,503b2: Remote

[0061] 504: Carbon-Silicon Bond

[0062] 506: Covalent Bond

[0063] 508: Carbon atom

[0064] 600a: Carbon chain structure

[0065] 600b: Ring-shaped carbon molecule

[0066] 700: Plasma jet device

[0067] 702: Solution

[0068] 704: Plasma

[0069] 802: Conductive materials

[0070] 900: Methods

[0071] 902,904,906,908,910,912: Steps

[0072] S: silanol group

[0073] R: first organic functional group (organic functional group)

[0074] R': second organic functional group

[0075] R”: Molecular structure

[0076] A: Illustration DETAILED DESCRIPTION

[0077] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present disclosure. Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first component is formed on or located on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present disclosure may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0078] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and other similar terms may be used herein to describe the relationship between an element or component as shown in the figure and other elements or components. In addition to the orientation shown in the drawings, the spatially relative terms also include different orientations of the device in use or operation. The device can be rotated arbitrarily (for example, rotated 90 degrees or to other orientations), and the spatially relative descriptions used herein can also be interpreted based on the rotated orientation. Furthermore, unless otherwise explicitly stated, each element with the same element number is assumed to be composed of the same material and has a thickness within the same thickness range.

[0079] Typically, in a semiconductor package, multiple semiconductor integrated circuit (IC) chips (i.e., "chips") can be mounted on a common substrate. The semiconductor package typically includes a housing that surrounds the IC die to protect the IC die from damage. The housing can also provide heat dissipation for the semiconductor package. The increased complexity of semiconductor packaging devices may create challenges associated with the need to reduce ohmic losses and thereby reduce heat generation and signal propagation delays. In order to mitigate such problems, new designs are needed that reduce interconnect lengths by increasing package density. There is also a continuing need for improved die-to-die bonding structures and methods. A promising method for bonding package components includes forming hybrid bonding structures that include metal-to-metal direct bonding between conductive bonding structures and dielectric-to-dielectric direct bonding between dielectric interfaces.

[0080] Various embodiments disclosed herein may benefit by providing an organic base layer that may be used in an improved dielectric-to-dielectric bonding process. Using an organic base layer may produce dielectric-to-dielectric bonds having increased strength relative to not using an organic base layer. The organic base layer may also allow dielectric-to-dielectric bonds to be formed at an annealing temperature that is much lower than the annealing temperature of a process that does not include an organic base layer. The organic base layer may have the effect of reducing internal stresses between bonded dielectric layers and may also allow dielectric layer surfaces having a greater degree of roughness to be bonded than using other dielectric-to-dielectric bonding processes.

[0081] A semiconductor structure of an embodiment may include a first component having a first electrical bonding structure formed in a first dielectric layer, a second component having a second electrical bonding structure formed in a second dielectric layer, and an organic substrate layer formed between the first dielectric layer and the second dielectric layer. The organic substrate layer may include a carbon chain structure, and the first dielectric layer is bonded to the second dielectric layer by bonds formed between the first dielectric layer, the second dielectric layer, and the organic substrate layer. The carbon chain structure may be characterized by a carbon number between 10 and 1000 and a hydrogen to carbon ratio (H / C) greater than 2, so that the organic substrate layer has a thickness of 0.5 nm to 30 nm. The carbon chain structure may include functional groups that form bonds between the carbon chain structures.

[0082] Another semiconductor structure may include a first component, the first component including a first dielectric layer and a first organic base layer formed on a first surface of the first dielectric layer, the first organic base layer including a first carbon chain structure. Each of the first carbon chain structures may include a first proximal end bonded to the first dielectric layer with a first carbon-silicon bond, and a first distal end including a first organic functional group. The semiconductor structure may also include a second component, the second component including a second dielectric layer and a second organic base layer formed on a second surface of the second dielectric layer, the second organic base layer including a second carbon chain structure. Each of the second carbon chain structures may include a second proximal end bonded to the second dielectric layer with a second carbon-silicon bond, and a second distal end including a second organic functional group. The first component and the second component may be bonded to each other through a covalent bond formed between the first organic functional group and the second organic functional group.

[0083] An embodiment method of forming a semiconductor structure may include providing a first component including a first dielectric layer, providing a second component including a second dielectric layer, depositing a first organic base layer including a first carbon chain structure on a first surface of the first dielectric layer, and depositing a second organic base layer including a second carbon chain structure on a second surface of the second dielectric layer. The method may also include placing the first component and the second component adjacent to each other so that the first surface faces the second surface. In some embodiments, the first surface may be parallel to the second surface. The method may also include bonding the first component to the second component by forming a covalent bond between the first carbon chain structure and the second carbon chain structure, thereby forming the semiconductor structure.

[0084] The various embodiment structures and methods disclosed herein may be used to form a chip assembly structure in which various circuits (e.g., memory arrays and peripheral circuits that control the operation of the memory arrays) may be implemented in different semiconductor dies. The semiconductor dies of the embodiments may be formed to have certain components that may be formed in a front-end-of-line (FEOL) process, in addition to other circuit components (e.g., interconnect structures formed with dielectric layers) formed in a back-end-of-line (BEOL) process, where the front-end process is to produce circuit components (e.g., CMOS logic circuits) in or on a semiconductor substrate.

[0085] As used herein, a "back-end of line" component or "BEOL" component refers to any component formed at a contact level or a metal interconnect level. A "metal interconnect level" refers to a level through which a metal interconnect structure of a metal line or metal via structure extends vertically. As used herein, a "front-end of line" component or "FEOL" component refers to any component formed before any contact level structure is formed, if a contact level structure is subsequently formed, or if a contact level structure or any metal interconnect structure is not formed (i.e., no contact layer structure or any metal interconnect structure is subsequently formed).

[0086] In some embodiments, a chip assembly structure may include a semiconductor die stack, the semiconductor die stack including two or more double-sided semiconductor dies, each double-sided semiconductor die having a center portion (formed in a FEOL process) disposed between a front-side interconnect structure and a back-side interconnect structure (formed in a corresponding BEOL process). For example, a die stack may include a first double-sided semiconductor die and a second double-sided semiconductor die. The first semiconductor die may include a first front-side interconnect structure and a first back-side interconnect structure, and the second semiconductor die may include a second front-side interconnect structure and a second back-side interconnect structure.

[0087] The first semiconductor die and the second semiconductor die may be electrically connected to each other by electrically connecting the first backside interconnect structure of the first semiconductor die to the second frontside interconnect structure of the second semiconductor die. In other embodiments, a chip assembly structure may include a semiconductor die stack including two or more single-sided dies having a backside FEOL portion and a frontside BEOL portion. The backside FEOL portion may include an electrical contact structure formed as a through-substrate via, and the frontside BEOL portion may include an interconnect structure formed in a dielectric material.

[0088] In various embodiments, the first semiconductor die and the second semiconductor die can be integrated into the chip assembly structure using a die-to-die connection, which can be achieved using a hybrid bonding process. The hybrid bonding process can produce a metal-to-metal direct bond between a first electrical bonding structure of a first backside interconnect structure and a second electrical bonding structure of a second frontside interconnect structure. This hybrid bonding process can also produce a dielectric-to-dielectric direct bond between a first dielectric layer of the first backside interconnect structure and a second dielectric layer of the second frontside interconnect structure. Various other bonding structures can be used to form a die-to-die connection, as described in more detail below.

[0089] Each semiconductor die in the chip stack may include circuit components configured to provide a corresponding function (e.g., logic, memory, image processing, power transmission, analog circuits, etc.). Because different semiconductor dies can provide different functions, a set of processing steps that can be used to manufacture a first semiconductor die (e.g., a memory die) and a set of processing steps that can be used to manufacture a second semiconductor die (e.g., a logic die) can be independently selected. The independently manufactured semiconductor dies can then be joined together in a semiconductor die stack. In this way, the performance of the first semiconductor die can be optimized without considering how the second semiconductor die can be optimized and / or without considering how the optimization of the first semiconductor die can negatively affect the second semiconductor die, or vice versa. For example, a memory die can be optimized with a primary focus on the density of memory cells, and a logic die can be optimized with a primary focus on device speed, reducing process variability, and reliability of the semiconductor device during operation (including, but not limited to, reliability of the device relative to power supply voltage changes).

[0090] The individual manufacturing processes and optimization of each semiconductor die in a semiconductor die stack can allow the production of chip assembly structures at a lower cost and with improved performance relative to semiconductor devices manufactured using other methods. In some embodiments, a standard layout of electrical bonding structures within the front and back interconnect structures of different semiconductor dies can allow multiple different types of semiconductor dies to be electrically connected to each other to form a chip assembly structure.

[0091] Figure 1 is a vertical cross-sectional view of a first chip assembly structure 100a including a first semiconductor die 102 and a second semiconductor die 104, showing a first bonding configuration 106a according to various embodiments, and Figure 2 is a vertical cross-sectional view of another chip assembly structure 100 b including a first semiconductor die 102 and a second semiconductor die 104 according to various embodiments, and Figure 2 Additional bonding configurations (106b, 106c, 106d, 106e) are shown. The first semiconductor die 102 can be configured as a control circuit-containing die, which can include a control circuit, and the second semiconductor die 104 can be configured to provide specific functions (e.g., memory, logic, etc.). The control circuit of the first semiconductor die 102 can include field effect transistors configured to control the operation of the second semiconductor die 104. Each of the first semiconductor die 102 and the second semiconductor die 104 can be configured as a double-sided semiconductor die or a single-sided semiconductor die.

[0092] The following reference Figure 1 and Figure 2 The described embodiments merely illustrate various ways of bonding two structures together. These examples relate to bonding a first semiconductor die 102 to a second semiconductor die 104. However, the disclosed embodiments are not limited to bonding between semiconductor die, and may include bonding between any components of a semiconductor package structure, such as bonding logic to memory, bonding logic to logic, bonding between logic and bridge die, bonding between die and wafer, wafer to chip bonding, and the like. Various types of die-to-die bonding may be used, such as bonding by Figure 1 and Figure 2 As shown in the various bonding configurations (such as 106 a , 106 b , 106 c , 106 d , and 106 e ) shown in FIG. 1 , the first semiconductor die 102 is electrically connected to the second semiconductor die 104 .

[0093] In an exemplary embodiment, the first semiconductor die 102 may include a first electrical bonding structure 108a, and the second semiconductor die 104 may include a second electrical bonding structure 108b. In an embodiment where the second semiconductor die 104 is configured as a memory die, at least a subset of the second electrical bonding structures 108b may be electrically connected to a metal interconnect structure in the memory die. Figure 1 As shown, the first electrical bonding structure 108a may be laterally surrounded by a first bonding-level dielectric layer 110a, which may include a dielectric material (e.g., silicon oxide) that may provide a dielectric-to-dielectric bond, or may include a passivation dielectric material (e.g., silicon nitride or silicon carbonitride). Similarly, the second electrical bonding structure 108b may be formed within the second bonding-level dielectric layer 110b.

[0094] According to one embodiment, the die-to-die bonding between the first semiconductor die 102 and the second semiconductor die 104 may be performed using metal-to-metal bonding (eg, see Figure 1 106a), or through-substrate-via-mediated bonding (e.g., see Figure 2106a). As used herein, "metal-to-metal bonding" refers to a bonding method and a bonding structure, wherein the bonding structure is formed by direct contact between a first metal surface (e.g., the first electrical bonding structure 108a in the bonding configuration 106a) and a second metal surface (e.g., the second electrical bonding structure 108b in the bonding configuration 106a), and internal diffusion of metal atoms across a bonding interface between the first metal surface and the second metal surface. An exemplary metal-to-metal bonding is copper-to-copper bonding. In embodiments where grain-to-grain bonding uses metal-to-metal bonding, the first electrical bonding structure 108a (e.g., formed as a first copper bonding pad) can be directly bonded to the second electrical bonding structure 108b (e.g., formed as a second copper bonding pad).

[0095] In one embodiment, dielectric bonding between paired dielectric material layers (e.g., first bonding-level dielectric layer 110a, second bonding-level dielectric layer 110b) may be used in combination with metal-to-metal bonding. This type of bonding (i.e., having metal-to-metal bonding and dielectric-to-dielectric bonding) may be referred to herein as hybrid bonding. In embodiments using hybrid bonding (e.g., see Figure 1 In the bonding configuration 106a in FIG. 1 , the first bonding level dielectric layer 110a can be bonded to the second bonding level dielectric layer 110b by dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding. Dielectric-to-dielectric bonding is generated by atomic interactions (e.g., van der Waals forces, hydrogen bonding, covalent bonding) occurring at the interface between the two dielectric materials, as described with reference to FIG. FIG. 3A to FIG. 3C A more detailed description is given.

[0096] As used herein, "through substrate via mediated bonding" refers to a bonding method or bonding structure in which an array of through substrate via (TSV) structures 112, 112a, 112b (e.g., see Figure 2 The bonding configurations 106b, 106c, 106d and 106e in the embodiment are used to provide bonding between the first semiconductor die 102 and the second semiconductor die 104, wherein the TSV structures 112, 112a, 112b extend vertically through a surrounding matrix material (the first bonding-level dielectric layer 110a and / or the second bonding-level dielectric layer 110b). In a first exemplary embodiment, as Figure 2As shown in the bonding configuration 106b shown, the array of TSV structures 112 can include a second electrical bonding structure 108b. In other words, the second electrical bonding structure 108b can be formed as an array of TSV structures 112. In this embodiment, an array of solder portions 114 can be used to provide bonding between the second electrical bonding structure 108b (which is the TSV structure 112) and the first electrical bonding structure 108a. In a second exemplary embodiment, as shown in FIG. Figure 2 As shown in the bonding configuration 106c, a substrate 116 including an array of TSV structures 112 may be provided. A first array of solder portions 114a may be used to attach the first electrical bonding structure 108a to the array of TSV structures 112, and a second array of solder portions 114b may be used to attach the second electrical bonding structure 108b to the array of TSV structures 112.

[0097] In the third exemplary embodiment, as Figure 2 In the illustrated bonding configuration 106d, the array of TSV structures 112 may include a first electrical bonding structure 108a. In other words, the first electrical bonding structure 108a may be formed as an array of TSV structures 112. In this embodiment, an array of solder portions 114 may be used to provide bonding between the first electrical bonding structure 108a (which is a TSV structure 112) and the second electrical bonding structure 108b. In a fourth embodiment, as shown in FIG. Figure 2 As shown in the bonding configuration 106e, each of the first electrical bonding structure 108a and the second electrical bonding structure 108b can be formed into a corresponding TSV structure array (112a, 112b). In this embodiment, the array of solder portions 114 can be used to provide bonding between the first electrical bonding structure 108a (which is formed as the first TSV structure 112a) and the second electrical bonding structure 108b (which is formed as the second TSV structure 112b).

[0098] In an embodiment where the second semiconductor die 104 is configured as a memory die and the first semiconductor die 102 is configured as a die including a control circuit, the control circuit can be realized by Figure 1 The metal-to-metal bonding between the paired electrical bonding structures (first electrical bonding structure 108a, second electrical bonding structure 108b) in the bonding configuration 106a is shown, or by Figure 2 The array of TSV structures (eg, TSV structures 112, 112a, 112b) shown in bonding configurations 106b, 106c, 106d, and 106e allows electrical nodes of a memory die to be connected to electrical nodes of a die containing control circuitry.

[0099] The memory die (e.g., the second semiconductor die 104) may include electrical connections for all bit lines and all word lines in one or more memory arrays in the memory die, and the die containing control circuitry (e.g., the first semiconductor die 102) may include the entirety of the control circuitry for the memory die. For example, the die containing control circuitry may include all peripheral circuits, including but not limited to bit line drivers, word line drivers, sense amplifiers, design-for-testability (DFT) circuits, scan chain circuits, built-in self-test (BIST) circuits, error checking and correction circuits (ECCs), phase-locked loop (PLL) circuits, electronically programmable fuse (e-Fuse) circuits, input / output (IO) circuits, voltage generator (power supply) circuits, etc.

[0100] Generally speaking, the front side (ie, Figure 1 and Figure 2 the bottom side in the embodiment) or the back side (ie, Figure 1 and Figure 2 The top side in the embodiment of the present invention can be used to form the first electrical bonding structure 108a. Similarly, the front side (i.e., the bottom side) or the back side (i.e., the top side) of the second semiconductor die 104 can be used to form the second electrical bonding structure 108b. In this way, the second semiconductor die 104 can be bonded to the first semiconductor die 102 using front-to-front bonding, front-to-back bonding, back-to-front bonding, or back-to-back bonding. Furthermore, in some embodiments, in addition to the memory die, at least one additional structure can be integrated into the second semiconductor die 104, which can include at least one BEOL structure, such as a memory die, a logic die, etc.

[0101] As described above, dielectric-to-dielectric bonding and / or metal-to-metal bonding (i.e., direct bonding or fusion bonding) is a wafer bonding process in which a chemical bond is formed between two surfaces. In some embodiments of a fusion bonding process, the two materials to be bonded must be sufficiently clean, flat, and smooth to avoid the formation of unbonded areas (e.g., voids, bubbles, etc.). The direct bonding process may include wafer pretreatment, pre-bonding (e.g., at room temperature), and annealing at elevated temperatures. For example, direct bonding between two silicon surfaces or silicon oxide surfaces may occur due to intermolecular interactions such as van der Waals forces, hydrogen bonds, and the formation of covalent bonds.

[0102] In a first step, the two surfaces to be bonded may be cleaned to remove impurities, particles, and / or other contaminants from the respective surfaces to be bonded. In order to achieve cleaning without reducing the surface quality, the surfaces to be bonded may be subjected to one or more dry or wet cleaning processes. The dry cleaning process may include plasma treatment or ultraviolet (UV) / ozone cleaning, while the wet chemical cleaning process may include treating the surfaces to be bonded with one or more wet chemical solutions. In an exemplary embodiment, the wet cleaning process may include applying a first solution (e.g., NH4OH (29%) + H2O2 (30%) + deionized water [1:1:5]), followed by applying a second solution (e.g., HCl (37%) + H2O2 (30%) + deionized water [1:1:6]). Organic contaminants and particles may be removed with the first solution at a temperature between 70°C and 80°C, and the cleaning may last for 5 to 10 minutes. Metal ions may be removed with the second solution at a temperature of approximately 80°C, and the cleaning may last for 10 minutes. After the cleaning process is completed, the two surfaces to be bonded may be rinsed with deionized water or stored in deionized water.

[0103] Figure 3A is a vertical cross-sectional view of an intermediate structure 300a in a pre-bonding configuration prior to forming a direct dielectric-to-dielectric bond, the intermediate structure 300a including a first junction-level dielectric layer 110a and a second junction-level dielectric layer 110b. Figure 3A The pre-bonding configuration shown may be formed by placing a first bonding level dielectric layer 110a and a second bonding level dielectric layer 110b (both of which have been cleaned) in close proximity to each other. Figure 3A As shown, for example, the first surface 302a of the first bonding-level dielectric layer 110a can be positioned to face the second surface 302b of the second bonding-level dielectric layer 110b. In some embodiments, the first surface 302a can be parallel to the second surface 302b. In some embodiments, the first bonding-level dielectric layer 110a and the second bonding-level dielectric layer 110b can be surface oxide layers of the corresponding two silicon wafers. After performing the cleaning process, each of the first bonding-level dielectric layer 110a and the second bonding-level dielectric layer 110b can have chemically adsorbed water molecules (H2O) connected to the silicon oxide surface (e.g., the first surface 302a, the second surface 302b) of the corresponding dielectric layer (the first bonding-level dielectric layer 110a, the second bonding-level dielectric layer 110b), for example Figure 3A shown.

[0104] Figure 3AThe pre-bonding configuration can correspond to a first separation distance 304a between the first surface 302a and the second surface 302b. For example, the first separation distance 304a can be between 1.1nm and 1.2nm. Under such separation, chemically adsorbed water molecules may begin to interact and form bonds. Bonding may include hydrogen bonds and van der Waals interactions between water molecules. In addition to this relatively weak interaction, strong covalent bonds may also begin to form. In this regard, silanol groups (i.e., Si-OH groups) can begin to polymerize (i.e., form covalent bonds) at room temperature. The polymerization process is controlled by the chemical equation: Si-OH+OH-Si→Si-O-Si+H2O, producing direct Si-O-Si bonds (i.e., siloxane compounds) and releasing water molecules (H2O).

[0105] After the pre-bonding process is performed in air, in a special gas, or in a vacuum, an annealing process may be performed on the first bonding level dielectric layer 110a and the second bonding level dielectric layer 110b at an elevated temperature to cause further polymerization of the silanol groups. During the annealing process, additional Si-O-Si bonds may be formed and additional water molecules may be released. The water molecules generated during the polymerization reaction may migrate or diffuse along the interface between the first surface 302a and the second surface 302b during the annealing process.

[0106] Figure 3B During the formation of a direct dielectric-to-dielectric bond (i.e., a covalent bond), including Figure 3A A vertical cross-sectional view of another intermediate structure 300b of a bonding configuration of the first bonding level dielectric layer 110a and the second bonding level dielectric layer 110b. Figure 3A Compared to the configuration shown, Figure 3B The bonding strength between the first surface 302a and the second surface 302b is increased. Figure 3A Compared to the configuration shown in FIG. 1 , the separation distance between the first surface 302a and the second surface 302b can be reduced. Figure 3B As shown, during the annealing process, when additional Si-O-Si bonds are formed, the separation distance can be reduced to a second separation distance 304b having a value between 0.55 nm and 0.65 nm. Under further annealing, the separation between the first surface 302a and the second surface 302b can continue to decrease as the bonding strength increases until a bonding structure 300c is formed (see, for example, Figure 3C In this regard, the bonding structure may have a third separation distance 304c which may be between 0.3 nm and 0.5 nm.

[0107] Figure 3Cis a vertical cross-sectional view of a bonding structure 300c after forming a direct dielectric-to-dielectric bond between the first bonding-level dielectric layer 110a and the second bonding-level dielectric layer 110b. Figure 3C The bonding structure 300c can be formed at the end of the annealing process. The annealing process provides a certain amount of thermal energy for the molecular substances that undergo chemical reactions. This thermal energy can cause additional silanol groups to react with each other, thereby generating highly stable chemical bonds between Si and O atoms at the interface between the first surface 302a and the second surface 302b. The number of covalent bonds formed may depend on the amount of energy transferred to the bonding molecules, which in turn depends on the annealing temperature. Therefore, within a certain temperature range, the interfacial bonding strength can increase with the increase of the annealing temperature. For example, between room temperature and a temperature of 110°C (i.e., during the pre-bonding stage), the interfacial bonding energy (i.e., representing the interfacial bonding strength) may be relatively low (i.e., with a low proportion of covalent bonds). At such a temperature, the polymerization of silanol can begin, but is limited. At this stage, water molecules diffuse at the bonding interface, causing various rearrangements of the silanol molecules, forming more hydrogen bonds between chemically adsorbed water molecules (i.e., hydrogen bonds are weaker bonds relative to Si-O-Si covalent bonds).

[0108] At a temperature of 110°C to 150°C, the silanol groups polymerize, thereby producing siloxane and water. At a given annealing temperature, which can be maintained for a sufficient time, a thermodynamic equilibrium can be established, in which the first portion of the unreacted silanol groups can be in equilibrium with the second portion of the siloxane (i.e., the chemical chain of the Si-O-Si bonding group). Therefore, for a given temperature range, increasing the annealing temperature can increase the second portion of the siloxane and, accordingly, increase the interfacial bonding strength. In this regard, the interfacial bonding strength can increase with temperature from 150°C to 800°C until most or all of the OH groups are polymerized and the composite strength reaches a constant value. At above 800°C, the native oxide may become viscous and may flow at the interface, thereby increasing the area of ​​the contact surface. At such a temperature, the diffusion of trapped hydrogen molecules along the interface can be enhanced, and the size of the interfacial voids can be reduced or eliminated. In some embodiments, the annealing process ends by cooling the bonding structure 300c to room temperature.

[0109] Figure 44 is a vertical cross-sectional view of a semiconductor structure 400 with an improved dielectric-to-dielectric bonding structure according to various embodiments. The semiconductor structure 400 may include a first component 402a and a second component 402b. The first component 402a may include a first electrical bonding structure 108a formed in a first dielectric layer 110a, and the second component 402b may include a second electrical bonding structure 108b formed in a second dielectric layer 110b. As described above, the first dielectric layer 110a (referred to as the first bonding-level dielectric layer 110a in the above example) may be formed of silicon dioxide, silicon nitride, silicon carbonitride, etc., and may be formed above a first semiconductor substrate 406a. The first semiconductor substrate 406a may be a silicon substrate, a silicon-on-insulator (SOI) substrate, etc. Similarly, the second dielectric layer 110b (referred to as the second bonding-level dielectric layer 110b in the above example) may be formed of silicon dioxide, silicon nitride, silicon carbonitride, etc., and may be formed on a second semiconductor substrate 406b. The second semiconductor substrate 406 b may also be a silicon substrate, a silicon-on-insulator (SOI) substrate, etc. In an exemplary embodiment, the first semiconductor substrate 406 a may be mounted to a carrier substrate 412 .

[0110] The semiconductor structure 400 may further include an organic base layer 408 formed between the first dielectric layer 110a and the second dielectric layer 110b, such that the first dielectric layer 110a is bonded to the second dielectric layer 110b via chemical bonds formed between the first dielectric layer 110a, the organic base layer 408, and the second dielectric layer 110b. Figure 5A and Figure 5B In more detail, the organic base layer 408 may include a carbon chain structure (eg, carbon chain structures 502a and 502b), and may have a thickness between 0.5 nm and 30 nm.

[0111] The organic base layer 408 can be used for improved fusion bonding (i.e., dielectric-to-dielectric) bonding processes. In this regard, the organic base layer 408 can be selectively placed on the dielectric bonding surfaces (see first surface 302a, second surface 302b in FIGS. 3A and 3B ) of the dielectric layers to be bonded (e.g., first bonding level dielectric layer 110a, second bonding level dielectric layer 110b) and can be used to bond the dielectric layers to the substrates without the organic base layer 408 (i.e., using the same method as described above). FIG. 3A to FIG. 3CThe organic base layer 408 can result in a dielectric-to-dielectric bond with increased strength, as compared to the dielectric-to-dielectric bond produced by the process similar to the process described above with reference to FIGS. 3A to 3C (i.e., up to 800° C.). The use of the organic base layer 408 can allow the dielectric-to-dielectric bond to be formed at a significantly reduced annealing temperature (i.e., between 150° C. and 350° C.) as compared to the temperature in the annealing process described above with reference to FIGS. 3A to 3C (i.e., up to 800° C.). The organic base layer 408 can also be used to reduce the internal stress between the bonded dielectric layers (e.g., the first bonding level dielectric layer 110 a, the second bonding level dielectric layer 110 b), and can also allow the bonded surfaces to have a greater roughness than can be tolerated using the process described above with reference to FIGS. 3A to 3C above. Figure 4 The semiconductor structure 400 may further include a metal-to-metal bond formed between the first electrical bonding structure 108a and the second electrical bonding structure 108b, as shown above. Figure 1 and Figure 2 There is a more detailed description of the process.

[0112] According to various embodiments, the first component 402a may be as described above with reference to Figure 1 , Figure 2 A semiconductor die (e.g., first semiconductor die 102, second semiconductor die 104) is described. For example, the first component 402a may include a circuit (not shown) formed in a FEOL process or in a BEOL process. The first component 402a may also include a first electrical interconnect structure 410a electrically coupled to the first electrical bonding structure 108a. The first electrical interconnect structure 410a may be formed in the first semiconductor substrate 406a. Similarly, the second electrical interconnect structure 410b may be formed in the second semiconductor substrate 406b. However, as described above, the disclosed embodiments need not be limited to bonding between semiconductor dies (e.g., first semiconductor die 102, second semiconductor die 104), and may include bonding between any components of a semiconductor package structure (e.g., semiconductor package structures 100a, 100b), such as bonding of a memory on top of a logic element, bonding of a logic element on top of a logic element, bonding between a logic element and a bridge die, bonding between dies and wafers, and bonding between wafers.

[0113] For example, the second component 402b may be one of a second semiconductor die (eg, the first semiconductor die 102, the second semiconductor die 104), an interposer, or a package substrate. The second component 402b may include a second electrical interconnect structure 410b electrically coupled to the second electrical bonding structure 108b. Figure 4As shown, the second component 402b may further include a third electrical bonding structure 108c formed on a side of the second component 402b opposite to the second electrical bonding structure 108b. The third bonding structure may be electrically connected to the second electrical bonding structure 108b via a second electrical interconnect structure 410b. The solder portion 114 may also be disposed on a surface of the third electrical bonding structure 108c, so that the second component 402b may be electrically connected to a third component (not shown), thereby forming the above-described Figure 2 The semiconductor package structure shown has a stack (eg, semiconductor package structures 100a, 100b). Or, Figure 4 The second component 402b may be an interposer or a package substrate. Figure 4 The semiconductor structure 400 may be configured to be electrically connected to a printed circuit board (not shown) in a subsequent packaging assembly operation.

[0114] Figure 5A According to various embodiments, an organic base layer 408 (eg, see Figure 4 ) is a vertical cross-sectional view of an intermediate structure 500a, the intermediate structure 500a comprising a first dielectric layer 110a and a second dielectric layer 110b. Figure 5A As shown, the organic base layer 408 may include a plurality of carbon chain structures (e.g., a first carbon chain structure 502a, a second carbon chain structure 502b). In this regard, the first carbon chain structure 502a may be formed on the first surface 302a of the first dielectric layer 110a, and the second carbon chain structure 502b may be formed on the second surface 302b of the second dielectric layer 110b. As shown, the first dielectric layer 110a and the second dielectric layer 110b may be disposed adjacent to each other so that the first surface 302a faces the second surface 302b. In some embodiments, the first surface 302a may be parallel to the second surface 302b. Each carbon chain structure (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b) may include carbon-silicon bonds 504 at the first surface 302a of the first dielectric layer 110a and at the second surface 302b of the second dielectric layer 110b. The intermediate structure 500a may correspond to a pre-bonded configuration, wherein the first surface 302a and the second surface 302b may be separated by a first separation distance 304a, which may be between 0.5 nm and 30 nm.

[0115] According to various embodiments, the carbon chain structure (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b) may further include one or more organic functional groups (R, R') bonded to one or more carbon atoms in the carbon chain structure (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b). In this regard, each of the carbon chain structures (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b) may include a corresponding proximal end (e.g., the proximal end 503a1, the proximal end 503b1) bonded to the corresponding dielectric layer (e.g., the first dielectric layer 110a, the second dielectric layer 110b) using a carbon-silicon bond 504, and a corresponding distal end (e.g., the distal end 503a2, the distal end 503b2) bonded to the respective organic functional groups (R, R'), such as Figure 5A As shown. The organic functional groups (R, R') may include one or more of amines, epoxides, carboxyl groups, isocyanate groups, hydroxyl groups, and compounds formed by reactions between two or more of amines, epoxides, carboxyl groups, isocyanate groups, and hydroxyl groups. The presence of the organic functional groups (R, R') may promote the bonding between the carbon chain structures (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b), as shown in FIG. Figure 5B and Figure 5C The content described in further detail.

[0116] Figure 5B is Figure 5A FIG. 5 is a vertical cross-sectional view of a bonding structure 500 b after a direct dielectric-to-dielectric bonding is formed between the first dielectric layer 110 a and the second dielectric layer 110 b . Figure 5C 1 shows an exemplary chemical reaction that may occur between an organic functional group (R, R') and a carbon chain structure (a first carbon chain structure 502a, a second carbon chain structure 502b) according to various embodiments. Figure 5C As shown, an epoxide group may be an example of a first organic functional group R that may be connected to the first carbon chain structure 502a, and an amine group may be an example of a second organic functional group R' that may be connected to the second carbon chain structure 502b. Figure 5C As shown, the first organic functional group R can chemically react with the second organic functional group R' to form a bonded molecular structure R".

[0117] like Figure 5C As shown, the bonded molecular structure R" may include a covalent bond 506 that joins the first carbon chain structure 502a to the second carbon chain structure 502b. In this example, the covalent bond 506 may be formed between the nitrogen atom of the second organic functional group R' (i.e., the amine group) and one of the carbon atoms 508 of the first organic functional group R (i.e., the epoxide group). According to some embodiments, the intermediate structure 500a may be subjected to a high temperature between 150°C and 350°C and 0.1N / cm 2Up to 500N / cm 2 In addition to the reaction between the organic functional groups (e.g., the first organic functional group R, the second organic functional group R') formed at the ends of the carbon chain structures (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b), other reactions (e.g., the reaction between the organic functional groups connected to the sides of the carbon chain structures (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b)) may also occur between adjacent carbon chain structures (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b) in the side chain reaction.

[0118] Fig. 6A An exemplary carbon chain structure 600a having a hydrogen / carbon ratio greater than 2 is shown, and Figure 6B A comparative example cyclic carbon molecule 600b is shown having a hydrogen / carbon ratio of approximately 1 according to various embodiments. Measurements made using techniques such as time-of-flight secondary ion mass spectroscopy (ToF-SIMS) can be used to determine the hydrogen / carbon ratio of a molecular structure as well as the carbon number (i.e., the number of atoms in the structure). Fig. 6A As shown, a hydrogen / carbon ratio greater than 2 indicates a carbon chain structure (i.e., having a carbon-carbon single bond), while a hydrogen / carbon ratio close to 1 indicates a carbon structure without a chain structure. For example, the cyclic molecule C6H6 (i.e., benzene) has a carbon single bond and a carbon double bond, and therefore is not a carbon chain structure. According to various embodiments, the carbon chain structure (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b) may have a carbon number (i.e., the number of atoms in the chain) between 10 and 1000. The formed organic base layer 408 may have a corresponding thickness (i.e., Figure 5B The value of the second separation distance 304b in can be between 0.5nm and 30nm. These values ​​of the carbon number and thickness of the organic substrate layer 408 can represent preferred values ​​for the bonding characteristics of the organic substrate layer 408. In this regard, too long carbon chains may become distorted and therefore may have reduced bonding efficiency due to steric hindrance. Similarly, in embodiments where the chain is too short, there may be fewer functional groups available to form chemical bonds.

[0119] Figure 73D perspective view of a plasma jet device 700 that can be used to deposit an organic base layer 408 on the first surface 302a of the first dielectric layer 110a according to various embodiments. In this regard, a solution 702 including a carbon chain structure 502 dissolved in an organic solvent can be formed. In a first chemical synthesis process, the carbon chain structure 502 can be formed as a precursor compound, wherein the carbon chain structure 502 can each have a first end bonded to a silanol group S (i.e., a molecule including a Si-OH group). In various embodiments, the organic functional group R can be one of an amine, an epoxide, a carboxyl group, an isocyanate group, a hydroxyl group, and a compound formed by reacting two or more of the amine, epoxide, carboxyl group, isocyanate group, and hydroxyl group.

[0120] The solution 702 may then be introduced into the plasma jet device 700, after which the plasma jet device 700 may form a plasma 704 containing fragments of the precursor compound. Next, the plasma 704 may be directed to the first surface 302a of the first dielectric layer 110a. As shown in inset A, the carbon chain structure 502 may be bonded to the surface 302a, such that the silanol group S forms a bond with the inorganic main chain (i.e., Si-O-Si structure) at the first surface 302a of the first dielectric layer 110a. Thus, the carbon chain structure 502 may each have a proximal end 503a1 bonded to the first dielectric layer 110a via the first carbon-silicon bond 504 and a distal end 503a2 to which the organic functional group R is attached, as described above. Figure 5A and Figure 5B The above-mentioned deposition process using the plasma jet device 700 is only an example of a method for depositing the organic base layer 408 on the first surface 302a of the first dielectric layer 110a. In other embodiments, other techniques such as spin coating or spray deposition may also be used to form the organic base layer 408.

[0121] FIG. 8A to FIG. 8D 8 are vertical cross-sectional views of intermediate structures 800a to 800d used in the formation of a semiconductor structure, respectively, according to various embodiments. Fig. 8A As shown, the intermediate structure 800a may include a first component 402a having a first electrical interconnect structure 410a formed in a first bonding-level dielectric layer 110a. The first bonding-level dielectric layer 110a may be formed over a first semiconductor substrate 406a. The first semiconductor substrate 406a may be a silicon substrate, a silicon-on-insulator (SOI) substrate, etc. The intermediate structure 800a may also have a conductive material 802 formed over a top surface of the first bonding-level dielectric layer 110a.

[0122] The conductive material 802 may be formed over an opening (not shown) in the first bonding-level dielectric layer 110a. In this regard, an opening may be etched in the first bonding-level dielectric layer 110a to expose a top surface of the first electrical interconnect structure 410a. The conductive material 802 may be deposited over the opening in the first bonding-level dielectric layer 110a using various techniques, such as by electroplating. In this manner, the conductive material 802 may be in electrical contact with the first electrical interconnect structure 410a. A planarization process (e.g., chemical mechanical planarization (CMP)) may then be performed to remove excess portions of the conductive material 802 formed over the top surface of the intermediate structure 800a, thereby forming Figure 8B The intermediate structure 800b. Figure 8B As shown, the formed intermediate structure 800 b may include a first electrical bonding structure 108 a formed within the first bonding-level dielectric layer 110 a .

[0123] In a further operation, a first organic base layer 408a may be formed over the first bonding-level dielectric layer 110a, such as Figure 8C As shown in the intermediate structure 800c. Figure 8C As shown in the illustration A in FIG. 1 , the first organic base layer 408a may include a plurality of first carbon chain structures 502a, which are attached to an inorganic main chain (i.e., Si-O-Si structure) formed on the first bonding-level dielectric layer 110a. Figure 7 , a plasma jet device 700 that can be used to perform a plasma jet deposition process can be used to deposit the first organic base layer 408a over the first bonding-level dielectric layer 110a. Alternatively, other techniques, such as spray deposition or spin coating, can be used to deposit the first organic base layer 408a. In addition, the first organic base layer 408a can be selectively deposited over the surface of the first bonding-level dielectric layer 110a. For example, a patterned mask material (not shown), such as a photoresist, can be used to shield the first electrical bonding structure 108a so that the first organic base layer 408a is not formed over the first electrical bonding structure 108a.

[0124] Fig.8DThe intermediate structure 800d can be formed by the intermediate structure 800c, which is formed by placing the second component 402b near the first component 402a so that the first surface 302a of the first bonding level dielectric layer 110a is oriented and parallel to the second surface 302b of the second bonding level dielectric layer 110b. As shown in the figure, the second component 402b may include a second electrical bonding structure 108b formed in the second bonding level dielectric layer 110b. The second electrical bonding structure 108b can be electrically connected to the second electrical interconnect structure 410b, and the second bonding level dielectric layer 110b can be formed above the second semiconductor substrate 406b. The second component 402b may also include a second organic base layer 408b formed above the surface of the second bonding level dielectric layer 110b. In addition, the second organic base layer 408b can be selectively deposited on the surface of the second bonding level dielectric layer 110b. In this regard, as described above, a patterned mask material (not shown) such as photoresist may be used to mask the second electrical bonding structure 108b so that the second organic base layer 408b is not formed on the second electrical bonding structure 108b.

[0125] Afterwards, a bonding process may be performed to bond the carbon chain structures (eg, the first carbon chain structure 502a and the second carbon chain structure 502b) of the organic base layer 408 to form a bonded semiconductor structure (see Figure 4 and 5B , 400, 500b), as referred to above and FIG. 5A to FIG. 5C In this regard, the first organic functional group R connected to the first carbon chain structure 502a can react with the second organic functional group R' connected to the second carbon chain structure 502b. Figure 5C As described above, the reaction of the first organic functional group R and the second organic functional group R' can form a new molecular structure R" that combines the first carbon chain structure 502a with the second carbon chain structure 502b. In this regard, one or more covalent bonds 506 can be formed between the first carbon chain structure 502a and the second carbon chain structure 502b, such as Figure 5C Shown and described in more detail above.

[0126] Fig. 9Flowchart showing steps of a method 900 for forming a semiconductor structure 400 according to various embodiments. In step 902, the method 900 may include providing a first component 402a having a first dielectric layer 110a, and in step 904, the method 900 may include providing a second component 402b having a second dielectric layer 110b. In step 906, the method 900 may include depositing a first organic base layer 408a having a first carbon chain structure 502a on a first surface 302a of the first dielectric layer 110a. Similarly, in step 908, the method 900 may include depositing a second organic base layer 408b having a second carbon chain structure 502b on a second surface 302b of the second dielectric layer 110b. In step 910, the method 900 may include placing the first component 402a and the second component 402b adjacent to each other so that the first surface 302a faces the second surface 302b. In some embodiments, the first surface 302a may be parallel to the second surface 302b. At step 912, the method 900 may include bonding the first component 402a to the second component 402b by forming a covalent bond 506 between the first carbon chain structure 502a and the second carbon chain structure 502b to form the semiconductor structure 400 (eg, referring to Figures 4 to 5C ).

[0127] When forming the covalent bond 506 according to step 912, the method 900 may further include applying a pressure of 0.1 N / cm 2 and 500N / cm 2 A pressure between the first surface 302a and the second surface 302b forces the first surface 302a and the second surface 302b to press against each other, and heats the semiconductor structure 400 to a high temperature between 150°C and 350°C. According to step 906, a first organic base layer 408a is deposited on the first surface 302a, and according to step 908, a second organic base layer 408b is deposited on the second surface 302b. The method 900 may also include forming a solution 702 including a carbon chain structure (e.g., a first carbon chain structure 502a, a second carbon chain structure 502b) in an organic solvent. The method 900 may also include depositing the solution 702 on the first surface 302a and the second surface 302b, thereby forming the first organic base layer 408a and the second organic base layer 408b, respectively. In some embodiments, according to steps 906 and 908 of method 900, depositing the solution 702 may also include performing a plasma spray process (e.g., referring to Figure 7 and related descriptions), a spin coating process or a spray coating process, thereby depositing the solution 702 on the first surface 302a and the second surface 302b.

[0128] According to method 900, forming solution 702 may also include forming a precursor compound having a carbon chain structure (e.g., a first carbon chain structure 502a, a second carbon chain structure 502b), each carbon chain structure having a first end bonded to a silanol group S and a second end bonded to an organic functional group (e.g., a first organic functional group R, a second organic functional group R'), and dissolving the precursor compound in an organic solvent. According to method 900, the organic functional group (R, R') may include one of the following, such as an amine, an epoxide, a carboxyl group, an isocyanate group, a hydroxyl group, or a compound formed by a reaction between two or more of amine, an epoxide, a carboxyl group, an isocyanate group, and a hydroxyl group. According to method 900, forming a precursor compound may also include forming a carbon chain structure (e.g., a first carbon chain structure 502a, a second carbon chain structure 502b), the carbon number of which is between 10 and 1000 and has a hydrogen-to-carbon ratio H / C greater than 2.

[0129] With reference to all the drawings and according to various embodiments of the present disclosure, a semiconductor structure 400 is provided. The semiconductor structure 400 may include a first component 402a having a first electrical bonding structure 108a formed in a first dielectric layer 110a and a second component 402b having a second electrical bonding structure 108b formed in a second dielectric layer 110. The semiconductor structure 400 may also include an organic base layer 408 formed between the first dielectric layer 110a and the second dielectric layer 110b, the organic base layer 408 including a carbon chain structure (e.g., a first carbon chain structure 502a, a second carbon chain structure 502b). In this regard, the first dielectric layer 110a may be bonded to the second dielectric layer 110b by bonding formed between the first dielectric layer 110a, the organic base layer 408, and the second dielectric layer 110b. The semiconductor structure 400 may also include a metal-to-metal bond formed between the first electrical bonding structure 108a and the second electrical bonding structure 108b.

[0130] According to various embodiments, the carbon chain structure (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b) is characterized by having a carbon number between 10 and 1000 and a hydrogen-to-carbon ratio (H / C) greater than 2. In addition, the organic base layer 408 may have a thickness between 0.5 nanometers (nm) and 30 nm. The carbon chain structure (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b) may also include a carbon-silicon bond 504 at the first surface 302a of the first dielectric layer 110a and at the second surface 302b of the second dielectric layer 110b. The carbon chain structure (e.g., the first carbon chain structure 502a, the second carbon chain structure 502b) may also include one or more organic functional groups (e.g., a first organic functional group R, a second organic functional group R') bonded to one or more carbon atoms in the carbon chain structure. In various embodiments, the organic functional group (e.g., the first organic functional group R, the second organic functional group R') may include one or more of amines, epoxides, carboxyls, isocyanate groups, hydroxyl groups, and compounds formed by reactions between two or more of amines, epoxides, and carboxyl groups.

[0131] According to some embodiments, the first component 402a may be a semiconductor die (e.g., the first semiconductor die 102, the second semiconductor die 104) including a first electrical interconnection structure 410a electrically coupled to the first electrical bonding structure 108a. The second component 402b may be one of the second semiconductor die (e.g., the first semiconductor die 102, the second semiconductor die 104), an interposer, or a package substrate. In addition, the second component 402b may include a second electrical interconnection structure 410b electrically coupled to the second electrical bonding structure 108b.

[0132] According to other embodiments, another semiconductor structure 400 is provided. The semiconductor structure 400 may include a first component 402a including a first dielectric layer 110a and a first organic base layer 408a including a first carbon chain structure 502a formed on a first surface 302a of the first dielectric layer 110a. The first carbon chain structures 502a may each include a first proximal end 503a1 bonded to the first dielectric layer 110a using a first carbon-silicon bond 504, and a first distal end 503a2 including a first organic functional group R. The first carbon chain structure 502a is characterized by a carbon number of 10 to 1000 and a hydrogen-to-carbon ratio H / C greater than 2. According to various embodiments, the first organic functional group R may include one of an amine, an epoxide, a carboxyl group, an isocyanate group, a hydroxyl group, or a compound formed by a reaction between two or more of amine, epoxide, carboxyl group, isocyanate group, and hydroxyl group.

[0133] According to various embodiments, the semiconductor structure 400 may further include a second component 402b, the second component 402b including a second dielectric layer 110b and a second organic base layer 408b formed on a second surface 302b of the second dielectric layer 110b, the second organic base layer 408b including a second carbon chain structure 502b. The second carbon chain structures 502b may each include a second proximal end 503b1 bonded to the second dielectric layer 110b using a second carbon-silicon bond 504 and a second distal end 503b2 including a second organic functional group R'. In various embodiments, the first component 402a and the second component 402b may be bonded to each other by a covalent bond 506 formed between the first organic functional group R and the second organic functional group R'. The combined thickness of the first organic base layer and the second organic base layer may be between 0.5nm and 30nm.

[0134] The disclosed embodiments may provide some benefits by providing an organic base layer 408 that may be used in an improved dielectric-to-dielectric bonding process. The organic base layer 408 may produce a dielectric-to-dielectric bond having increased strength relative to a dielectric-to-dielectric bond produced without the organic base layer 408. The provision of the organic base layer 408 allows the dielectric-to-dielectric bond to be formed at a significantly reduced annealing temperature (e.g., between 150° C. and 350° C.) relative to the annealing temperature of a process that does not include the organic base layer 408 (e.g., up to 800° C.). The organic base layer 408 may function to reduce internal stresses between the bonded dielectric layers (e.g., the first bonding level dielectric layer 110a, the second bonding level dielectric layer 110b), and may also allow the bonded dielectric bonding surfaces (e.g., the first surface 302a, the second surface 302b) to have a greater degree of roughness than can be tolerated using other dielectric-to-dielectric bonding processes.

[0135] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can easily design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent structures do not deviate from the concept and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the concept and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be defined as defined by the claims.

Claims

1. A semiconductor structure, characterized in that: a first component including a first electrical bonding structure formed in a first dielectric layer; a second component including a second electrical bonding structure formed in the second dielectric layer; and An organic base layer, including a carbon chain structure, is formed between the first dielectric layer and the second dielectric layer, so that the first dielectric layer can be bonded to the second dielectric layer through bonds formed between the first dielectric layer, the organic base layer, and the second dielectric layer.

2. The semiconductor structure of claim 1, wherein the carbon chain structures are characterized by having a carbon number between 10 and 1000.

3. The semiconductor structure of claim 1, wherein the carbon chain structures are characterized by a hydrogen-to-carbon ratio greater than 2. 4 . The semiconductor structure of claim 1 , wherein the carbon chain structures further comprise carbon-silicon bonds on a first surface of the first dielectric layer and a second surface of the second dielectric layer.

5. A semiconductor structure, characterized in that: a first component including a first dielectric layer; and a first organic base layer, including a first carbon chain structure, formed on a first surface of the first dielectric layer, The first carbon chain structures respectively include: a first proximal end bonded to the first dielectric layer with a first carbon-silicon bond; and A first distal end includes a first organic functional group.

6. The semiconductor structure of claim 5, further comprising: a second component comprising a second dielectric layer; as well as a second organic base layer, including a second carbon chain structure, formed on a second surface of the second dielectric layer, The second carbon chain structures respectively include: a second proximal end bonded to the second dielectric layer via a second carbon-silicon bond; and a second distal end, comprising a second organic functional group, and The first component and the second component are bonded to each other through a covalent bond formed between the first organic functional group and the second organic functional group.

7. A method for forming a semiconductor structure, characterized in that: providing a first component including a first dielectric layer; providing a second component including a second dielectric layer; Depositing a first organic base layer including a first carbon chain structure on a first surface of the first dielectric layer; Depositing a second organic base layer including a second carbon chain structure on a second surface of the second dielectric layer; Disposing the first component and the second component adjacent to each other so that the first surface faces the second surface; as well as The first component and the second component are bonded by covalent bonds formed between the first carbon chain structures and the second carbon chain structures, thereby forming the semiconductor structure.

8. The method for forming a semiconductor structure according to claim 7, wherein bonding the first component and the second component further comprises: Apply at 0.1N / cm 2 and 500N / cm 2 A pressure therebetween forces the first surface and the second surface against each other; and The semiconductor structure is heated to a high temperature between 150°C and 350°C.

9. The method for forming a semiconductor structure as claimed in claim 7, wherein the first organic base layer and the second organic base layer are deposited on the first surface and the second surface respectively, further comprising: forming a solution comprising a carbon chain structure in an organic solvent; depositing the solution on the first surface and the second surface to form the first organic substrate layer and the second organic substrate layer, respectively; Depositing the solution may further include performing a plasma spraying process, a spin coating process or a spray coating process, so as to deposit the solution on the first surface and the second surface.

10. The method for forming a semiconductor structure according to claim 9, wherein forming the solution further comprises: forming a precursor compound including the carbon chain structures, each of the carbon chain structures having a first end bonded to a silanol group and a second end bonded to an organic functional group; and dissolving the precursor compound in the organic solvent, The organic functional group includes one of amine, epoxide, carboxyl, isocyanate, hydroxyl, or a compound formed by a reaction between two or more of amine, epoxide, carboxyl, isocyanate, and hydroxyl.

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