Methods and structures for shielding electromagnetic interference in photonic integrated circuits of stacked electronic integrated circuits

Abstract

The invention relates to a method and structure for shielding electromagnetic interference in a photonic integrated circuit (PIC) stacked on an electronic integrated circuit (EIC). According to the invention, the problem of electromagnetic interference is solved by adopting the through hole penetrating through the bulk silicon substrate of the PIC. The invention also uses a conductive layer covering the backside of the PIC bulk silicon substrate on which a metal heat spreader may be placed. Now, the vias may make electrical contacts from a reference mesh formed for a light emitting component of the PIC on one or more metal layers of the PIC to the conductive layer on the backside of the PIC. This arrangement allows for a robust electrical connection and allows the metal heat sink to act as a robust ground, thus terminating the electromagnetic field.

Description

Technical Field

[0001] The subject technology relates to semiconductor devices and methods of manufacturing the same. Background Art

[0002] The process of packaging silicon photonics often involves 3D stacking of electronic ICs (EICs) and photonic ICs (PICs). PICs are usually equipped with a modulator on the transmitter (Tx) side and a photodiode on the receiver (Rx) side, with multiple channels for both transmission and reception. PICs usually have a fairly thick bulk silicon, about 700 microns.

[0003] The design of the modulator usually includes a transmission line of specific length and characteristic impedance. Depending on the manufacturing foundry, this transmission line may not be shielded, which can lead to the emission of electric and magnetic fields. These fields can penetrate the 3D stack in all three dimensions.

[0004] Fields extending across the X and Y dimensions can potentially be terminated by vias connected to the reference net. However, in the Z direction, the field can propagate unrestricted within the bulk silicon of the PIC, limiting the extent to which grounding can be achieved in the Z direction.

[0005] In addition, a metal plate is often used on the back side of the PIC for effective heat dissipation, but is not electrically grounded. This setup can often result in high levels of electrical coupling or crosstalk between the transmitter and receiver paths. Electromagnetic interference in PICs originates primarily from light-transmitting components (such as unshielded transmission lines) to light-detecting components (such as photodetectors). Due to the lack of proper electrical shielding, the field from the transmission line can be directed toward the highly sensitive photodetector, exacerbating the problem. Summary of the invention

[0006] On the one hand, the present disclosure relates to an integrated circuit device, which includes: a printed circuit board (PCB); a first circuit on a first substrate, the first substrate including a first surface and a second surface, the first surface coupled to the PCB, the second surface including a first plurality of contacts coupled to the first circuit; a second circuit on a second substrate, the second substrate including a third surface and a fourth surface, the second circuit disposed on the first circuit, the second circuit including at least a first component and a second component, the third surface including a second plurality of contacts coupled to the first component and the second component, the second plurality of contacts coupled to the first plurality of contacts; a conductive material layer disposed on the fourth surface; a metal layer disposed in a dielectric between the first component and the third surface; a first plurality of through holes extending from the fourth surface through the second substrate to at least partially surround the first component, the first plurality of through holes coupled to the conductive material layer and the metal layer; and a second plurality of through holes extending from the fourth surface through the second substrate to at least partially surround the second component, the second plurality of through holes coupled to the conductive material layer and the metal layer.

[0007] On the other hand, the present disclosure relates to a method for suppressing electrical coupling in a photonics integrated circuit, the method comprising: providing a substrate comprising a first surface and a second surface, the second surface being opposite to the first surface; encapsulating a first photonic component and a second photonic component on the first surface, the first photonic component comprising at least a light emitter, the second photonic component comprising at least a light detector; forming an electrical reference grid based on at least one metal layer positioned in a dielectric, the dielectric at least partially covering the light emitter and the light detector; forming a first plurality of through holes through the substrate from the second surface to couple to the electrical reference grid, the first plurality of through holes being arranged to at least partially surround the light emitter; and forming a conductive layer on the second surface of the substrate, the conductive layer coupled to the first plurality of through holes and the electrical reference grid to form an electrical shield for the first photonic component.

[0008] On the other hand, the present disclosure relates to a photonics integrated device with electromagnetic shielding, comprising: a substrate having a first surface and a second surface, the second surface being opposite to the first surface; a circuit formed on the first surface, the circuit comprising at least a first component and a second component, the first component comprising at least a light emitter, and the second component comprising at least a light detector; a metal layer disposed in a dielectric on the first surface, the metal layer being an electrical reference having a ground connection; a first plurality of through-holes passing through the substrate from the second surface, the first plurality of through-holes being configured to couple to the electrical reference and at least partially surround the first component; a second plurality of through-holes passing through the substrate from the second surface, the second plurality of through-holes being configured to couple to the electrical reference and at least partially surround the second component; and a conductive layer disposed on the second surface of the substrate, the conductive layer being coupled to the first plurality of through-holes and the second plurality of through-holes to form a first electromagnetic shield and a second electromagnetic shield for the first component and the second component, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and the accompanying drawings, in which the same reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When a reference numeral is cited without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0010] Figure 1 is a schematic diagram of a photonic integrated circuit stacked on an electronic integrated circuit according to some embodiments of the subject technology.

[0011] Figure 2 is a schematic diagram of a photonic integrated circuit with through silicon via and backside metallization based electromagnetic shielding stacked on an electronic integrated circuit in accordance with some embodiments of the subject technology.

[0012] Figure 3 is a schematic top view of a photonic integrated circuit including a co-packaged transmitter and receiver according to one embodiment of the subject technology.

[0013] Figure 4 is a schematic perspective view of electromagnetic shielding based on through silicon vias and backside metallization according to an embodiment of the subject technology.

[0014] Figure 5 is a graph comparing crosstalk isolation for one Tx-Rx channel in three shielding models according to some embodiments of the subject technology. DETAILED DESCRIPTION

[0015] The subject technology relates to semiconductor devices and manufacturing methods. In a specific embodiment, a method for shielding electromagnetic interference in a silicon photonic integrated circuit is provided. The method includes forming a plurality of vias from a reference mesh at the top of the front through a bulk silicon substrate to a conductive layer covering the back side of the photonic integrated circuit chip. This arrangement allows for a stable electrical connection and allows a metal heat sink coupled to the back side to act as a stable ground, thus terminating the electric and magnetic fields. Other embodiments exist.

[0016] In the following description, for purposes of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, by the same token, a single feature or multiple features of any described embodiment should not be considered essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0017] In the examples, the term "circuit board", including the references to "main circuit board" and "small size circuit board", also known as a printed circuit board (PCB), refers to a flat rigid board made of insulating material (usually fiberglass or plastic) that contains a complex network of metal paths or "traces" that form the circuit system for various electronic devices. Components such as resistors, capacitors, and integrated circuits are then mounted on the circuit board and their leads are soldered to the corresponding traces to form a functioning electronic circuit. "Main" or "small size" mainly refers to the lateral size of the circuit board, which is one of the important features of the present disclosure.

[0018] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element or have an intervening element present between the elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements. When an element is referred to herein as being "electrically coupled" to another element, it is understood that the element may be directly connected to the other element via an electrical conductor.

[0019] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or have intervening elements present between the elements. Conversely, when an element is referred to as being "directly disposed" relative to another element, it is understood that in the "direct" instance there are no intervening elements. However, the presence of a direct disposition does not exclude other instances in which intervening elements may be present.

[0020] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be joined directly to the other element (without any intervening elements) or with an intervening element present between the joined elements. Conversely, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining in which intervening elements may be present.

[0021] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer or conductive material layer may include a variety of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a variety of dielectric materials or multiple layers of dielectric materials. A "metal layer" or metallic material layer is only one type of conductive layer. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intermediary element present between the coupled or connected layers. Conversely, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there is no intermediary element between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which an intermediary element may be present.

[0022] In addition, the terms left, right, front, back, top, bottom, forward, backward, clockwise and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0023] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context otherwise indicates, the intermediary processes may occur before and / or after any portion of the described processes, and that various other processes may be reordered, added, and / or omitted according to various embodiments.

[0024] Unless otherwise indicated, all numbers used herein to indicate quantities, dimensions, and the like are to be understood as being modified by the term "about" in all instances. In this application, unless otherwise specifically indicated, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "comprising" and "having", as well as other forms such as "includes," "included," "has," "have," and "had," are to be considered non-exclusive. In addition, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit, unless otherwise specifically indicated.

[0025] As used herein, the phrase "at least one" preceding a series of items separated by the terms "and" or "or" modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one" does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any one item and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In examples where selection of "at least one of each of A, B, and C," or alternatively, "at least one of A, at least one of B, and at least one of C," is intended, it is explicitly described as such.

[0026] A general aspect of the present disclosure includes an integrated circuit device with electromagnetic shielding to suppress crosstalk interference. The integrated circuit device also includes a printed circuit board (PCB). The device also includes a first circuit on a first substrate, the first substrate including a first surface and a second surface, the first surface is coupled to the PCB, and the second surface may include a first plurality of contacts coupled to the first circuit. The device also includes a second circuit on a second substrate, the second substrate including a third surface and a fourth surface. The second circuit includes at least a first component and a second component and is disposed on the first circuit. The third surface may include a second plurality of contacts coupled to at least the first component and the second component. The second plurality of contacts are coupled to the first plurality of contacts. The device also includes a conductive material layer disposed on the fourth surface. The device also includes a metal layer disposed in a dielectric between the first component and the third surface. The device also includes a first plurality of through holes extending from the fourth surface through the second substrate to at least partially surround the first component, the first plurality of through holes being coupled to the conductive material layer and the metal layer. The device also includes a second plurality of through holes extending from the fourth surface through the second substrate to at least partially surround the second component, the second plurality of through holes being coupled to the conductive material layer and the metal layer.

[0027] The embodiment may include one or more of the following features. The first component may include a device of at least one of an optical transmitter, a laser, an optical amplifier, and an optical modulator. The first plurality of through holes and the second plurality of through holes may include a through hole to through hole spacing of less than 1 mm for achieving -125 dB isolation between the first component and the second component to protect them from electromagnetic interference with a characteristic frequency of up to 30 GHz. The second component may include at least one photodetector, an optical receiver, and an optical sensor. The device may include an electrical reference network based on a metal layer with a single ground connection. The metal layer may include a first ground layer that at least partially covers the area of ​​the first component and a second ground layer that at least partially covers the area of ​​the second component, the first ground layer and the second ground layer being isolated and having independent ground connections. The device may include a first metal plate disposed on a first portion of the fourth surface coupled to the first plurality of through holes and the first ground layer for shielding the first component, and a second metal plate disposed on a second portion of the fourth surface coupled to the second plurality of through holes and the second ground layer for shielding the second component, the second metal plate being decoupled from the first metal plate. The device may include a barrier layer disposed between the fourth surface and the conductive material layer. The conductive material layer may include a Cu or Al layer or an alloy layer of Cu and Al or a heavily doped silicon layer.The device may include a metal plate coupled to the conductive material layer on the fourth surface and electrically grounded.

[0028] Another general aspect includes a method for suppressing electrical coupling in a photonic integrated circuit. The method also includes providing a substrate that may include a first surface and a second surface, the second surface being opposite to the first surface. The method also includes encapsulating a first photonic component and a second photonic component on the first surface. The first photonic component may include at least a light emitter, and the second photonic component may include at least a light detector. The method also includes forming an electrical reference mesh based on at least one metal layer positioned in a dielectric, the dielectric at least partially covering the light emitter and the light detector. The method also includes forming a first plurality of vias through the substrate from the second surface to couple to the electrical reference mesh, the first plurality of vias being disposed to at least partially surround the light emitter. The method also includes forming a conductive layer on the second surface of the substrate, the conductive layer coupled to the first plurality of vias and the electrical reference mesh to form an electrical shield for the first photonic component.

[0029] Embodiments may include one or more of the following features. The method may also include forming a second plurality of vias through the substrate from the second surface to couple to an electrical reference mesh, the second plurality of vias being disposed to at least partially surround the photodetector. The method may include forming a second conductive layer on the second surface of the substrate to couple to the second plurality of vias and the electrical reference mesh to form an electrical shield for the second photon component. Forming the electrical reference mesh may include forming a first reference mesh that at least partially covers an area associated with the photoemitter, and forming a second reference mesh that at least partially covers an area associated with the photodetector. The first reference mesh and the second reference mesh are electrically isolated from each other and are separately grounded. The method may include forming at least one first metal contact and at least one second metal contact on the first surface, the at least one first metal contact being arranged to couple to the photoemitter and the at least one second metal contact being arranged to couple to the photodetector. The method may include coupling the at least one first metal contact and the at least one second metal contact to corresponding contacts of an electronic integrated circuit, respectively.

[0030] Yet another general aspect includes a photonics integrated device with electromagnetic shielding. The photonics integrated device also includes a substrate having a first surface and a second surface, the second surface being opposite to the first surface. The device also includes a circuit formed on the first surface. The circuit may include at least a first component and a second component. The first component may include at least a light emitter. The second component may include at least a light detector. The device also includes a metal layer disposed in a dielectric on the first surface. The dielectric at least partially covers the circuit. The metal layer is used as an electrical reference, which is set to have a specific voltage potential level, such as 0V. The device also includes a first plurality of through holes passing through the substrate from the second surface, the first plurality of through holes being configured to couple to the electrical reference and at least partially surround the first component. The device also includes a second plurality of through holes passing through the substrate from the second surface, the second plurality of through holes being configured to couple to the electrical reference and at least partially surround the second component. The device also includes a conductive layer on the second surface of the substrate, the conductive layer coupled to the first plurality of through holes and the second plurality of through holes to form a first electromagnetic shield and a second electromagnetic shield for the first component and the second component, respectively.

[0031] Embodiments may include one or more of the following features. Wherein the first plurality of through holes and the second plurality of through holes may include a through hole to through hole spacing separation of less than 1 mm to achieve at least -125 dB isolation between the light emitter and the light detector for electromagnetic interference having a characteristic frequency of up to 30 GHz. The metal layer may include a first section and a second section respectively grounded and respectively coupled to the first plurality of through holes and the second plurality of through holes. The conductive layer may include a first portion and a second portion respectively coupled to the first section and the second section to be associated with a first electromagnetic shield and a second electromagnetic shield respectively, the first electromagnetic shield being decoupled from the second electromagnetic shield. Embodiments of the subject technology are illustrated by the examples shown below.

[0032] Figure 1 is a schematic diagram of a photonic integrated circuit stacked on an electronic integrated circuit according to some embodiments of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0033] like Figure 1 , a silicon photonics device is packaged in a 3D stacked form of an electronic integrated circuit (EIC) 200 and a photonic integrated circuit (PIC) 100. For example, the EIC 200 may include a Tx driver subcircuit configured by one or more transistors 230 and an Rx amplifier subcircuit configured by one or more transistors 240. For example, a subcircuit refers to one of the circuit components. For example, the circuit 100 may include a plurality of subcircuits for various functions. A plurality of conductive vias 272 and 273 are used to couple the Tx driver subcircuit and the Rx amplifier subcircuit to metal contacts 219, respectively, to form a plurality of electrical contacts on a first surface of the EIC 200. The EIC 200 is mounted on the surface of the printed circuit board (PCB) 300 by directly bonding the plurality of electrical contacts on the first surface 1 to corresponding surface contacts on the PCB 300 by means of solder 260. There may be multiple metal layers (211, 212, 217) separated from each other by inter-metal dielectrics (IMDs) disposed between the device layer (including the Tx driver subcircuit and the Rx amplifier subcircuit) and the first surface 1 to form various electrical signal distributions and to form one or more electrical references with specific potential levels set for the circuits in the device layer. Optionally, there may be one or more other layers 221 inside the IMDs for circuit system layout. In addition, several conductive vias 252 and 253 are used to couple one or more electrodes of transistors 230 and transistors 240 to the second surface 2 of the EIC 200 through the inter-layer dielectric (ILD) to form electrical contacts of a first group of circuits in the EIC 200. Optionally, some conductive vias 251, 254, 256 may be used to connect one or more electrical contacts on the first surface to one or more electrical contacts on the second surface 2 for device routing, grounding purposes, and electrical shielding between sub-circuits in the EIC 200. The EIC 200 is formatted as a microchip having a thickness thinned to about 65 um between the first surface 1 and the second surface 2 before being mounted on the PCB 300 .

[0034] The PIC 100 is based on a silicon substrate 101 having a front side and a back side. The front side may be referred to as a first surface and the back side may be referred to as a second surface, the second surface being opposite to the first surface. The PIC 100 may include a first photonic subcircuit and a second photonic subcircuit co-packaged on the front side of the silicon substrate. The first photonic subcircuit may include at least one light emitting component and the second photonic subcircuit may include at least one light detecting component. Light emitting components including light generating components such as lasers (and laser drivers), light amplifying components such as optical amplifiers, light modulating components such as optical modulators, and optical transmitters are typically large electromagnetic field emitters that cause high electromagnetic interference to neighboring devices. On the other hand, light detecting components including photodetectors (PDs) such as photodiodes (PIN diodes or avalanche PDs), optical receivers (including signal processing), and optical sensors typically generate low electromagnetic interference themselves, but are highly sensitive to electromagnetic interference from other circuits. In a case such as Figure 1 In the example shown in , the first photonic subcircuit includes a light transmitter and the second photonic subcircuit includes an optical receiver. The silicon substrate 101 is characterized by a thickness greater than 700um between the front side and the back side, and a high resistivity of >750 ohm-cm, having the required mechanical strength and electrical properties for forming co-packaged integrated circuits and multiple discrete devices. Between the device layer and the front side of the silicon substrate, there may be a buried oxide layer 110. In some embodiments, the silicon substrate 101 is a silicon-on-insulator (SOI) substrate. Of course, other types of substrates may be used, such as pure silicon, silicon nitride, indium phosphide, gallium arsenide, or glass substrates, depending on the application.

[0035] refer to Figure 1, the transmitter and receiver are co-packaged sub-circuits on the front side of the silicon substrate 101. In an example, the optical transmitter includes at least a modulator 130, such as a Si-SiN-Si modulator with a transmission line (not shown). The optical receiver may include at least a photodiode 140, such as a SiGe photodiode. An interlayer dielectric (ILD) film may cover the PIC 100. Then, a plurality of metal layers 121, 122, 123 having a specific pattern are formed on the ILD film. These metal layers separated by the intermetallic dielectric (IMD) may have been designed for electrical signal distribution for the modulator 130 and the photodiode 140. In a specific embodiment, one or more of the plurality of metal layers (121, 122, 123) may be connected by internal connections to form a common electrical reference network. Optionally, the electrical reference network may include one or more metal layers or metal grids or networks spanning a specific spatial range. Optionally, the electrical reference network may be set to a certain voltage level, such as 3.3V, or electrically grounded. The plurality of metal layers may include a metal contact 129 disposed at a topmost layer over the third surface 3, i.e., the front side of the silicon substrate. Both the modulator 130 and the photodiode 140 may have one or more associated electrodes connected to the metal contact 129 through one or more conductive vias 152 and 153, respectively, which are patterned to form a second group of electrical contacts on the third surface 3 of the PIC 100.

[0036] In general, an electrical reference, often referred to as a reference plane or reference grid, is a stable point of known voltage against which other potentials are measured. This reference is critical in the design and analysis of electronic circuits and systems. In some embodiments, this reference grid is a "ground" or "common" node in a circuit that physically connects part of an electrical system to the earth, which serves as a universally available reference point. In some embodiments, "ground" does not refer to a physical connection to the earth, but rather to a point designated as a zero voltage reference for a circuit. Optionally, the electrical reference grid is a grounded metal layer. A reference grid or plane in a printed circuit board (PCB) design or the substrate of a circuit die is a grid or layer of conductive material, usually copper, that serves as a common return path for current and reference voltage levels. It can also provide a continuous low impedance path for the return of high frequency signals, which can help reduce noise and electromagnetic interference (EMI).

[0037] The PIC 100 is stacked on the EIC 200 by directly bonding the second group of electrical contacts on the third surface 3 to the first group of electrical contacts on the second surface 2 via solder 160. Thus, the modulator 130 in the PIC 100 will perform its signal modulation function based on the drive signal delivered from the Tx driver subcircuit 230 in the EIC 200. The Rx amplifier subcircuit 240 will also perform its amplification function on the electrical signal output from the photodiode 140. This is just a simple description of a single signal transmit / receive (Tx-Rx) channel of the device. Optionally, there are multiple Tx-Rx channels for transmitters and receivers. Optionally, the modulator design uses a transmission line with a finite length at a specific characteristic impedance. Depending on the manufacturing process, this transmission line may be unshielded. This unshielded transmission line typically results in electric and magnetic fields that can penetrate the three-dimensional stack of PICs on the EIC in all three directions. The lateral extension of the electromagnetic field in the X and Y dimensions may be terminated by those conductive vias on the reference net. However, in the Z direction, electromagnetic fields induced by some active components including the transmitter subcircuit may propagate unhindered in or outside the PIC bulk silicon substrate 101 to generate electrical crosstalk with other subcircuits in the PIC including a receiver subcircuit with sensitive circuitry like a photodiode. For PICs with co-packaged subcircuits, not limited to only transmitter or receiver subcircuits, proper electrical shielding will be critical to suppress high frequency electrical coupling between closely packaged subcircuits.

[0038] For general purposes, the term "integrated circuit (IC)" (or simply "circuit") mentioned in this specification refers to a microelectronic device that incorporates various electronic components (such as transistors, diodes, resistors and capacitors) into a single semiconductor substrate configured with one or more functions. It usually refers to an electronic IC or EIC, also commonly referred to as a microchip or chip. "Photonic integrated circuit (PIC)" is a microelectronic device that specifically integrates various photonic components and functions onto a single chip. Similar to EIC, photonic integrated circuits provide a compact and highly integrated solution for controlling and manipulating optical signals. It usually incorporates active and passive optical components, including a combination of lasers, modulators, detectors, waveguides, splitters, couplers, filters and other optical elements. EIC or PIC may include multiple subcircuits packaged together in the same chip. "Subcircuit" refers to a unit device with a specific function configured within a "circuit". For example, "transmitter subcircuit" refers to a unit device of a PIC that performs light emission, which includes functions such as optical signal generation (laser), signal modulation, power amplification, wavelength division or others. The subcircuits of the PIC may be coupled with the subcircuits of the EIC, for example, the modulator in the transmitter subcircuit may require the driver subcircuit in the EIC to allow the digital signal (i.e., data) to be properly transmitted via the optical signal. The Rx amplifier subcircuit in the EIC may receive and process the electrical signal transmitted from the photodiode, converting the optical signal into an electrical signal in the PIC. Since multiple subcircuits are co-packaged in one PIC chip, the crosstalk between these subcircuits (especially for some subcircuits that generate high-frequency electric fields) interferes with the sensitive detection circuit systems in some other subcircuits.

[0039] Figure 2 Schematic diagram of a photonic integrated circuit with through silicon via based electromagnetic shielding and backside metallization stacked on an electronic integrated circuit according to some embodiments of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. Figure 2 Demonstrating EM shielding based on through silicon vias and backside metallization Figure 1 An improved layout of a silicon photonics device of the present invention. As mentioned, there is already a reference mesh formed between the circuit layer and the third surface of the PIC 100. This reference mesh covers an area spanning both the first and second photonic subcircuits in the XY dimensions of the PIC chip. The reference mesh can be connected to a single ground connection. Optionally, the reference mesh can be divided into two sections. The first section can be located in an area associated with the first photonic subcircuit and the second section can be located in an area associated with the second photonic subcircuit. Optionally, the first section of the reference mesh and the second section of the reference mesh can be grounded separately. Either way, the reference mesh can be used as a basis for forming an electrical shield for one or both of the first photonic subcircuit and the second photonic subcircuit to suppress electromagnetic crosstalk therebetween.

[0040] For example, a plurality of vias 451, 452, 461, 462 are formed from the back side of the silicon substrate 101 to vertically penetrate the silicon substrate to reach the metal layer of the reference grid. Before forming these through silicon vias, the silicon substrate 101 may be thinned to a thickness approximately the same as the EIC 200, such as 65um. After the vias are formed by a series of masking, photolithography, etching, and cleaning processes, they may be filled with a metal material to be conductive and able to share the same potential with the reference grid, such as a common ground. In an embodiment, these vias are formed with selected locations such that a first plurality of vias (such as vias 451 and vias 452) are configured to surround a first photonic subcircuit including at least the modulator 130, and a second plurality of vias (such as vias 461 and vias 462) are configured to surround a second photonic subcircuit including at least the photodiode 140. In an embodiment, these vias are not necessarily physically adjacent to each other to form a solid wall, but are formed at a certain via-to-via spacing distance. Depending on the type and application of the photonics circuit, the electromagnetic interference between different sub-circuits may have different frequencies of concern. For example, a transmission line-based modulator may cause electromagnetic interference (EMI) to an adjacent optical detection circuit system primarily in the frequency range from 13 GHz to 25 GHz. Based on a fiber optic transceiver, the common bandwidth ranges from 5 GHz to 30 GHZ. These frequency ranges correspond to wavelengths greater than 10 mm. If the through-hole spacing distance is set to 1 mm, which is about 10% of the EMI wavelength, then these through-holes can effectively block the EMI field from expanding. In the XY dimension, the first plurality of through-holes (e.g., through-holes 451, through-holes 452) effectively form a shielding wall surrounding the first photonic sub-circuit and the second plurality of through-holes (e.g., through-holes 361, through-holes 462) also effectively form a shielding wall surrounding the second photonic sub-circuit.

[0041] Further references Figure 2 , a conductive layer 410 may be formed on the back side of the silicon substrate 101. The conductive layer 410 may be formed by depositing a metal material (such as copper or aluminum or a CuAl alloy) with a thickness of about 0.5 um. The conductive layer 410 may be formed by doping a Si layer at the back side of the silicon substrate 101 with high electron impurities. Typically, before forming the conductive layer 410, a barrier layer may be first deposited on the back side of the silicon substrate. The barrier layer prevents the metal material from diffusing downward into the silicon substrate. The barrier layer at the corresponding point of each through hole (e.g., through hole 452) on the back side may be etched away to allow the conductive layer 410 to form an electrical contact with the filling metal material in the through hole. Thus, the conductive layer 410 provides electrical shielding in the Z dimension. The conductive layer is combined with the first plurality of through holes and the reference mesh to form a first electrical shielding cage that completely covers the first photonic subcircuit and extends into the body region of the silicon substrate 101. The conductive layer 410 together with the second plurality of vias and the reference mesh also forms a second electrical shielding cage to completely cover the second photonic subcircuit including a bulk region extending into the bulk silicon substrate 101 .

[0042] Optionally, the conductive layer 410 may be divided into two sections, the first section being associated with the first electrical shielding cage for shielding only the first photonic subcircuit, and the second section being associated with the second electrical shielding cage for shielding the second photonic subcircuit. In some embodiments, two metal plates may be added to couple with the two sections of the conductive layer 410. A first metal plate 421 is attached to the first section of the conductive layer, and a second metal plate 422 isolated from the first metal plate 421 may be attached to the second section of the conductive layer. This is also compatible with the optional provision of two separate reference nets as suggested in some embodiments. Then, the two electrical shielding cages may be independently grounded. The grounded metal plate 421 may effectively terminate the electromagnetic field to prevent the EMI field from extending from the first subcircuit (e.g., a modulator with a transmission line) to the adjacent second subcircuit (e.g., a photodiode). For example, it may be advantageous to have an "Rx GND" and "TxGND" reference net in the PIC and EIC. In some embodiments, the reference nets in the system (if they are provided in a printed circuit board) will be connected together to have a common ground.

[0043] Figure 3 is a schematic top view of a photonic integrated circuit including a co-packaged transmitter and receiver according to an embodiment of the subject technology. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. Figure 3 An example of a silicon photonics device in a chip is shown, the chip having a PIC stacked on an EIC mounted on a printed circuit board 300. In the top view, only the PIC is visible, which includes, as an example, a transmitter subcircuit 130 and a receiver subcircuit 140. The transmitter 130 has four channels of transmission lines, represented as 131, 132, 133 and 134 respectively. Each transmission line is associated with an output terminal, represented as TxOut0, TxOut1, TxOut2 and Txout3 for channels 1 to 4 respectively. The electromagnetic interference generated by an optical transmitter is usually in the form of radiated electromagnetic fields, rather than conducted interference. The intensity of radiated electromagnetic interference (EMI) depends on factors such as power level, channel frequencies involved, proximity to other devices and the surrounding environment. The electrical signal driving the modulator can generate EMI, especially at higher frequencies. The transmit output terminal where the electrical signal is converted to an optical signal can be the main source of EMI radiation. Therefore, it is critical to have an electromagnetic shield to enclose at least these Tx output terminals to prevent the electromagnetic field from extending to affect other subcircuits in the same silicon photonics device package.

[0044] Receiver 140 also has 4 channels, each of which includes at least a photodiode, such as 141, 142, 143 and 144. Photodiodes are very sensitive to EMI caused by other nearby circuits. Specifically, at the optical input terminals represented as RxIn0, RxIn1, RxIn2 and RxIn3. The optical input terminals of the receiver are usually designed to detect and amplify weak optical signals. EMI can introduce additional noise or interference, reduce the sensitivity of the receiver and potentially reduce its ability to accurately detect and interpret input signals. EMI can increase the background noise of the receiver and reduce the overall signal-to-noise ratio. This will affect the ability of the receiver to distinguish between desired signals and undesired noise, resulting in a decrease in the quality and reliability of the received data. High levels of EMI can cause errors in the received data stream, increasing the bit error rate of the system. This can cause data corruption, loss of synchronization and overall system performance degradation. Therefore, it is important to have an electromagnetic shield to enclose at least the Rx input terminal to prevent the ambient electromagnetic field generated by the adjacent subcircuit from interfering with the performance of the receiver subcircuit.

[0045] refer to Figure 3 , to provide electromagnetic shielding that matches the requirements for the transmitter 130 or the receiver 140, a reference mesh 120 formed below the circuit plane of the silicon photonics device in the chip on the PCB can be utilized. The reference mesh 120 is made of one or more of a plurality of metal layers separated by intermetallic dielectrics. The plurality of metal layers are also used to form one or more electrical distributions or help connect the circuit electrodes through some conductive vias to connect to metal contacts on the chip surface for bonding with another chip or printed circuit board. The reference mesh 120 can be electrically grounded to provide electric field termination. Optionally, the reference mesh 120 can have two halves, one below the transmitter 130 and the other below the receiver 140. Optionally, the two reference meshes can be grounded separately, such as one is Tx GND and the other is Rx GND, so that they are completely isolated from each other.

[0046] In addition, in the vertical direction (perpendicular to the reference grid 120), a shielding structure may be formed to surround at least the transmitter 130 or the receiver 140. In an embodiment, the shielding structure is formed along Figure 3. Since the actual chip portion above the transmitter 130 and the receiver 140 is bulk silicon of a silicon substrate for silicon photonics devices, the plurality of conductive pillars are actually a plurality of through silicon vias (TSVs) filled with a metal material. Therefore, a first shield 450 is formed by the first plurality of conductive vias together with the reference mesh 120 below to completely surround the transmitter 130, especially the four TxOut terminals. A second shield 460 is formed by the second plurality of conductive vias together with the reference mesh 120 below to completely surround the receiver 140 including the four RxIn terminals. Since the frequencies of interest in Tx-Rx crosstalk EMI are in the range of 13 to 25 GHz, corresponding to a wavelength range greater than 10 mm, a plurality of vias with a pitch of 1 mm or less may be sufficient to block EMI.

[0047] Figure 4 is a schematic perspective view of an electromagnetic shield based on through silicon vias and backside metallization according to an embodiment of the subject technology. This figure is merely an example, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications. Figure 4 Another visual illustration of electromagnetic shielding based on through silicon vias and backside metallization for a silicon photonics device of a 3D stacked package with a photonic integrated circuit on an electronic integrated circuit is provided. As shown, the electronic integrated circuit includes two subcircuits 230 and 240 disposed at the lower portion of the stacked package. The photonic integrated circuit based on a silicon substrate includes two subcircuits 130 and 140 located above the two subcircuits 230 and 240 of the electronic integrated circuit, respectively. The photonic subcircuit 130 in the photonic integrated circuit includes a 4-channel transmitter having at least four Tx output terminals 131. The photonic subcircuit 140 in the photonic integrated circuit includes a 4-channel receiver having at least four Rx input terminals 144.

[0048] In some embodiments, an electromagnetic shielding cage for such a silicon photonics device is provided by: 1) placing a reference mesh 120 below the photonics subcircuit to be electrically grounded; 2) forming a plurality of vias 450 and 460 (in Figure 4 1) 3) filling a plurality of vias 450 and 460 to establish a potential consistent with the reference grid; 4) forming a conductive layer 410 overlying the back side of the silicon substrate to form two electromagnetic shielding cages respectively surrounding the photon subcircuit 130 and the photon subcircuit 140. In particular, the shielding cage (450) should completely terminate the extended electromagnetic field induced by the Tx output terminal 131 of the photon subcircuit 130 and prevent the electromagnetic field from interfering with the Rx input terminal 144 of the photon subcircuit 140.

[0049] Figure 5 is a graph comparing crosstalk isolation for one Tx-Rx channel in three shielding models according to some embodiments of the subject technology. This figure is only an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. Figure 5 Simulation results showing crosstalk isolation from single-channel Tx output to Rx input based on three electrical shielding models.

[0050] Curve 501 corresponds to an unshielded model (at least in the Z direction) of a silicon photonic device with a 3D stack of photonic ICs on an electronic IC (see Figure 1 ). The frequencies of interest are in the range of 13 GHz to 25 GHz. Simulation results indicate that the isolation between the Tx output and the Rx input in one transmit / receive channel is approximately -75 dB across the frequency range of 13 to 25 GHz.

[0051] Curve 502 corresponds to a model for electromagnetic shielding based on conductive vias and backside metallization for the same silicon photonics device (see Figure 2 ). As shown by curve 502, the simulation results produce much better isolation ranging from -135dB to -125dB, indicating that the electromagnetic shielding structure according to an embodiment of the subject technology effectively suppresses and contains the electromagnetic interference between the Tx output and the Rx input of the photonic integrated circuit. The 2D mapping of the field expansion of the Tx output (not shown) shows that the electric field is substantially terminated at the first shielding cage (450, see Figure 4 ) and at the border of the shielding cage for Rx input (460, see Figure 4 ) No field extension was found.

[0052] Curve 503 corresponds to a reference model without full shielding, but only with an RF absorber placed on the back side of the silicon substrate of the photonic integrated circuit. The results show that the added RF absorber provides only a small improvement in crosstalk isolation. The 2D field mapping (not shown) of this model also indicates that there is still a large amount of field extending from the Tx output to the Rx input. This proves that the methods and structures for shielding Tx-Rx crosstalk in photonic integrated circuits in the present disclosure are effective at suppressing high-frequency electrical coupling between two photonic subcircuits (such as a transmitter and a receiver) at a very basic level.

[0053] Although the above is a comprehensive description of specific embodiments, various modifications, alternative structures and equivalents may be used. Therefore, the above description and illustration should not be taken as limiting the scope of the subject technology defined by the appended claims.

Claims

1. An integrated circuit device, comprising: Printed circuit board PCB; a first circuit on a first substrate, the first substrate comprising a first surface and a second surface, the first surface being coupled to the PCB, the second surface comprising a first plurality of contacts coupled to the first circuit; a second circuit on a second substrate, the second substrate comprising a third surface and a fourth surface, the second circuit being disposed on the first circuit, the second circuit comprising at least a first component and a second component, the third surface comprising a second plurality of contacts coupled to the first component and the second component, the second plurality of contacts being coupled to the first plurality of contacts; a conductive material layer disposed on the fourth surface; a metal layer disposed in the dielectric between the first component and the third surface; a first plurality of vias extending from the fourth surface through the second substrate to at least partially surround the first component, the first plurality of vias being coupled to the conductive material layer and the metal layer; and A second plurality of vias extend from the fourth surface through the second substrate to at least partially surround the second component, the second plurality of vias being coupled to the conductive material layer and the metal layer.

2. The device of claim 1, wherein the first component comprises at least one of an optical transmitter, a laser, an optical amplifier, and an optical modulator.

3. The device of claim 1, wherein the second component comprises at least one of a photodetector, an optical receiver, and an optical sensor.

4. The apparatus of claim 1, further comprising an electrical reference net based on the metal layer having a single ground connection.

5. The device of claim 1, wherein the metal layer comprises a first ground layer at least partially covering an area of ​​the first component and a second ground layer at least partially covering an area of ​​the second component, the first ground layer and the second ground layer being isolated and having independent ground connections.

6. The device of claim 1, further comprising a barrier layer disposed between the fourth surface and the layer of conductive material. 7 . The device according to claim 1 , wherein the conductive material layer comprises a Cu or Al layer, an alloy layer of Cu and Al, or a heavily doped silicon layer.

8. The apparatus of claim 2, wherein the first plurality of vias or the second plurality of vias comprises a via-to-via pitch separation of less than 1 mm for achieving at least -125 dB isolation between the first component and the second component from electromagnetic interference having a characteristic frequency up to 30 GHz.

9. The device of claim 1, further comprising a metal plate coupled to the conductive material layer on the fourth surface and electrically grounded.

10. The device according to claim 5 further comprises a first metal plate located on a first portion of the fourth surface and coupled to the first plurality of through holes and the first ground layer for shielding the first component; and a second metal plate located on a second portion of the fourth surface and coupled to the second plurality of through holes and the second ground layer for shielding the second component, the second metal plate being decoupled from the first metal plate.

11. A method for suppressing electrical coupling in a photonic integrated circuit, the method comprising: Providing a substrate including a first surface and a second surface, wherein the second surface is opposite to the first surface; Encapsulating a first photon component and a second photon component on the first surface, the first photon component comprising at least a light emitter, the second photon component comprising at least a light detector; forming an electrical reference grid based on at least one metal layer positioned in a dielectric medium at least partially covering the light emitter and the light detector; forming a first plurality of vias through the substrate from the second surface to couple to the electrical reference net, the first plurality of vias being disposed to at least partially surround the light emitter; and A conductive layer is formed on the second surface of the substrate, the conductive layer coupled to the first plurality of vias and the electrical reference net to form an electrical shield for the first photonic component.

12. The method of claim 11, further comprising forming a second plurality of vias through the substrate from the second surface to couple to the electrical reference net, the second plurality of vias being disposed to at least partially surround the photodetector.

13. The method of claim 11, further comprising forming a second conductive layer on the second surface of the substrate to couple to the second plurality of vias and the electrical reference net to form an electrical shield for the second photonic component.

14. The method of claim 11 , wherein forming the electrical reference grid comprises forming a first reference grid that at least partially covers an area associated with the light emitter, and forming a second reference grid that at least partially covers an area associated with the light detector, the first reference grid and the second reference grid being isolated from each other and separately grounded.

15. The method of claim 11, further comprising forming at least one first metal contact and at least one second metal contact on the first surface, the at least one first metal contact arranged to couple to the light emitter and the at least one second metal contact arranged to couple to the light detector.

16. The method of claim 15, further comprising coupling the at least one first metal contact and the at least one second metal contact, respectively, to corresponding contacts of an electronic integrated circuit.

17. A photonics integrated device with electromagnetic shielding, comprising: A substrate having a first surface and a second surface, wherein the second surface is opposite to the first surface; a circuit formed on the first surface, the circuit comprising at least a first component and a second component, the first component comprising at least a light emitter, the second component comprising at least a light detector; a metal layer disposed in the dielectric on the first surface, the metal layer being an electrical reference having a ground connection; a first plurality of vias extending through the substrate from the second surface, the first plurality of vias configured to couple to the electrical reference and at least partially surround the first component; a second plurality of vias extending through the substrate from the second surface, the second plurality of vias configured to couple to the electrical reference and at least partially surround the second component; and A conductive layer disposed on the second surface of the substrate is coupled to the first and second pluralities of vias to form a first electromagnetic shield and a second electromagnetic shield for the first component and the second component, respectively.

18. The device of claim 17, wherein the first plurality of vias and the second plurality of vias comprise a via-to-via pitch separation of less than 1 mm to achieve -125 dB isolation between the optical emitter and the optical detector from electromagnetic interference having a characteristic frequency up to 30 GHz.

19. The device of claim 17, wherein the metal layer comprises first and second segments that are individually grounded and coupled to the first and second pluralities of vias, respectively.

20. The device of claim 19, wherein the conductive layer comprises a first portion and a second portion coupled to the first segment and the second segment, respectively, to be associated with the first electromagnetic shield and the second electromagnetic shield, respectively, the first electromagnetic shield being decoupled from the second electromagnetic shield.

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