Gate drive circuit, power conversion device, and motor unit

Abstract

The invention provides a gate drive circuit, a power conversion device, and a motor unit, the gate drive circuit includes: a first terminal to which a first potential is applied; a second terminal to which a second potential is applied; a third terminal connected to a gate terminal of the switching element; a first switch connected between the first terminal and the first node; a first diode having an anode terminal connected to the first node and a cathode terminal connected to the second node; an inductor connected between the first node and the third node; a second switch connected between the second node and the third node; a third switch connected between the second terminal and a third node; and a fourth switch connected between the second terminal and a fourth node, the first switch including a P-channel MOS-FET, the second switch, the third switch, and the fourth switch including an N-channel MOS-FET, the second node being directly or indirectly connected to the fourth node, and the fourth node being directly or indirectly connected to the third terminal.

Description

Technical Field

[0001] The present invention relates to a gate drive circuit, a power conversion device and a motor unit. Background Art

[0002] In recent years, SiC (silicon carbide) switching elements have attracted attention as power semiconductor switching elements that can cope with high withstand voltage, high heat resistance, and high-speed switching. In the case of SiC switching elements, due to low transconductance, the on-resistance does not decrease until a sufficiently high voltage is applied to the gate terminal, resulting in conduction loss.

[0003] High-speed switching of the switching element reduces the loss, but on the other hand, it worsens the noise and surge. When the switching element is turned on, the reverse recovery current generated by the body diode parasitic in the switching element is superimposed on the current waveform of the switching element. When the switching element is turned on at a high speed, the above-mentioned reverse recovery current becomes steep, thereby causing the worsening of noise and surge. When the switching element is turned off, a surge voltage is generated due to the parasitic inductance component of the current path of the switching element.

[0004] For example, Patent Document 1 discloses a gate driving circuit having a circuit configuration for reducing switching loss and noise as a gate driving circuit for driving a switching element.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2005-039988 Summary of the invention

[0006] As described above, there has been a demand for the development of a gate drive circuit that can achieve both reduction in switching loss of a switching element to be driven and suppression of noise and surge generated during switching.

[0007] The present invention is proposed in view of the above situation, and its purpose is to provide a gate drive circuit that can take into account both reducing the switching loss of the switching element that is the driving object and suppressing the noise and surge generated during switching, as well as a power conversion device and a motor unit equipped with the gate drive circuit.

[0008] One mode of the gate drive circuit of the present invention is a gate drive circuit for driving a switching element, comprising: a first terminal, to which a first potential is applied; a second terminal, to which a second potential lower than the first potential is applied; a third terminal, which is connected to the gate terminal of the switching element; a first switch, which is connected between the first terminal and a first node; a first diode, which has an anode terminal connected to the first node and a cathode terminal connected to the second node; an inductor, which is connected between the first node and a third node; a second switch, which is connected between the second node and the third node; a third switch, which is connected between the second terminal and the third node; and a fourth switch, which is connected between the second terminal and a fourth node, the first switch includes a P-channel MOS-FET, the second switch, the third switch and the fourth switch include N-channel MOS-FET, the second node is directly or indirectly connected to the fourth node, and the fourth node is directly or indirectly connected to the third terminal.

[0009] One embodiment of the power conversion device of the present invention comprises: a bridge circuit having a plurality of switching elements; a plurality of gate drive circuits which are provided corresponding to each of the plurality of switching elements and drive the corresponding switching elements; and a control unit which controls the plurality of gate drive circuits, wherein the plurality of gate drive circuits respectively comprise: a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; a third terminal connected to the gate terminal of the corresponding switching element; a first switch connected between the first terminal and a first node; a first diode having an anode terminal connected to the first node and a cathode terminal connected to the second node; an inductor connected between the first node and a third node; a second switch connected between the second node and the third node; a third switch connected between the second terminal and the third node; and a fourth switch connected between the second terminal and a fourth node, wherein the first switch comprises a P-channel MOS-FET, the second switch, the third switch and the fourth switch comprise an N-channel MOS-FET, the second node is directly or indirectly connected to the fourth node, and the fourth node is directly or indirectly connected to the third terminal.

[0010] One aspect of a motor unit of the present invention includes: a motor; and the power conversion device of the above aspect that supplies electric power to the motor.

[0011] According to the above aspects of the present invention, it is possible to provide a gate drive circuit that can achieve both reduction in switching loss of a switching element to be driven and suppression of noise and surge generated during switching, as well as a power conversion device and a motor unit including the gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a diagram schematically showing the structure of the motor unit 1 in the first embodiment.

[0013] Figure 2 1 is a circuit configuration diagram of the gate drive circuit GDA in the first embodiment.

[0014] Figure 3 1 is a first diagram showing the path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on.

[0015] Figure 4 3 is a second diagram showing the path of the current flowing through the gate drive circuit GDA when the switching element TR is turned on.

[0016] Figure 5 3 is a third diagram showing the path of the current flowing through the gate drive circuit GDA when the switching element TR is turned on.

[0017] Figure 6 1 is a diagram showing an example of waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned on.

[0018] Figure 7 1 is a first diagram showing the path of a current flowing through the gate drive circuit GDA when the switching element TR is turned off.

[0019] Figure 8 1 is a second diagram showing the path of the current flowing through the gate drive circuit GDA when the switching element TR is turned off.

[0020] Fig. 9 1 is a diagram showing an example of waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned off.

[0021] Fig.10 It is a circuit configuration diagram of a gate driving circuit GDB in the second embodiment.

[0022] Fig.11 1 is a first diagram showing the path of a current flowing through the gate drive circuit GDB when the switching element TR is turned on.

[0023] Fig.12 3 is a second diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned on.

[0024] Fig.13 3 is a third diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned on.

[0025] Fig.144 is a diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned on.

[0026] Fig.15 1 is a first diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned off.

[0027] Fig.16 1 is a second diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned off.

[0028] Fig.17 : is a circuit configuration diagram showing a first modification example of the gate drive circuit GDA.

[0029] Fig.18 2 is a circuit configuration diagram showing a second modification example of the gate drive circuit GDA.

[0030] Fig.19 1 is a circuit configuration diagram showing a third modified example of the gate drive circuit GDA. DETAILED DESCRIPTION

[0031] Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

[0032] [First embodiment]

[0033] First, a first embodiment of the present invention will be described. Figure 1 Schematically shows the structure of the motor unit 1 in the first embodiment. Figure 1 As shown, the motor unit 1 includes a motor 10 and a power conversion device 20. For example, the motor unit 1 is a driving motor unit mounted on an electric vehicle. Electric vehicles include electric vehicles, hybrid vehicles, plug-in hybrid vehicles, and fuel cell vehicles. For example, the motor 10 is a three-phase AC motor. The power conversion device 20 provides power to the motor 10.

[0034] The power conversion device 20 is connected to the motor 10 and the first DC power source 2, and performs mutual conversion between DC power and three-phase AC power. For example, when the power conversion device 20 functions as an inverter, the power conversion device 20 converts the DC power supplied from the first DC power source 2 into three-phase AC power and outputs it to the motor 10. For example, the first DC power source 2 is a driving battery that outputs a relatively high DC voltage among a plurality of batteries mounted on the electric vehicle.

[0035] The power conversion device 20 includes a bridge circuit 21, six gate drive circuits GD1 to GD6, a control unit 22, a smoothing capacitor 23, and a power supply circuit 24. In the present embodiment, the bridge circuit 21 is a three-phase full-bridge circuit having six switching elements TR1 to TR6. In the present embodiment, the switching elements TR1 to TR6 included in the bridge circuit 21 are, for example, N-channel MOS-FETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The switching elements TR1 to TR6 may also be IGBTs (Insulated-Gate Bipolar Transistors). In addition, the switching elements TR1 to TR6 may be switching elements made of SiC or switching elements made of Si.

[0036] The switching elements TR1, TR3 and TR5 are high-side switches of the bridge circuit 21. The drain terminals of the switching elements TR1, TR3 and TR5 are connected to the positive terminal of the first DC power supply 2. The switching elements TR2, TR4 and TR6 are low-side switches of the bridge circuit 21. The source terminals of the switching elements TR2, TR4 and TR6 are connected to the negative terminal of the first DC power supply 2.

[0037] The source terminal of the switching element TR1 is connected to the drain terminal of the switching element TR2 and the U-phase terminal of the motor 10. The source terminal of the switching element TR3 is connected to the drain terminal of the switching element TR4 and the V-phase terminal of the motor 10. The source terminal of the switching element TR5 is connected to the drain terminal of the switching element TR6 and the W-phase terminal of the motor 10.

[0038] The switching element TR1 has a body diode BD1 parasitic between the drain and source of the switching element TR1. As an equivalent circuit, the anode terminal of the body diode BD1 is connected to the source terminal of the switching element TR1, and the cathode terminal of the body diode BD1 is connected to the drain terminal of the switching element TR1.

[0039] Similar to the switching element TR1, the switching element TR2 has a body diode BD2. The switching element TR3 has a body diode BD3. The switching element TR4 has a body diode BD4. The switching element TR5 has a body diode BD5. The switching element TR6 has a body diode BD6.

[0040] The six gate drive circuits GD1 to GD6 are respectively provided corresponding to the six switching elements TR1 to TR6 to drive the corresponding switching elements. In addition, "driving the switching element" includes the case where the switching element is turned on by charging the input capacitance of the switching element and the case where the switching element is turned off by discharging the input capacitance of the switching element.

[0041] The gate drive circuit GD1 is provided corresponding to the switching element TR1, and drives the switching element TR1 according to the control signal input from the control unit 22. The gate drive circuit GD1 is connected to the gate terminal and the source terminal of the switching element TR1. The gate drive circuit GD2 is provided corresponding to the switching element TR2, and drives the switching element TR2 according to the control signal input from the control unit 22. The gate drive circuit GD2 is connected to the gate terminal and the source terminal of the switching element TR2.

[0042] The gate drive circuit GD3 is provided corresponding to the switching element TR3, and drives the switching element TR3 according to the control signal input from the control unit 22. The gate drive circuit GD3 is connected to the gate terminal and the source terminal of the switching element TR3. The gate drive circuit GD4 is provided corresponding to the switching element TR4, and drives the switching element TR4 according to the control signal input from the control unit 22. The gate drive circuit GD4 is connected to the gate terminal and the source terminal of the switching element TR4.

[0043] The gate drive circuit GD5 is provided corresponding to the switching element TR5, and drives the switching element TR5 according to the control signal input from the control unit 22. The gate drive circuit GD5 is connected to the gate terminal and the source terminal of the switching element TR5. The gate drive circuit GD6 is provided corresponding to the switching element TR6, and drives the switching element TR6 according to the control signal input from the control unit 22. The gate drive circuit GD6 is connected to the gate terminal and the source terminal of the switching element TR6.

[0044] The details will be described later, and the six gate drive circuits GD1 to GD6 have the same circuit structure. In the following description, when it is not necessary to distinguish the gate drive circuits GD1 to GD6, the gate drive circuits GD1 to GD6 are collectively referred to as gate drive circuits GDA. In addition, in the following description, the switching elements TR1 to TR6 are sometimes collectively referred to as switching elements TR, and the body diodes BD1 to BD6 are collectively referred to as body diodes BD.

[0045] The control unit 22 controls the gate drive circuits GD1 to GD6 by outputting control signals to the gate drive circuits GD1 to GD6. The details will be described later. The control signals output from the control unit 22 control the on timing and off timing of the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 included in the gate drive circuits GD1 to GD6.

[0046] For example, the control unit 22 has a function of communicating with an ECU (Electronic Control Unit) mounted on an electric vehicle. The control unit 22 receives a speed command signal from the ECU as a higher-level control device, and outputs a control signal for rotating the motor 10 at a target speed indicated by the speed command signal to the gate drive circuits GD1 to GD6, respectively. For example, the control unit 22 is a processor having a built-in memory not shown. As an example, the control unit 22 is an MCU (Microcontroller Unit). The control unit 22 controls the gate drive circuits GD1 to GD6 according to a program pre-stored in the memory.

[0047] The smoothing capacitor 23 is a capacitor connected in parallel with the first DC power supply 2. In addition, the smoothing capacitor 23 does not necessarily need to be arranged inside the power conversion device 20, and may be arranged outside the power conversion device 20.

[0048] The power supply circuit 24 is connected to the second DC power supply 3. For example, the second DC power supply 3 is a battery that outputs a relatively low DC voltage among a plurality of batteries mounted on the electric vehicle. The power supply circuit 24 generates a first power supply voltage Vdd used as a power supply voltage for each of the gate drive circuits GD1 to GD6 and a second power supply voltage Vc used as a power supply voltage for the control unit 22 based on the DC voltage supplied from the second DC power supply 3.

[0049] The power supply circuit 24 outputs the first power supply voltage Vdd to each of the gate drive circuits GD1 to GD6, and outputs the second power supply voltage Vc to the control unit 22. For example, the power supply circuit 24 is a regulator or a DC-DC converter. In addition, the DC voltage output from the first DC power supply 2 can also be used as the first power supply voltage Vdd supplied to the gate drive circuits GD1 to GD6.

[0050] Below, refer to Figure 2 , the structure of the gate driving circuit GDA in the first embodiment is described in detail. Figure 2 This is the circuit structure diagram of the gate drive circuit GDA. Figure 2 As shown, the gate drive circuit GDA includes a first terminal P1, a second terminal P2, a third terminal P3, a fourth terminal P4, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, an inductor L1, a first diode D1, and a first resistor Rg1.

[0051] The first terminal P1 is a terminal to which a first potential V1 is applied. The second terminal P2 is a terminal to which a second potential V2 lower than the first potential V1 is applied. The potential difference between the first potential V1 and the second potential V2 is equal to the first power supply voltage Vdd output from the power supply circuit 24. That is, the first power supply voltage Vdd output from the power supply circuit 24 is input to the gate drive circuit GDA via the first terminal P1 and the second terminal P2.

[0052] The third terminal P3 is a terminal connected to the gate terminal of the switching element TR corresponding to the gate drive circuit GDA. The fourth terminal P4 is a terminal connected to the source terminal of the switching element TR. For example, when the switching element TR is an IGBT, the fourth terminal P4 is connected to the emitter terminal of the switching element TR. In addition, the fourth terminal P4 is directly connected to the second terminal P2.

[0053] The first switch SW1 includes a P-channel MOS-FET. “The first switch SW1 includes a P-channel MOS-FET” means that the first switch SW1 may be composed of a single P-channel MOS-FET or a P-channel MOS-FET and a resistor connected in series. Figure 2 In this embodiment, the first switch SW1 is constituted by a single P-channel MOS-FET. When the first switch SW1 is constituted by a P-channel MOS-FET and a resistor connected in series, the resistor is preferably connected to the drain side of the P-channel MOS-FET.

[0054] The first switch SW1 has a first body diode SD1 parasitic between the drain and source of the first switch SW1, i.e., a P-channel MOS-FET. As an equivalent circuit, the anode terminal of the first body diode SD1 is connected to the drain terminal of the first switch SW1, and the cathode terminal of the first body diode SD1 is connected to the source terminal of the first switch SW1.

[0055] The first switch SW1 is connected between the first terminal P1 and the first node N1. That is, the source terminal of the first switch SW1 is connected to the first terminal P1. The drain terminal of the first switch SW1 is connected to the first node N1. The gate terminal of the first switch SW1 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the first switch SW1.

[0056] The first diode D1 has an anode terminal connected to the first node N1 and a cathode terminal connected to the second node N2. The inductor L1 is connected between the first node N1 and a third node N3.

[0057] The second switch SW2 includes an N-channel MOS-FET. “The second switch SW2 includes an N-channel MOS-FET” means that the second switch SW2 can be composed of an N-channel MOS-FET single body, or can be composed of an N-channel MOS-FET and a resistor connected in series. Figure 2 As shown, in this embodiment, the second switch SW2 is constituted by an N-channel MOS-FET single body. In addition, when the second switch SW2 is constituted by an N-channel MOS-FET and a resistor connected in series, it is preferable to connect the resistor to the drain side of the N-channel MOS-FET.

[0058] The second switch SW2 has a second body diode SD2 parasitic between the drain and source of the second switch SW2, i.e., an N-channel MOS-FET. As an equivalent circuit, the anode terminal of the second body diode SD2 is connected to the source terminal of the second switch SW2, and the cathode terminal of the second body diode SD2 is connected to the drain terminal of the second switch SW2.

[0059] The second switch SW2 is connected between the second node N2 and the third node N3. That is, the source terminal of the second switch SW2 is connected to the third node N3. The drain terminal of the second switch SW2 is connected to the second node N2. The gate terminal of the second switch SW2 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the second switch SW2.

[0060] The third switch SW3 includes an N-channel MOS-FET. Its meaning is the same as that of the second switch SW2. Figure 2 As shown, in this embodiment, an example is given in which the third switch SW3 is composed of an N-channel MOS-FET single body.

[0061] The third switch SW3 has a third body diode SD3 parasitic between the drain and source of the third switch SW3, i.e., an N-channel MOS-FET. As an equivalent circuit, the anode terminal of the third body diode SD3 is connected to the source terminal of the third switch SW3, and the cathode terminal of the third body diode SD3 is connected to the drain terminal of the third switch SW3.

[0062] The third switch SW3 is connected between the second terminal P2 and the third node N3. That is, the source terminal of the third switch SW3 is connected to the second terminal P2. The drain terminal of the third switch SW3 is connected to the third node N3. The gate terminal of the third switch SW3 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the third switch SW3.

[0063] The fourth switch SW4 includes an N-channel MOS-FET. Its meaning is the same as that of the second switch SW2. Figure 2As shown, in this embodiment, an example is given in which the fourth switch SW4 is composed of a single N-channel MOS-FET.

[0064] The fourth switch SW4 has a fourth body diode SD4 parasitic between the drain and source of the fourth switch SW4, i.e., an N-channel MOS-FET. As an equivalent circuit, the anode terminal of the fourth body diode SD4 is connected to the source terminal of the fourth switch SW4, and the cathode terminal of the fourth body diode SD4 is connected to the drain terminal of the fourth switch SW4.

[0065] The fourth switch SW4 is connected between the second terminal P2 and the fourth node N4. That is, the source terminal of the fourth switch SW4 is connected to the second terminal P2. The drain terminal of the fourth switch SW4 is connected to the fourth node N4. The gate terminal of the fourth switch SW4 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the fourth switch SW4.

[0066] The second node N2 is directly connected to the fourth node N4. Although the details will be described later, the second node N2 may be indirectly connected to the fourth node N4 via the fifth switch SW5. In this way, the second node N2 is directly or indirectly connected to the fourth node N4.

[0067] The first resistance element Rg1 is connected between the fourth node N4 and the third terminal P3. That is, the fourth node N4 is indirectly connected to the third terminal P3 via the first resistance element Rg1. The first resistance element Rg1 has a function as a gate resistor that limits the current flowing through the gate terminal of the switching element TR. The first resistance element Rg1 may be connected between the gate terminal of the switching element TR and the third terminal P3. In this case, the fourth node N4 is directly connected to the third terminal P3. In this way, the fourth node N4 is directly or indirectly connected to the third terminal P3.

[0068] Below, refer to Figures 3 to 6 , the operation of the gate drive circuit GDA when the switching element TR is turned on is described.

[0069] Figure 3 1 is a first diagram showing the path of the current flowing through the gate drive circuit GDA when the switch element TR is turned on. When the control unit 22 turns on the switch element TR, at the first timing, the first switch SW1 is turned on, and the second switch SW2, the third switch SW3, and the fourth switch SW4 are turned off. As a result, after the first timing, the current Figure 3 The flow is shown in the path indicated by the dashed arrow.

[0070] That is, after the first timing, the current flows in the order of the first terminal P1, the first switch SW1, the first node N1, the first diode D1, the second node N2, the fourth node N4 and the first resistor Rg1, and the current flows into the gate terminal of the switching element TR via the third terminal P3. Thus, after the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd.

[0071] Figure 6 : is a diagram showing an example of the waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned on. Figure 6 In the example, time t1 corresponds to the first timing. Figure 6 As shown, after time t1 corresponding to the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, whereby the on-resistance of the switching element TR decreases with the passage of time, and thus the drain current Id increases with the passage of time.

[0072] Figure 4 2 is a second diagram showing the path of the current flowing through the gate drive circuit GDA when the switch element TR is turned on. The control unit 22 turns on the third switch SW3 at the second timing after the first timing. As a result, after the second timing, the current Figure 4 Flows in the path indicated by the dashed arrow.

[0073] That is, after the second timing, in addition to the current flowing in the order of the first terminal P1, the first switch SW1, the first node N1, the first diode D1, the second node N2, the fourth node N4 and the first resistor Rg1, the current flows in the order of the first node N1, the inductor L1 and the third switch SW3. Therefore, after the second timing, while the input capacitance of the switch element TR is charged with the first power supply voltage Vdd, energy is accumulated in the inductor L1.

[0074] exist Figure 6 In the embodiment, the second timing is a time point between the first timing (time t1) and the time point at which the peak value of the reverse recovery current appears in the drain current Id. In other words, the second timing is preset as a time point between the first timing and the time point at which the peak value of the reverse recovery current appears in the drain current Id, and the control unit 22 turns on the third switch SW3 at the second timing preset in this way. In addition, the second timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0075] In addition, in the above description, an example is shown in which the control unit 22 turns on the third switch SW3 at the second timing, but the present invention is not limited to this. The control unit 22 may turn on the third switch SW3 at the first timing simultaneously with the first switch SW1. Alternatively, the control unit 22 may turn on the third switch SW3 in advance before the first timing. In these cases, after the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and energy is accumulated in the inductor L1.

[0076] Figure 5 3 is a third diagram showing the path of the current flowing through the gate drive circuit GDA when the switch element TR is turned on. The control unit 22 turns on the second switch SW2 and turns off the third switch SW3 at the third timing after the second timing. As a result, after the third timing, the current flows along Figure 5 The flow path is shown by the dashed arrow.

[0077] That is, after the third timing, the current flows in the order of the first terminal P1, the first switch SW1, the first node N1, the inductor L1, the third node N3, the second switch SW2, the second node N2, the fourth node N4 and the first resistor Rg1, and the current flows into the gate terminal of the switching element TR via the third terminal P3. Thus, after the third timing, since the energy accumulated in the inductor L1 is released as current, the potential of the second node N2 becomes higher than the first power supply voltage Vdd, and the current flowing into the gate terminal of the switching element TR increases. As a result, after the third timing, the input capacitance of the switching element TR is charged with a voltage higher than the first power supply voltage Vdd, so the charging speed of the input capacitance of the switching element TR increases.

[0078] exist Figure 6 In the example, time t2 corresponds to the third timing. Figure 6 As shown in FIG. 1 , the third timing (time t2) is a time point after the time point at which the peak value of the reverse recovery current appears in the drain current Id. In other words, the third timing is preset as a time point after the time point at which the peak value of the reverse recovery current appears in the drain current Id, and the control unit 22 turns on the second switch SW2 and turns off the third switch SW3 at the third timing preset in this way. In addition, the third timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0079] After all the energy stored in the inductor L1 is released as current, the current is Figure 3The current flows through the path shown, i.e., the first terminal P1, the first switch SW1, the first node N1, the first diode D1, the second node N2, the fourth node N4, and the first resistor Rg1 in this order, and the current flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after all the energy stored in the inductor L1 is released as current, the input capacitor of the switching element TR is charged with the first power supply voltage Vdd again.

[0080] exist Figure 6 In FIG. 1 , time t3 corresponds to the time point when all the energy stored in the inductor L1 is released as current. Figure 6 As shown, for example, when the switch element TR is completely turned on at time t3, the drain-source voltage Vds becomes substantially 0 V at time t3, and the drain current Id is maintained at a constant value after time t3.

[0081] As described above, when the switching element TR is turned on, the gate drive circuit GDA is controlled so that the charging speed of the input capacitance of the switching element TR increases from the third timing, which is a time point later than the time point when the peak value of the reverse recovery current appears in the drain current Id, thereby suppressing the generation of noise and surge caused by the reverse recovery current and reducing the switching loss during the conduction. In particular, since the charging speed increases in the second half of the conduction operation, the overdrive voltage can be quickly applied to the gate terminal of the switching element TR. As a result, the conduction loss in the second half of the conduction operation can be suppressed.

[0082] Next, refer to Figures 7 to 9 , describing the operation of the gate drive circuit GDA when the switching element TR is turned off.

[0083] Figure 7 1 is a first diagram showing the path of the current flowing through the gate drive circuit GDA when the switch element TR is turned off. When the control unit 22 turns off the switch element TR, the first switch SW1 is turned off at the fourth timing, and the second switch SW2, the third switch SW3, and the fourth switch SW4 are turned on. As a result, after the fourth timing, the current Figure 7 The flow is in the path shown by the dashed arrow.

[0084] That is, after the fourth timing, the current flows in the order of the third terminal P3, the first resistor element Rg1, the fourth node N4 and the fourth switch SW4, and at the same time, the current flows in the order of the fourth node N4, the second node N2, the second switch SW2, the third node N3 and the third switch SW3, releasing the current to the wiring connected to the source terminal of the switching element TR via the fourth terminal P4.

[0085] Fig. 9: is a diagram showing an example of the waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned off. Fig. 9 In the example, time t4 corresponds to the fourth timing. Fig. 9 As shown in FIG. 1 , after the time t4 corresponding to the fourth timing, the discharge current is Figure 7 As the current flows in the path shown, the on-resistance of the switching element TR increases with time, and thus the drain-source voltage Vds increases with time.

[0086] Figure 8 is a second diagram showing the path of the current flowing through the gate drive circuit GDA when the switch element TR is turned off. The control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at the fifth timing after the fourth timing. As a result, after the fifth timing, the current Figure 8 The flow is in the path shown by the dashed arrow in FIG. Figure 8 An example is shown in which both the second switch SW2 and the third switch SW3 are turned off.

[0087] That is, after the fifth timing, the current flows in the order of the third terminal P3, the first resistor Rg1, the fourth node N4, and the fourth switch SW4, and is released to the wiring connected to the source terminal of the switch element TR via the fourth terminal P4.

[0088] exist Fig. 9 In FIG. 1 , time t5 corresponds to the fifth timing. Fig. 9 As shown in FIG. 1 , the fifth timing (time t5) is a time point before the time point when the peak value of the surge voltage appears in the drain-source voltage Vds. In other words, the fifth timing is preset as a time point before the time point when the peak value of the surge voltage appears in the drain-source voltage Vds, and the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at the fifth timing preset in this way. In addition, the fifth timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0089] As described above, when the switching element TR is turned off, at the beginning of the turn-off operation, the input capacitance of the switching element TR is discharged through two discharge paths, namely, the discharge path including the second switch SW2 and the third switch SW3 and the discharge path including the fourth switch SW4. As a result, the discharge speed of the input capacitance of the switching element TR increases, so that the switching loss at the time of turn-off can be reduced. In addition, from the fifth timing, the input capacitance of the switching element TR is discharged only through the discharge path including the fourth switch SW4, wherein the fifth timing is a time point before the peak of the surge voltage appears in the drain-source voltage Vds. As a result, before the peak of the surge voltage appears in the drain-source voltage Vds, the discharge speed is reduced, so that the height of the peak of the surge voltage can be reduced. As a result, the noise and surge generated at the time of turn-off can be suppressed.

[0090] As described above, according to the gate drive circuit GDA of the first embodiment, it is possible to achieve both reduction in switching loss of the switching element TR to be driven and suppression of noise and surge generated during switching.

[0091] In addition, when the second switch SW2 is turned on at the third timing, a voltage higher than the first power supply voltage Vdd needs to be applied to the gate terminal of the second switch SW2 which is an N-channel MOS-FET. However, as described in the following modified example, when the second switch SW2 has a second body diode SD2, it is not necessary to turn on the second switch SW2 at the third timing.

[0092] When the second switch SW2 is turned on at the fourth timing, the third switch SW3 is also turned on, so the source potential of the second switch SW2 is consistent with the negative potential of the first power supply voltage Vdd, that is, the second potential V2. Therefore, when the second switch SW2 is turned on at the fourth timing, the first power supply voltage Vdd or a voltage obtained by dividing the first power supply voltage Vdd can be applied to the gate terminal of the second switch SW2.

[0093] When the first switch SW1 and the fourth switch SW4 are turned on, the second potential V2 or a potential between the first potential V1 and the second potential V2 may be applied to their respective gate terminals. When the third switch SW3 is turned on, the first potential V1 or a potential between the first potential V1 and the second potential V2 may be applied to the gate terminal of the third switch SW3. That is, the first switch SW1, the third switch SW3, and the fourth switch SW4 can be driven within a voltage range between the first potential V1 and the second potential V2.

[0094] [Second embodiment]

[0095] Next, a second embodiment of the present invention is described. The second embodiment differs from the first embodiment in that the power conversion device 20 has a gate drive circuit GDB having a structure different from that of the gate drive circuit GDA. That is, in the second embodiment, the structure of the power conversion device 20 other than the gate drive circuit GDB and the structure of the motor unit 1 are the same as those of the first embodiment, so only the structure and operation of the gate drive circuit GDB are described below.

[0096] Fig.10 2 is a circuit diagram of a gate drive circuit GDB in the second embodiment. Fig.10 and Figure 2 It can be seen that the gate drive circuit GDB in the second embodiment is different from the gate drive circuit GDA in the first embodiment in that it further includes a fifth switch SW5 connected between the second node N2 and the fourth node N4. That is, in the gate drive circuit GDB, the second node N2 is indirectly connected to the fourth node N4 via the fifth switch SW5.

[0097] The fifth switch SW5 includes a P-channel MOS-FET. Its meaning is the same as that of the first switch SW1. Fig.10 As shown, in this embodiment, an example is given in which the fifth switch SW5 is composed of a single P-channel MOS-FET.

[0098] The fifth switch SW5 has a fifth body diode SD5 parasitic between the drain and source of the fifth switch SW5, i.e., a P-channel MOS-FET. As an equivalent circuit, the anode terminal of the fifth body diode SD5 is connected to the drain terminal of the fifth switch SW5, and the cathode terminal of the fifth body diode SD5 is connected to the source terminal of the fifth switch SW5.

[0099] The fifth switch SW5 is connected between the second node N2 and the fourth node N4. That is, the source terminal of the fifth switch SW5 is connected to the second node N2. The drain terminal of the fifth switch SW5 is connected to the fourth node N4. The gate terminal of the fifth switch SW5 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the fifth switch SW5.

[0100] Below, refer to Figures 11 to 14 , describing the operation of the gate drive circuit GDB when the switching element TR is turned on.

[0101] Fig.11 1 is a first diagram showing the path of the current flowing through the gate drive circuit GDB when the switch element TR is turned on. When the control unit 22 turns on the switch element TR, the first switch SW1 and the third switch SW3 are turned on at a first timing, and the second switch SW2 and the fifth switch SW5 are turned off. As a result, after the first timing, the current Fig.11 The flow is shown in the path indicated by the dashed arrow.

[0102] That is, after the first timing, current flows in the order of the first terminal P1, the first switch SW1, the first node N1, the inductor L1, and the third switch SW3. Therefore, after the first timing, energy is accumulated in the inductor L1.

[0103] In addition, the fourth switch SW4 may be turned off at the first timing, but in order to prevent the gate voltage of the switching element TR from being unstable, the fourth switch SW4 is preferably turned on at the first timing.

[0104] Fig.12 2 is a second diagram showing the path of the current flowing through the gate drive circuit GDB when the switch element TR is turned on. The control unit 22 turns off the fourth switch SW4 and turns on the fifth switch SW5 at the second timing after the first timing. As a result, after the second timing, the current Fig.12 The flow is shown in the path indicated by the dashed arrow.

[0105] That is, after the second timing, in addition to the current flowing in the order of the first terminal P1, the first switch SW1, the first node N1, the inductor L1, and the third switch SW3, the current flows in the order of the first node N1, the first diode D1, the second node N2, the fifth switch SW5, the fourth node N4, and the first resistor Rg1, and the current flows into the gate terminal of the switching element TR via the third terminal P3. Therefore, after the second timing, while the input capacitance of the switching element TR is charged by the first power supply voltage Vdd, energy is accumulated in the inductor L1.

[0106] In the second embodiment, the second timing is set as a predetermined time point after the first timing as the time for energy to be accumulated in the inductor L1 , and the control unit 22 turns off the fourth switch SW4 and turns on the fifth switch SW5 at the second timing set in advance.

[0107] In addition, in the above description, an example is shown in which the control unit 22 turns on the first switch SW1 and the third switch SW3 at the first timing, turns off the second switch SW2 and the fifth switch SW5, turns off the fourth switch SW4 at the second timing, and turns on the fifth switch SW5, but the present invention is not limited thereto. For example, the control unit 22 may turn on the first switch SW1, the third switch SW3, and the fifth switch SW5 at the first timing, and turns off the second switch SW2 and the fourth switch SW4. In this case, after the first timing, while the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, energy is accumulated in the inductor L1.

[0108] Alternatively, the control unit 22 may turn on the first switch SW1 and the fifth switch SW5 at the first timing, turn off the second switch SW2, the third switch SW3, and the fourth switch SW4, and turn on the third switch SW3 at the second timing. In this case, after the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and after the second timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and energy is stored in the inductor L1.

[0109] Fig.13 3 is a third diagram showing the path of the current flowing through the gate drive circuit GDB when the switch element TR is turned on. The control unit 22 turns on the second switch SW2 and turns off the third switch SW3 at the third timing after the second timing. As a result, after the third timing, the current Fig.13 The flow is in the path shown by the dashed arrow.

[0110] That is, after the third timing, the current flows in the order of the first terminal P1, the first switch SW1, the first node N1, the inductor L1, the third node N3, the second switch SW2, the second node N2, the fifth switch SW5, the fourth node N4 and the first resistor Rg1, and the current flows into the gate terminal of the switching element TR via the third terminal P3. Thus, after the third timing, since the energy accumulated in the inductor L1 is released as current, the potential of the second node N2 becomes higher than the first power supply voltage Vdd, and the current flowing into the gate terminal of the switching element TR increases. As a result, after the third timing, the input capacitance of the switching element TR is charged with a voltage higher than the first power supply voltage Vdd, so the charging speed of the input capacitance of the switching element TR increases.

[0111] As in the first embodiment, in the second embodiment, the third timing is also preset as a time point after the time point at which the peak value of the reverse recovery current appears in the drain current Id, and the control unit 22 turns on the second switch SW2 and turns off the third switch SW3 at the third timing preset in this way. In addition, the third timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0112] Fig.14 The fourth diagram shows the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned on. After all the energy stored in the inductor L1 is released as current, the current flows as Fig.14The current flows through the path shown in the figure, that is, the first terminal P1, the first switch SW1, the first node N1, the first diode D1, the second node N2, the fifth switch SW5, the fourth node N4 and the first resistor Rg1 in this order, and the current flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after all the energy stored in the inductor L1 is released as current, the input capacitor of the switching element TR is charged with the first power supply voltage Vdd again.

[0113] As described above, when the switching element TR is turned on, the gate drive circuit GDB is controlled so that the charging speed of the input capacitance of the switching element TR increases from the third timing, which is a time point later than the time point at which the peak value of the reverse recovery current appears in the drain current Id, thereby suppressing the generation of noise and surge caused by the reverse recovery current and reducing the switching loss during the conduction. In particular, since the charging speed increases in the second half of the conduction operation, the overdrive voltage can be quickly applied to the gate terminal of the switching element TR. As a result, the conduction loss in the second half of the conduction operation can be suppressed.

[0114] Next, refer to Fig.15 and Fig.16 , describing the operation of the gate drive circuit GDB when the switching element TR is turned off.

[0115] Fig.15 1 is a first diagram showing the path of the current flowing through the gate drive circuit GDB when the switch element TR is turned off. When the control unit 22 turns off the switch element TR, the first switch SW1 is turned off at the fourth timing, and the second switch SW2, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 are turned on. As a result, after the fourth timing, the current Fig.15 The flow is shown in the path indicated by the dashed arrow.

[0116] That is, after the fourth timing, the current flows in the order of the third terminal P3, the first resistor element Rg1, the fourth node N4 and the fourth switch SW4. At the same time, the current flows in the order of the fourth node N4, the fifth switch SW5, the second node N2, the second switch SW2, the third node N3 and the third switch SW3, and releases the current to the wiring connected to the source terminal of the switching element TR via the fourth terminal P4.

[0117] Fig.16 2 is a second diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned off. Fig.16 As shown in FIG. 1 , the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at the fifth timing after the fourth timing. As a result, after the fifth timing, the current Fig.16 The flow is in the path shown by the dashed arrow. Fig.16 An example is shown in which both the second switch SW2 and the third switch SW3 are turned off.

[0118] That is, after the fifth timing, current flows in the order of the third terminal P3, the first resistor Rg1, the fourth node N4, and the fourth switch SW4, and is discharged to the wiring connected to the source terminal of the switch element TR via the fourth terminal P4.

[0119] As in the first embodiment, in the second embodiment, the fifth timing is also preset to a time point before the time point at which the peak of the surge voltage appears in the drain-source voltage Vds, and the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at the fifth timing preset in this way. In addition, the fifth timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0120] As described above, when the switching element TR is turned off, at the beginning of the turn-off operation, the input capacitance of the switching element TR is discharged through two discharge paths, namely, the discharge path including the second switch SW2, the third switch SW3, and the fifth switch SW5 and the discharge path including the fourth switch SW4. As a result, the discharge speed of the input capacitance of the switching element TR increases, so that the switching loss at the time of turn-off can be reduced. In addition, from the fifth timing, the input capacitance of the switching element TR is discharged only through the discharge path including the fourth switch SW4, wherein the fifth timing is a time point before the peak of the surge voltage appears in the drain-source voltage Vds. As a result, the discharge speed decreases before the peak of the surge voltage appears in the drain-source voltage Vds, so the height of the peak of the surge voltage can be reduced. As a result, the noise and surge generated at the time of turn-off can be suppressed.

[0121] As described above, according to the gate drive circuit GDB of the second embodiment, it is possible to take into account the reduction of the switching loss of the switching element TR as the driving object and the suppression of the noise and surge generated during switching, similarly to the gate drive circuit GDA of the first embodiment. In addition, in the structure of the gate drive circuit GDA of the first embodiment, there is the following restriction: after charging the input capacitance of the switching element TR with the first power supply voltage Vdd at the first timing, the energy accumulation of the inductor L1 starts at the second timing, or both are started at the first timing. On the other hand, the structure of the gate drive circuit GDB of the second embodiment does not have such a restriction. Therefore, the second embodiment has a higher degree of freedom in circuit design than the first embodiment.

[0122] In addition, similarly to the first embodiment, in the second embodiment, when the second switch SW2 is turned on at the third timing, it is necessary to apply a voltage higher than the first power supply voltage Vdd to the gate terminal of the second switch SW2 which is an N-channel MOS-FET. However, as described in the following modified example, when the second switch SW2 has a second body diode SD2, it is not necessary to turn on the second switch SW2 at the third timing.

[0123] In the second embodiment, similarly to the first embodiment, when the second switch SW2 is turned on at the fourth timing, the first power supply voltage Vdd or a voltage obtained by dividing the first power supply voltage Vdd may be applied to the gate terminal of the second switch SW2.

[0124] When the fifth switch SW5 is turned on at the second timing, the source potential of the fifth switch SW5, which is a P-channel MOS-FET, is equal to or greater than the positive potential of the first power supply voltage Vdd, that is, the first potential V1. Therefore, when the fifth switch SW5 is turned on at the second timing, the second potential V2 or a potential between the first potential V1 and the second potential V2 may be applied to the gate terminal of the fifth switch SW5.

[0125] If the fifth switch SW5 is to be maintained in the on state after the fourth timing, the negative potential of the first power supply voltage Vdd, that is, a potential lower than the second potential V2, needs to be applied to the gate terminal of the fifth switch SW5. However, as described in the modified example described later, when the fifth switch SW5 has a fifth body diode SD5, it is not necessary to turn on the fifth switch SW5 at the fourth timing. That is, the fifth switch SW5 can be driven within the voltage range between the first potential V1 and the second potential V2.

[0126] As in the first embodiment, in the second embodiment, when the first switch SW1 and the fourth switch SW4 are turned on, the second potential V2 or a potential between the first potential V1 and the second potential V2 may be applied to the respective gate terminals. When the third switch SW3 is turned on, the first potential V1 or a potential between the first potential V1 and the second potential V2 may be applied to the gate terminal of the third switch SW3. That is, the first switch SW1, the third switch SW3, and the fourth switch SW4 can be driven within a voltage range between the first potential V1 and the second potential V2.

[0127] [Modifications]

[0128] The present invention is not limited to the above-described embodiment, and the various configurations described in this specification can be appropriately combined within a range that does not contradict each other. For example, the following modified examples can be cited.

[0129] (1) The gate drive circuit GDA of the first embodiment may further include a second diode having an anode terminal connected to the third node N3 and a cathode terminal connected to the second node N2. The second diode may be a second body diode SD2 parasitic on the second switch SW2.

[0130] In such a modified example, the control unit 22 turns on the first switch SW1 at the first timing and turns off the second switch SW2 and the fourth switch SW4 when turning on the switch element TR. In addition, the control unit 22 turns on the third switch SW3 at a second timing before the first timing, at the first timing, or after the first timing. In addition, the control unit 22 turns off the third switch SW3 at a third timing after the second timing.

[0131] Thus, when the gate drive circuit GDA includes the second diode, it is not necessary to turn on the second switch SW2 at the third timing. This is because after the third timing, the current flowing through the inductor L1 flows through the second node N2, the fourth node N4, the first resistor Rg1 and the third terminal P3 via the second diode (second body diode SD2).

[0132] (2) The gate drive circuit GDB of the second embodiment may further include a second diode and a third diode. The second diode has an anode terminal connected to the third node N3 and a cathode terminal connected to the second node N2. The third diode has an anode terminal connected to the fourth node N4 and a cathode terminal connected to the second node N2. The second diode may be a second body diode SD2 parasitic on the second switch SW2. The third diode may be a fifth body diode SD5 parasitic on the fifth switch SW5.

[0133] In such a modified example, the control unit 22 turns on the first switch SW1 and the third switch SW3 at the first timing, and turns off the second switch SW2 and the fifth switch SW5, when turning on the switch element TR. In addition, the control unit 22 turns off the fourth switch SW4 and turns on the fifth switch SW5 at the second timing after the first timing. In addition, the control unit 22 turns off the third switch SW3 at the third timing after the second timing.

[0134] Thus, when the gate driving circuit GDB includes the second diode, it is not necessary to turn on the second switch SW2 at the third timing. This is because after the third timing, the current flowing through the inductor L1 flows through the second node N2, the fifth switch SW5, the fourth node N4, the first resistor Rg1, and the third terminal P3 via the second diode (second body diode SD2).

[0135] In addition, in such a modified example, the control unit 22 turns off the first switch SW1 and the fifth switch SW5 at the fourth timing, and turns on the second switch SW2, the third switch SW3, and the fourth switch SW4 when turning off the switch element TR. In addition, the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at the fifth timing after the fourth timing.

[0136] Thus, when the gate driving circuit GDB includes the third diode, it is not necessary to turn on the fifth switch SW5 at the fourth timing. This is because after the fourth timing, the current flowing from the third terminal P3 to the fourth node N4 flows through the second node N2, the second switch SW2, the third node N3 and the third switch SW3 via the third diode (fifth body diode SD5).

[0137] (3) In the gate drive circuit GDA of the first embodiment, when the total value of the on-resistance value of the second switch SW2 and the on-resistance value of the third switch SW3 is smaller than the on-resistance value of the fourth switch SW4, the control unit 22 may control the gate drive circuit GDA as follows. That is, the control unit 22 turns off the first switch SW1 and the fourth switch SW4 at the fourth timing, and turns on the second switch SW2 and the third switch SW3, while turning off the switch element TR. In addition, the control unit 22 turns on the fourth switch SW4 at the fifth timing after the fourth timing, and turns off at least one of the second switch SW2 and the third switch SW3.

[0138] In the above case, after the fourth timing, the current flows in the order of the third terminal P3, the first resistor Rg1, the fourth node N4, the second node N2, the second switch SW2, the third node N3, and the third switch SW3, but the current does not flow in the fourth switch SW4. After the fifth timing, the current flows in the order of the third terminal P3, the first resistor Rg1, the fourth node N4, and the fourth switch SW4.

[0139] (4) In the gate drive circuit GDB of the second embodiment, when the total value of the on-resistance value of the second switch SW2, the on-resistance value of the third switch SW3, and the on-resistance value of the fifth switch SW5 is smaller than the on-resistance value of the fourth switch SW4, the control unit 22 may control the gate drive circuit GDB as follows. That is, the control unit 22 turns off the first switch SW1 and the fourth switch SW4 at the fourth timing, and turns on the second switch SW2, the third switch SW3, and the fifth switch SW5, while turning off the switch element TR. In addition, the control unit 22 turns on the fourth switch SW4 at the fifth timing after the fourth timing, and turns off at least one of the second switch SW2 and the third switch SW3.

[0140] In the above case, after the fourth timing, the current flows in the order of the third terminal P3, the first resistor Rg1, the fourth node N4, the fifth switch SW5, the second node N2, the second switch SW2, the third node N3, and the third switch SW3, but the current does not flow in the fourth switch SW4. After the fifth timing, the current flows in the order of the third terminal P3, the first resistor Rg1, the fourth node N4, and the fourth switch SW4.

[0141] (5) Fig.17 1 is a circuit diagram showing a first variation of the gate drive circuit GDA. Fig.17 As shown, the gate drive circuit GDA may also include a second resistor element Rg2 and a third resistor element Rg3 instead of the first resistor element Rg1. The second resistor element Rg2 is connected in series with the first diode D1 between the first node N1 and the second node N2. The third resistor element Rg3 is connected in series with the inductor L1 between the first node N1 and the third node N3. In this case, the fourth node N4 is directly connected to the third terminal P3.

[0142] Alternatively, you can Fig.17 The structure shown is applied to the gate driving circuit GDB of the second embodiment.

[0143] (6) Fig.18 2 is a circuit diagram showing a second modified example of the gate drive circuit GDA. Fig.18 As shown, the gate drive circuit GDA may further include a clamp diode D2. The clamp diode D2 has an anode terminal connected to the third terminal P3 and a cathode terminal connected to the first terminal P1.

[0144] When the energy stored in the inductor L1 is excessive, the gate voltage of the switching element TR rises significantly, which may cause the switching element TR to be destroyed. By providing the clamp diode D2 as described above, the gate voltage of the switching element TR is clamped to the first power supply voltage Vdd, thereby preventing the switching element TR from being destroyed.

[0145] Alternatively, you can Fig.18 The structure shown is applied to the gate driving circuit GDB of the second embodiment.

[0146] (7) Fig.19 2 is a circuit diagram showing a third modified example of the gate drive circuit GDA. Fig.19 As shown, the gate drive circuit GDA may also include a fifth terminal P5 to which a third potential V3 lower than the first potential V1 and higher than the second potential V2 is applied. In this case, the fourth terminal P4 is directly connected to the fifth terminal P5.

[0147] The sum of the potential difference Vdd1 between the first potential V1 and the third potential V3 and the potential difference Vdd2 between the third potential V3 and the second potential V2 is equal to the first power supply voltage Vdd. In the case of the third modification of the gate drive circuit GDA, the power supply circuit 24 generates a DC voltage corresponding to the potential difference Vdd1 and a DC voltage corresponding to the potential difference Vdd2, and outputs them to the gate drive circuit GDA.

[0148] As described above, by adopting a structure in which the second terminal P2, which is the connection destination of the third switch SW3 and the fourth switch SW4, becomes a negative voltage relative to the source terminal of the switching element TR, the turn-off operation of the switching element TR can be accelerated, thereby further reducing the switching loss at the time of turn-off. In addition, in the case of adopting a structure using a high-side switching element TR and a low-side switching element TR as in the bridge circuit 21, the occurrence of false triggering can be suppressed.

[0149] Alternatively, you can Fig.19 The structure shown is applied to the gate driving circuit GDB of the second embodiment.

[0150] Furthermore, the present technology can adopt the following structures.

[0151] (1) A gate drive circuit that drives a switching element, the gate drive circuit comprising: a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; a third terminal connected to the gate terminal of the switching element; a first switch connected between the first terminal and a first node; a first diode having an anode terminal connected to the first node and a cathode terminal connected to the second node; an inductor connected between the first node and a third node; a second switch connected between the second node and the third node; a third switch connected between the second terminal and the third node; and a fourth switch connected between the second terminal and a fourth node, the first switch comprising a P-channel MOS-FET, the second switch, the third switch and the fourth switch comprising an N-channel MOS-FET, the second node being directly or indirectly connected to the fourth node, and the fourth node being directly or indirectly connected to the third terminal.

[0152] (2) The gate drive circuit according to (1), further comprising a fifth switch connected between the second node and the fourth node, wherein the fifth switch includes a P-channel MOS-FET.

[0153] (3) The gate driving circuit according to (1) or (2), further comprising a first resistance element connected between the fourth node and the third terminal.

[0154] (4) The gate drive circuit according to (1) or (2) further includes a second resistor element connected in series with the first diode between the first node and the second node, and the fourth node is directly connected to the third terminal.

[0155] (5) The gate drive circuit according to any one of (1) to (4), further comprising a clamp diode having an anode terminal connected to the third terminal and a cathode terminal connected to the first terminal.

[0156] (6) The gate drive circuit according to any one of (1) to (5), further comprising a fourth terminal connected to a source terminal or an emitter terminal of the switching element, wherein the fourth terminal is directly connected to the second terminal.

[0157] (7) The gate drive circuit according to any one of (1) to (5) further comprises: a fourth terminal connected to the source terminal or the emitter terminal of the above-mentioned switching element; and a fifth terminal to which a third potential lower than the above-mentioned first potential and higher than the above-mentioned second potential is applied, and the above-mentioned fourth terminal is directly connected to the above-mentioned fifth terminal.

[0158] (8) A power conversion device, comprising: a bridge circuit having a plurality of switching elements; a plurality of gate drive circuits, which are provided corresponding to each of the plurality of switching elements and drive the corresponding switching elements; and a control unit, which controls the plurality of gate drive circuits, wherein the plurality of gate drive circuits respectively comprise: a first terminal, to which a first potential is applied; a second terminal, to which a second potential lower than the first potential is applied; a third terminal, which is connected to a gate terminal of the corresponding switching element; a first switch, which is connected between the first terminal and a first node; and a first diode, which has an anode connected to the first node. a cathode terminal connected to the second node; an inductor connected between the first node and the third node; a second switch connected between the second node and the third node; a third switch connected between the second terminal and the third node; and a fourth switch connected between the second terminal and the fourth node, the first switch including a P-channel MOS-FET, the second switch, the third switch and the fourth switch including an N-channel MOS-FET, the second node being directly or indirectly connected to the fourth node, and the fourth node being directly or indirectly connected to the third terminal.

[0159] (9) According to the power conversion device described in (8), the above-mentioned second node is directly connected to the above-mentioned fourth node, and the above-mentioned control unit turns on the above-mentioned first switch at a first timing and turns off the above-mentioned second switch and the above-mentioned fourth switch when turning on the above-mentioned switching element, turns on the above-mentioned third switch at a second timing before the above-mentioned first timing, at the above-mentioned first timing or after the above-mentioned first timing, and turns on the above-mentioned second switch at a third timing after the above-mentioned second timing and turns off the above-mentioned third switch.

[0160] (10) According to the power conversion device described in (8), the above-mentioned second node is directly connected to the above-mentioned fourth node, and the above-mentioned gate drive circuit also has a second diode, which has an anode terminal connected to the above-mentioned third node and a cathode terminal connected to the above-mentioned second node. When the above-mentioned control unit turns on the above-mentioned switching element, the above-mentioned first switch is turned on at a first timing, and the above-mentioned second switch and the above-mentioned fourth switch are turned on at a second timing before the above-mentioned first timing, at the above-mentioned first timing, or after the above-mentioned first timing, and the above-mentioned third switch is turned off at a third timing after the above-mentioned second timing.

[0161] (11) According to the power conversion device described in (8), the above-mentioned second node is directly connected to the above-mentioned fourth node, and the above-mentioned control unit disconnects the above-mentioned first switch at a fourth timing when the above-mentioned switching element is disconnected, and connects the above-mentioned second switch, the above-mentioned third switch and the above-mentioned fourth switch, and disconnects at least one of the above-mentioned second switch and the above-mentioned third switch at a fifth timing after the above-mentioned fourth timing.

[0162] (12) According to the power conversion device described in (8), the above-mentioned gate drive circuit also has a fifth switch, which is connected between the above-mentioned second node and the above-mentioned fourth node and includes a P-channel MOS-FET. The above-mentioned control unit turns on the above-mentioned first switch and the above-mentioned third switch at a first timing and turns off the above-mentioned second switch and the above-mentioned fifth switch when turning on the above-mentioned switching element, turns off the above-mentioned fourth switch at a second timing after the above-mentioned first timing and turns on the above-mentioned fifth switch, and turns on the above-mentioned second switch at a third timing after the above-mentioned second timing and turns off the above-mentioned third switch.

[0163] (13) According to the power conversion device described in (8), the above-mentioned gate drive circuit further includes: a fifth switch, which is connected between the above-mentioned second node and the above-mentioned fourth node, and includes a P-channel MOS-FET; and a second diode, which has an anode terminal connected to the above-mentioned third node and a cathode terminal connected to the above-mentioned second node, and when the above-mentioned switching element is turned on, the above-mentioned control unit turns on the above-mentioned first switch and the above-mentioned third switch at a first timing, and turns off the above-mentioned second switch and the above-mentioned fifth switch, and turns on the above-mentioned fifth switch at a second timing after the above-mentioned first timing, and turns off the above-mentioned third switch at a third timing after the above-mentioned second timing.

[0164] (14) According to the power conversion device described in (8), the above-mentioned gate drive circuit also has a fifth switch, which is connected between the above-mentioned second node and the above-mentioned fourth node and includes a P-channel MOS-FET. The above-mentioned control unit disconnects the above-mentioned first switch at a fourth timing when the above-mentioned switching element is disconnected, and connects the above-mentioned second switch, the above-mentioned third switch, the above-mentioned fourth switch and the above-mentioned fifth switch, and disconnects at least one of the above-mentioned second switch and the above-mentioned third switch at a fifth timing after the above-mentioned fourth timing.

[0165] (15) According to the power conversion device described in (8), the above-mentioned gate drive circuit further includes: a fifth switch, which is connected between the above-mentioned second node and the above-mentioned fourth node, and includes a P-channel MOS-FET; and a third diode, which has an anode terminal connected to the above-mentioned fourth node and a cathode terminal connected to the above-mentioned second node, and when the above-mentioned switching element is disconnected, the above-mentioned control unit disconnects the above-mentioned first switch and the above-mentioned fifth switch at a fourth timing, and connects the above-mentioned second switch, the above-mentioned third switch and the above-mentioned fourth switch, and disconnects at least one of the above-mentioned second switch and the above-mentioned third switch at a fifth timing after the above-mentioned fourth timing.

[0166] (16) In the power conversion device according to any one of (8) to (15), the gate drive circuit further includes a first resistance element connected between the fourth node and the third terminal.

[0167] (17) According to the power conversion device described in any one of (8) to (15), the above-mentioned gate drive circuit also has a second resistance element connected in series with the above-mentioned first diode between the above-mentioned first node and the above-mentioned second node, and the above-mentioned fourth node is directly connected to the above-mentioned third terminal.

[0168] (18) In the power conversion device according to any one of (8) to (17), the gate drive circuit further includes a clamping diode having an anode terminal connected to the third terminal and a cathode terminal connected to the first terminal.

[0169] (19) According to the power conversion device described in any one of (8) to (18), the above-mentioned gate drive circuit also has a fourth terminal connected to the source terminal or the emitter terminal of the above-mentioned switching element, and the above-mentioned fourth terminal is directly connected to the above-mentioned second terminal.

[0170] (20) According to the power conversion device described in any one of (8) to (18), the above-mentioned gate drive circuit also has: a fourth terminal, which is connected to the source terminal or the emitter terminal of the above-mentioned switching element; and a fifth terminal, which is applied with a third potential lower than the above-mentioned first potential and higher than the above-mentioned second potential, and the above-mentioned fourth terminal is directly connected to the above-mentioned fifth terminal.

[0171] (21) A motor unit comprising: a motor; and the power conversion device according to any one of (8) to (20), which supplies electric power to the motor.

[0172] Explanation of symbols

[0173] 1…motor unit, 2…first DC power supply, 3…second DC power supply, 10…motor, 20…power conversion device, 21…bridge circuit, 22…control unit, 23…smoothing capacitor, 24…power supply circuit, GD1~GD6, GDA, GDB…gate drive circuit, TR1~TR6, TR…switching element, P1…first terminal, P2…second terminal, P3…third terminal, P4…fourth terminal, P5…fifth terminal, SW1…first switch, SW2…second switch, SW3…third switch, SW4…fourth switch, SW5…fifth switch, L1…inductor, D1…first diode, Rg1…first resistor, N1…first node, N2…second node, N3…third node, N4…fourth node.

Claims

1. A gate drive circuit for driving a switching element, characterized in that: The gate drive circuit comprises: a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; a third terminal connected to the gate terminal of the switching element; a first switch connected between the first terminal and a first node; a first diode having an anode terminal connected to the first node and a cathode terminal connected to a second node; an inductor connected between the first node and a third node; a second switch connected between the second node and the third node; a third switch connected between the second terminal and the third node; as well as a fourth switch connected between the second terminal and a fourth node, The first switch comprises a P-channel MOS-FET, The second switch, the third switch and the fourth switch include N-channel MOS-FETs, The second node is directly or indirectly connected to the fourth node, The fourth node is directly or indirectly connected to the third terminal.

2. The gate driving circuit according to claim 1, characterized in that: The gate drive circuit further includes: a fifth switch connected between the second node and the fourth node, The fifth switch includes a P-channel MOS-FET.

3. The gate driving circuit according to claim 1, characterized in that: The gate driving circuit further includes a first resistance element connected between the fourth node and the third terminal.

4. The gate driving circuit according to claim 1, characterized in that: A second resistor element connected in series with the first diode is further provided between the first node and the second node. The fourth node is directly connected to the third terminal.

5. The gate driving circuit according to claim 1, characterized in that: The gate drive circuit further includes a clamp diode having an anode terminal connected to the third terminal and a cathode terminal connected to the first terminal.

6. The gate drive circuit according to any one of claims 1 to 5, characterized in that: The gate drive circuit further includes: a fourth terminal connected to a source terminal or an emitter terminal of the switching element; The fourth terminal is directly connected to the second terminal.

7. The gate drive circuit according to any one of claims 1 to 5, characterized in that: The gate drive circuit further comprises: a fourth terminal connected to a source terminal or an emitter terminal of the switching element; and a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied, The fourth terminal is directly connected to the fifth terminal.

8. A power conversion device, characterized in that: have: A bridge circuit having a plurality of switching elements; A plurality of gate driving circuits, which are provided corresponding to each of the plurality of switching elements and drive the corresponding switching element; as well as a control unit that controls the plurality of gate drive circuits, The plurality of gate drive circuits respectively include: a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; A third terminal connected to a gate terminal of the corresponding switching element; a first switch connected between the first terminal and a first node; a first diode having an anode terminal connected to the first node and a cathode terminal connected to a second node; an inductor connected between the first node and a third node; a second switch connected between the second node and the third node; a third switch connected between the second terminal and the third node; a fourth switch connected between the second terminal and a fourth node, The first switch comprises a P-channel MOS-FET, The second switch, the third switch and the fourth switch include N-channel MOS-FETs, The second node is directly or indirectly connected to the fourth node, The fourth node is directly or indirectly connected to the third terminal.

9. The power conversion device according to claim 8, characterized in that: The second node is directly connected to the fourth node, When the control unit turns on the switch element, the control unit performs the following control: At a first timing, the first switch is turned on, and the second switch and the fourth switch are turned off; turning on the third switch at a second timing before the first timing, at the first timing, or after the first timing; as well as At a third timing after the second timing, the second switch is turned on, and the third switch is turned off.

10. The power conversion device according to claim 8, characterized in that: The second node is directly connected to the fourth node, The gate drive circuit further includes: a second diode having an anode terminal connected to the third node and a cathode terminal connected to the second node, The control unit performs the following control when turning on the switch element: At a first timing, the first switch is turned on, and the second switch and the fourth switch are turned off; turning on the third switch at a second timing before the first timing, at the first timing, or after the first timing; as well as At a third timing after the second timing, the third switch is turned off.

11. The power conversion device according to claim 8, characterized in that: The second node is directly connected to the fourth node, The control unit performs the following control when turning off the switching element: At a fourth timing, the first switch is turned off, and the second switch, the third switch, and the fourth switch are turned on; as well as At a fifth timing after the fourth timing, at least one of the second switch and the third switch is turned off.

12. The power conversion device according to claim 8, characterized in that: The gate drive circuit further includes: a fifth switch connected between the second node and the fourth node and including a P-channel MOS-FET, The control unit performs the following control when turning on the switch element: At a first timing, the first switch and the third switch are turned on, and the second switch and the fifth switch are turned off; At a second timing after the first timing, the fourth switch is turned off and the fifth switch is turned on; as well as At a third timing after the second timing, the second switch is turned on, and the third switch is turned off.

13. The power conversion device according to claim 8, characterized in that: The gate drive circuit further comprises: a fifth switch connected between the second node and the fourth node and comprising a P-channel MOS-FET; as well as a second diode having an anode terminal connected to the third node and a cathode terminal connected to the second node, The control unit performs the following control when turning on the switch element: At a first timing, the first switch and the third switch are turned on, and the second switch and the fifth switch are turned off; At a second timing after the first timing, the fourth switch is turned off and the fifth switch is turned on; as well as At a third timing after the second timing, the third switch is turned off.

14. The power conversion device according to claim 8, characterized in that: The gate drive circuit further includes: a fifth switch connected between the second node and the fourth node and including a P-channel MOS-FET, The control unit performs the following control when turning off the switching element: At a fourth timing, the first switch is turned off, and the second switch, the third switch, the fourth switch, and the fifth switch are turned on; At a fifth timing after the fourth timing, at least one of the second switch and the third switch is turned off.

15. The power conversion device according to claim 8, characterized in that: The gate drive circuit further comprises: a fifth switch connected between the second node and the fourth node and comprising a P-channel MOS-FET; as well as a third diode having an anode terminal connected to the fourth node and a cathode terminal connected to the second node, The control unit performs the following control when turning off the switching element: At a fourth timing, the first switch and the fifth switch are turned off, and the second switch, the third switch, and the fourth switch are turned on; as well as At a fifth timing after the fourth timing, at least one of the second switch and the third switch is turned off.

16. The power conversion device according to claim 8, characterized in that: The gate driving circuit further includes a first resistance element connected between the fourth node and the third terminal.

17. The power conversion device according to claim 8, characterized in that: The gate drive circuit further includes: a second resistor element connected in series with the first diode between the first node and the second node; The fourth node is directly connected to the third terminal.

18. The power conversion device according to claim 8, characterized in that: The gate drive circuit further includes a clamp diode having an anode terminal connected to the third terminal and a cathode terminal connected to the first terminal.

19. The power conversion device according to claim 8, characterized in that: The gate drive circuit further includes a fourth terminal connected to a source terminal or an emitter terminal of the switching element. The fourth terminal is directly connected to the second terminal.

20. The power conversion device according to claim 8, characterized in that: The gate drive circuit further comprises: a fourth terminal connected to a source terminal or an emitter terminal of the switching element; and a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied, The fourth terminal is directly connected to the fifth terminal.

21. A motor unit, characterized in that: have: Motor; and The power conversion device according to any one of claims 8 to 20, which supplies electric power to the motor.

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