Three-dimensional switching voltage regulator

Abstract

There is provided a switching voltage regulator including: a conversion circuit configured to receive an input voltage and generate an output voltage through a switching operation; and a control circuit configured to cause an output voltage to be generated by controlling a switching operation, in which the conversion circuit includes: at least one switch formed on the first die and configured to perform the switching operation under control of the control circuit; and at least one blocking transistor formed on the second die and electrically connected to the at least one first transistor, and wherein the first die is vertically stacked on the second die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0106210 filed on August 14, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a switching voltage regulator. Background Art

[0004] Electronic products are usually supplied with a constant voltage as an operating voltage. Therefore, a voltage controller is usually required to supply a constant voltage to the electronic products. A switching voltage regulator can be used as a voltage controller.

[0005] The switching voltage regulator outputs a constant voltage through the switching operation of the internal switch. Therefore, the conversion efficiency of the switching voltage regulator is associated with the switching loss that occurs during the switching operation. It is necessary to reduce this switching loss to improve the conversion efficiency of the switching voltage regulator. Summary of the invention

[0006] The present disclosure provides a switching voltage regulator with reduced switching losses.

[0007] According to one aspect of the present disclosure, a switching voltage regulator includes: a conversion circuit configured to receive an input voltage and generate an output voltage through a switching operation; and a control circuit configured to generate an output voltage by controlling the switching operation, wherein the conversion circuit includes: at least one switch formed on a first die and configured to perform a switching operation under the control of the control circuit; and at least one blocking transistor formed on a second die and electrically connected to the at least one first transistor, and wherein the first die is vertically stacked on the second die.

[0008] According to one aspect of the present invention, a switching voltage regulator includes: a first converter, which is connected to an input voltage and includes a first plurality of switches operating at a first switching frequency; and a second converter, which is connected to a ground voltage and includes a second plurality of switches operating at a second switching frequency, wherein the second switching frequency is higher than the first switching frequency, wherein the first plurality of switches are formed on a first bare core, and the second plurality of switches are formed on a second bare core, and wherein the first bare core and the second bare core are manufactured by different processes having different figure of merit (FOM) characteristics.

[0009] According to one aspect of the present disclosure, a switching voltage regulator includes: a substrate; a first bare core stacked on the substrate, wherein a blocking transistor and a control circuit are formed on the first bare core; and a second bare core stacked on the first bare core, wherein a plurality of transistors are formed on the second bare core, wherein the blocking transistor is configured to block an input voltage, wherein the plurality of transistors are configured to perform a switching operation under the control of the control circuit, and wherein the blocking transistor and the plurality of transistors are configured to operate as a conversion circuit of a DC-DC converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1A is a block diagram illustrating an example of a switching voltage regulator according to an example embodiment;

[0012] Figure 1B It is shown Figure 1A A schematic diagram of an example of a three-dimensional implementation of a power stage circuit;

[0013] Figure 2A It is shown Figure 1A A circuit diagram showing an example in which the conversion circuit is implemented as a buck converter;

[0014] Figure 2B It is shown Figure 2A a circuit diagram of an example of a first switch;

[0015] Figure 2C It is shown Figure 2A a circuit diagram of an example of a second switch;

[0016] Figure 3A It is shown Figure 1A A circuit diagram of an example in which the conversion circuit is implemented as a buck converter;

[0017] Figure 3B It is shown Figure 3A a circuit diagram of an example of a first switch;

[0018] Figure 3C It is shown Figure 3A a circuit diagram of an example of a second switch;

[0019] Figure 4A It is shown Figure 1A A circuit diagram of an example in which the conversion circuit is implemented as a buck converter;

[0020] Figure 4B It is shown Figure 4Aa circuit diagram of an example of a first switch;

[0021] Figure 4C It is shown Figure 4A a circuit diagram of an example of a second switch;

[0022] Figure 5 It is shown Figure 1A A schematic diagram of an example in which the conversion circuit is implemented as a buck converter;

[0023] Figure 6 It is shown Figure 1A A schematic diagram of an example in which the conversion circuit is implemented as a buck converter;

[0024] Figure 7 It is shown Figure 1A A schematic diagram of an example in which the conversion circuit is implemented as a buck converter;

[0025] Figure 8 It is shown Figure 1A A circuit diagram showing an example in which the conversion circuit is implemented as a boost converter;

[0026] Fig. 9 It is shown Figure 1A A circuit diagram of an example in which the conversion circuit is implemented as a merged converter;

[0027] Fig.10 It is shown Figure 1A A circuit diagram of an example in which the conversion circuit is implemented as a merged converter;

[0028] Fig.11A It is shown Figure 1A A block diagram of an example of a control circuit;

[0029] Fig. 11B It is shown Fig.11A A schematic diagram of an example of a control circuit being implemented on a single die;

[0030] Fig. 12A It is shown Figure 1A A block diagram of an example of a control circuit;

[0031] Fig. 12B It is shown Fig. 12A A schematic diagram of an example where the control circuit of is implemented in three dimensions; and

[0032] Fig.13A , Fig. 13B , Fig. 13C and Fig.13D is a schematic diagram illustrating an example of a three-dimensional implementation of a switching voltage regulator according to an example embodiment. DETAILED DESCRIPTION

[0033] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0034] In the following description, the same reference numerals refer to the same elements throughout the specification. Well-known functions or configurations are not described in detail because they would obscure one or more example embodiments with unnecessary detail. Depending on the embodiment, multiple "units," "modules," "components," and "blocks" may be implemented as a single component, or a single "unit," "module," "component," and "block" may include multiple components.

[0035] It will be understood that when an element is referred to as being “connected to” or “connected to” another element, it can be directly or indirectly connected to the other element.

[0036] Furthermore, when a component “includes” or “comprises” an element, unless there is a specific description contrary thereto, the component may further include other elements, rather than excluding other elements.

[0037] Throughout the specification, when a member is 'on' another member, this includes not only when the member is in contact with the other member but also when another member exists between the two members.

[0038] Herein, the expression "at least one of a, b, or c" means "only a", "only b", "only c", "both a and b", "both a and c", "both b and c", or "all of a, b, and c".

[0039] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, the present disclosure should not be limited by these terms. These terms are only used to distinguish one element from another.

[0040] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0041] Figure 1A is a block diagram showing an example of a switching voltage regulator 1000 according to an example embodiment, and Figure 1B is a schematic diagram illustrating an example of a three-dimensional implementation of the power stage circuit 110 of FIG. 1 .

[0042] The switching voltage regulator 1000 according to the example embodiment can be implemented using at least two bare cores, wherein each of the two bare cores is formed by a different process. For example, a device with large switching loss can be formed on a bare core formed by a process with a relatively improved figure of merit (FOM) characteristic, and other devices can be formed on a bare core formed by a process with a relatively low FOM characteristic. Therefore, according to the example embodiment, the switching loss of the switching voltage regulator 1000 can be reduced.

[0043] As reference below Figure 1A and Figure 1B Described in more detail, the switching voltage regulator 1000 may include a conversion circuit 100 and a control circuit 200 .

[0044] The conversion circuit 100 may receive an input voltage and may generate an output voltage through a switching operation. For example, the conversion circuit 100 may be implemented as a DC-DC converter. In an embodiment, the conversion circuit 100 may output a constant voltage.

[0045] In an example embodiment, the conversion circuit 100 can be implemented as a buck converter. As used herein, a buck converter may also be referred to herein as a step-down converter. In an embodiment, the conversion circuit 100 can generate an output voltage lower than an input voltage by repeatedly turning on and off a switch operation at regular intervals.

[0046] In an example embodiment, the conversion circuit 100 can be implemented as a boost converter. As used herein, a boost converter may also be referred to as a step-up converter. In an embodiment, the conversion circuit 100 can generate an output voltage higher than an input voltage by repeatedly turning on and off a switch operation at regular intervals.

[0047] In an example embodiment, the conversion circuit 100 may be implemented as a buck-boost converter supporting the functions of both a buck converter and a boost converter. Hereinafter, for brevity of description, the conversion circuit 100 implemented as a buck converter will be mainly described.

[0048] The conversion circuit 100 may include a power stage circuit 110. The power stage circuit 110 may receive an input voltage and may include at least one transistor that performs a switching operation. According to an example embodiment, the conversion circuit 100 may further include a filter circuit including a combination of an inductor and a capacitor. The filter circuit may filter the voltage sent from the power stage circuit 110 to output a direct current (DC) voltage.

[0049] In an example embodiment, the power stage circuit 110 may be implemented using devices formed on different bare cores. For example, the devices constituting the power stage circuit 110 may be formed on different bare cores. In an embodiment, the bare cores corresponding to the power stage circuit 110 may be formed by different processes. Therefore, the FOM characteristics of the bare cores corresponding to the power stage circuit 110 may be different from each other. The FOM characteristics may include on-resistance (Ron) characteristics and / or gate charge (Qg) characteristics.

[0050] For example, according to example embodiments, among the devices constituting the power stage circuit 110, the device that performs a switching operation at a high speed may be formed on a die having a relatively improved FOM characteristic, and the remaining devices may be formed on a die having a relatively low FOM characteristic. Therefore, the switching loss of the power stage circuit 110 may be effectively reduced.

[0051] This will now be described in more detail. The power stage circuit 110 may include devices belonging to the first region 111 and devices belonging to the second region 112. For example, the devices belonging to the first region 111 may include transistors that perform switching operations at high speed, and the devices belonging to the second region 112 may include transistors that block input voltage and / or transistors that perform switching operations at low speed.

[0052] In an embodiment, the first die Die1 is formed by a process having a relatively improved FOM characteristic, and the second die Die2 is formed by a process having a relatively low FOM characteristic. In such an embodiment, a device belonging to the first region 111 may be implemented on the first die Die1, and a device belonging to the second region 112 may be implemented on the second die Die2. Therefore, a transistor that performs a switching operation at a high speed may be implemented on the first die Die1 having a relatively improved FOM characteristic, and a transistor that performs a blocking operation may be implemented on the second die Die2 having a relatively low FOM characteristic.

[0053] Typically, the conversion efficiency of a switching voltage regulator is affected by the losses caused by parasitic resistance in the power transmission path and the switching losses that occur during the switching operation. In order to reduce the losses caused by parasitic resistance in the power transmission path, the switching voltage regulator can be placed as close to the load as possible. In such a configuration, the values ​​of the inductors and capacitors of the associated filter circuits can be reduced by placing the switching voltage regulator as close to the load as possible. In addition, the increase in switching frequency will reduce the values ​​of the inductors and capacitors. However, the increased switching frequency also leads to an increase in switching losses. Therefore, it is necessary to reduce the switching losses caused by high-speed switching operations to increase the conversion efficiency of the switching voltage regulator.

[0054] According to example embodiments, the power stage circuit 110 may implement transistors that perform high-speed switching operations on the first die Die1 having improved FOM characteristics. Therefore, switching losses of the power stage circuit 110 may be significantly reduced.

[0055] When a device that is not related to or is not affected by switching loss (such as a transistor that performs a blocking operation or a transistor that performs a switching operation at a low speed) is implemented on the first bare core Die1 with an improved FOM characteristic, the number of stages that should be stacked to receive voltages may increase. However, due to the increased number of stacked stages, delays may increase. In addition, in order to properly control the voltages of each stage, the complexity of the circuit may increase, and balancing capacitors, etc. may be required.

[0056] According to example embodiments, the power stage circuit 110 may implement devices other than transistors that perform switching operations at high speed on the second die Die2 having relatively low FOM characteristics. Therefore, problems such as increased circuit complexity and delay caused by an increase in the number of stacked stages may be solved.

[0057] According to an example embodiment, Figure 1B As shown in , the power stage circuit 110 can be implemented in a three-dimensional form by vertically stacking the first bare die Die1 and the second bare die Die2 manufactured by different processes. Therefore, the power transmission path between the first bare die Die1 and the second bare die Die2 can be significantly reduced, so that the parasitic resistance component can be reduced. In addition, due to the stacked configuration, the area occupied by the power stage circuit 110 on the plane can also be reduced.

[0058] Continue to refer Figure 1A , the control circuit 200 may control the overall operation of the conversion circuit 100. For example, the control circuit 200 may generate a gate voltage to be supplied to the gate of a transistor included in the conversion circuit 100, and may supply the generated gate voltage to the conversion circuit 100. In addition, the control circuit 200 may control the on / off cycle (i.e., the open / close cycle) of the switching operation of the transistor included in the conversion circuit 100.

[0059] As described above, the switching voltage regulator 1000 according to the example embodiment may include a device having a large switching loss. The device having a large switching loss may be formed on a bare die having a relatively improved FOM characteristic, and the remaining devices may be formed on a bare die having a relatively low FOM characteristic. Therefore, the switching loss of the switching voltage regulator 1000 according to the example embodiment may be reduced.

[0060] Figure 2A , Figure 2B and Figure 2C is shown implemented as a buck converter Figure 1A A schematic diagram of an example of a conversion circuit. Figure 2A is shown implemented as a buck converter Figure 1A Circuit diagram of an example of a conversion circuit, Figure 2B It is shown Figure 2A An example circuit diagram of the first switch, and Figure 2C It is shown Figure 2A A circuit diagram of an example of a second switch.

[0061] refer to Figure 2A , the conversion circuit 100A may include a power stage circuit 110A and a filter circuit 120A.

[0062] The power stage circuit 110A may include a first switch SW1, a second switch SW2, a first transistor M1, and a second transistor M2, all of which are connected in series. For example, the power stage circuit 110A may be implemented by stacking the first switch SW1, the second switch SW2, the first transistor M1, and the second transistor M2.

[0063] The first switch SW1 may have one end receiving an input voltage Vin and may be responsive to a control circuit 200 (see Figure 1A ) to perform a high-speed switching operation. The second switch SW2 may have one end connected to a ground voltage, and may perform a high-speed switching operation in response to the control of the control circuit 200. The first switch SW1 may be referred to as a high-side switch, and the second switch SW2 may be referred to as a low-side switch.

[0064] The first transistor M1 and the second transistor M2 may be disposed between the first switch SW1 and the second switch SW2. According to an example embodiment, the first transistor M1 may be implemented as a PMOS (p-channel metal oxide semiconductor) transistor, and the second transistor M2 may be implemented as an NMOS (n-channel metal oxide semiconductor) transistor. A voltage "Vin-a" may be applied to the gate of the first transistor M1, and a voltage "a" may be applied to the gate of the second transistor M2. The first transistor M1 and the second transistor M2 may be used to block the input voltage Vin and adjust the voltage corresponding to the first switch SW1 and the second switch SW2. Each of the first transistor M1 and the second transistor M2 may be referred to as a blocking transistor.

[0065] The filter circuit 120A may include an inductor L and a capacitor C, and may operate as an LC filter.

[0066] In an example embodiment, the first switch SW1 and the second switch SW2 of the power stage circuit 110A may be disposed in the first region 111A, and the devices disposed in the first region 111A may be implemented on the first bare die Die1 by a process having a relatively improved FOM characteristic (see Figure 1B ).

[0067] For example, Figure 2B As shown, the first switch SW1 may include a plurality of PMOS transistors P1 to Pm and a driver 11, and may be implemented to perform a switching operation in response to gate voltages Vp1 to Vpm received from the control circuit 200. In an embodiment, a process having a relatively improved FOM characteristic is used so that the transistors P1 to Pm included in the first switch SW1 may have a relatively small size compared to the first transistor M1 and the second transistor M2.

[0068] Similarly, if Figure 2C As shown, the second switch SW2 may include a plurality of NMOS transistors N1 to Nm and a driver I2, and may be implemented to perform a switching operation in response to gate voltages Vn1 to Vnm received from the control circuit 200. In an embodiment, a process having a relatively improved FOM characteristic is used so that the transistors N1 to Nm included in the second switch SW2 have a relatively small size compared to the first transistor M1 and the second transistor M2.

[0069] As described above, the switches SW1 and SW2 included in the power stage circuit 110A may be implemented by a process having a relatively improved FOM characteristic for the switching loss of the power stage circuit 110A.

[0070] In example embodiments, the first transistor M1 and the second transistor M2 of the power stage circuit 110A may be disposed in the second region 112A. The device implemented on the second die Die2 by a process having a relatively low FOM characteristic (see Figure 1B ).

[0071] Therefore, the first transistor M1 and the second transistor M2 can be implemented with a relatively simple structure. Therefore, the overall complexity of the power stage circuit 110A can be reduced.

[0072] Therefore, the power stage circuit 110A according to example embodiments may have reduced switching loss without increasing the complexity of the circuit.

[0073] Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B and Figure 4C It is shown Figure 1A A schematic diagram of an example in which the conversion circuit is implemented as a buck converter. FIG. 3A to FIG. 3C An example of how switching is implemented when a relatively high voltage corresponds to a switch performing a high-speed switching operation is shown. FIG. 4A to FIG. 4C An alternative example of a switch is shown in which a relatively high voltage corresponds to a switch that performs a high-speed switching operation.

[0074] For ease of description, an example is provided in which Figure 3A and Figure 4A The conversion circuit is implemented as the same buck converter as described in Figure 2. Figure 3A In FIG. 1 , an example of providing a voltage of “Vin / 2” to the first transistor M1 and the second transistor M2 is provided. Figure 4A , an example of providing a voltage of “2 / 3*Vin” and a voltage of “1 / 3*Vin” to the first transistor M1 and the second transistor M2, respectively, is provided.

[0075] refer to Figure 3A , the conversion circuit 100A-1 can be implemented to provide a voltage of "Vin / 2" to each of the first transistor M1 and the second transistor M2. In this embodiment, the first transistor M1 and the second transistor M2 can block the voltage of "Vin / 2". Therefore, each of the first switch SW1 and the second switch SW2 can correspond to the voltage "Vin / 2". For example, each of the first switch SW1 and the second switch SW2 should be able to withstand a relatively high voltage level "Vin / 2" during the switching operation.

[0076] In an embodiment, the first switch SW1 may be implemented as a stack of a relatively large number of transistors, such as Figure 3B For example, the first switch SW1 may be implemented by connecting three transistors P1 to P3 in series.

[0077] Similarly, the second switch SW2 may be implemented by stacking a relatively large number of transistors, such as Figure 3C For example, the second switch SW2 may be implemented by connecting three transistors N1 to N3 in series.

[0078] refer to Figure 4A , the conversion circuit 100A-2 can be implemented to provide a voltage of "2 / 3*Vin" and a voltage of "1 / 3*Vin" to the first transistor M1 and the second transistor M2, respectively. In this embodiment, the first transistor M1 and the second transistor M2 can block the voltage of "2 / 3*Vin". Therefore, the first switch SW1 and the second switch SW2 can each correspond to the voltage "Vin / 3". For example, each of the first switch SW1 and the second switch SW2 should be able to withstand a relatively low voltage level "Vin / 3" during the switching operation.

[0079] In an embodiment, the first switch SW1 may be implemented as a stack of a relatively small number of transistors, such as Figure 4B For example, the first switch SW1 may be implemented by connecting two transistors P1 and P2 in series.

[0080] Similarly, the second switch SW2 can be implemented as a stack of a relatively small number of transistors, such as Figure 4C For example, the second switch SW2 may be implemented by connecting two transistors N1 and N2 in series.

[0081] As described above, the number of stages of stacked transistors included in the conversion circuit 100A can vary, and these stacked transistors can be implemented using a process with improved FOM characteristics based on the level of the voltage blocked by the blocking transistor. For example, the higher the level of the voltage blocked by the blocking transistor, the fewer the number of stages of the stacked transistors constituting the switch can be designed.

[0082] Figure 5 It is shown Figure 1A FIG. 1 is a diagram of an example in which the conversion circuit is implemented as a buck converter. Figure 5 The conversion circuit 100B is similar to Figure 2A Therefore, for the sake of brevity of description, redundant description will be omitted below.

[0083] refer to Figure 5 , the conversion circuit 100B may include a power stage circuit 110B and a filter circuit 120B.

[0084] In an example embodiment, the first switch SW1 of the power stage circuit 110B may be disposed in the first region 111B. The first switch SW1 disposed in the first region 111B may be implemented on the first die Die1 by a process having a relatively improved FOM characteristic. The second switch SW2 and the first transistor M1 and the second transistor M2 of the power stage circuit 110B may be disposed in the second region 112B, and the devices disposed in the second region 112B may be implemented on the second die Die2 by a process having a relatively low FOM characteristic.

[0085] In the case of a buck converter, the switching loss occurring in the first switch SW1 (high-side switch) is greater than the switching loss occurring in the second switch SW2 (low-side switch). Therefore, the second switch SW2 can be formed together with the first transistor M1 and the second transistor M2 by a process having a relatively low FOM characteristic, such as Figure 5 shown.

[0086] Figure 6 It is shown Figure 1AA schematic diagram of an example in which the conversion circuit is implemented as a buck converter. Figure 6 The conversion circuit 100C is similar to Figure 2A Therefore, for the sake of brevity of description, redundant description will be omitted below.

[0087] refer to Figure 6 The conversion circuit 100C may include a power stage circuit 110C and a filter circuit 120C. The power stage circuit 110C may include a first auxiliary circuit 131 and a second auxiliary circuit 132 .

[0088] The first auxiliary circuit 131 may include a third transistor M3 and a fourth transistor M4. The third transistor M3 may have one end connected to the gate of the first transistor M1 and the other end connected to the first switch SW1. The fourth transistor M4 may have one end connected to the gate of the second transistor M2 and the other end connected to the second switch SW2.

[0089] The second auxiliary circuit 132 may include a fifth transistor M5 and a sixth transistor M6. The fifth transistor M5 may have one end connected to the first node A1 and the other end connected to the first switch SW1. The sixth transistor M6 may have one end connected to the first node A1 and the other end connected to the second switch SW2.

[0090] The first auxiliary circuit 131 and the second auxiliary circuit 132 may control the voltage level Vp at the second node A2 and the voltage level Vn at the third node A3 so that the levels Vp and Vn do not exceed a predetermined voltage. For example, the first auxiliary circuit 131 and the second auxiliary circuit 132 control the voltage level Vp at the second node A2 so that the voltage level Vp does not exceed the voltage "Vin-a", and may control the voltage level Vn at the third node A3 so that the voltage level Vn does not exceed the voltage "a".

[0091] In example embodiments, the first auxiliary circuit 131 may be disposed in the first region 111C, and the device disposed in the first region 111C may be implemented on the first bare die Die1 through a process having a relatively improved FOM characteristic. The second auxiliary circuit 132 may be disposed in the second region 112C, and the device disposed in the second region 112C may be implemented on the second bare die Die2 through a process having a relatively low FOM characteristic.

[0092] However, the foregoing is merely an example, and both the first auxiliary circuit 131 and the second auxiliary circuit 132 may be disposed in the first region 111C. Alternatively, both the first auxiliary circuit 131 and the second auxiliary circuit 132 may be disposed in the second region 112C. In an example embodiment, the conversion circuit 100C may include only one of the first auxiliary circuit 131 and the second auxiliary circuit 132.

[0093] Through these auxiliary circuits 131 and 132, according to example embodiments, the conversion circuit 100C can control "Vp / Vn" to change only within a safe operation area (SOA). Therefore, the reliability of the transistor included in the first region 111C formed by a process having relatively improved FOM characteristics can be improved.

[0094] Figure 7 It is shown Figure 1A A schematic diagram of an example in which the conversion circuit is implemented as a buck converter. Figure 7 The conversion circuit 100D is similar to Figure 2A Therefore, for the sake of brevity of description, redundant description will be omitted below.

[0095] refer to Figure 7 The conversion circuit 100D may include a power stage circuit 110D and a filter circuit 120D. The power stage circuit 110D may include first to fourth switches SW1 to SW4.

[0096] and Figure 2A The conversion circuit 100A is different. Figure 7 The conversion circuit 100D may include two switches SW1 and SW3 connected in parallel as high-side switches. The first switch SW1 may be disposed in the second region 112D. Therefore, the first switch SW1 may be implemented on the first bare die Die1 by a process having a relatively improved FOM characteristic. The third switch SW3 may be disposed in the first region 111D. Therefore, the third switch SW3 may be implemented on the second bare die Die2 by a process having a relatively low FOM characteristic. The third switch SW3 may be implemented as, for example, one or more PMOS transistors.

[0097] In addition, the conversion circuit 100D may include two switches SW2 and SW4 connected in parallel as low-side switches. The second switch SW2 may be arranged in the second region 112D. Therefore, the second switch SW2 may be implemented on the first bare die Die1 by a process having a relatively improved FOM characteristic. The fourth switch SW4 may be arranged in the first region 111D. Therefore, the fourth switch SW4 may be implemented on the second bare die Die2 by a process having a relatively low FOM characteristic. The fourth switch SW4 may be implemented, for example, with one or more NMOS transistors.

[0098] As described above, the conversion circuit 100D according to the example embodiment may include a plurality of switches connected in parallel to the high side and the low side, respectively. The switches included in the high side may be formed by different processes, and the switches included in the low side may also be formed by different processes.

[0099] However, the foregoing is merely an example, and the conversion circuit 100D according to the example embodiment may include a plurality of switches connected in parallel to only one of the high side and the low side.

[0100] In Figure 2 to Figure 7 In the embodiment, the conversion circuit has been described as being implemented as a buck converter. However, this is only an example, and the conversion circuit according to the example embodiment can be implemented as various circuits. In the following, other embodiments of the conversion circuit will be described in more detail.

[0101] Figure 8 It is shown Figure 1A A circuit diagram of an example in which a conversion circuit is implemented as a boost converter.

[0102] refer to Figure 8 , the conversion circuit 100E may include a power stage circuit 110E, an inductor L, and a capacitor C. The inductor L may be connected between the input voltage Vin and the first node A1 of the power stage circuit 110E. The capacitor C may be connected between the ground voltage and the power stage circuit 110E.

[0103] In an example embodiment, the power stage circuit 110E may include first and second switches SW1 and SW2 and first and second transistors M1 and M2. The first and second switches SW1 and SW2 may be disposed in the first region 111E and may be implemented on the first die Die1 by a process having a relatively improved FOM characteristic. The first and second transistors M1 and M2 may be disposed in the second region 112E and may be implemented on the second die Die2 by a process having a relatively low FOM characteristic.

[0104] As described above, the conversion circuit 100E according to example embodiments may be implemented as a boost converter, and switching loss may be significantly reduced.

[0105] Fig. 9 It is shown Figure 1A The conversion circuit is implemented as a circuit diagram of an example of a combined converter. Fig. 9 In FIG. 5 , a two-stage combining converter is shown as an example.

[0106] refer to Fig. 9 , the conversion circuit 100F may include a first converter 140 and a second converter 150 .

[0107] The first converter 140 may include a combination of multiple switches and capacitors. For example, the first converter 140 may include first to seventh switches S1 to S7 and first and second capacitors C1 and C2. Fig. 9 The first switch S1 to the seventh switch S7 can respond to the control circuit 200 (see Figure 1A ) to perform switching operation so as to be periodically turned on and off (i.e., opened and closed).

[0108] The second converter 150 may include a combination of multiple switches, capacitors, and inductors. For example, the second converter 150 may include an eighth switch S8 and a ninth switch S9, a third capacitor C3 and a fourth capacitor C4, and an inductor L. The eighth switch S8 and the ninth switch S9 may perform a switching operation in response to the control of the control circuit 200 to be periodically turned on and off (i.e., opened and closed).

[0109] The first converter 140 may receive an input voltage Vin and may reduce the input voltage Vin through a switching operation. The first converter 140 may operate at a relatively low switching frequency compared to the second converter 150 .

[0110] The second converter 150 may receive the reduced input voltage from the first converter 140 and may output the reduced input voltage as a direct current (DC) voltage. Compared to the first converter 140, the second converter 150 may operate at a relatively high switching frequency.

[0111] In an example embodiment, the switches S1 to S7 of the first converter 140 may be disposed in the second region 112F, and the switches S1 to S7 of the first converter 140 should be able to withstand a high voltage when operating at a relatively low switching frequency. Therefore, the switches S1 to S7 of the first converter 140 may be implemented on the second bare die Die2 by a process having a relatively low FOM characteristic.

[0112] In an example embodiment, switches S8 and S9 of the second converter 150 may be disposed in the first region 111F, and switches S8 and S9 of the second converter 150 should be able to withstand low voltages when operating at a relatively high switching frequency. Therefore, switches S8 and S9 of the second converter 150 may be implemented on the first bare die Die1 by a process having a relatively improved FOM characteristic.

[0113] As described above, the conversion circuit 100F according to the example embodiment can be implemented by two converters with different switching frequencies. In one embodiment, the converters can be formed by different processes, respectively. Therefore, the switching loss of the conversion circuit 100F can be reduced.

[0114] It should be understood that Fig. 9 The two-stage combining converter is an example and may be modified in various ways according to the example embodiments.

[0115] In example embodiments, the third capacitor C3 may be omitted. For example, the second converter 150 may be configured to include eighth and ninth switches S8 and S9, a fourth capacitor C4, and an inductor L.

[0116] Alternatively, in an example embodiment, the third capacitor C3 may be implemented to have a relatively low capacitance. For example, the second converter 150 may include an eighth switch S8 and a ninth switch S9, a third capacitor C3 and a fourth capacitor C4, and an inductor L, and the third capacitor C3 may be implemented to have a higher capacitance than that of the fourth capacitor C4.

[0117] Even when the third capacitor C3 is omitted or implemented to have a low capacitance, the first converter 140 and the second converter 150 may be formed by different processes. Therefore, the switching loss of the conversion circuit 100F may be reduced.

[0118] Fig.10 It is shown Figure 1A The conversion circuit is implemented as a circuit diagram of an example of a combined converter. Fig. 9 , Fig.10 The conversion circuit 100G may be implemented as a two-stage combining converter. Fig.10 The conversion circuit 100G is similar to Fig. 9 Therefore, for the sake of brevity of description, redundant description will be omitted below.

[0119] refer to Fig.10 , the conversion circuit 100G may include a first converter 140_1 and a second converter 150_1.

[0120] The first converter 140_1 may include a combination of a plurality of switches and a single capacitor. For example, the first converter 140_1 may include first to fourth switches S1 to S4 and a first capacitor C1. Fig.10 The first switch S1 to the fourth switch S4 may be operated at a relatively low switching frequency.

[0121] The second converter 150_1 may include a combination of multiple switches, multiple capacitors, and multiple inductors. For example, the second converter 150_1 may include fifth to seventh switches S5 to S7, second and third capacitors C2 and C3, and first and second inductors L1 and L2. The fifth to seventh switches S5 to S7 may operate at a relatively high switching frequency.

[0122] In an example embodiment, switches S1 to S4 of the first converter 140_1 may be disposed in the second region 112G, and switches S1 to S4 of the first converter 140_1 should be able to withstand high voltages when operating at a relatively low switching frequency. Switches S5 to S7 of the second converter 150_1 may be disposed in the first region 111G, and switches S5 to S7 of the second converter 150_1 should be able to withstand low voltages when operating at a relatively high switching frequency. Therefore, switches S1 to S4 of the first converter 140_1 and switches S5 to S7 of the second converter 150_1 may be formed by different processes. Therefore, the switching loss of the conversion circuit 100G may be reduced.

[0123] Fig.11A It is shown Figure 1A A block diagram of an example of a control circuit. Fig. 11B It is shown Fig.11A FIG. 1 is a diagram of an example of a control circuit implemented on a single die.

[0124] refer to Fig.11A The control circuit 200A may include an amplifier 231 , a comparator 232 , a trigger 233 , a gate controller 234 , a first voltage generator 235 , and a second voltage generator 236 .

[0125] The amplifier 231 may receive the output voltage Vout from the conversion circuit 100. The amplifier 231 may compare the output voltage Vout with the reference voltage Vref to output a result of the comparison as a first signal SNG1.

[0126] The comparator 232 may receive the sawtooth waveform signal Vsaw. The comparator 232 may receive the first signal SNG1 from the amplifier 231. The comparator 232 may compare the sawtooth waveform signal Vsaw with the first signal SNG1 to output the comparison result as the second signal SNG2. Although a sawtooth waveform is used in this example, the present disclosure is not limited thereto.

[0127] The flip-flop 233 may receive the clock signal CLK and the second signal SNG2. The flip-flop 233 may output an output signal Q and an inverted output signal Qb based on the clock signal CLK and the second signal SNG2.

[0128] The gate controller 234 may receive the output signal Q and the inverted output signal Qb from the flip-flop 233. The gate controller 234 may generate a signal to be provided to the conversion circuit 100A (see FIG. 1 ) based on the output signal Q and the inverted output signal Qb. Figure 2A ) switches P1 to Pm and N1 to Nm (see Figure 2B )’s gate voltage.

[0129] The first voltage generator 235 may generate a voltage which is provided to the transistors M1 and M2 (see FIG. Figure 2A )’s gate voltage.

[0130] The second voltage generator 236 may generate a reference voltage Vref provided to the amplifier 231 .

[0131] In an example embodiment, the control circuit 200A may be implemented by a single process. For example, the control circuit 200A may be implemented on the second die Die2 by a process having a relatively low FOM characteristic, such as Fig. 11B In an embodiment, the control circuit 200A may be connected to the conversion circuit 100 (see Figure 1A ) are implemented together on the second bare die Die2.

[0132] However, the foregoing is merely an example, and the example embodiments are not limited thereto. For example, the control circuit 200A may be implemented on an independent die on which the devices of the conversion circuit 100 are not implemented. In an embodiment, the control circuit 200A may be implemented to be vertically stacked on the die Die1 and Die2 on which the conversion circuit 100 is implemented, so that the loss caused by the parasitic resistance is significantly reduced.

[0133] Fig. 12A It is shown Figure 1A A block diagram of an example of a control circuit. Fig. 12B It is shown Fig. 12A Schematic diagram of an example of a control circuit implemented in three-dimensional form. Fig. 12A The control circuit 200B is similar to Fig.11A Therefore, for the sake of brevity of description, redundant description will be omitted below.

[0134] refer to Fig. 12AThe control circuit 200B may include an analog-to-digital converter 241 , a digital pulse width modulator (hereinafter referred to as “digital PWM”) 242 , a gate controller 243 , a first voltage generator 244 and a second voltage generator 245 .

[0135] The analog-to-digital converter 241 may receive the output voltage Vout from the conversion circuit 100. The analog-to-digital converter 241 may compare the output voltage Vout with a reference voltage Vref, convert the analog output voltage Vout into a digital output voltage, and output the digital output voltage.

[0136] The digital PWM 242 may receive the digital output voltage from the analog-to-digital converter 241. The digital PWM 242 may adjust the pulse width of the digital output voltage and may transmit the adjusted result to the gate controller 243.

[0137] The gate controller 243 may generate a signal to be provided to the conversion circuit 100A (see Figure 2A ) switches P1 to Pm and N1 to Nm (see Figure 2B ) gate voltage. The first voltage generator 244 may generate a voltage which is provided to the transistors M1 and M2 (see Figure 2A ) The second voltage generator 245 may generate a reference voltage Vref provided to the analog-to-digital converter 241.

[0138] In example embodiments, the control circuit 200B may be implemented by different processes.

[0139] For example, considering performance, power, and area (PPA), it may be more efficient to implement the digital PWM 242 using a process having relatively improved FOM characteristics. Fig. 12A and Fig. 12B As shown in FIG. 2 , the analog / digital converter 241, the digital PWM 242, and the gate controller 243 of the control circuit 200B may be disposed in the first region 210, and the devices disposed in the first region 210 may be implemented on the first bare die Die1 through a process having a relatively improved FOM characteristic. In an embodiment, the devices of the control circuit 200B may be connected to the conversion circuit 100 disposed in the first region 111 (see FIG. 2 ). Figure 1A ) are implemented together on the first bare die Die2.

[0140] In addition, for example, in view of the bipolar characteristics of the voltage generator 245 that generates the reference voltage Vref, etc., it may be more efficient to implement the voltage generator 245 by a process having a relatively low FOM characteristic. Fig. 12A and Fig. 12B As shown in FIG. 1 , the first voltage generator 244 and the second voltage generator 245 of the control circuit 200B may be disposed in the second region 220, and the devices disposed in the second region 220 may be implemented on the second bare die Die2 by a process having a relatively low FOM characteristic. In an embodiment, the devices of the control circuit 200B may be connected to the conversion circuit 100 disposed in the second region 112 (see FIG. 1 ). Figure 1A ) are implemented together on the second bare die Die2.

[0141] As described above, the control circuit 200B according to example embodiments may be implemented in a three-dimensional form through various processes.

[0142] FIG. 13A to FIG. 13D is a schematic diagram illustrating an example of a three-dimensional implementation of a switching voltage regulator according to an example embodiment.

[0143] A switching voltage regulator according to an example embodiment can be implemented in a three-dimensional form by a plurality of bare cores stacked vertically on a substrate. The bare cores of the switching voltage regulator are manufactured by processes having different FOM characteristics, and can be joined to each other in a face-to-face (F2F) or face-to-back (F2B) configuration. For example, the devices constituting the conversion circuit of the switching voltage regulator can be implemented on each of the plurality of bare cores, and the devices formed on different bare cores can be electrically connected to each other in the vertical direction. Therefore, not only the switching loss of the switching voltage regulator can be reduced, but also the length of the power transmission path can be reduced, and thus the loss caused by the parasitic resistance can be significantly reduced.

[0144] refer to Fig.13A , the switching voltage regulator 1000A may be implemented in a F2F configuration. For example, an active surface of the first die Die1 and an active surface of the second die Die2 may be bonded to each other.

[0145] In more detail, the substrate SUB may be electrically connected to an external circuit such as a printed circuit board (PCB) through the internal connection terminals BP. Fig.13A shown.

[0146] A plurality of bare cores may be stacked on a substrate SUB in a direction perpendicular to a plane of the substrate SUB. For example, a first bare core Die1 may be disposed on a second bare core Die2. The second bare core Die2 may be electrically connected to the substrate SUB through one or more first bumps BP1. The first bare core Die1 may be electrically connected to the second bare core Die2 through one or more second bumps BP2.

[0147] The first die Die1 and the second die Die2 may be formed by processes having different FOM characteristics. For example, the first die Die1 may be formed by a process having a relatively improved FOM characteristic, and the second die Die2 may be formed by a process having a relatively low FOM characteristic.

[0148] The devices included in the switching voltage regulator 1000A may be implemented on the first die Die1 and the second die Die2. For example, the first switch SW1 and the second switch SW2 of the power stage circuit 110 that perform high-speed switching operations may be implemented on the first die Die1, and the first transistor M1 and the second transistor M2 of the power stage circuit 110 that block the input voltage may be implemented on the second die Die2.

[0149] exist Fig.13A In FIG. 2 , the control circuit 200 is shown as being implemented on the second die Die2 , but this is only an example, and devices constituting the control circuit 200 may be implemented on each of the first die Die1 and the second die Die1 .

[0150] The input voltage Vin and the ground voltage Vss may be transmitted to the first switch SW1 and the second switch SW2 through the internal connection terminal BP and the first and second bumps BP1 and BP2 .

[0151] refer to Fig. 13B , the switching voltage regulator 1000B can be implemented in an F2B configuration. To the extent that the switching voltage regulator 1000B is similar to the switching voltage regulator 1000A, redundant descriptions are omitted for brevity of description. For example, the active surface of the first bare die Die1 can be bonded to the rear surface of the second bare die Die2, or the rear surface of the first bare die Die1 can be bonded to the active surface of the second bare die Die2.

[0152] refer to Fig. 13C In the switching voltage regulator 1000C, a first die Die1 having an improved FOM characteristic may be stacked on a substrate SUB, and a second die Die2 having a low FOM characteristic may be stacked on the first die Die1. To the extent that the switching voltage regulator 1000C is similar to the switching voltage regulator 1000A, redundant descriptions are omitted for the sake of brevity. For example, the switching voltage regulator 1000C may use a first die Die1 having a relatively improved FOM characteristic as a bottom plate and a second die Die2 having a low FOM characteristic as a top plate.

[0153] refer to Fig.13D, the switching voltage regulator 1000D may be implemented to include an on-chip inductor, wherein the inductor L is implemented on the first die Die1 or the second die Die2. To the extent that the switching voltage regulator 1000D is similar to the switching voltage regulator 1000A, redundant descriptions are omitted for brevity of description.

[0154] For example, the inductor L may be implemented together with the first transistor M1 and the second transistor M2 on the second die Die2 having a low FOM characteristic, such as Fig.13D However, this is only an example, and the inductor L may be implemented on the first die Die1. In addition, according to example embodiments, the capacitor may also be implemented as an on-chip capacitor implemented on the first die Die1 or the second die Die2.

[0155] As described above, the switching voltage regulator according to example embodiments may have reduced switching loss.

[0156] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A switching voltage regulator, comprising: A conversion circuit configured to receive an input voltage and generate an output voltage through a switching operation; as well as a control circuit configured to generate the output voltage by controlling the switch operation, Wherein, the conversion circuit comprises: at least one switch formed on the first die and configured to perform the switching operation under the control of the control circuit; and at least one blocking transistor formed on the second die and electrically connected to the at least one first transistor, and Wherein, the first bare core is vertically stacked on the second bare core.

2. The switching voltage regulator according to claim 1, wherein: The at least one switch formed on the first die includes: A first switch configured to receive the input voltage; and a second switch connected to a ground voltage, and The control circuit is configured to open and close the first switch and open and close the second switch.

3. The switching voltage regulator according to claim 2, wherein: The first switch includes a plurality of p-channel metal oxide semiconductor (PMOS) transistors connected in series, and The second switch includes a plurality of n-channel metal oxide semiconductor (NMOS) transistors connected in series.

4. The switching voltage regulator according to claim 3, wherein: Based on a voltage supplied to a gate of the at least one blocking transistor, the number of the plurality of PMOS transistors and the number of the plurality of NMOS transistors are determined.

5. The switching voltage regulator according to claim 4, wherein: The number of the plurality of PMOS transistors and the number of the plurality of NMOS transistors decrease as a level of a voltage blocked by the at least one blocking transistor increases.

6. The switching voltage regulator according to claim 2, wherein: The at least one blocking transistor comprises: a first transistor electrically connected to the first switch; and A second transistor is serially connected to the first transistor and is electrically connected to the second switch.

7. The switching voltage regulator according to claim 1, wherein: The conversion circuit also includes at least one switch formed on the second die and configured to perform the switching operation under the control of the control circuit.

8. The switching voltage regulator according to claim 7, wherein: The at least one blocking transistor comprises: a p-channel metal oxide semiconductor (PMOS) transistor electrically connected to the at least one switch formed on the first die; and An n-channel metal oxide semiconductor (NMOS) transistor is serially connected to the PMOS transistor and is electrically connected to the at least one switch formed on the second die.

9. The switching voltage regulator according to claim 1, wherein: The at least one switch formed on the first die includes: A first switch configured to receive the input voltage; and The second switch, connected to ground voltage, Wherein, the at least one blocking transistor formed on the second bare core comprises: a first transistor having one terminal electrically connected to the first switch; and a second transistor having one terminal connected to the first transistor and another terminal electrically connected to the second switch, and Wherein, the conversion circuit further includes: a third transistor formed on the first die and having one end connected to the first switch and the other end electrically connected to the gate of the first transistor; and A fourth transistor is formed on the first die and has one end connected to the second switch and the other end electrically connected to the gate of the second transistor.

10. The switching voltage regulator according to claim 9, wherein: The conversion circuit further includes a fifth transistor and a sixth transistor, and Wherein, the fifth transistor and the sixth transistor are formed on the second bare core, the fifth transistor and the sixth transistor are connected in series to each other, the fifth transistor is connected in parallel to the first transistor, and the sixth transistor is connected in parallel to the second transistor.

11. The switching voltage regulator according to claim 1, wherein: The conversion circuit also includes at least one switch formed on the second die and connected in series to the at least one blocking transistor.

12. The switching voltage regulator according to claim 11, wherein: The at least one switch formed on the first die includes: a plurality of p-channel metal oxide semiconductor (PMOS) transistors connected in series and configured to receive the input voltage; and a plurality of n-channel metal oxide semiconductor (NMOS) transistors connected in series and configured to be connected to a ground voltage, and Wherein, the at least one switch formed on the second bare core includes: a first switch connected in parallel to the plurality of PMOS transistors and configured to receive the input voltage; and A second switch is connected in parallel to the plurality of NMOS transistors and is connected to the ground voltage.

13. The switching voltage regulator of claim 1 , further comprising: an inductor electrically connected between the input voltage and the at least one blocking transistor; as well as A capacitor is electrically connected between the at least one switch and a ground voltage.

14. The switching voltage regulator according to claim 1, wherein: The control circuit is formed on the second bare core.

15. The switching voltage regulator according to claim 1, wherein: The control circuit comprises: a gate controller formed on the first die and configured to generate a first gate voltage that controls the at least one switch; and A voltage generator is formed on the second die and is configured to generate a second gate voltage that controls the at least one blocking transistor.

16. The switching voltage regulator according to claim 1, wherein: The first die and the second die are bonded to each other in a face-to-face F2F configuration.

17. The switching voltage regulator according to claim 1, wherein: The first die and the second die are bonded to each other in a face-to-back F2B configuration.

18. The switching voltage regulator according to claim 1, wherein: The conversion circuit also includes an inductor formed on the second die and electrically connected to the at least one blocking transistor.

19. A switching voltage regulator comprising: a first converter connected to an input voltage and comprising a first plurality of switches operated at a first switching frequency; as well as a second converter connected to a ground voltage and comprising a second plurality of switches operated at a second switching frequency, wherein the second switching frequency is higher than the first switching frequency, wherein the first plurality of switches are formed on a first die and the second plurality of switches are formed on a second die, and The first bare core and the second bare core are manufactured by different processes with different figure of merit FOM characteristics.

20. A switching voltage regulator comprising: substrate; a first die stacked on the substrate, wherein a blocking transistor and a control circuit are formed on the first die; and a second die stacked on the first die, wherein a plurality of transistors are formed on the second die, wherein the blocking transistor is configured to block an input voltage, wherein the plurality of transistors are configured to perform a switching operation under the control of the control circuit, Wherein, the blocking transistor and the plurality of transistors are configured to operate as a conversion circuit of a DC-DC converter.

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