Time-interleaved analog-to-digital converter and gain correction method

Abstract

A time-interleaved analog-to-digital converter and a gain correction method are provided. A time-interleaved analog-to-digital converter includes a plurality of sampling circuits, a plurality of amplifier circuits, a plurality of analog-to-digital converter circuits, and detector circuitry. The plurality of sampling circuits are used for sampling an input signal according to a plurality of first frequency signals to generate a plurality of first signals. The plurality of amplifier circuits are used for generating a plurality of second signals according to the first signals. The plurality of analog-to-digital converter circuits are used for converting the second signals to generate a plurality of digital signals. The detector circuitry is configured to adjust a delay time of each of the first frequency signals and correct gains of the amplifier circuits according to the digital signals.

Description

Technical Field

[0001] The present invention relates to an analog-to-digital converter, and more particularly to a time-interleaved analog-to-digital converter and a gain correction method thereof, which can reduce sampling time mismatch to improve gain correction accuracy. Background Art

[0002] In existing time-interleaved analog-to-digital converters, multiple channels sample input signals in a fixed sampling order. However, in practical applications, multiple frequency signals that control the sampling order may have mismatches or skews, resulting in inaccurate sampling time points. On the other hand, as the number of channels increases, the mismatches caused by process variations and other reasons in the actual circuit will also increase, so that multiple channels may also have gain mismatches. The above-mentioned multiple mismatches may affect each other, thereby affecting the operation of the corresponding correction circuit, resulting in reduced correction accuracy. For example, timing mismatches will affect the calculation accuracy of the gain correction circuit, making it impossible to effectively eliminate the gain error between multiple channels. Summary of the invention

[0003] In some embodiments, one of the purposes of the present invention is (but not limited to) to provide a time-interleaved analog-to-digital converter and a gain correction method thereof that can reduce sampling time mismatch to improve gain correction accuracy, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, the time-interleaved analog-to-digital converter includes a plurality of sampling circuits, a plurality of amplifier circuits, a plurality of analog-to-digital converter circuits, and a detector circuit system. The plurality of sampling circuits are used to sample input signals according to a plurality of first frequency signals to generate a plurality of first signals. The plurality of amplifier circuits are used to generate a plurality of second signals according to the first signals. The plurality of analog-to-digital converter circuits are used to convert the second signals to generate a plurality of digital signals. The detector circuit system is used to adjust the delay time of each of the first frequency signals and to calibrate the gain of the amplifier circuits according to the digital signals.

[0005] In some embodiments, the gain correction method includes the following operations: sampling an input signal according to a plurality of first frequency signals to generate a plurality of first signals; amplifying the first signals by a plurality of amplifier circuits to generate a plurality of second signals; performing a plurality of analog-to-digital conversions according to the second signals to generate a plurality of digital signals; and adjusting a delay time of each of the first frequency signals and correcting the gain of the amplifier circuits according to the digital signals.

[0006] The features, implementation and effects of the present invention will be described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of a time-interleaved analog-to-digital converter is provided according to some embodiments of the present invention;

[0008] Figure 2 According to some embodiments of the present invention, Figure 1 A schematic diagram of a detector circuit system in FIG.

[0009] Figure 3A According to some embodiments of the present invention, Figure 2 Schematic diagram of the gain error calculation circuit in;

[0010] Figure 3B According to some embodiments of the present invention, Figure 2 A schematic diagram of a delay control circuit in; and

[0011] Figure 4 A flow chart of a gain calibration method is drawn according to some embodiments of the present invention. DETAILED DESCRIPTION

[0012] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the context of this application, are merely illustrative and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0013] As used herein, "coupled" or "connected" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit, and the term "circuit" may be a device that is connected in a certain manner by at least one transistor and / or at least one active and passive component to process signals.

[0014] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this document, the terms first, second, third, etc. are used to describe and identify each component. Therefore, the first component in this document can also be referred to as the second component without departing from the original intention of the case. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

[0015] Figure 1A schematic diagram of a time-interleaved analog-to-digital converter 100 is drawn according to some embodiments of the present invention. The time-interleaved analog-to-digital converter 100 includes a plurality of sampling circuits 110[1]-110[4], a plurality of amplifier circuits 120[1]-120[4], a plurality of analog-to-digital converter circuits 130[1]-130[4], and a detector circuit system 140. The plurality of sampling circuits 110[1]-110[4] samples an input signal SIN according to a plurality of clock signals CK1[1]-CK1[4] to generate a plurality of signals S1[1]-S1[4] respectively. In detail, the sampling circuit 110[1] is selectively turned on according to the clock signal CK1[1] to sample the input signal SIN to generate the signal S1[1]. By analogy, the corresponding relationship between the multiple sampling circuits 110[2]~110[4], the multiple frequency signals CK1[2]~CK1[4] and the multiple signals S1[2]~S1[4] can be understood. In some embodiments, each of the multiple sampling circuits 110[1]~110[4] may include, but is not limited to, a switch (not shown) and a capacitive element (not shown). The switch can be turned on according to a corresponding one of the multiple frequency signals CK1[1]~CK1[4] to transmit the input signal SIN to the capacitive element. The capacitive element can store the input signal SIN to generate a corresponding one of the multiple signals S1[1]~S1[4]. With the above configuration, the multiple sampling circuits 110[1]~110[4] can be turned on at different times to sample the input signal SIN in sequence, thereby equivalently improving the overall sampling rate.

[0016] The plurality of amplifier circuits 120[1] to 120[4] are used to generate a plurality of signals S2[1] to S2[4] according to the signals S1[1] to S1[4]. In detail, the amplifier circuit 120[1] is used to generate a signal S2[1] according to the signal S1[1]. Similarly, the corresponding relationship between the plurality of amplifier circuits 120[2] to 120[4], the plurality of signals S1[2] to S1[4], and the plurality of signals S2[2] to S2[4] can be understood. In some embodiments, each of the plurality of amplifier circuits 120[1] to 120[4] can be operated as a buffer circuit to improve the driving capability. For example, each of the plurality of amplifier circuits 120[1] to 120[4] can be, but not limited to, a source follower having an ideal voltage gain of 1.

[0017] The multiple analog-to-digital converter circuits 130[1]-130[4] are used to convert the multiple signals S2[1]-S2[4] to generate multiple digital signals D[1]-D[4]. In detail, the analog-to-digital converter circuit 130[1] can perform analog-to-digital conversion on the signal S2[1] to generate the digital signal D[1]. By analogy, the corresponding relationship between the multiple analog-to-digital converter circuits 130[2]-130[4], the multiple signals S2[2]-S2[4] and the multiple digital signals D[2]-D[4] can be understood. In different embodiments, the multiple analog-to-digital converter circuits 130[1]-130[4] can be various types of analog-to-digital converter circuits. For example, each of the plurality of ADC circuits 130[1]-130[4] may be, but is not limited to, a successive approximation register (SAR) ADC circuit, a pipeline ADC circuit, a flash ADC circuit, etc.

[0018] The detector circuit system 140 is used to adjust the delay time of each of the multiple frequency signals CK1[1]-CK1[4], thereby controlling the sampling time of the multiple sampling circuits 110[1]-110[4] on the input signal SIN. In this way, the influence of the timing mismatch (timing mismatch or timing skew) between the multiple sampling circuits 110[1]-110[4] can be reduced. On the other hand, the detector circuit system 140 can also be used to correct the gain of at least one of the multiple amplifier circuits 120[1]-120[4] according to the multiple digital signals D[1]-D[4], thereby reducing the gain mismatch (gain mismatch) between the multiple channels corresponding to the multiple amplifier circuits 120[1]-120[4].

[0019] In some embodiments, the detector circuit system 140 can be used to adjust the delay time of each of the plurality of clock signals CK1[1]-CK1[4] during a predetermined period, and perform an average operation based on two of the plurality of digital signals D[1]-[4] during the predetermined period to calculate the gain error of a corresponding one of the plurality of amplifier circuits 120[1]-120[4], so as to correct the gain of the corresponding one of the plurality of amplifier circuits 120[1]-120[4] according to the gain error. In other words, the timing mismatch between the plurality of sampling circuits 110[1]-110[4] can be continuously adjusted during the predetermined period (for example, the delay time can be gradually increased, gradually decreased, or randomly changed during the predetermined period), and the influence of the timing mismatch can be reduced by the accumulation and averaging operations during the predetermined period. In this way, the detector circuit system 140 can more accurately detect the gain errors between the multiple channels corresponding to the multiple amplifier circuits 120[1] to 120[4], thereby more accurately adjusting the gains of the multiple amplifier circuits 120[1] to 120[4]. In some embodiments, the aforementioned preset period can be a period for performing gain calibration on the multiple amplifier circuits 120[1] to 120[4]. The relevant operations of the detector circuit system 140 will be described later. Figure 2 , Figure 3A and Figure 3B illustrate.

[0020] In actual applications, due to the influence of process variation, voltage variation and / or temperature variation, errors may exist between circuit components in multiple channels of a time-interleaved analog-to-digital converter, resulting in gain errors between multiple channels. For example, due to the influence of one or more of the above-mentioned variations, the voltage gain of any one of the multiple amplifier circuits 120[1] to 120[4] is not 1. This will reduce the performance of the time-interleaved analog-to-digital converter. In some related technologies, the time-interleaved analog-to-digital converter directly performs gain correction between multiple channels without eliminating the influence of timing mismatch. In these related technologies, due to the influence of negative factors such as actual timing mismatch and / or bandwidth mismatch, the digital signals generated by multiple channels in the time-interleaved analog-to-digital converter may have lower accuracy or distortion. In this way, accurate gain correction cannot be effectively performed. Compared with the above-mentioned technology, in some embodiments of the present case, the detector circuit system 140 can adjust the sampling time of each channel to reduce the influence of timing mismatch on gain correction, thereby more accurately performing gain correction between multiple channels.

[0021] exist Figure 1In the example of FIG. 1 , the time-interleaved analog-to-digital converter 100 includes four channels. For example, the sampling circuit 110[1], the amplifier circuit 120[1], and the analog-to-digital converter circuit 130[1] correspond to the first channel. The sampling circuit 110[2], the amplifier circuit 120[2], and the analog-to-digital converter circuit 130[2] correspond to the second channel. Similarly, the configuration of the third channel and the fourth channel can be understood. Figure 1 The number of channels shown is only an example, and the present invention is not limited thereto. It should be understood that in different embodiments, the time-interleaved analog-to-digital converter 100 may include N channels, where N may be a positive integer greater than or equal to 2.

[0022] In some embodiments, the time-interleaved analog-to-digital converter 100 may further include a skew calibration circuit (not shown). Under this condition, the detector circuit system 140 may stop adjusting the delay time of the multiple frequency signals CK1[1]~CK1[4] after the gain calibration is completed. In other words, the detector circuit system 140 may adjust the delay time of the multiple frequency signals CK1[1]~CK1[4] only during the period of calibrating the gain of the multiple amplifier circuits 120[1]~120[4], thereby improving the accuracy of the gain calibration. After the gain calibration is completed, the detector circuit system 140 may stop adjusting the delay time of the multiple frequency signals CK1[1]~CK1[4] to avoid affecting the operation of the skew calibration circuit.

[0023] Figure 2 According to some embodiments of the present invention, Figure 1 Schematic diagram of the detector circuit system 140 in FIG. The detector circuit system 140 includes a plurality of gain error calculation circuits 210 [ 1 ] to 210 [ 3 ], a gain correction circuit 220 and a delay control circuit 230 .

[0024] The plurality of gain error calculation circuits 210[1]-210[3] are used to calculate the gain errors GD[2]-GD[4] associated with the amplifier circuits 120[1]-120[4] according to the plurality of digital signals D[1]-D[4], so as to correct the gains of the amplifier circuits 120[1]-120[4]. For example, the gain error calculation circuit 210[1] may calculate the gain error GD[2] associated with the amplifier circuit 120[2] relative to the amplifier circuit 120[1] according to the digital signal D[1] and the digital signal D[2]. The gain error calculation circuit 210[2] may calculate the gain error GD[3] associated with the amplifier circuit 120[3] relative to the amplifier circuit 120[1] according to the digital signal D[1] and the digital signal D[3]. Similarly, the gain error calculation circuit 210 [ 3 ] may calculate a gain error GD[ 4 ] associated with the amplifier circuit 120 [ 4 ] relative to the amplifier circuit 120 [ 1 ] based on the digital signal D[ 1 ] and the digital signal D[ 4 ].

[0025] The gain correction circuit 220 may execute a correction algorithm based on the multiple gain errors determined by the multiple gain error calculation circuits 210[1]-210[3] to adjust the gain of at least one of the multiple amplifier circuits 120[1]-120[4]. For example, if the gain error of the amplifier circuit 120[1] is large, the gain correction circuit 220 may issue a control signal to adjust the circuit setting (such as, but not limited to, bias setting or programmable gain setting) in the amplifier circuit 120[2] to correct the gain of the amplifier circuit 120[2]. In some embodiments, the gain correction circuit 220 may be implemented by at least one digital circuit that can execute an existing gain correction algorithm.

[0026] The delay control circuit 230 is used to gradually adjust the delay time of each of the multiple frequency signals CK1[1]~CK1[4] according to the frequency signal CK2. For example, the delay control circuit 230 can determine the adjustment amount of the delay time (for example, dly mentioned later) according to the frequency signal CK2, and use the adjustment amount dly to adjust the multiple frequency signals CK1[1]~CK1[4]. In some embodiments, the frequency of the frequency signal CK2 is the same as the frequency of each of the multiple frequency signals CK1[1]~CK1[4]. In some embodiments, the target phases of the multiple frequency signals CK1[1]~CK1[4] are sequentially different by a preset phase difference. For example, the target phases of the multiple frequency signals CK1[1]~CK1[4] can be sequentially set to 0 degrees, 90 degrees, 180 degrees and 270 degrees, so that the multiple sampling circuits 110[1]~110[4] can be turned on at different periods.

[0027] Explained another way, in some embodiments, based on mathematical concepts, Figure 1The sampling time t(i) of the plurality of sampling circuits 110[1] to 110[4] in can be expressed as follows:

[0028] t(i)=T(i)+τ(i)+dly,i=1,2,3,4

[0029] Wherein T(i) is the target time point (corresponding to the aforementioned target phase) at which a corresponding one of the plurality of sampling circuits 110[1]-110[4] (e.g., sampling circuit 110[i]) samples the input signal SIN according to a corresponding one of the plurality of frequency signals CK1[1]-CK1[4] (e.g., frequency signal CK1[i]), τ(i) is the timing error associated with the sampling circuit 110[i], and dly is the delay time adjustment amount of a corresponding one of the plurality of frequency signals CK1[1]-CK1[4] (e.g., frequency signal CK1[i]). It can be understood from the above formula that during the process of gain calibration performed by the detector circuit system 140, the sampling time of the plurality of sampling circuits 110[1]-110[4] can be added with a delay time adjustment amount. In this way, the detector circuit system 140 can use accumulation and averaging operations in the calculation of gain calibration to reduce the influence of timing mismatch on gain calibration, thereby improving the accuracy of gain calibration.

[0030] In the above example, the detector circuit system 140 introduces the same delay time adjustment amount to the multiple frequency signals CK1[1]-CK1[4], but the present invention is not limited to this. In other embodiments, the detector circuit system 140 can also introduce different delay time adjustment amounts to the multiple frequency signals CK1[1]-CK1[4]. For example, the detector circuit system 140 can include multiple delay control circuits 230, and each delay time control circuit 230 is used to determine the delay time adjustment amount of a corresponding one of the multiple frequency signals CK1[1]-CK1[4].

[0031] Figure 3A According to some embodiments of the present invention, Figure 2 Schematic diagram of the gain error calculation circuit 210 [1] in FIG. In this example, the gain error calculation circuit 210 [1] may include an absolute value circuit 310, an absolute value circuit 312, a subtractor circuit 314, and an average circuit 316.

[0032] The absolute value circuit 310 is used to generate an absolute value signal AD[2] according to a first digital signal (e.g., digital signal D[2]) among the plurality of digital signals D[1]-D[4], wherein the value of the absolute value signal AD[2] is the absolute value of the digital signal D[2]. The absolute value circuit 312 is used to generate an absolute value signal AD[1] according to a second digital signal (e.g., digital signal D[1]) among the plurality of digital signals D[1]-D[4], wherein the value of the absolute value signal AD[1] is the absolute value of the digital signal D[1]. The subtractor circuit 314 is used to determine a difference DV between the absolute value signal AD[2] and the absolute value signal AD[1]. The averaging circuit 316 is used to average the difference DV to determine a gain error GD[2] of a corresponding one of the plurality of amplifier circuits 120[1]-120[4] (in this example, the amplifier circuit 120[2]). For example, the averaging circuit 316 may accumulate the difference DV during the aforementioned predetermined period, and average the accumulated results to determine the gain error GD[2].

[0033] In the above example, the gain of the channel corresponding to the amplifier circuit 120[1] is set as a reference value. Thus, the gain error between the multiple amplifier circuits 120[2]-120[4] can be confirmed by comparing the digital signal D[1] related to the reference value with other digital signals D[2]-D[4] (i.e., other digital signals related to the gains of the channels corresponding to other amplifier circuits 120[2]-120[4]).

[0034] In some embodiments, each of the absolute value circuit 310, the absolute value circuit 312, the subtractor circuit 314, and the average circuit 316 can be implemented by at least one digital logic circuit. The above configuration of the gain error calculation circuit 210 [1] is for example only, and the present invention is not limited thereto. For example, each of the absolute value circuit 310 and the absolute value circuit 320 can be implemented by, but not limited to, a square circuit or a square root circuit. Figure 2 The configuration of other gain error calculation circuits 210[2] to 210[3] in FIG. Figure 3A I understand, so I won't repeat it.

[0035] Figure 3B According to some embodiments of the present invention, Figure 2 Schematic diagram of the delay control circuit 230 in FIG. In this example, the delay control circuit 230 includes a flip-flop circuit 320, an adder circuit 322, a multiplier circuit 324, and a plurality of adder circuits 326[1] to 326[4].

[0036] The flip-flop circuit 320 is used to output the signal S3 as a counting signal SC according to the frequency signal CK2. In some embodiments, the flip-flop circuit 320 can be, but not limited to, a D-type flip-flop circuit. The adder circuit 322 is used to add the counting signal SC to a preset value P to generate the signal S3. In some embodiments, the preset value P can be set to, but not limited to, 1. The multiplier circuit 324 is used to multiply the signal S3 with the delay signal SD to generate a signal S4, wherein the delay signal SD is equivalent to a unit of delay adjustment, and the signal S4 is used to indicate the adjustment amount dly of the delay time. With the above-mentioned setting, the flip-flop circuit 320 can continuously update the counting signal SC through the triggering of the frequency signal CK2, thereby gradually increasing the adjustment amount dly. Multiple adder circuits 326[1]~326[4] can add the signal S4 to the multiple frequency signals CK1[1]~CK1[4] respectively, thereby adjusting the multiple frequency signals CK1[1]~CK1[4].

[0037] As described above, in some embodiments, the detector circuit system 140 may stop adjusting the delay time of the multiple frequency signals CK1[1]-CK1[4] after the gain calibration is completed. In other words, during the gain calibration process, the multiple adder circuits 326[1]-326[4] may add the signal S4 to the multiple frequency signals CK1[1]-CK1[4] respectively, and output the added results as updated multiple frequency signals CK1[1]-CK1[4] to adjust the sampling time of the multiple sampling circuits 110[1]-110[4]. After the gain calibration is completed, the multiple adder circuits 326[1]-326[4] may stop operating without continuing to adjust the delay time. Under this condition, the detector circuit system 140 may use other circuits (for example, but not limited to, a multiplexer) to provide the multiple frequency signals CK1[1]-CK1[4] to the multiple sampling circuits 110[1]-110[4] without adjusting the delay time.

[0038] In some embodiments, the flip-flop circuit 320 , the adder circuit 322 , the multiplier circuit 324 , and each of the plurality of adder circuits 326 [ 1 ] to 326 [ 4 ] may be implemented by at least one digital logic circuit. Figure 3B The configuration shown is for example only and the present invention is not limited thereto. In different embodiments, the delay control circuit 230 may gradually decrease the adjustment amount dly, alternately increase and decrease the adjustment amount dly, or randomly change the adjustment amount dly during the preset period. Various ways of changing the adjustment amount dly are all within the scope of the present invention.

[0039] Figure 4A flow chart of a gain calibration method 400 is drawn according to some embodiments of the present invention. In operation S410, an input signal is sampled according to a plurality of first frequency signals to generate a plurality of first signals. In operation S420, the first signals are amplified by a plurality of amplifier circuits to generate a plurality of second signals. In operation S430, a plurality of analog-to-digital conversions are performed according to the second signals to generate a plurality of digital signals. In operation S440, a delay time of each of the first frequency signals is adjusted, and the gain of the amplifier circuits is calibrated according to the digital signals.

[0040] The multiple operations in the gain correction method 400 can refer to the description of the aforementioned embodiments, so they will not be repeated here. The multiple operations in the gain correction method 400 are only examples and are not limited to being performed in the order in this example. Without violating the operating mode and scope of the various embodiments of the present case, the various operations in the gain correction method 400 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, the various operations in the gain correction method 400 can be performed simultaneously or partially simultaneously. In some embodiments, the gain correction method 400 may also include the following operations: after correcting the gains of the amplifier circuits, check whether the gain errors of all amplifier circuits are less than or equal to the target value. If the gain errors of all amplifier circuits are less than or equal to the target value, the gain correction is terminated. Alternatively, if the gain errors of all amplifier circuits are not less than or equal to the target value, the gain correction method 400 is executed again to continue the gain correction.

[0041] In summary, the time-interleaved analog-to-digital converter and gain calibration method provided in some embodiments of the present invention can adjust the sampling time of multiple channels during the gain calibration period to reduce the impact of timing mismatch between multiple channels, thereby improving the accuracy of gain calibration.

[0042] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. A person having ordinary knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit contents of the present case. All these changes may fall within the scope of the patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be subject to the scope defined by the claims of this specification.

[0043]

Explanation of symbols

[0044] 100: Time-interleaved analog-to-digital converter

[0045] 110[1]~110[4]: Sampling circuit

[0046] 120[1]~120[4]:Amplifier circuit

[0047] 130[1]~130[4]:Analog-to-digital converter circuit

[0048] 140: Detector circuit system

[0049] 210[1]~210[3]: Gain error calculation circuit

[0050] 220: Gain correction circuit

[0051] 230: Delay control circuit

[0052] 310, 312: Absolute value circuit

[0053] 314: Subtractor Circuit

[0054] 316: Average Circuit

[0055] 320: Flip-flop circuit

[0056] 322: Adder Circuit

[0057] 324: Multiplier Circuit

[0058] 326[1]~326[4]:Adder circuit

[0059] 400: Gain correction method

[0060] AD[1], AD[2]: Absolute value signal

[0061] CK1[1]~CK1[4], CK2: frequency signal

[0062] D[1]~D[4]: digital signal

[0063] DV: Difference

[0064] GD[2]~GD[4]: Gain error

[0065] P: Preset value

[0066] S1[1]~S1[4], S2[1]~S2[4], S3, S4: Signal

[0067] S410, S420, S430, S440: Operation

[0068] SC: Count signal

[0069] SD: Delayed signal

[0070] SIN: Input signal.

Claims

1. A time-interleaved analog-to-digital converter, characterized in that: include: A plurality of sampling circuits, for sampling an input signal according to a plurality of first frequency signals to generate a plurality of first signals; A plurality of amplifier circuits, used for generating a plurality of second signals according to the first signals; A plurality of analog-to-digital converter circuits, for converting the second signals to generate a plurality of digital signals; as well as The detector circuit system is used to adjust the delay time of each of the first frequency signals and calibrate the gain of the amplifier circuits according to the digital signals.

2. The time-interleaved analog-to-digital converter of claim 1, wherein: The detector circuit system is used to adjust the delay time within a preset period, and perform an average operation according to two of the digital signals within the preset period to calculate the gain error of a corresponding one of the amplifier circuits, so as to correct the gain of the corresponding one of the amplifier circuits according to the gain error.

3. The time-interleaved analog-to-digital converter of claim 1, wherein: The detector circuit system is used to gradually adjust the delay time within a preset period.

4. The time-interleaved analog-to-digital converter according to claim 3, wherein: The detector circuit system is also used to stop adjusting the delay time after the preset period.

5. The time-interleaved analog-to-digital converter of claim 3, wherein: The preset period is a period during which the detector circuit system calibrates the gains of the amplifier circuits.

6. The time-interleaved analog-to-digital converter of claim 1, wherein: The detector circuit system includes: a plurality of gain error calculation circuits for calculating a plurality of gain errors associated with the amplifier circuits according to the digital signals to correct the gains of the amplifier circuits; and The delay control circuit is used for gradually adjusting the delay time of each of the first frequency signals according to the second frequency signal.

7. The time-interleaved analog-to-digital converter of claim 6, wherein: One of the gain error calculation circuits includes: A first absolute value circuit, configured to generate a first absolute value signal according to a first digital signal among the digital signals, wherein a value of the first absolute value signal is an absolute value of the first digital signal; A second absolute value circuit, configured to generate a second absolute value signal according to a second digital signal among the digital signals, wherein a value of the second absolute value signal is an absolute value of the second digital signal; a subtractor circuit for determining a difference between the first absolute value signal and the second absolute value signal; and The averaging circuit is used to average the difference to determine the gain error of a corresponding one of the amplifier circuits.

8. The time-interleaved analog-to-digital converter of claim 6, wherein: The delay control circuit comprises: a flip-flop circuit, configured to output the third signal as a counting signal according to the second frequency signal; a first adder circuit, configured to add the count signal and a preset value to generate the third signal; and a multiplier circuit for multiplying the third signal and the delay signal to generate a fourth signal, wherein the fourth signal is used to indicate the adjustment amount of the delay time; and The plurality of second adders are used to respectively add the fourth signal to the first frequency signals to adjust the first frequency signals.

9. The time-interleaved analog-to-digital converter of claim 8, wherein: The default value is 1.

10. A gain correction method, characterized in that: include: Sampling an input signal according to a plurality of first frequency signals to generate a plurality of first signals; amplifying the first signals by a plurality of amplifier circuits to generate a plurality of second signals; Performing a plurality of analog-to-digital conversions according to the second signals to generate a plurality of digital signals; and The delay time of each of the first frequency signals is adjusted, and the gains of the amplifier circuits are corrected according to the digital signals.

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