Integrator operating based on variable current

Abstract

The invention provides an integrator based on variable current operation. The integrator comprises an operational amplifier, wherein the operational amplifier comprises an amplification stage circuit and a bias circuit. The amplifier stage circuit is used for providing an amplification gain, and the bias circuit is coupled to the amplifier stage circuit and is used for controlling a bias condition of the amplifier stage circuit according to a variable current output by a variable current source. In a sampling phase of the integrator, the variable current source switches the variable current to a sampling current value. In an integration phase of the integrator, the variable current source switches the variable current to an integrated current value. In particular, the sampled current value is less than the integrated current value.

Description

Technical Field

[0001] The present invention relates to an integrator, and in particular to an integrator operating based on a variable current. Background Art

[0002] A typical delta-sigma analog-to-digital converter may include components such as a loop filter, a quantizer, a digital-to-analog converter, and a decimation filter to perform high-resolution analog-to-digital conversion on signals with high resolution requirements (such as audio signals). However, the loop filter is typically composed of analog circuits that consume a lot of power (such as an integrator including an operational amplifier). In certain low-power applications, how to reduce the power consumption of the loop filter (such as the integrator therein) becomes an important issue.

[0003] Therefore, a novel integrator current biasing architecture is needed to reduce the overall power consumption without changing the existing architecture. Summary of the invention

[0004] The object of the present invention is to provide an integrator based on a variable current operation to reduce the power consumption of the integrator in a discrete delta-sigma analog-to-digital conversion operation.

[0005] At least one embodiment of the present invention provides an integrator operating based on a variable current. The integrator includes an operational amplifier, wherein the operational amplifier includes an amplifier stage circuit and a bias circuit coupled to the amplifier stage circuit. The amplifier stage circuit is used to provide an amplification gain, and the bias circuit is used to control a bias condition of the amplifier stage circuit according to the variable current output by a variable current source. In a sampling phase of the integrator, the variable current source switches the variable current to a sampling current value. In an integration phase of the integrator, the variable current source switches the variable current to an integration current value. In particular, the sampling current value is less than the integration current value.

[0006] The integrator provided by the embodiment of the present invention can be operated based on the corresponding current value in the sampling stage and the integration stage, especially using a smaller current value in the sampling stage with a lower speed requirement and using a larger current value in the integration stage with a higher speed requirement. Therefore, the present invention can reduce the overall power consumption without affecting the operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of an integrator according to an embodiment of the present invention.

[0008] Figure 2 According to an embodiment of the present invention Figure 1 Schematic diagram of the control clock associated with the integrator is shown.

[0009] Figure 3 According to an embodiment of the present invention Figure 1 Schematic diagram of an operational amplifier in an integrator is shown.

[0010] Figure 4 According to an embodiment of the present invention Figure 3 A schematic diagram of an implementation of a variable current source in an operational amplifier is shown.

[0011] Figure 5 According to another embodiment of the present invention Figure 3 A schematic diagram of an implementation of a variable current source in an operational amplifier is shown.

[0012] Figure 6 According to another embodiment of the present invention Figure 3 A schematic diagram of an implementation of a variable current source in an operational amplifier is shown.

[0013] Explanation of symbols

[0014] 10: Switched Capacitor Integrator

[0015] V IN : Input signal

[0016] V OUT : Output signal

[0017] C1, C2: capacitors

[0018] S1~S4:switch

[0019] P1, P2: Control clock

[0020] A0: Gain

[0021] 100: Operational Amplifier

[0022] 110: Amplifier circuit

[0023] 120: Bias circuit

[0024] 121: Variable current source

[0025] I OUT :Variable current

[0026] VDD: Supply voltage terminal

[0027] VINN,VINP: Input terminals

[0028] VON, VOP: Output terminals

[0029] MA0, MA1, MA2, MB0, MB1: P-type transistors

[0030] MA3, MA4, MB2: N-type transistor

[0031] 40,50,60: variable current source

[0032] 400,500,600,620: Constant current source

[0033] I IN : Constant current

[0034] NOUT: Output terminal

[0035] M40~M42,M51,M52,M61~M64: N-type transistor

[0036] S41, S42, S51~S55, S61~S66: switch

[0037] C5, C6: capacitors DETAILED DESCRIPTION

[0038] Figure 1 FIG. 1 is a schematic diagram of an integrator (such as a switched capacitor integrator 10) according to an embodiment of the present invention. Figure 1 As shown, the switched capacitor integrator 10 may include an operational amplifier 100, wherein A0 may represent the gain of the operational amplifier 100. The switched capacitor integrator 10 may further include a plurality of switches (such as switches S1, S2, S3, and S4) and a plurality of capacitors C1 and C2. The switch S1 is coupled between the input terminal of the switched capacitor integrator 10 and the first terminal (e.g., the left terminal) of the capacitor C1, and the switch S2 is coupled between the second terminal (e.g., the right terminal) of the capacitor C1 and the negative output terminal (e.g., the negative output terminal) of the operational amplifier 100. Figure 1 The positive input terminal of the operational amplifier 100 (in the figure) is marked with “-” for simplicity), the switch S3 is coupled between the second terminal of the capacitor C1 and a reference voltage terminal (such as a ground voltage terminal), and the switch S4 is coupled between the first terminal of the capacitor C1 and the reference voltage terminal. Figure 1 The input terminal of the switched capacitor integrator 10 can receive an input signal V IN And according to the ratio of capacitors C2 and C1, the input signal V IN The output signal V is integrated to generate an output signal V at the output terminal of the switched capacitor integrator 10 (eg, the output terminal of the operational amplifier 100). OUT It should be noted that Figure 1The switched capacitor integrator 10 shown in the figure only shows a single-ended circuit structure for the purpose of illustration, but not for limiting the present invention. Figure 1 The architecture shown and the above description provide the corresponding differential circuit architecture, which will not be described here for the sake of brevity.

[0039] In this embodiment, whether the switches S1 and S3 are turned on (eg, turned on) is controlled by a control clock P1, and whether the switches S2 and S4 are turned on is controlled by a control clock P2. Figure 2 According to an embodiment of the present invention Figure 1 A schematic diagram of control clocks associated with the switched capacitor integrator 10 is shown, wherein the control clocks P1 and P2 can be generated by a non-overlapping clock generator based on a system clock. The period when the control clock P1 is at a high level (e.g., having a logic value of "1") can represent the period when the switches S1 and S3 are turned on, and the period when the control clock P1 is at a low level (e.g., having a logic value of "0") can represent the period when the switches S1 and S3 are turned off. Similarly, the period when the control clock P2 is at a high level (e.g., having a logic value of "1") can represent the period when the switches S2 and S4 are turned on, and the period when the control clock P2 is at a low level (e.g., having a logic value of "0") can represent the period when the switches S2 and S4 are turned off.

[0040] In this embodiment, the period when the control clock P1 is at a high level can be used as a sampling phase of the switched capacitor integrator 10, and the period when the control clock P2 is at a high level can be used as an integration phase of the switched capacitor integrator 10. In the sampling phase (e.g., during the sampling phase), switches S1 and S3 are turned on and switches S2 and S4 are turned off, so the input signal V IN can be sampled onto capacitor C1, wherein the operational amplifier 100 is only used to maintain the output signal V during the sampling phase. OUT In the integration phase (e.g., during the integration phase), switches S2 and S4 are turned on and switches S1 and S3 are turned off, so that the charge on capacitor C1 is transferred to capacitor C2 for signal integration operation, wherein the operational amplifier 100 can be based on the input signal V in the integration phase. IN and the ratio of capacitors C2 and C1 will output signal V OUT The voltage level is driven to the result after integration. Based on the above characteristics, the operation speed requirement of the operational amplifier 100 in the sampling stage is lower than the operation speed requirement in the integration stage. Therefore, the present invention provides different bias currents to the operational amplifier 100 in the sampling stage and the integration stage respectively, so that the power consumption of the operational amplifier 100 can be effectively reduced without significantly affecting the overall performance.

[0041] Figure 3 According to an embodiment of the present invention Figure 1 FIG. 1 is a schematic diagram of an operational amplifier 100 in a switched capacitor integrator 10, wherein the operational amplifier 100 is operated based on a supply voltage terminal VDD to amplify a differential input signal between input terminals VINP and VINN to generate a differential output signal between output terminals VOP and VON. Figure 1 As shown, the operational amplifier 100 may include an amplifier stage circuit 110 and a bias circuit 120, wherein the bias circuit 120 is coupled to the amplifier stage circuit 110. In this embodiment, the amplifier stage circuit 110 is used to provide an amplification gain (for example, A0), and the bias circuit 120 is used to adjust a variable current I outputted by a variable current source 121. OUT Control a bias condition of the amplifier stage circuit 110. For example, in the sampling phase of the switched capacitor integrator 10, the variable current source 121 can OUT In the integration phase of the switched capacitor integrator 10, the variable current source 121 can switch the variable current I OUT Switching to an integrated current value. In particular, the sampling current value is smaller than the integrated current value.

[0042] In this embodiment, the amplifier stage circuit 110 can be implemented with a single-stage amplifier architecture, wherein the amplifier stage circuit 110 can include a plurality of transistors, such as P-type transistors MA0, MA1 and MA2 and N-type transistors MA3 and MA4. In addition, the bias circuit 120 can include a variable current source 121 and at least one current mirror circuit, wherein the at least one current mirror circuit is coupled to the variable current source 121 and the amplifier stage circuit 110, and is used to adjust the current according to the variable current I OUT One or more bias voltages are generated to control the bias condition of the amplifier stage circuit 110. In this embodiment, the at least one current mirror circuit may include a P-type transistor MB0, wherein the P-type transistor MB0 may be configured to control the bias condition of the amplifier stage circuit 110 according to the variable current I OUT Generate a bias voltage of the P-type transistor MA0 (eg, a gate voltage of the P-type transistor MA0) so that the current output by the P-type transistor MA0 (ie, the bias current of the amplifier stage circuit 110) changes with the variable current I OUT In addition, the bias voltages of the N-type transistors MA3 and MA4 (eg, the gate voltages of the N-type transistors MA3 and MA4) can be controlled by the P-type transistors MB1 and the N-type transistors MB2. Figure 3 The architecture of the current mirror can be used to convert the variable current I OUTThe change of is applied to the bias voltage of the amplifier stage circuit 110 and thereby controls the speed (eg, operating bandwidth) and power consumption of the operational amplifier 100, so it is not described here for the sake of simplicity. In addition, Figure 3 The amplifier stage circuit 110 shown in the embodiment is for illustration purposes only and is not intended to limit the present invention. For example, the amplifier stage circuit 110 may be implemented using other architectures such as a multi-stage amplifier, a cascode amplifier, etc., and those skilled in the art should be able to implement the amplifier stage circuit 110 based on the above description and the present invention. Figure 3 The illustrated structure can be used to analogize how to implement the bias circuit 120 corresponding to the different structures of the amplifier stage circuits 110 , which will not be described here for the sake of brevity.

[0043] Figure 4 According to an embodiment of the present invention Figure 3 FIG. 1 is a schematic diagram of an implementation of the variable current source 121 (eg, the variable current source 40) in the operational amplifier 100. Figure 4 As shown, the variable current source 40 may include a constant current source 400, an output circuit (such as an N-type transistor M40), a first current mirror circuit (such as an N-type transistor M41), and a second current path circuit (such as an N-type transistor M42). In this embodiment, the constant current source 400 is used to output a constant current I IN , and the N-type transistor M40 is used to output a variable current I OUT For example, the N-type transistor M40 may be coupled between an output terminal NOUT and the reference voltage terminal (eg, a ground voltage terminal), wherein the output terminal NOUT is coupled to Figure 3 The P-type transistor MB0 is shown, but the present invention is not limited thereto. In addition, the N-type transistor M41 is used to receive the constant current I in the sampling phase. IN According to a first predetermined ratio (eg, the size ratio between the N-type transistors M40 and M41) and the constant current I IN The N-type transistor M40 is controlled (eg, the gate voltage of the N-type transistor M40 is controlled) so that the variable current I OUT is switched to the sampled current value (eg, constant current I IN The N-type transistor M42 is used to receive the constant current I in the integration phase. IN According to a second predetermined ratio and the constant current I IN The N-type transistor M40 is controlled (eg, the gate voltage of the N-type transistor M40 is controlled) so that the variable current I OUT is switched to the integrated current value (eg, constant current I IN multiplied by the second predetermined ratio).

[0044] In this embodiment, the variable current source 40 may further include switches S41 and S42, wherein the switch S41 is coupled between the N-type transistor M41 and the constant current source 400, and the switch S42 is coupled between the N-type transistor M42 and the constant current source 400. In particular, whether the switch S41 is turned on is controlled by the control clock P1, and whether the switch S42 is turned on is controlled by the control clock P2. Therefore, the switch S41 is used to be turned on in the sampling phase to couple the N-type transistor M41 to the constant current source 400 to change the variable current I OUT The switch S42 is switched to the sampled current value, and the switch S42 is used to be turned on in the integration phase to couple the N-type transistor M42 to the constant current source 400 to change the variable current I OUT Switch to this integrated current value.

[0045] Figure 5 According to another embodiment of the present invention Figure 3 FIG. 1 is a schematic diagram of an implementation of the variable current source 121 (eg, the variable current source 50) in the operational amplifier 100. Figure 5 As shown, the variable current source 50 may include a constant current source 500, at least one transistor (such as N-type transistors M51 and M52), and a capacitor C5. In this embodiment, the constant current source 500 is used to output a constant current I IN In addition, the N-type transistors M51 and M52 are used to generate a constant current I IN A control voltage is stored on the capacitor C5, and the N-type transistors M51 and M52 are used to generate the integrated current value according to the control voltage during the integration stage.

[0046] In the present embodiment, the variable current source 50 may further include switches S51, S52, S53, S54 and S55, wherein the switch S51 is coupled between the N-type transistor M51 and the constant current source 500, the switch S52 is coupled between the gate and the drain of the N-type transistor M51, the switch S53 is coupled between the gate and the drain of the N-type transistor M52, the switch S54 is coupled between the N-type transistor M51 and the output terminal NOUT, and the switch S55 is coupled between the N-type transistor M52 and the output terminal NOUT. In particular, whether each of the switches S51, S52 and S53 is turned on is controlled by the control clock P1, and whether the switches S54 and S55 are turned on is controlled by the control clock P2. Therefore, the switches S51, S52 and S53 are used to be turned on in the sampling phase so that the N-type transistors M51 and M52 receive the constant current I through the switch S51. IN , wherein the switches S52 and S53 are turned on in the sampling phase so that the N-type transistors M51 and M52 are switched on according to the constant current I INThe control voltage is stored on the capacitor C5. For example, the capacitor C5 can be coupled to the gates of the N-type transistors M51 and M52, so that when the N-type transistors M51 and M52 respond to the constant current I IN When the gate voltage is generated, the gate voltage can be stored on the capacitor C5 as the control voltage. In addition, the switches S54 and S55 are used to be turned on in the integration phase so that the N-type transistors M51 and M52 are turned on according to the control voltage (for example, the N-type transistors M51 and M52 are turned on according to the constant current I IN The gate voltage generated by the integrated current value is the variable current I OUT Output to the output terminal NOUT.

[0047] It should be noted that since the switches S54 and S55 are closed during the sampling phase, the variable current I OUT During the sampling phase, it is switched to 0 (i.e., the sampled current value is 0). Figure 4 The variable current source 40 shown, Figure 5 The variable current source 50 shown does not have a static current that continuously flows out from the output terminal NOUT, thereby further reducing the overall power consumption.

[0048] However, when the operating speed of the switched capacitor integrator 10 is increased (for example, the frequency of the system clock is increased), the variable current I OUT The practice of switching to 0 during the sampling phase may cause the overall circuit to be unable to ensure the stability of the overall circuit when repeatedly switching between the sampling phase and the integration phase. Based on the requirement of high-speed operation, the variable current source 50 can be further improved to Figure 6 The variable current source 60 shown in FIG. Figure 6 According to another embodiment of the present invention Figure 3 FIG. 4 is a schematic diagram of an implementation of a variable current source 121 (eg, variable current source 60 ) in the operational amplifier 100 .

[0049] like Figure 6 As shown, the variable current source 60 may include constant current sources 600 and 620, at least one transistor (such as N-type transistors M61 and M62), a current mirror circuit (such as N-type transistor M63), an output circuit (such as N-type transistor M64), and a capacitor C6. In this embodiment, the constant current source 600 is used to output a first constant current (such as a constant current I IN ), and the constant current source 620 is used to output a second constant current (such as the constant current I IN One tenth of the constant current I IN / 10”)). It should be noted that the second constant current is preferably smaller than the first constant current, but the present invention is not limited thereto. In addition, the ratio between the first constant current and the second constant current is only for the purpose of illustration and is not intended to limit the present invention, wherein the ratio between the first constant current and the second constant current may be varied in response to requirements such as operating speed and power consumption. In addition, the N-type transistors M61 and M62 are used to sample the constant current I IN A control voltage (for example, N-type transistors M61 and M62 are set according to the constant current I IN The gate voltage generated by the N-type transistor M61 and the N-type transistor M62 are used to generate the integrated current value according to the control voltage in the integration stage. In particular, the N-type transistor M63 is used to receive the constant current I from the constant current source 620. IN / 10 is based on a predetermined ratio (for example, the size ratio between the N-type transistors M63 and M64) and the constant current I IN / 10 controls the N-type transistor M64 to generate the sampled current value (eg, constant current I IN / 10 multiplied by the predetermined ratio), and the N-type transistor M64 is used to output a variable current I having the sampled current value in the sampling phase. OUT .

[0050] In the present embodiment, the variable current source 60 may further include switches S61, S62, S63, S64, S65 and S66, wherein the switch S61 is coupled between the N-type transistor M61 and the constant current source 600, the switch S62 is coupled between the gate and the drain of the N-type transistor M61, the switch S63 is coupled between the gate and the drain of the N-type transistor M62, the switch S64 is coupled between the N-type transistor M61 and the output terminal NOUT, the switch S65 is coupled between the N-type transistor M62 and the output terminal NOUT, and the switch S66 is coupled between the N-type transistor M64 and the output terminal NOUT. In particular, whether each of the switches S61, S62, S63 and S66 is turned on is controlled by the control clock P1, and whether the switches S64 and S65 are turned on is controlled by the control clock P2. Therefore, the switches S61, S62 and S63 are used to be turned on in the sampling phase so that the N-type transistors M61 and M62 receive the constant current I through the switch S61. IN , wherein the switches S62 and S63 are turned on in the sampling phase so that the N-type transistors M61 and M62 are switched on according to the constant current I IN The control voltage is stored on the capacitor C5. For example, the capacitor C6 can be coupled to the gates of the N-type transistors M61 and M62, so that when the N-type transistors M61 and M62 respond to the constant current I INWhen the gate voltage is generated, the gate voltage can be stored on the capacitor C6 as the control voltage. In addition, the switches S64 and S65 are used to be turned on in the integration phase so that the N-type transistors M61 and M62 are turned on according to the control voltage (for example, the N-type transistors M61 and M62 are turned on according to the constant current I IN The gate voltage generated by the integrated current value is the variable current I OUT It should be noted that the switch S66 is used to be turned on in the sampling phase so that the N-type transistor M64 transmits the variable current I having the sampled current value through the switch S66. OUT Output to the output terminal NOUT. Figure 5 In the embodiment, the variable current source 60 uses the N-type transistor M64 to output the variable current I in the sampling stage. OUT , so the variable current I OUT The current value in the sampling phase (ie, the sampling current) is non-zero. Under this architecture, the quiescent current of the freewheeling output terminal NOUT can be controlled within an allowable range, and the variable current I OUT It will be too low during the sampling phase to ensure that the switched capacitor integrator 10 can still operate properly when the frequency of the system clock is increased.

[0051] In some embodiments, the above-mentioned integrated current value can be designed to be switchable. For example, the integrated current value can include a first integrated current value and a second integrated current value. When the switched capacitor integrator 10 operates at a first frequency, the variable current source 121 can change the variable current I OUT When the switched capacitor integrator 10 operates at a second frequency, the variable current source 121 can switch the variable current I OUT In particular, when the second frequency is greater than the first frequency, the second integrated current value can be designed to be greater than the first integrated current value, and the first integrated current value can be designed to be greater than the sampling current value. Therefore, when the switched capacitor integrator 10 operates at the first frequency, the variable current I OUT The switching between the sampling current value and the first integrated current value may be switched in response to the switching between the sampling phase and the integration phase. When the switched capacitor integrator 10 operates at the second frequency, the variable current I OUT The sampling current value and the second integrated current value may be switched in response to the switching between the sampling phase and the integration phase.

[0052] The above switchable design for the integral current value can be applied to Figures 4 to 6The structure shown in any one of the above-mentioned integrated current values ​​should be understood by those skilled in the art based on the control method of the above-mentioned multiple integrated current values. Figures 4 to 6 The architecture shown in any one of the above embodiments adds corresponding current branches and / or switch controls to implement an architecture with multiple integrated current values. For the sake of simplicity, the relevant details are not repeated here.

[0053] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An integrator operating on a variable current, comprising: An operational amplifier comprising: an amplifier stage circuit for providing an amplification gain; and a bias circuit coupled to the amplifier stage circuit and used to control a bias condition of the amplifier stage circuit according to the variable current output by a variable current source; in: In a sampling phase of the integrator, the variable current source switches the variable current to a sampled current value; In an integration phase of the integrator, the variable current source switches the variable current to an integrated current value; and The sampled current value is smaller than the integrated current value.

2. The integrator of claim 1 , wherein the bias circuit comprises the variable current source, and further comprises: At least one current mirror circuit is coupled to the variable current source and the amplifier stage circuit, and is used to generate one or more bias voltages according to the variable current to control the bias condition of the amplifier stage circuit.

3. The integrator as claimed in claim 1, wherein the variable current source comprises: a constant current source, used for outputting a constant current; an output circuit, used to output the variable current; a first current mirror circuit, used for receiving the constant current in the sampling phase to control the output circuit according to a first predetermined ratio and the constant current, so that the variable current is switched to the sampled current value; and A second current mirror circuit is used to receive the constant current in the integration phase to control the output circuit according to a second predetermined ratio and the constant current, so that the variable current is switched to the integration current value.

4. The integrator as claimed in claim 3, wherein the variable current source further comprises: a first switch coupled between the first current mirror circuit and the constant current source, and configured to be turned on during the sampling phase to couple the first current mirror circuit to the constant current source; and A second switch is coupled between the second current mirror circuit and the constant current source, and is used to be turned on in the integration phase to couple the second current mirror circuit to the constant current source.

5. The integrator as claimed in claim 1, wherein the variable current source comprises: a constant current source, configured to output a constant current; and At least one transistor, wherein the at least one transistor is used to store a control voltage on a capacitor according to the constant current in the sampling phase, and the at least one transistor is used to generate the integrated current value according to the control voltage in the integration phase.

6. The integrator as claimed in claim 5, wherein the variable current source further comprises: a first switch coupled between the at least one transistor and the constant current source, and configured to be turned on in the sampling phase so that the at least one transistor receives the constant current through the first switch; a second switch coupled between a gate and a drain of the at least one transistor, configured to be turned on during the sampling phase so that the at least one transistor stores the control voltage on the capacitor according to the constant current, wherein the capacitor is coupled to the gate of the at least one transistor; and At least one third switch is coupled between the at least one transistor and an output terminal, and is used to be turned on in the integration phase so that the at least one transistor outputs the variable current having the integrated current value to the output terminal according to the control voltage.

7. The integrator of claim 1 , wherein the variable current source comprises: a first constant current source, used for outputting a first constant current; At least one transistor, wherein the at least one transistor is used to store a control voltage on a capacitor according to the first constant current in the sampling phase, and the at least one transistor is used to generate the integrated current value according to the control voltage in the integration phase; a second constant current source, used for outputting a second constant current; an output circuit for outputting the variable current having the sampled current value during the sampling phase; and A current mirror circuit is used for receiving the first constant current to control the output circuit to generate the sampled current value according to a predetermined ratio and the second constant current.

8. The integrator as claimed in claim 7, wherein the variable current source further comprises: a first switch, coupled between the at least one transistor and the first constant current source, and configured to be turned on in the sampling phase so that the at least one transistor receives the first constant current through the first switch; at least one second switch, coupled between a gate and a drain of the at least one transistor, and configured to be turned on during the sampling phase so that the at least one transistor stores the control voltage on the capacitor according to the first constant current, wherein the capacitor is coupled to the gate of the at least one transistor; at least one third switch coupled between the at least one transistor and an output terminal, and configured to be turned on during the integration phase so that the at least one transistor outputs the variable current having the integrated current value to the output terminal according to the control voltage; and A fourth switch is coupled between the output circuit and the output terminal and is used to be turned on in the sampling phase so that the output circuit outputs the variable current having the sampled current value to the output terminal through the fourth switch.

9. An integrator as described in claim 1, wherein the integrated current value includes a first integrated current value and a second integrated current value; when the integrator operates at a first frequency, the variable current source switches the variable current to the first integrated current value during the integration phase; and when the integrator operates at a second frequency, the variable current source switches the variable current to the second integrated current value during the integration phase. 10 . The integrator of claim 9 , wherein the second frequency is greater than the first frequency, the second integrated current value is greater than the first integrated current value, and the first integrated current value is greater than the sampling current value.

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