Semiconductor structure processing method, semiconductor structure and semiconductor processing device

Abstract

The invention discloses a semiconductor structure processing method, a semiconductor structure and a semiconductor processing device. The processing method comprises the steps that a substrate is provided and comprises a base layer arranged on the substrate, the base layer is provided with a slope structure, the side portion of the base layer gradually extends outwards in the direction from the top surface to the substrate, the slope structure is covered with a cut-off layer, and a dielectric layer is arranged on the cut-off layer; starting a source radio frequency and a bias radio frequency, introducing a first etching gas, and etching the dielectric layer until the third-type hole exposes the cut-off layer; reducing the power of bias radio frequency, so that the openings of the first type of holes, the second type of holes and the third type of holes are laterally etched; and second etching gas is introduced, the cut-off layer exposed by the third type of holes is etched, and the flow of the second etching gas is linearly increased at the slope k along with the etching time until the cut-off layer of the third type of holes is etched to the preset depth. By controlling the allowance of the cut-off layer in the through holes with different depths and different depth-to-width ratios, the process window of the subsequent process of striking the cut-off layer is expanded.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device processing, and in particular relates to a semiconductor structure processing method, a semiconductor structure and a semiconductor processing device. Background Art

[0002] With the advent of the big data era, the demand for storage has increased exponentially. To meet this demand, the technology of storage chips has transformed from 2D NAND to 3D NAND, which has higher storage density but more complex structure.

[0003] For high-density or ultra-high-density structures, one of the challenges faced in plasma etching is the increasing aspect ratio required to meet design requirements, especially when holes or grooves of different depths and aspect ratios need to be etched simultaneously on the same structure, where at least some of the holes or grooves have a high aspect ratio. The existing technology is not easy to make holes or grooves of different depths and different aspect ratios meet the predetermined depth when etching holes or grooves of different depths in the same structure. Excessive etching or insufficient etching often occurs, resulting in a narrow process window in the subsequent process of further etching through the protective layer at the bottom of the hole or groove. Summary of the invention

[0004] The purpose of the present invention is to expand the process window of a semiconductor structure for forming holes or grooves of different depths and different aspect ratios. By adjusting the bias RF power and the type and flow rate of the etching gas, the margin of the cut-off layer in holes of different depths and different aspect ratios can be regulated, so that the margin of the cut-off layer in a deep hole with a large aspect ratio can be slightly smaller than or equal to the margin of the cut-off layer in a hole of medium depth and a small aspect ratio.

[0005] In order to achieve the above object, the present invention provides a method for processing a semiconductor structure, comprising the following steps:

[0006] A substrate is provided, the substrate comprising a base layer arranged on a substrate, the base layer having a slope structure formed by gradually extending the side from the top surface toward the substrate, the slope structure is covered with a cut-off layer, and a dielectric layer is arranged on the cut-off layer;

[0007] Turning on the source radio frequency and the bias radio frequency, introducing the first etching gas, etching the dielectric layer, and forming a plurality of first-type holes, second-type holes, and third-type holes with different aspect ratios, until the third-type holes expose the cutoff layer; wherein the third-type holes 深宽比 >Second type hole 深宽比 >First type of hole 深宽比 ;

[0008] Reducing the power of the bias radio frequency so that the openings of the first type of holes, the second type of holes, and the third type of holes are lateral-etched for a preset time;

[0009] A second etching gas is introduced to etch the cutoff layer exposed by the third type of holes. During the etching process, the flow rate of the second etching gas increases linearly with the etching time at a slope k until the cutoff layer of the third type of holes is etched to a preset depth.

[0010] Optionally, the slope k is 0.6-1.2.

[0011] Optionally, the second etching gas includes C x H y F z Gas, 0≤x<2, y>0, z≥0.

[0012] Optionally, the second etching gas includes at least one of difluoromethane (CH2F2), trifluoromethane (CHF3), monofluoromethane (CH3F) and hydrogen (H2).

[0013] Optionally, the second etching gas includes CH2F2, wherein the flow rate of CH2F2 is 15 sccm to 30 sccm.

[0014] Optionally, the second etching gas also includes oxygen (O2).

[0015] Optionally, the volume ratio of CH2F2 to O2 is 0.4:1 to 0.6:1.

[0016] Optionally, the volume of CH2F2 and O2 accounts for 10% to 20% of the total volume of the first etching gas and the second etching gas.

[0017] Optionally, it is characterized in that the process gas pressure is 20mT to 30mT.

[0018] Optionally, when the source radio frequency and the bias radio frequency are turned on, the frequency of the source radio frequency is 60 MHz, and the power is 2500 W to 3000 W; the frequency of the bias radio frequency is 400 Khz, and the power is 15000 to 18000 W.

[0019] Optionally, when reducing the power of the bias radio frequency, the power of the bias radio frequency is reduced by 1000w-1500w to form a carbon-containing deposition layer at the bottom of the second type of holes.

[0020] Optionally, the first etching gas includes hexafluorobutadiene (C4F6).

[0021] Optionally, the first etching gas further includes at least one of octafluorocyclobutane (C4F8), O2, octafluoropropane (C3F8), octafluorocyclopentene (C5F8) and hexafluorobenzene (C6F6).

[0022] Optionally, the first etching gas further includes an auxiliary gas, the auxiliary gas includes a rare gas, and the rare gas is at least one of argon (Ar), krypton (Kr) and xenon (Xe).

[0023] Optionally, the auxiliary gas is a mixture of Ar, nitrogen (N2) and carbon monoxide (CO).

[0024] Optionally, the depth-to-width ratio of the third type of hole is 19:1≤≤25:1; the depth-to-width ratio of the second type of hole is 14:1≤≤19:1; and the depth-to-width ratio of the first type of hole is <8:1.

[0025] Optionally, when the cutoff layer of the third type of hole is etched to the preset depth, the bottom of the first type of hole has a carbon-containing deposition layer with a thickness of 600nm to 1000nm; the bottom of the second type of hole has a carbon-containing deposition layer with a thickness of 35nm to 45nm; the bottom of the third type of hole has a carbon-containing deposition layer with a thickness of 1nm to 10nm.

[0026] Optionally, the base layer is a stacked structure, and in the slope structure, the side edge of each stack extends outward relative to the side edge of the upper stack, and the upper surface of the extended portion formed by each stack is farther away from the top outer surface of the dielectric layer than the upper surface of the extended portion formed by the upper stack, and a plurality of the extended portions form a step shape, so that the slope structure is stepped.

[0027] Optionally, the stacked layer at least includes a conductor layer and an insulating layer, the topmost layer of the stacked layer structure is a conductor layer, the conductor layer is a polysilicon layer or a conductive metal layer, and the insulating layer is a silicon oxide layer.

[0028] The present invention also provides a semiconductor structure, comprising:

[0029] substrate;

[0030] A base layer, formed on the substrate, the base layer having a slope structure formed by gradually extending the side from the top surface toward the substrate;

[0031] a cut-off layer overlying the slope structure; and

[0032] A dielectric layer is arranged on the cutoff layer, and a plurality of first-type holes, second-type holes and third-type holes with different aspect ratios are formed on the dielectric layer by any of the processing methods described above, and a carbon-containing deposition layer with a preset thickness is formed on the cutoff layer.

[0033] Optionally, the stop layer comprises nitride, and the nitride is selected from at least one of SiN, AlN, GaN, InN, AlN, AlGaN, InGaN and InGaAlN.

[0034] Optionally, the dielectric layer is a silicon oxide layer.

[0035] The present invention also provides a semiconductor processing device, comprising:

[0036] an etching chamber for processing a substrate;

[0037] A gas supply assembly, used for introducing reaction gas;

[0038] source RF and bias RF; and

[0039] A control unit is used to control the steps of any of the above-mentioned methods for processing the semiconductor structure.

[0040] Compared with the prior art, the technical solution of the present invention has at least the following technical effects:

[0041] The present invention reduces the power of bias radio frequency until the third type of hole exposes the cutoff layer, so that the bottom characteristic dimension (BCD) of the bottom of the third type of hole can be opened, which is convenient for etching the cutoff layer in the third type of hole, and can increase the carbon-containing deposition layer of the second type of hole, thereby delaying the etching of the cutoff layer in the second type of hole.

[0042] Furthermore, the present invention also introduces a second etching gas that is beneficial to etching deep holes. The flow rate of the second etching gas increases linearly, so that the cutoff layer in the third type of hole can be etched to a set depth, while only the carbon-containing deposition layer is consumed in the second type of hole. The cutoff layer in the second type of hole is almost not etched, thereby achieving control of the remaining amount of the cutoff layer in through holes or grooves of different depths and different aspect ratios, and expanding the process window for penetrating the cutoff layer process. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of a semiconductor structure of a three-dimensional storage device.

[0044] Figure 2 A schematic diagram of a cut-off semiconductor structure of a three-dimensional memory device.

[0045] Figure 3 A schematic diagram of a short-circuit semiconductor structure of a three-dimensional memory device.

[0046] Figure 4 The present invention is a flowchart of a method for processing a semiconductor structure.

[0047] Figure 5 The figure is a schematic diagram of the etching morphology of the bottom of each hole in the semiconductor structure during the processing method of the semiconductor structure of the present invention.

[0048] Figure 6It is a schematic diagram of linearly increasing the flow rate of the second etching gas in a semiconductor structure processing method of the present invention.

[0049] Figure 7 It is a schematic diagram of a semiconductor structure of the present invention.

[0050] Figure 8 : This is a comparison diagram of the semiconductor structure before and after the test of an embodiment of the present invention, wherein a is a structural schematic diagram of the substrate to be processed, b is a distribution diagram of the remaining amount of silicon nitride at different steps as the depth of the contact through hole in the semiconductor structure processed by the embodiment, c is a schematic diagram of the morphology of the semiconductor structure prepared by the embodiment after removing the carbon-containing deposition layer, and d is a schematic diagram of the morphology of the semiconductor structure prepared by the embodiment after the step of removing the carbon-containing deposition layer and penetrating the silicon nitride.

[0051] Fig. 9 The figure is a distribution diagram of the silicon nitride residue at different steps in the semiconductor structure processed by the comparative example as a function of the depth of the contact through hole.

[0052] Figure ID:

[0053] Substrate 10

[0054] Base layer 11

[0055] Layer 110

[0056] Oxide layer 111

[0057] Polysilicon layer 112

[0058] Extension 113

[0059] Cut-off layer 12

[0060] Dielectric layer 13

[0061] Contact through hole 131

[0062] Type I hole 1311

[0063] The second type of hole 1312

[0064] The third type of hole 1313

[0065] Deposition layer 132

[0066] Mask layer 14

[0067] The mask opening 141 . DETAILED DESCRIPTION

[0068] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0069] In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0070] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0071] Currently, there are two technical routes for 3D NAND: the all-around gate (GAA) + charge trap (Charge Trap) technology route and the all-around gate GAA (Gate all around) + floating gate (Floating gate) technology route.

[0072] Taking the floating gate technology route as an example, the three-dimensional memory device has the following features: Figure 1The semiconductor structure shown comprises: a substrate 10, a base layer 11, a stop layer 12 and a dielectric layer 13. In this example, the substrate 10 is made of polysilicon. The base layer 11 is a stacked structure, which is formed by stacking a number of stacks 110. Each stack 110 comprises an oxide layer 111 and a polysilicon layer 112. The upper surface of each stack 110 is the upper surface of the polysilicon layer 112. The edge of one side of each stack 110 extends outward relative to the edge of the side of the stack 110 above it. The upper surface of the extension portion 113 formed by each stack 110 is longer than the upper surface of the extension portion 113 formed by the stack 110 above it. The multiple extension portions 113 form steps, so that one side of the base layer 11 has a stepped slope structure. The stop layer 12 covers the slope structure. The dielectric layer 13 is formed on the stop layer 12, and the upper surface of the dielectric layer 13 is flush with the upper surface of the base layer 11. The cut-off layer 12 physically isolates the dielectric layer 13 from the base layer 11. The dielectric layer 13 is formed with a plurality of contact holes 131 of different depths, the bottom of the contact holes 131 is the polysilicon layer 112, and the contact holes 131 can be filled with metal, so that the contact holes 131 can independently connect the polysilicon layers 112 of different depths to the outside, and adjacent contact holes 131 are isolated by the dielectric layer 13. This structure can electrically connect the memory cells of different layers (pages) to the peripheral circuit through mutually insulated contact holes, so as to independently perform read and write operations on the memory cells of different layers.

[0073] The process flow of forming the above-mentioned memory cell structure is as follows: First, a stacked structure of an oxide layer 111 and a polysilicon (Poly Si) layer 112 is alternately deposited as a base layer 11, and then a step-shaped slope structure is etched on one side of the stacked structure using a mask. In order to prevent damage to the polysilicon layer 112 during the hole-etching process, a stop layer 12 is deposited on the slope structure for protection. In this example, the stop layer 12 is a silicon nitride stop layer (SiN stop layer). A dielectric layer 13 is then deposited on the stop layer 12. Then, the dielectric layer 13 is etched to simultaneously form contact holes 131 of different depths. After the dielectric layer 13 is etched, a silicon nitride punch step (SiN punchstep) with a very high selectivity of silicon nitride to polysilicon is performed to open the silicon nitride stop layer at different heights, exposing the polysilicon layer 112 at the bottom of the contact through hole 131, and filling the contact through hole 131 with conductive materials such as metal, so that the contact through hole 131 can electrically connect the polysilicon layer 112 at different depths to the peripheral circuit.

[0074] For the convenience of description, the present invention divides the contact holes 131 formed at different depths into three types of holes according to different depth ranges (see Figure 1 ):

[0075] Shallow holes, e.g., with a depth-to-width ratio of <8:1, are recorded as first-type holes 1311;

[0076] Medium depth holes, e.g., with aspect ratios between 14:1 and 19:1, are referred to as second type holes 1312; and

[0077] A deep hole, for example, having a depth-to-width ratio between 19:1 and 25:1, is referred to as a third type hole 1313 .

[0078] The distance between the cutoff layer exposed by the first type of hole 1311 and the edge of the hole opening of the first type of hole is the depth of the first type of hole 1311, which is recorded as h1; the distance between the cutoff layer exposed by the second type of hole 1312 and the edge of the hole opening of the second type of hole is the depth of the second type of hole 1312, which is recorded as h2; the distance between the cutoff layer exposed by the third type of hole 1313 and the edge of the hole opening of the third type of hole is the depth of the third type of hole 1313, which is recorded as h3; wherein, h1<h2<h3.

[0079] In the conventional process, after the through hole etching (CT etch) of the dielectric layer 13 is completed, the recess range of the cutoff layer 12 in the contact through hole 131 of different depths is relatively large. As the depth of the contact through hole 131 increases, the remaining amount of the cutoff layer in each hole generally presents a U-shaped distribution, that is, the remaining amount of the cutoff layer in the first type of hole 1311 and the third type of hole 1313 is relatively thick, while the remaining amount of the cutoff layer in the second type of hole 1312 is relatively thin. This is because during the etching process of the dielectric layer 13, the cutoff layer at the bottom of the first type of hole 1311 is first exposed to the plasma. Since the aspect ratio of the first type of hole 1311 is relatively small, the non-volatile reaction by-products generated by etching can easily enter the bottom of the hole to form a thicker carbon-containing deposition layer. The reaction by-products are mainly carbon-containing polymers, and their general formula can be C x F y , x and y represent the number of atoms. The thicker deposition layer can shield the cut-off layer at the bottom of the first type of hole 1311, so that the cut-off layer is protected from strong ion bombardment and damage, so the remaining amount of the cut-off layer in the first type of hole 1311 is thicker. For the second type of hole 1312, when the etching of the dielectric layer 13 continues and the cut-off layer at the bottom of the second type of hole 1312 is exposed, the hole depth is greater than that of the first type of hole 1311, and the aspect ratio is also greater. At this time, the reaction byproduct C x F y The distance to the bottom of the second type of pores through molecular thermal motion becomes longer, and the C that can reach the bottom of the second type of pores x F yThe amount of fluorine (F) decreases. Therefore, the deposited layer on the surface of the cutoff layer at the bottom of the second type hole 1312 will be relatively thin. However, ion bombardment and small molecule fluorine (F)-containing radicals (radicals) can also enter the bottom of the second type hole 1312. Ion bombardment can easily penetrate the thinner deposited layer, causing the F-containing radicals to react with the cutoff layer and etch more of the cutoff layer, resulting in a relatively thin cutoff layer at the bottom of the second type hole, and even causing the cutoff layer to be broken down and damage the polysilicon layer underneath. For the third type hole 1313, when the etching of the dielectric layer 13 continues to expose the cutoff layer at the bottom of the third type hole 1313, its aspect ratio is already large enough, and the sidewalls of the third type hole 1313 are longer, which will consume more F radicals, so the radicals that can reach the bottom of the third type hole 1313 become extremely few. Although the deposition layer on the surface of the cut-off layer in the third-type hole 1313 is less than that in the second-type hole 1312, the reaction precursor F radical is also insufficient, so the reaction with the cut-off layer is very slow, and the cut-off layer is etched less, resulting in a larger amount of the cut-off layer remaining in the third-type hole 1313. After the etching of the dielectric layer contact through hole is completed, the excessive amount of the cut-off layer remaining in the third-type hole 1313 will affect the subsequent process of punching through the cut-off layer.

[0080] The process of punching through the stop layer is used to selectively bombard and remove the stop layer 12 without damaging the polysilicon layer 112 underneath, and is mainly a physical bombardment process. Under the same process conditions, the impact force received at the bottom of the contact through hole 131 is directly related to the hole depth, that is, the greater the depth of the hole, the smaller the impact force received. Since the depth h3 of the third type of hole 1313 is greater than the depth h2 of the second type of hole 1312 and the depth h1 of the first type of hole 1311, under the same power, the impact force received by the stop layer at the bottom of the third type of hole 1313 will be the smallest. When the thickness of the stop layer of each hole is the same, the process time required to punch through the stop layer of the third type of hole 1313 is the longest. Since the process of punching through the cutoff layer is performed on the contact holes 131 of different depths at the same time, when the remaining amount of the cutoff layer in the contact holes 131 of different depths is U-shaped, that is, the remaining amount of the cutoff layer in the first type of hole 1311 and the third type of hole 1313 is relatively thick, and the remaining amount of the cutoff layer in the second type of hole is relatively thin, after the punching step is performed for a certain period of time, the cutoff layer in the second type of hole 1312 has been broken through to expose the polysilicon layer below, and continuing the punching step will cause damage to the polysilicon layer at the bottom of the second type of hole 1312; at this time, the cutoff layer in the third type of hole 1313 has not been punched through, and the punching step needs to be continued. If the punching step is stopped at this time, since the cutoff layer in the third type of hole 1313 has not been fully opened, the contact hole 131 will be broken and lose control of the word line (WL), such as Figure 2 As shown; if the punching step is continued until the cutoff layer in the third type hole 1313 is punched through and removed, the polysilicon layer at the bottom of the second type hole 1312 may be damaged or even punched through to connect with the next layer of polysilicon layer, resulting in a short circuit between adjacent WLs, such as Figure 3 Therefore, when the remaining amount of the cutoff layer in the contact through hole 131 is U-shaped, or the remaining amount of the cutoff layer in the second type hole 1312 is less than that in the third type hole 1313, under the same process conditions, the process window of the process of punching through the cutoff layer will be narrower.

[0081] Therefore, controlling the remaining amount of the stop layer in contact holes of different depths becomes a key point and a challenge point in the staircase CT etch process.

[0082] In order to use uniform process conditions in the process of punching through the cutoff layer and achieve different penetration depths, for the cutoff layer at the bottom of the contact through-holes of different depths, only the cutoff layer is broken through without breaking through or damaging the base layer covered by the cutoff layer. The present invention proposes a novel etching method, which can realize the control of the remaining thickness of the cutoff layer in the contact through-holes of different depths in the step through-hole etching, so that the remaining amount of the cutoff layer in the third type of hole 1313 is not higher than the remaining amount of the cutoff layer in the second type of hole 1312, thereby expanding the process window of the process of punching through the cutoff layer. The following is combined with Figure 4-7 The process steps of the present invention, the etching morphology of the holes in each step and the reaction mechanism are described respectively.

[0083] like Figure 4 As shown, a method for processing a semiconductor structure of the present invention comprises the following steps:

[0084] Step S1, providing a substrate, the substrate comprising a base layer arranged on a substrate, the base layer having a slope structure formed by gradually extending the side from the top surface toward the substrate, the slope structure is covered with a cutoff layer, and a dielectric layer is arranged on the cutoff layer.

[0085] The material of the substrate may be at least one of silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), and the like.

[0086] The base layer may be a polysilicon layer, a silicon oxide layer, or a laminated structure composed of alternating conductor layers and insulating layers. The material of the conductor layer includes polysilicon or a conductive metal, such as tungsten (W). The material of the insulating layer is a dielectric material such as silicon oxide. In this example, the conductor layer is a polysilicon layer, and the insulating layer is a silicon oxide layer.

[0087] In this paper, the slope is defined as the ratio of the base height H where the gradient segment appears from the sidewall profile to the horizontal distance L from the sidewall of the gradient segment (see Figure 7). The purpose of forming a slope on one side of the base layer is to form contact holes of different depths. By filling the contact holes with conductive materials, polysilicon layers of different depths can be connected to peripheral circuits. In this example, a slope structure is provided on one side of the base layer, but it is not limited thereto. Both sides may also have a slope structure. In this example, the horizontal length of the base layer gradually increases from the top of the base layer to the substrate direction. It can be understood that the situation in which the horizontal length of the base layer gradually shortens from the top of the base layer to the substrate direction is also applicable to the present invention.

[0088] The cut-off layer is provided to avoid damaging the base layer when etching the dielectric layer. The cut-off layer comprises a nitride, and at least one of SiN, AlN, GaN, InN, AlN, AlGaN, InGaN and InGaAlN can be selected. As an example, the cut-off layer can be silicon nitride.

[0089] The dielectric layer is formed on the cutoff layer. The side of the dielectric layer in contact with the cutoff layer has a slope extending from the top surface to the substrate. The length of the cross section of the dielectric layer in the horizontal direction gradually becomes shorter. The slope of the side of the dielectric layer is consistent with the slope of the side of the base layer, and the direction is opposite. Therefore, the upper surface of the dielectric layer is flush with the upper surface of the base layer. By etching the dielectric layer, mutually insulated contact holes with different depths can be formed. The bottom of the contact hole formed by punching through the cutoff layer is a conductor layer. When the contact hole is filled with a conductor material, the conductor layers of each layer at different depths can be electrically connected to the external circuit through the contact hole. In this example, the material of the dielectric layer is silicon oxide.

[0090] Step S2, turning on the source RF and the bias RF, introducing the first etching gas, etching the dielectric layer, forming a plurality of first-type holes, second-type holes and third-type holes with different aspect ratios, until the third-type holes expose the cutoff layer; wherein the third-type holes 深宽比 >Second type hole 深宽比 >First type of hole 深宽比 .

[0091] The source RF is used to dissociate the first etching gas to form a plasma. The plasma is highly active and can react with the dielectric layer to etch and form a contact hole. The bias RF is used to physically bombard the dielectric layer of the substrate to assist in etching. When the source RF and the bias RF are turned on, the frequency of the source RF is 60MHz and the power is 2500W to 3000W; the frequency of the bias RF is 400Khz and the power is 15000W to 18000W.

[0092] In order to prevent the first type of holes 1311 from being etched too quickly, the first etching gas is selected to form a deposition layer while etching the dielectric layer. The deposition layer is mainly carbon-containing C xF y The polymer molecules are easily deposited into the first type of pores to form a deposition layer, which masks the etching layer and slows down the etching rate. The first etching gas usually includes C4F6. According to the different aspect ratios of the contact through holes and the distribution of the first type of pores, the second type of pores, and the third type of pores, the first etching gas may also include at least one of C4F8, O2, C3F8, C5F8 and C6F6.

[0093] In some embodiments, the first etching gas further includes an auxiliary gas, the auxiliary gas includes a rare gas, and the rare gas is at least one of argon (Ar), krypton (Kr) and xenon (Xe). The molecular weight of the rare gas is relatively large, and the positive ions dissociated by the source radio frequency can assist physical bombardment.

[0094] In some embodiments, the auxiliary gas is a mixture of Ar, nitrogen (N2) and carbon monoxide (CO). When the source RF is turned on, the positive ions dissociated from the nitrogen can modify the mask to prevent the mask opening from being blocked. CO can provide carbon ions to assist in forming a deposition layer.

[0095] The main gas dissociation equation of the first etching gas is as follows:

[0096] e - +C4F6→CF * +CF2 * +CF3 * +F * +C2F4 + +e -

[0097] C4F8→CF * +CF2 * +CF3 * +C2F4 + +F * +e -

[0098] e - +O2→O * +O * +e -

[0099] Ar→Ar + +e -

[0100] N2→N2 + +e -

[0101] e - +CO→C+O+e -

[0102] Step S2 is in the first stage of etching. The etching morphology of the contact through hole 131 (the first type of hole 1311, the second type of hole 1312 and the third type of hole 1313) is as follows: Figure 5 As shown in a, in order to clearly illustrate the bottom morphology of each hole, only the portion of each hole close to the cut-off layer 12 is captured in the figure.

[0103] The following reactions mainly occur in the first type of pores 1311:

[0104] e - +CF2 * +C2F4 + +CF * +SiO2→CO↑+SiF4↑+C+C+e -

[0105] Initially, the first etching gas etches the silicon oxide dielectric layer in the first type of pores 1311, and generates a small amount of byproduct C x F y The polymer and byproducts are deposited at the bottom of the hole. At this time, the etching rate is greater than the deposition rate. Since the distance h1 between the cut-off layer at the bottom of the first type of hole 1311 and the hole mouth (see Figure 7 ) is small. When etching to the cut-off layer, the depth-width ratio of the first type of hole 1311 is small. The byproducts generated during etching easily fall into the first type of hole 1311 and are deposited at the bottom of the first type of hole 1311. The deposition layer deposited at the bottom masks the cut-off layer at the bottom of the hole, so that the etching rate of the cut-off layer is slowed down. Due to the etching selectivity of the cut-off layer, the downward etching rate is further slowed down until the etching rate is less than the deposition rate, and the net deposition layer gradually increases. As an example, in the first stage of etching, the thickness of the net deposition layer in the first type of hole 1311 is 400nm to 800nm.

[0106] The following reactions mainly occur in the second type of pores 1312:

[0107] e - +CF2*+CF*+SiO2→CO↑+SiF4↑+C+e -

[0108] Initially, the first etching gas etches the silicon oxide dielectric layer in the second type of hole 1312, and generates a small amount of byproduct C x F y The polymer and byproducts are deposited at the bottom of the hole. At this time, the etching rate is greater than the deposition rate. Since the distance h2 between the cut-off layer exposed by the second type hole 1312 and the hole edge of the second type hole is greater than h1 (see Figure 7), when etching to the cut-off layer, the depth-to-width ratio of the formed second-type pores 1312 is greater than that of the first-type pores 1311, and larger molecules are not easy to enter the second-type pores 1312. The byproducts that fall into the second-type pores 1312 and deposit at the bottom thereof are relatively few. The deposition layer deposited at the bottom of the second-type pores is very thin. In this example, the thickness of the deposition layer is 10nm to 20nm, which is not enough to resist ion bombardment and small molecule fluorine-containing free radicals. Therefore, when the cut-off layer of the first-type pores 1311 has stopped being etched, the etching of the cut-off layer of the second-type pores 1312 continues slowly. In order to prevent the cut-off layer of the second-type pores 1312 from being etched too much and being easily broken through in the subsequent process of punching through the cut-off layer, measures need to be taken.

[0109] The following reactions mainly occur in the third type of pores 1313:

[0110] e - +CF * +SiO2→CO↑+SiF4↑+e -

[0111] Initially, the first etching gas etches the dielectric layer in the third type hole 1313, and generates a very small amount of byproduct C x H y The polymer and byproducts are deposited at the bottom of the hole. At this time, the etching rate is greater than the deposition rate. Since the distance h3 between the cut-off layer exposed by the third-type hole 1313 and the edge of the hole mouth of the third-type hole is the largest (see Figure 7 ), the depth and width of the third-type hole 1313 formed by etching to the cut-off layer are larger than those of the first-type hole 1311 and the second-type hole 1312, and only very small molecules can enter the third-type hole 1313, so there are very few byproducts that fall into the third-type hole 1313 and deposit at the bottom thereof, and there is almost no deposition layer at the bottom of the third-type hole 1313. In addition, due to the etching selectivity of the cut-off layer, when etching to the cut-off layer, the downward etching rate is almost stagnant, and measures need to be taken to continue etching the cut-off layer of the third-type hole 1313 so that the thickness of the remaining amount of the cut-off layer meets the requirements. Furthermore, since it is difficult for the first etching gas to enter the third-type hole 1313 with a high aspect ratio, there may be a dielectric layer residue at the bottom of the third-type hole 1313, forming a V-shape, and measures need to be taken to open the bottom BCD of the third-type hole.

[0112] Step S3, reducing the power of the bias radio frequency, so that the openings of the first type of aperture 1311, the second type of aperture 1312 and the third type of aperture 1313 are lateral-etched for a preset time.

[0113] The preset time can be preset according to the over-etching amount of the third type of holes, and can also be preset according to the time it takes for the BCD of the first type of holes, the second type of holes, and the third type of holes to reach the target size.

[0114] In order to open the bottom BCD of the third type hole 1313 and make the bottom of the third type hole 1313 present an ideal flat state, the power of the bias RF is reduced, and the flow rate and type of the first etching gas remain unchanged. The dissociation equation of the first etching gas is the same as step 1, so it is not repeated.

[0115] Step S3 is the second stage of etching, and the etching morphology of each hole is as follows: Figure 5 As shown in b.

[0116] The following reactions mainly occur in the first type of pores 1311 (forming a carbon-containing deposition layer):

[0117] e-+CO→C+O+e-

[0118] e - +C2F4+→CF3*+C+e -

[0119] The power of the bias RF is reduced, and the bombardment force is weakened, so that the downward etching rate in the first type of hole 1311 is further slowed down, and a carbon-containing deposition layer is mainly formed. The net deposition layer at the bottom of the first type of hole 1311 increases, and the thickness of the net deposition layer can reach 450nm to 850nm. Due to the masking of the hole bottom cutoff layer by the net deposition layer, it is difficult for the first etching gas to etch downward, but it etches the side wall of the first type of hole 1311 to a certain extent, so that the bottom BCD of the first type of hole 1311 increases. In order to maintain the consistency of the feature size, the bottom BCD of the first type of hole 1311 can be made slightly smaller than the target size during design, and when the bottom BCD of the first type of hole 1311 increases, it just reaches the target size.

[0120] The following reactions mainly occur in the second type of holes 1312 (the carbon-containing deposition layer is formed while etching the sidewall dielectric layer):

[0121] e-+CF2*+CF*+SiO2→CO↑+SiF4↑+C+e-

[0122] The power of the bias RF is reduced, and the bombardment force is weakened, so that the downward etching rate in the second type of hole 1312 is further slowed down, and the first etching gas etches the sidewall of the second type of hole 1312 to a certain extent, so that the bottom BCD of the second type of hole 1312 increases. In order to maintain the consistency of the characteristic size, the bottom BCD of the second type of hole 1312 can be made slightly smaller than the target size during design, and the target size is just reached when the bottom BCD of the second type of hole 1312 increases. And because carbon-containing byproducts are formed during the etching reaction, the net deposition layer at the bottom of the second type of hole 1312 increases, and the thickness of the net deposition layer can reach 15nm to 20nm.

[0123] The following reactions mainly occur in the third type of holes 1313 (the dielectric layer remaining on the bottom sidewall is etched, and no carbon-containing deposition layer is formed):

[0124] e-+CF*+SiO2→CO↑+SiF4↑+e-

[0125] The power of the bias RF is reduced, and the bombardment force is weakened, so that the downward etching rate in the third-type hole 1313 is further slowed down. The first etching gas etches the dielectric layer remaining on the bottom sidewall of the third-type hole 1313 to a certain extent, so that the bottom BCD of the third-type hole 1313 increases. And because the molecules entering the third-type hole 1313 are small molecules, such as CF*, when they react with the dielectric layer, almost no carbon-containing C x F y Byproduct, there is almost no net deposition layer at the bottom of the third type hole 1313. In this example, the overetching amount of the third type hole 1313 reaches 3%, that is, taking step S2 etching for 100 seconds as an example, the etching time of step S3 is about 3 seconds. It can also be determined according to the observed BCD of the third type hole 1313. The bottom of the third type hole 1313 is basically flat, and the BCD reaches the target size.

[0126] In order to open the BCD at the bottom of the third type hole 1313, a net carbon-containing deposition layer is formed at the bottom of the second type hole 1312 to mask the cutoff layer and avoid excessive etching of the cutoff layer in the second type hole 1312. When the power of the bias RF is reduced, the power of the bias RF can be reduced by 1000w to 1500w.

[0127] In step S4, a second etching gas is introduced to etch the cutoff layer exposed by the third type hole 1313. During the etching process, the flow rate of the second etching gas increases linearly with the etching time at a slope k until the cutoff layer of the third type hole 1313 is etched to a preset depth.

[0128] The second etching gas is mainly used to etch the cut-off layer in the third type of hole 1313 with a large depth-to-width ratio. Generally speaking, the second etching gas molecules are relatively small and can easily enter the holes or grooves with a large depth-to-width ratio, which is conducive to deep hole etching. The second etching gas includes C x H y F z gas, 0≤x<2, y>0, z≥0. As an example, the second etching gas may include at least one of CH2F2, CHF3, CH3F and H2.

[0129] In some embodiments, the second etching gas includes CH2F2, wherein the flow rate of CH2F2 is 15 sccm to 30 sccm. The following takes CH2F2 as an example to illustrate the etching state of each hole in step S4.

[0130] In step S4, the first etching gas and the second etching gas are included at the same time. The gas dissociation equation includes the same part as step S1, and also includes the dissociation of the newly added second etching gas CH2F2. The dissociation equation is as follows:

[0131] e - +CH2F2→CHF2 + +CH2F + +H * +F * +e -

[0132] Step S4 can be divided into two stages: the third stage of etching and the fourth stage of etching. When the flow rate of the second etching gas increases linearly with the slope k as the etching progresses, the etching process enters the fourth stage from the third stage, which is marked by the fact that the net deposition layer in the second type of hole 1312 no longer increases. As an example, the slope k can be 0.6 to 1.2. The etching morphology of each hole in the third stage of etching is as follows: Figure 5 As shown in c, the etching morphology of each hole in the fourth stage of etching is as follows Figure 5 As shown in d.

[0133] In the third stage of etching, the amount of the second etching gas is small, and at this time, the following reactions mainly occur in the first type of holes 1311 (forming a deposition layer):

[0134] e-+CO→C+O+e -

[0135] e - +C2F4 + →CF3 * +C+e -

[0136] The deposition layer continues to form in the first type of holes 1311 , and the net deposition layer increases. The thickness of the net deposition layer in the first type of holes 1311 reaches 500 nm to 900 nm.

[0137] The following reactions mainly occur in the second type of pores 1312 (forming a deposition layer):

[0138] e - +CHF2 + +CH2F + →C+HF↑+e -

[0139] The active ions formed after the dissociation of the small molecule CH2F2 in the second etching gas enter the second type of pores 1312 to form a carbon-containing deposition layer. Due to the masking of the deposition layer, the second etching gas forms a deposition layer before contacting the cut-off layer, and the net deposition layer increases. The thickness of the net deposition layer in the second type of pores 1312 reaches 35nm to 45nm.

[0140] The following reactions mainly occur in the third type of holes 1313 (etching stop layer):

[0141] e - +CHF2 + +CH2F + +Si3N4→SiF4↑+NH3↑+HCN↑+e -

[0142] Since the third type of pores 1313 are not masked by the deposition layer, the CHF2 formed by the dissociation of small molecules CH2F2 + 、CH2F + After entering the third type hole 1313 with a relatively high aspect ratio, it is easy to react with the cutoff layer to form volatile products, which are drawn out of the reaction chamber without forming a net deposition layer, that is, the thickness of the net deposition layer in the third type hole 1313 is 0.

[0143] As the flow rate of the second etching gas increases linearly, the etching process enters the fourth stage. In the fourth stage, the gas dissociation equation is the same as that in the third stage.

[0144] The main reaction in the first type of pores 1311 is the same as that in the third stage. The net deposition layer in the first type of pores 1311 continues to increase, and the thickness reaches 600nm to 1000nm.

[0145] The following reactions mainly occur in the second type of pores 1312:

[0146] C+H*+CF2*→CF2+CH↑+e -

[0147] The net deposition layer in the second type of pores 1312 no longer increases, the small molecules consume the carbon-containing deposition layer, and a new fluorocarbon deposition layer is generated at the same time. The thickness of the net deposition layer in the second type of pores 1312 is maintained at approximately 35nm to 45nm, so that the second etching gas cannot contact the stop layer and will not over-etch the stop layer.

[0148] The following reactions mainly occur in the third type of pores 1313:

[0149] e - +CHF2++CH2F++Si3N4→SiF4↑+NH3↑+HCN+e - +C

[0150] C+H*+CF2*→CF2+CH↑+e -

[0151] While etching the stop layer, a thin C x F yThe thickness of the net deposition layer in the third type of aperture 1313 is about 5 nm, and can reach 1 nm to 10 nm depending on the amount of CH2F2. When the thickness of the cut-off layer of the third type of aperture 1313 is etched to meet the requirements, for example, when it is equivalent to the thickness of the cut-off layer of the second type of aperture 1312, the etching is finished.

[0152] In some embodiments, the second etching gas further comprises O2. The volume of CH2F2 and O2 accounts for 10% to 20% of the total volume of the first etching gas and the second etching gas. The mixed gas of CH2F2 and O2 increases linearly, such as Figure 6 As shown, as an example, the slope k can be 0.6 to 1.2 sccm / min. The volume ratio of CH2F2 to O2 is 0.4:1 to 0.6:1. The amount and proportion of the second etching gas can be adjusted according to the etching conditions of the third type of holes 1313.

[0153] In the present invention, the process gas pressure can also be controlled to be 20mT to 30mT by controlling the opening of the vacuum pump.

[0154] like Figure 7 As shown, the semiconductor structure formed by the method of the present invention includes: a substrate 10, a base layer 11, a stop layer 12, and a dielectric layer 13.

[0155] The base layer 11 is formed on the substrate 10. In this example, the base layer 11 is a laminated structure, formed by stacking a plurality of laminates 110. The side edge of each laminate 110 extends outward relative to the side edge of the upper laminate 110, and the upper surface of the extension portion 113 formed by each laminate 110 is farther from the top outer surface of the dielectric layer than the upper surface of the extension portion 113 formed by the upper laminate 110, so that one side of the base layer 11 has a slope structure gradually extending outward from the top surface toward the substrate.

[0156] The cut-off layer 12 covers the slope structure.

[0157] The dielectric layer 13 is arranged on the cutoff layer 12, and a plurality of first-type holes 1311, second-type holes 1312 and third-type holes 1313 with different aspect ratios are formed on the dielectric layer 13 by the above method, and a carbon-containing deposition layer 132 of a preset thickness is formed on the cutoff layer 12 in each hole.

[0158] In some embodiments, the bottom of the first type of holes 1311 has a carbon-containing deposition layer 132 with a thickness of 600nm to 1000nm; the bottom of the second type of holes 1312 has a carbon-containing deposition layer 132 with a thickness of 35nm to 45nm; the bottom of the third type of holes 1313 has a carbon-containing deposition layer 132 with a thickness of 1nm to 10nm.

[0159] In this example, the plurality of extension portions 113 form a step shape, so that the slope structure of the base layer 11 is stepped. On the slope structure, the stop layer 12 covers the sidewalls of the stack and the extension portions 113. The etching selectivity of the stop layer 12 to the dielectric layer 13 is higher than the etching selectivity of the stack 110 to the dielectric layer 13, so that in the etching process of etching the dielectric layer to form a contact through hole, the stop layer 12 can protect the stack 110.

[0160] The stack 110 includes at least a conductor layer and an insulating layer, and the top layer of the stack structure is a conductor layer. The conductor layer is a polysilicon layer or a conductive metal layer, and the insulating layer is a silicon oxide layer. In some embodiments, the stack 110 includes at least a silicon oxide layer 111 and a polysilicon layer 112, and the top layer of the stack structure is a polysilicon layer 112.

[0161] The beneficial effects of the present invention are described below by comparing specific embodiments with comparative examples.

[0162] Example

[0163] Provide a substrate such as Figure 8 As shown in a, the base wafer includes a base layer 11 disposed on a substrate 10, the base layer 11 having a slope structure formed by a side portion gradually extending outward from the top surface toward the substrate, the slope structure is covered with a cutoff layer 12, and a dielectric layer 13 is disposed on the cutoff layer 12. In this example, the base layer 11 is a stacked structure formed by alternating stacking of conductor layers and insulating layers, wherein the conductor layer is a polysilicon layer 112, the insulating layer is a silicon oxide layer 111; the cutoff layer 12 is a silicon nitride layer; and the dielectric layer 13 is a silicon oxide layer. The top of the base layer 11 and the top of the dielectric layer 13 are in the same plane, and are both covered with a patterned mask layer 14, the mask layer 14 is provided with an opening 141, and the dielectric layer 13 to be etched can be exposed through the opening 141 to perform etching to form a contact through hole 131 (see Figure 8 d).

[0164] The source RF and bias RF are turned on, the source RF frequency is 60MHz, the power is 3000W, the bias RF frequency is 400KHz, and the power is 17000W. The process temperature is 70°C, the opening of the vacuum pump is controlled, the pressure in the chamber is maintained at 30mT, and the first etching gas is introduced, which contains: 37sccm of C4F6, 40sccm of C4F8, 35sccm of O2, 50sccm of N2, 270sccm of CO and 80sccm of Ar. The dielectric layer 928s is etched to form a plurality of first-type holes 1311, second-type holes 1312 and third-type holes 1313 with different aspect ratios, and the third-type holes 1313 expose the cutoff layer 12.

[0165] Continue to introduce the first etching gas at the above flow rate, keep the source RF power unchanged, and keep the pressure and process temperature in the chamber unchanged. Lower the power of the bias RF to 15000w to cause the openings of the first type of holes 1311, the second type of holes 1312 and the third type of holes 1313 to be laterally etched for 60s.

[0166] Continue to introduce the first etching gas at the above flow rate, keep the source RF power, bias RF power, chamber pressure, and process temperature unchanged, then introduce 15sccm of O2 and 20sccm of CH2F2 to etch the cutoff layer exposed by the third type hole 1313. During the etching process, the flow rates of O2 and CH2F2 gradually increase with the etching time until the cutoff layer of the third type hole 1313 is etched to a preset depth. At this time, the total flow rate of O2 is 54sccm, and the flow rate of CH2F2 is 28sccm. The distribution diagram of the residual amount of silicon nitride at different steps in the semiconductor structure obtained by the above treatment with the depth of the contact through hole 131 is shown in FIG. Figure 8 As shown in b, the figure shows the experimental results of this embodiment: by controlling the linear increase of the flow rate of CH2F2 / O2, the silicon nitride residue of the third type of hole 1313 can be minimized, and the silicon nitride residue distribution diagram of the third type of hole 1313 and the second type of hole 1312 can be flattened to obtain a smaller concave range of silicon nitride residue, which greatly increases the process window for the next step of breaking through the silicon nitride process. The morphology after removing the carbon-containing deposition layer is as follows Figure 8 As shown in c, the thickness of the remaining amount of the silicon nitride cut-off layer gradually decreases as the depth of the contact hole increases. After the step of punching through the silicon nitride, the morphology of the semiconductor structure is as follows Figure 8 As shown in d, each contact through hole 131 stops at the surface of the polysilicon layer 112, and neither short circuit nor open circuit occurs.

[0167] Comparative Example

[0168] The same substrate as in the embodiment is provided and processed by a conventional capacitively coupled plasma (CCP) etching method: the first etching gas C4F6 / C4F8 / O2 / Ar / CO / N2 in the embodiment is used as the etching gas throughout the process (the flow rates of each gas are the same as in the embodiment), and the distribution of the remaining amount of silicon nitride with the depth of the contact through hole 131 in the formed step through hole is as shown in FIG. Fig. 9 As shown, the silicon nitride residue is distributed in a U-shape, the silicon nitride residue in the shallowest hole (first type hole 1311) and the deepest hole (third type hole 1313) is relatively thick, while the silicon nitride residue in the hole of intermediate depth (second type hole 1312) is relatively thin. The concave range of the silicon nitride residue distribution is relatively large, resulting in a relatively small process window for the step of punching through the silicon nitride.

[0169] In summary, the present invention can control the thickness of the carbon-containing deposition layer on the cutoff layer in the step through hole by adjusting the power of the bias RF, introducing the second etching gas and controlling the flow rate of the second etching gas, thereby realizing the regulation of the distribution of the remaining amount of the cutoff layer in the holes of different depths after the etching is completed. The holes can be evenly distributed, or the remaining amount of the cutoff layer in the deepest hole (third type hole) can be the least or equivalent to the remaining amount of the cutoff layer in the hole of medium depth (second type hole), thereby effectively expanding the process window for forming the step through hole.

[0170] Furthermore, the present invention also discloses a semiconductor structure, which utilizes the above-mentioned plasma processing method to etch a substrate containing a base layer, a cutoff layer and a dielectric layer to obtain first-type holes, second-type holes and third-type holes with different aspect ratios and different depths, and forms a carbon-containing deposition layer of preset thickness on the cutoff layer at the bottom of the hole to facilitate the next step of etching through the cutoff layer.

[0171] Furthermore, the present invention also discloses a semiconductor processing device, including an etching chamber, inside which an etching process can be performed to process a substrate; a gas supply component, used to introduce reaction gas into the etching chamber; source radio frequency and bias radio frequency, used to generate plasma in the etching chamber; a control unit, used to control the processing method of the above-mentioned semiconductor structure to obtain a suitable cutoff layer state.

[0172] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A method for processing a semiconductor structure, characterized in that: The steps include: A substrate is provided, the substrate comprising a base layer arranged on a substrate, the base layer having a slope structure formed by gradually extending the side from the top surface toward the substrate, the slope structure is covered with a cut-off layer, and a dielectric layer is arranged on the cut-off layer; Turning on the source radio frequency and the bias radio frequency, introducing the first etching gas, etching the dielectric layer, and forming a plurality of first-type holes, second-type holes, and third-type holes with different aspect ratios, until the third-type holes expose the cutoff layer; wherein the third-type holes 深宽比 >Second type hole 深宽比 >First type of hole 深宽比 ; Reducing the power of the bias radio frequency so that the openings of the first type of holes, the second type of holes, and the third type of holes are lateral-etched for a preset time; A second etching gas is introduced to etch the cutoff layer exposed by the third type of holes. During the etching process, the flow rate of the second etching gas increases linearly with the etching time at a slope k until the cutoff layer of the third type of holes is etched to a preset depth.

2. The method for processing a semiconductor structure according to claim 1, wherein: The slope k is 0.6-1.

2.

3. The method for processing a semiconductor structure according to claim 1, wherein: The second etching gas includes C x H y F z Gas, 0≤x<2, y>0, z≥0.

4. The method for processing a semiconductor structure according to claim 3, wherein: The second etching gas includes at least one of CH2F2, CHF3, CH3F and H2.

5. The method for processing a semiconductor structure according to claim 3, wherein: The second etching gas includes CH2F2, wherein the flow rate of CH2F2 is 15 sccm to 30 sccm.

6. The method for processing a semiconductor structure according to claim 5, wherein: The second etching gas also includes O2.

7. The method for processing a semiconductor structure according to claim 6, wherein: The volume ratio of CH2F2 to O2 is 0.4:1 to 0.6:

1.

8. The method for processing a semiconductor structure according to claim 7, wherein: The volume of CH2F2 and O2 accounts for 10% to 20% of the total volume of the first etching gas and the second etching gas.

9. The method for processing a semiconductor structure according to claim 1, wherein: The process gas pressure is 20mT~30mT.

10. The method for processing a semiconductor structure according to claim 1, wherein: When the source radio frequency and the bias radio frequency are turned on, the frequency of the source radio frequency is 60 MHz, and the power is 2500 W to 3000 W; the frequency of the bias radio frequency is 400 Khz, and the power is 15000 W to 18000 W.

11. The method for processing a semiconductor structure according to claim 1, wherein: When the power of the bias radio frequency is reduced, the power of the bias radio frequency is reduced by 1000w to 1500w, so as to form a carbon-containing deposition layer at the bottom of the second type of holes.

12. The method for processing a semiconductor structure according to claim 1, wherein: The first etching gas includes C4F6.

13. The method for processing a semiconductor structure according to claim 12, wherein: The first etching gas also includes at least one of C4F8, O2, C3F8, C5F8 and C6F6.

14. The method for processing a semiconductor structure according to claim 1 or 12, characterized in that: The first etching gas further includes an auxiliary gas, the auxiliary gas includes a rare gas, and the rare gas is at least one of argon (Ar), krypton (Kr) and xenon (Xe).

15. The method for processing a semiconductor structure according to claim 14, wherein: The auxiliary gas is a mixture of Ar, N2 and CO.

16. The method for processing a semiconductor structure according to claim 1, wherein: 19:1≤Third type hole 深宽比 ≤25:1; 14:1≤Second type hole 深宽比 ≤19:1; first type of hole 深宽比 <8:

1.

17. The method for processing a semiconductor structure according to claim 1, wherein: When the cutoff layer of the third type of holes is etched to the preset depth, the bottom of the first type of holes has a carbon-containing deposition layer with a thickness of 600nm to 1000nm; the bottom of the second type of holes has a carbon-containing deposition layer with a thickness of 35nm to 45nm; the bottom of the third type of holes has a carbon-containing deposition layer with a thickness of 1nm to 10nm.

18. The method for processing a semiconductor structure according to claim 1, wherein: The base layer is a stacked structure. In the slope structure, the side edge of each stack extends outward relative to the side edge of the upper stack. The upper surface of the extended portion formed by each stack is farther away from the top outer surface of the dielectric layer than the upper surface of the extended portion formed by the upper stack. Multiple extended portions form a step shape, making the slope structure stepped.

19. The method for processing a semiconductor structure according to claim 1, wherein: The stacked layer at least comprises a conductor layer and an insulating layer, the uppermost layer of the stacked layer structure is a conductor layer, the conductor layer is a polysilicon layer or a conductive metal layer, and the insulating layer is a silicon oxide layer.

20. A semiconductor structure, characterized in that: include: substrate; A base layer, formed on the substrate, the base layer having a slope structure formed by gradually extending the side from the top surface toward the substrate; a cut-off layer, overlying the slope structure; as well as A dielectric layer is arranged on the stop layer, and a plurality of first-type holes, second-type holes and third-type holes with different aspect ratios are formed on the dielectric layer by the method according to any one of claims 1 to 19, and a carbon-containing deposition layer with a preset thickness is formed on the stop layer.

21. The semiconductor structure according to claim 20, wherein: The stop layer includes nitride, and the nitride is selected from at least one of SiN, AlN, GaN, InN, AlN, AlGaN, InGaN and InGaAlN.

22. The semiconductor structure according to claim 20, wherein: The dielectric layer is a silicon oxide layer.

23. A semiconductor processing device, characterized in that: include: an etching chamber for processing a substrate; A gas supply assembly, used for introducing reaction gas; source RF and bias RF; as well as A control unit, used to control the steps of the processing method as described in any one of claims 1-19.

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