Manufacturing method of super junction device

Abstract

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; and injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, wherein the first selected region at least comprises a partial region, close to the transition region, of the terminal region. And forming a trench gate, removing the gate conductive material layer outside the gate trench of the trench gate, and enabling the top surface of the gate conductive material layer in the gate trench to be flat. And forming a well region and performing annealing. And forming a second groove. And growing a P-type doped second epitaxial layer in the second groove, completely removing the second epitaxial layer outside the second groove, and flattening the surface of the second epitaxial layer in the second groove. And a subsequent front process is completed, and a thermal process is set according to the requirement for controlling mutual diffusion of PN impurities of the super junction structure. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled, PN balance of a terminal region can be improved, BVdss of the device is improved, consistency of the BVdss is improved, and EAS capability is improved.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a superjunction (SJ) device. Background Art

[0002] Compared with the existing traditional VDMOS, the existing super junction MOSFET has been widely used in various electronic power fields due to its excellent device characteristics. Due to the special N pillar (N-type pillar) and P pillar (P-type pillar) in the super junction MOSFET structure, it can achieve a high breakdown voltage at a relatively high N-type epitaxial layer (NEPI) epitaxial concentration. Therefore, it has a low on-resistance and high breakdown voltage that exceeds the limit of Si.

[0003] There are two main manufacturing processes for existing super junction MOSFET devices. One is to accumulate mutually spaced P-type regions, namely P-type columns, and N-type regions, namely N-type columns, through multiple epitaxial deposition and photolithography. The other is to form P-type columns on a thick N epitaxial layer through deep trenches and trench filling, thereby forming mutually spaced P-type regions and N-type regions. In the existing deep trench technology, in order to implement the planarization process of deep trench P-type columns well, the P-type column formation process is usually placed before the polysilicon formation process such as the polysilicon formation process of the gate structure. At the same time, the P-type well process is sometimes placed after the P-type column is formed. In this way, the P-type column and the N-type column are formed after the P-type column of the trench is formed, and then go through the gate oxide process and other high-temperature process thermal processes, resulting in the mutual diffusion of P-type column impurities and N-type column impurities, which increases the source-drain on-resistance (Rdson) of the device and affects the chip performance.

[0004] After such setting, the vertical Vds is borne by the electric field established in the body after the PN column, i.e., the P-type column and the N-type column are exhausted. In the terminal area of ​​the chip, it is borne by the surface electric field formed after the PN column is exhausted. In the process of chip design and production, it is generally difficult to adjust the relationship curve between the source-drain breakdown voltage (BVdss) and the PN dose difference (what can actually be controlled is the concentration of P-type impurities) in the lateral terminal area and the BVdss and the P-N dose difference (what can actually be controlled is the concentration of P-type impurities) borne by the vertical electric field in the active area to be consistent. Therefore, the key process window of the device is lost, affecting the consistency of the chip BVdss. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a manufacturing method for a super junction device, which can independently set the thermal process of the trench gate, the thermal process of the well region and the thermal process of the super junction structure, so that the quality of the trench gate and the well region can be guaranteed, and the mutual diffusion of PN impurities in the super junction structure can be effectively controlled, which is conducive to realizing a super junction structure with a smaller step and reducing the on-resistance of the super junction device, while not increasing the process complexity and cost; it can also increase the PN balance of the terminal region, thereby increasing the source-drain breakdown voltage (BVdss) of the terminal region and further increasing the BVdss of the entire device, and can also expand the process window of the P-type doping concentration of the P-type column, improve the BVdss consistency of the device and enhance the single pulse avalanche energy (EAS) capability of the device.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a super junction device, comprising the following steps:

[0007] An N-type doped first epitaxial layer is grown on the surface of the semiconductor substrate.

[0008] The first P-type impurity is implanted into the surface area of ​​the first epitaxial layer of the first selected area by photolithography and ion implantation. The super junction device includes an active area, a transition area and a terminal area. The terminal area surrounds the active area, the transition area is located between the active area and the terminal area, and the first selected area includes at least a partial area of ​​the terminal area close to the transition area.

[0009] A plurality of trench gates are formed in the first epitaxial layer of the active region, the trench gates comprising a gate oxide layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench; each of the trench gates is located in a subsequent corresponding N-type column; the gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer in the gate trench is flat to ensure the implementation of a subsequent second trench formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process.

[0010] A P-type doped well region is formed in the active region and the transition region by photolithography and ion implantation and the well region is annealed. Each trench gate passes through the well region. The thermal process of the annealing of the well region is adjusted to push the well region to a set position and repair ion implantation damage.

[0011] Photolithography and etching are performed to form a plurality of second trenches in the first epitaxial layer, and the first epitaxial layer between the second trenches serves as an N-type column; the second trenches are located in the active area, the transition area and a partial area of ​​the terminal area close to the transition area.

[0012] A P-type doped second epitaxial layer is grown in the second trench, the second epitaxial layer outside the second trench is completely removed and the surface of the second epitaxial layer in the second trench is flattened, a P-type column is formed by the second epitaxial layer filled in the second trench, and a super junction structure is formed by alternating arrangement of the N-type column and the P-type column; outside the well region, the first P-type impurity is used to compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation.

[0013] A subsequent front process after the super junction structure is completed, wherein a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super junction structure so that the on-resistance of the super junction device meets the requirement;

[0014] Complete the backside process of super junction devices.

[0015] A further improvement is that the material of the semiconductor substrate includes silicon, the material of the first epitaxial layer includes silicon, and the material of the second epitaxial layer includes silicon.

[0016] A further improvement is that the steps of forming the trench gate include:

[0017] A first dielectric layer is formed on a top surface of the first epitaxial layer.

[0018] The formation area of ​​the gate trench is defined by photolithography.

[0019] The first dielectric layer and the first epitaxial layer in the formation region of the gate trench are sequentially etched to form the gate trench.

[0020] The gate oxide layer is formed by a thermal oxidation process.

[0021] The gate conductive material layer is formed.

[0022] A first chemical mechanical polishing process is performed to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer within the gate trench.

[0023] A further improvement is that the gate conductive material layer is made of polysilicon.

[0024] A further improvement is that before or after the first chemical mechanical polishing process, the method further comprises:

[0025] Perform a rapid thermal oxidation or a rapid thermal annealing.

[0026] A further improvement is that the maximum annealing temperature of the well region reaches above 1100° C. and the annealing time reaches above 30 minutes.

[0027] A further improvement is that before performing the photolithography process of the second trench, the method further includes: forming a hard mask layer.

[0028] In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

[0029] A further improvement is that the hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence.

[0030] After the etching of the second trench is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench are removed, and then the second epitaxial layer is grown.

[0031] Afterwards, a second chemical mechanical polishing process is used to planarize the second epitaxial layer, so as to completely remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

[0032] A further improvement is that the subsequent front surface process includes:

[0033] Photolithography and ion implantation are performed to form an N-type heavily doped source region, wherein the source region and the side surface of the corresponding gate trench are self-aligned.

[0034] The source region is annealed and activated. The annealing of the source region is performed in a furnace tube at a temperature below 950° C. or in a rapid thermal annealing.

[0035] A further improvement is that the subsequent front surface process further includes:

[0036] An interlayer film is formed, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer.

[0037] A contact hole opening is formed through the interlayer film.

[0038] A P-type heavily doped contact region is formed at the bottom of the contact hole opening.

[0039] A metal layer is filled in the contact hole opening to form a contact hole.

[0040] A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

[0041] A further improvement is that it also includes performing a front passivation protection process, the front passivation protection process including:

[0042] A dielectric protection layer is formed; the dielectric protection layer is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.

[0043] The dielectric protection layer is patterned by photolithography and dry etching to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0044] A further improvement is that it also includes performing a front passivation protection process, the front passivation protection process including:

[0045] A polyimide layer is formed.

[0046] The polyimide layer is patterned by photolithography and development to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0047] The polyimide layer is baked.

[0048] A further improvement is that the metal layer forming the contact hole comprises:

[0049] A barrier layer is formed, wherein the barrier layer is formed on the inner surface of the contact hole opening.

[0050] A tungsten layer is formed, the tungsten layer filling the contact hole opening.

[0051] The barrier layer and the tungsten layer also extend onto the surface of the interlayer film outside the contact hole opening.

[0052] The front metal layer is formed on the surface of the tungsten layer. When the front metal layer is patterned, the tungsten layer and the barrier layer in the front metal layer removal area are also removed, and the tungsten layer and the barrier layer are also retained in the front metal layer retention area.

[0053] Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before forming the front metal layer, and then a second barrier layer and the front metal layer are formed or the front metal layer is directly formed.

[0054] A further improvement is that the backside process includes:

[0055] The semiconductor substrate is back-thinned.

[0056] A heavily N-type doped drain region is formed; the semiconductor substrate is heavily N-type doped, and the drain region is directly composed of the thinned semiconductor substrate; or, the drain region is composed of a backside injection region in which the backside of the semiconductor substrate is heavily P-type doped.

[0057] A back metal layer is formed and a drain electrode is formed from the back metal layer.

[0058] A further improvement is that the setting of the thermal process corresponding to the subsequent front process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

[0059] A further improvement is that the second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant.

[0060] Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the second epitaxial layer is constant, and the doping concentration of the first epitaxial layer is set according to the side inclination angle and the depth of the second trench, and the doping concentration of the first epitaxial layer at the corresponding depth gradually increases from the bottom to the top of the second trench, so that the charge balance of each adjacent N-type column and the corresponding P-type column at each longitudinal position meets the requirements.

[0061] Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side inclination angle and depth of the second trench, and the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases from the bottom to the top of the second trench.

[0062] A further improvement is that after the first chemical mechanical polishing process, the process further includes making the top surface of the gate conductive material layer in the gate trench below the top surface of the first epitaxial layer outside the gate trench. to facilitate the subsequent formation of the second groove.

[0063] A further improvement is that, while forming the source region, a heavily N-type doped cutoff region is also formed in the surface region of the first epitaxial layer at the outer edge of the terminal region.

[0064] A further improvement is that the inner edge of the first selected area is located between the inner edge and the outer edge of the transition zone.

[0065] The outer edge of the first selected area is located inside the outer edge of the outermost P-type column.

[0066] Alternatively, the outer edge of the first selected area is flush with the outer edge of the outermost P-type column.

[0067] Alternatively, the outer edge of the first selected area is located outside the outer edge of the outermost P-type column, and there is a first distance between the outer edge of the first selected area and the outer edge of the terminal area, and the first distance is greater than the maximum distance at which penetration occurs between the outer edge of the first selected area and the outer edge of the terminal area.

[0068] A further improvement is that the first selected area is an open area of ​​a photoresist pattern formed by photolithography of the first P-type impurity.

[0069] Between the inner edge and the outer edge of the first selected area, the first selected area is fully open.

[0070] Alternatively, between the inner edge and the outer edge of the first selected region, the subsequent formation region of the P-type column is covered, and the outer region of the P-type column is opened.

[0071] A further improvement is that the implanted impurities of the first P-type impurity ion implantation include boron, and the implantation energy is 50keV-2MeV.

[0072] The implantation dose of the first P-type impurity ion implantation ensures that after the backside process is completed, the impurity concentration of the first P-type impurity is not higher than 20% of the N-type impurity concentration of the N-type region outside the P-type column, and the net doping of the N-type region outside the P-type column remains N-type doping.

[0073] A further improvement is that after the ion implantation of the first P-type impurity is completed, the method further comprises:

[0074] The first P-type impurity is annealed and activated, and the maximum value of the annealing temperature of the first P-type impurity is greater than 1100° C., and the minimum value of the annealing time is 60 minutes to 180 minutes.

[0075] The present invention makes special arrangements for the process flow of the super junction device, mainly placing the trench gate and well region forming processes with high requirements on the thermal process before the super junction structure forming process, and setting the flatness of the gate conductive material layer in the gate trench, including removing all the gate conductive material layers outside the gate trench and making the top surface of the gate conductive material layer in the gate trench flat, so as to ensure that the subsequent etching and filling processes of the second trench of the super junction structure are well implemented; since the trench gate and well region forming processes are placed before the super junction structure forming process, it is possible to avoid that the trench gate and well region forming processes with high requirements on the thermal process have an adverse effect on the super junction structure, so that the trench gate and the well region can adopt a higher thermal process according to their own needs, so that the quality of the trench gate and the well region is well guaranteed; at the same time, the present invention also controls the thermal process after the super junction structure, so as to ensure that the mutual diffusion of PN impurities in the super junction structure meets the requirements, so that the on-resistance of the super junction device meets the requirements. Since the mutual diffusion of PN impurities in the super junction structure can be well controlled, the step size of the super junction structure can be further reduced, thereby further reducing the on-resistance of the super junction device and improving the performance of the super junction device.

[0076] Although the present invention places the process of forming the trench gate and the well region before the process of forming the super junction structure, the present invention controls the flatness of the gate conductive material layer in the gate trench, which can ensure that the super junction structure can still be easily formed under the condition of forming the trench gate and the well region. Therefore, the present invention also has the advantage of not increasing the process complexity and cost.

[0077] Therefore, the present invention can independently set the thermal process of the trench gate, the thermal process of the well region and the thermal process of the super junction structure, so that the quality of the trench gate and the well region can be guaranteed while the mutual diffusion of PN impurities in the super junction structure can be effectively controlled, which is conducive to realizing a super junction structure with a smaller step and reducing the on-resistance of the super junction device, while not increasing the process complexity and cost.

[0078] The present invention also adds a first P-type impurity in the terminal region. Outside the well region, the first P-type impurity can compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation, so that the PN balance of the terminal region can be increased, that is, the charge matching between the P-type column and the N-type column, thereby increasing the source-drain breakdown voltage (BVdss) of the terminal region and further increasing the BVdss of the entire device, and can also expand the process window of the P-type doping concentration of the P-type column, improve the BVdss consistency of the device and enhance the EAS capability of the device. For example, by setting the first P-type impurity, the BVdss of the terminal region can be made greater than the BVdss of the active region, so The BVdss of the entire device is determined by the BVdss of the active area. The P-type doping concentration of the P-type column does not need to be used to adjust the difference in PN matching between the terminal area and the active area. The P-type doping concentration of the P-type column only needs to meet the BVdss requirement of the active area. Therefore, the process window of the P-type doping concentration of the P-type column is expanded, and the BVdss consistency of the device is increased. After the process window of the P-type doping concentration of the P-type column is expanded, the adjustment range of the P-type doping concentration of the P-type column will be increased, which is more conducive to improving the performance of the super junction device. For example, by increasing the P-type doping concentration of the P-type column, the EAS performance of the device can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0080] Figure 1 is a flow chart of a method for manufacturing a super junction device according to a first embodiment of the present invention;

[0081] Figure 2A-2L is a schematic diagram of the device structure in each step of the method for manufacturing a super junction device according to the first embodiment of the present invention;

[0082] Figure 3 is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the second embodiment of the present invention;

[0083] Figure 4 is a schematic diagram of the device structure of a super junction device formed by a method for manufacturing a super junction device according to a third embodiment of the present invention;

[0084] Figure 5 It is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0085] like Figure 1 FIG. 1 is a flow chart of a method for manufacturing a super junction device according to a first embodiment of the present invention; Figures 2A to 2L , which is a schematic diagram of the device structure in each step of the method for manufacturing a super junction device according to the first embodiment of the present invention; the method for manufacturing a super junction device according to the embodiment of the present invention comprises the following steps:

[0086] Step S101: Figure 2A As shown, an N-type doped first epitaxial layer 102 is grown on the surface of a semiconductor substrate 101 .

[0087] In the first embodiment of the present invention, the material of the semiconductor substrate 101 includes silicon, the material of the first epitaxial layer 102 includes silicon, and the material of the second epitaxial layer 108 formed subsequently includes silicon.

[0088] Step S102: Figure 2A As shown, the first P-type impurity 204 is implanted into the surface area of ​​the first epitaxial layer 102 of the first selected area 303 by photolithography and ion implantation. The super junction device includes an active area 201, a transition area 202 and a terminal area 203. The terminal area 203 surrounds the active area 201. The transition area 202 is located between the active area 201 and the terminal area 203. The first selected area 303 includes at least a portion of the terminal area 203 close to the transition area 202.

[0089] Figure 2A In the embodiment, the area of ​​the semiconductor substrate 101 is larger. Figure 2A On the cross section, curve AA indicates that the active area 201, the transition area 202 and the terminal area 203 are continuously distributed. The structure in the area omitted by curve AA can be referred to Figure 2A The structure shown in FIG. 1 is shown by the arrow line marked with 302.

[0090] In the first embodiment of the present invention, the first selected region 303 is an open region of a photoresist pattern formed by photolithography of the first P-type impurity 204. Before photolithography, an injection protection film 301 composed of a dielectric layer is formed. After photolithography, the injection protection film 301 is etched using the photoresist pattern as a mask, so that the first selected region 303 is transferred to the open region of the injection protection film 301.

[0091] Afterwards, ion implantation is performed using the implantation protection film 301 as a mask to implant the first P-type impurity 204 into the surface region of the first epitaxial layer 101 corresponding to the first selected region 303 . Figure 2A In the figure, the injected first P-type impurity 204 is represented by a hollow dot, indicating that the first P-type impurity 204 is injected into the surface region of the corresponding first epitaxial layer 101, but the net doping concentration of the surface region of the first epitaxial layer 101 injected with the first P-type impurity 204 is still N-type doping.

[0092] In the first embodiment of the present invention, the first selected region 303 is completely opened between the inner edge and the outer edge of the first selected region 303. In other embodiments, the subsequent formation region of the P-type column is covered between the inner edge and the outer edge of the first selected region 303, and the outer region of the P-type column is opened, that is, the first P-type impurity 204 is only injected into the surface region of the N-type column or the surface region of the first epitaxial layer 101 extending outside the super junction structure in the terminal region.

[0093] In the first embodiment of the present invention, the outer edge of the first selected area 303 is flush with the outer edge of the outermost P-type column.

[0094] The inner edge of the first selected region 303 is located at the inner edge of the transition region 202 , that is, the entire transition region 202 is implanted with the first P-type impurities 204 .

[0095] In some embodiments, the implanted impurities of the ion implantation of the first P-type impurity 204 include boron, and the implantation energy is 50 keV to 2 MeV.

[0096] The ion implantation dose of the first P-type impurity 204 ensures that after the subsequent back-side process is completed, that is, after the first P-type impurity 204 has undergone all thermal processes, the impurity concentration of the first P-type impurity 204 is not higher than 20% of the N-type impurity concentration of the N-type region outside the P-type column, and the net doping of the N-type region outside the P-type column remains N-type doping.

[0097] In some embodiments, after the ion implantation of the first P-type impurity 204 is completed, the following steps are further included:

[0098] The first P-type impurity 204 is annealed and activated, and the maximum annealing temperature of the first P-type impurity 204 is above 1100° C., and the minimum annealing time is 60 minutes to 180 minutes. In some preferred examples, the process parameters of the annealing of the first P-type impurity 204 are: a temperature of 1100° C. and a time of 60 minutes to 180 minutes or a temperature of 1175° C. and a time of 60 minutes to 180 minutes.

[0099] Step S103: Figure 2DAs shown, a plurality of trench gates are formed in the first epitaxial layer 102 of the active region 201, and the trench gates include a gate oxide layer 104 formed on the inner surface of the gate trench 103 and a gate conductive material layer 105 filled in the gate trench 103; each trench gate is located in a subsequent corresponding N-type column; the gate conductive material layer 105 outside the gate trench 103 is removed, and the top surface of the gate conductive material layer 105 in the gate trench 103 is flat to ensure the realization of the subsequent second trench 107 formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process.

[0100] In the first embodiment of the present invention, the steps of forming the trench gate include:

[0101] like Figure 2B As shown, a first dielectric layer 304 is formed on the top surface of the first epitaxial layer 102. The material of the first dielectric layer 304 is generally silicon oxide.

[0102] like Figure 2B As shown, photolithography defines the formation area of ​​the gate trench 103. The photolithography will form a photoresist pattern 305, and the open area of ​​the photoresist pattern 305 is the formation area of ​​the gate trench 103.

[0103] like Figure 2C As shown, the first dielectric layer 304 and the first epitaxial layer 102 in the formation region of the gate trench 103 are sequentially etched to form the gate trench 103. The photoresist pattern 305 will be removed before or after etching the first epitaxial layer 102 or consumed during the etching process.

[0104] like Figure 2D As shown, a thermal oxidation process is used to form the gate oxide layer 104. The thermal oxidation process has a high temperature thermal process. Since the thermal process corresponding to the thermal oxidation process is not affected by the super junction structure formed subsequently, the parameters of the thermal oxidation process can be set according to the need to form a gate oxide layer 104 with good quality, and finally the quality of the trench gate is guaranteed.

[0105] like Figure 2D As shown, a gate conductive material layer 105 is formed.

[0106] In the first embodiment of the present invention, the material of the gate conductive material layer 105 includes polysilicon.

[0107] like Figure 2D As shown, a first chemical mechanical polishing process is performed to planarize the gate conductive material layer 105 to remove the gate conductive material layer 105 on the top surface of the first epitaxial layer 102 outside the gate trench 103 and to planarize the top surface of the gate conductive material layer 105 in the gate trench 103 .

[0108] In the first embodiment of the present invention, after the first chemical mechanical polishing process, the top surface of the gate conductive material layer 105 in the gate trench 103 is located below the top surface of the first epitaxial layer 102 outside the gate trench 103. to facilitate the subsequent formation of the second trench 107, that is, to facilitate the subsequent process of the second trench 107 to achieve its goal.

[0109] In some embodiments, before or after the first chemical mechanical polishing process, the process further includes: performing a rapid thermal oxidation or performing a rapid thermal annealing.

[0110] like Figure 2D As shown, after the trench gate is formed, a protective film 205 is formed on the surface of the first epitaxial layer 102. The protective film 205 is formed by thinning the first dielectric layer 304, or by removing the first dielectric layer 304 and then oxidizing it. The protective film 205 can serve as a protective layer for subsequent ion implantation.

[0111] Step S104: Figure 2E As shown, a P-type doped well region 106 is formed in the active region 201 and the transition region 202 by photolithography and ion implantation, and the well region 106 is annealed, each trench gate passes through the well region 106, and the thermal process of the annealing of the well region 106 is adjusted to push the well region 106 to the set position and repair the ion implantation damage. The well region located in the transition region 202 is separately indicated by a mark 106a.

[0112] In the first embodiment of the present invention, the maximum annealing temperature of the well region 106 is above 1100° C., and the annealing time is above 30 minutes.

[0113] Step S105: Figure 2F As shown, photolithography and etching are performed to form a plurality of second trenches 107 in the first epitaxial layer 102 , and the first epitaxial layer 102 between the second trenches 107 serves as an N-type column; the second trenches 107 are located in a portion of the active region 201 , the transition region 202 and the terminal region 203 close to the transition region 202 .

[0114] In the first embodiment of the present invention, before performing the photolithography process of the second trench 107, the method further includes: forming a hard mask layer. The hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence.

[0115] In the etching process of the second trench 107 , the hard mask layer is etched first, and then the first epitaxial layer 102 is etched.

[0116] After the etching of the second trench 107 is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench 107 are removed, and then the subsequent growth of the second epitaxial layer 108 is performed.

[0117] Step S106: Figure 2F As shown, a P-type doped second epitaxial layer 108 is grown in the second trench 107, the second epitaxial layer 108 outside the second trench 107 is completely removed and the surface of the second epitaxial layer 108 in the second trench 107 is flattened, the second epitaxial layer 108 filled in the second trench 107 forms a P-type column, and the N-type column and the P-type column are alternately arranged to form a super junction structure; outside the well region 106, the first P-type impurity 204 is used to compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation.

[0118] The process then includes: planarizing the second epitaxial layer 108 by a second chemical mechanical polishing process, so as to completely remove the second epitaxial layer 108 outside the second trench 107 and make the surface of the second epitaxial layer 108 in the second trench 107 flat.

[0119] The N-type pillars and P-type pillars of the super junction structure achieve charge matching at each longitudinal position.

[0120] In some embodiments, the second trench 107 has a side vertical structure, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is constant.

[0121] In some embodiments, the second trench 107 may have a side inclined structure with a wide top and a narrow bottom, the doping concentration of the second epitaxial layer 108 may be constant, and the doping concentration of the first epitaxial layer 102 may be set according to the side inclination angle and the depth of the second trench 107. From the bottom to the top of the second trench 107, the doping concentration of the first epitaxial layer 102 at the corresponding depth may gradually increase so that the charge balance of adjacent N-type columns and corresponding P-type columns at each longitudinal position may meet the requirements.

[0122] In some embodiments, the second trench 107 may have a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is set according to the side inclination angle and the depth of the second trench 107, and the doping concentration of the second epitaxial layer 108 at the corresponding depth gradually decreases from the bottom to the top of the second trench 107.

[0123] Step S107 , after the super junction structure is completed, a subsequent front process is performed. In the subsequent front process, a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super junction structure so that the on-resistance of the super junction device meets the requirement.

[0124] In the first embodiment of the present invention, the setting of the thermal process corresponding to the subsequent front process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

[0125] In the first embodiment of the present invention, the subsequent front surface process includes:

[0126] like Figure 2G As shown, photolithography and ion implantation are performed to form an N-type heavily doped source region 109, and the source region 109 is self-aligned with the side surface of the corresponding gate trench 103. Before the formation of the source region 109, a protection film 206 needs to be formed.

[0127] In the first embodiment of the present invention, while forming the source region 109 , the process also includes forming an N-type heavily doped cutoff region 109 a in the surface region of the first epitaxial layer 102 at the outer edge of the termination region 203 .

[0128] The source region 109 is annealed and activated. The annealing of the source region 109 is performed in a furnace at a temperature below 950° C. or in a rapid thermal annealing.

[0129] like Figure 2H As shown, an interlayer film 110 is formed, and the interlayer film 110 is formed by stacking an undoped silicon dioxide layer and a BPSG layer.

[0130] like Figure 2G As shown, a contact hole opening 111 is formed through the interlayer film 110 . The contact hole opening 111 also penetrates into the first epitaxial layer 102 and passes through the surface source region 109 and contacts the well region 106 .

[0131] A contact hole opening 111 is also formed on the top of the stop region 109 a , and the bottom of the contact hole opening 111 also passes through the stop layer 109 a and contacts the first epitaxial layer 102 at the bottom.

[0132] like Fig.2I As shown, a P-type heavily doped contact region 207 , ie, a contact hole implantation (CT IMP), is formed at the bottom of the contact hole opening 111 .

[0133] A metal layer is filled in the contact hole opening 111 to form a contact hole.

[0134] The metal layers forming the contact holes include:

[0135] like Fig.2I As shown, a barrier layer 112 is formed, and the barrier layer 112 is formed on the inner surface of the contact hole opening 111 .

[0136] In some embodiments, the material of the barrier layer 112 includes a Ti layer and a TiN layer stacked in sequence.

[0137] like Figure 2J As shown, a tungsten layer 113 is formed, and the tungsten layer 113 fills the contact hole opening 111 .

[0138] The barrier layer 112 and the tungsten layer 113 also extend onto the surface of the interlayer film 110 outside the contact hole opening 111 .

[0139] like Figure 2J As shown, a front metal layer 114 is formed. The front metal layer 114 is patterned and etched to form a source and a gate. The source region 109 and the well region 106 are connected to the source through corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer 105 at the trench gate lead-out end. In some embodiments, the material of the front metal layer 114 includes AlCu.

[0140] In the first embodiment of the present invention, the front metal layer 114 is formed on the surface of the tungsten layer 113. When the front metal layer 114 is patterned, the tungsten layer 113 and the barrier layer 112 in the removal area of ​​the front metal layer 114 are also removed, and the tungsten layer 113 and the barrier layer 112 are also retained in the retention area of ​​the front metal layer 114.

[0141] In other embodiments, the barrier layer 112 and the tungsten layer 113 outside the contact hole opening 111 can be removed before forming the front metal layer 114, and then the second barrier layer and the front metal layer 114 can be formed. In some embodiments, the material of the second barrier layer includes a Ti layer and a TiN layer stacked in sequence. It is also possible to directly form the front metal layer 114 without forming the second barrier layer.

[0142] Figure 2J In the figure, the patterned front metal layer 114 includes: a source electrode corresponding to the mark 114a, a gate bus corresponding to the mark 114b, a transition region field plate corresponding to the mark 114c, a plurality of terminal region field plates corresponding to the marks 114d1, 114d2 to 114dx, a metal connected to the drain electrode corresponding to the mark 114e, and the bottom of the metal 114e is connected to the cut-off region 109a. Among them, the source electrode 114a and the gate bus 114b need to be separated, and the gate bus 114b and the transition region field plate 114c are an integrated structure or a separated structure; the terminal region field plates 114d1, 114d2 to 114dx are separated structures, and the number of the terminal region field plates 114d1, 114d2 to 114dx can be set according to needs, and the setting of the terminal region field plates 114d1, 114d2 to 114dx can also be cancelled.

[0143] In the first embodiment of the present invention, a front passivation protection process is further included. The front passivation protection process further includes:

[0144] like Figure 2K As shown, a dielectric protection layer 115 is formed; the dielectric protection layer 115 is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.

[0145] Photolithography and dry etching are performed to pattern the dielectric protection layer 115 to open the lead-out region of the source and the lead-out region of the gate.

[0146] like Figure 2L As shown, the front passivation protection process also includes:

[0147] A polyimide layer 116 is formed.

[0148] Photolithography and development are performed to pattern the polyimide layer 116 to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0149] The polyimide layer 116 is baked.

[0150] In the first embodiment of the present invention, the dielectric protection layer 115 and the polyimide layer 116 are stacked simultaneously.

[0151] In some embodiments, only the dielectric protection layer 115 can be formed, and the polyimide layer 116 can be omitted.

[0152] In some embodiments, the dielectric protection layer 115 can be omitted and only the polyimide layer 116 can be formed.

[0153] Step S108: Figure 2L As shown, the back side process of the super junction device is completed.

[0154] In the first embodiment of the present invention, the back surface process includes:

[0155] The semiconductor substrate 101 is backside thinned.

[0156] Forming an N-type heavily doped drain region. In the first embodiment of the present invention, the semiconductor substrate 101 is heavily doped with N-type, and the drain region is directly composed of the thinned semiconductor substrate 101. In this case, the drain region does not need to be further activated. In other embodiments, the drain region can also be composed of a back injection region in which the semiconductor substrate 101 is heavily doped with P-type on the back side, and the drain region needs to be activated later.

[0157] A back metal layer 117 is formed and a drain electrode is formed by the back metal layer 117. In some embodiments, the back metal layer 117 includes TiNiAg.

[0158] The first embodiment of the present invention makes a special arrangement for the process flow of the super junction device, mainly placing the formation process of the trench gate and the well region 106, which have high requirements on the thermal process, before the formation process of the super junction structure, and setting the flatness of the gate conductive material layer 105 in the gate trench 103, including removing all the gate conductive material layer 105 outside the gate trench 103 and making the top surface of the gate conductive material layer 105 in the gate trench 103 flat, so as to ensure that the subsequent etching and filling process of the second trench 107 of the super junction structure is well implemented; because the trench gate The formation process of the well region 106 is placed before the formation process of the super junction structure, so that the formation process of the trench gate and the well region 106 with high requirements for the thermal process can be avoided from having an adverse effect on the super junction structure. In this way, the trench gate and the well region 106 can adopt a high thermal process according to their own needs, so that the quality of the trench gate and the well region 106 is well guaranteed; at the same time, the first embodiment of the present invention also controls the thermal process after the super junction structure, which can ensure that the PN impurities of the super junction structure diffuse mutually to meet the requirements, so that the on-resistance of the super junction device can meet the requirements. Since the PN impurities of the super junction structure diffuse mutually to be well controlled, the stepping of the super junction structure can be further reduced, so that the on-resistance of the super junction device can be further reduced and the performance of the super junction device can be improved.

[0159] Although the first embodiment of the present invention places the process of forming the trench gate and the well region 106 before the process of forming the super junction structure, the first embodiment of the present invention controls the flatness of the gate conductive material layer 105 in the gate trench 103, which can ensure that the super junction structure can still be easily formed under the condition of forming the trench gate and the well region 106. Therefore, the first embodiment of the present invention also has the advantage of not increasing the process complexity and cost.

[0160] Therefore, the first embodiment of the present invention can independently set the thermal process of the trench gate, the thermal process of the well region 106 and the thermal process of the super junction structure, so that the quality of the trench gate and the well region 106 can be guaranteed while the mutual diffusion of PN impurities in the super junction structure can be effectively controlled, which is conducive to realizing a super junction structure with a smaller step and reducing the on-resistance of the super junction device, while not increasing the process complexity and cost.

[0161] The first embodiment of the present invention further adds a first P-type impurity 204 in the terminal region 203. Outside the well region 106, the first P-type impurity 204 can compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation, thereby increasing the PN balance of the terminal region 203, that is, the charge matching between the P-type column and the N-type column, thereby increasing the source-drain breakdown voltage (BVdss) of the terminal region 203 and further increasing the BVdss of the entire device, and further expanding the process window of the P-type doping concentration of the P-type column, improving the BVdss consistency of the device and enhancing the EAS capability of the device. For example, by setting the first P-type impurity 204, the BVdss of the terminal region 203 can be made greater than that of the active region 2 01, so the BVdss of the entire device is determined by the BVdss of the active area 201, the P-type doping concentration of the P-type column does not need to be used to adjust the difference in PN matching between the terminal area 203 and the active area 201, the P-type doping concentration of the P-type column only needs to meet the BVdss requirement of the active area 201, so the process window of the P-type doping concentration of the P-type column is expanded, and the BVdss consistency of the device is increased; after the process window of the P-type doping concentration of the P-type column is expanded, the adjustment range of the P-type doping concentration of the P-type column will be increased, which is more conducive to improving the performance of the super junction device. For example, by increasing the P-type doping concentration of the P-type column, the EAS performance of the device can be further improved.

[0162] like Figure 3 , which is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the second embodiment of the present invention; the difference from the method for manufacturing a super junction device according to the first embodiment of the present invention is that in the method for manufacturing a super junction device according to the second embodiment of the present invention:

[0163] The outer edge of the first selected region 303 is located outside the outer edge of the outermost P-type column, and there is a first distance between the outer edge of the first selected region 303 and the outer edge of the terminal region 203, and the first distance is greater than the maximum distance between the outer edge of the first selected region 303 and the outer edge of the terminal region 203 at which punch-through occurs. In the present application, the outer edge of the terminal region 203 refers to the inner edge of the cut-off region 109a; the maximum distance between the outer edge of the first selected region 303 and the outer edge of the terminal region 203 at which punch-through occurs refers to the maximum distance less than or equal to which the first P-type impurity 204 will be punched through with the N+ doped cut-off region 109a or the P+ doped contact region 207 corresponding to the bottom of the cut-off region 109a. In some embodiments, the first distance is greater than 10 microns.

[0164] like Figure 4 , which is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the third embodiment of the present invention; the difference from the method for manufacturing a super junction device according to the first embodiment of the present invention is that in the method for manufacturing a super junction device according to the third embodiment of the present invention:

[0165] The outer edge of the first selected region 303 is located inside the outer edge of the outermost P-type pillar.

[0166] like Figure 5 , which is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the fourth embodiment of the present invention; the difference from the method for manufacturing a super junction device according to the second embodiment of the present invention is that in the method for manufacturing a super junction device according to the fourth embodiment of the present invention:

[0167] The inner edge of the first selected region 303 is located at the outer edge of the transition region 202 , that is, the first P-type impurities 204 are not implanted into the entire transition region 202 .

[0168] In other embodiments, the inner edge of the first selected region 303 is located in other regions between the inner edge and the outer edge of the transition region 202 , that is, the first P-type impurities 204 are formed only in a portion of the transition region 202 .

[0169] In the first embodiment of the present invention, taking N-type MOSFET as an example, the thermal process after the formation of the P-type column can be greatly reduced, thereby further reducing the on-resistance of the device. The first embodiment of the present invention also adds a P-type ion implantation region in the terminal area to expand the process window of BVdss and P-type impurity concentration. By setting the terminal injection, that is, the first P-type impurity 204 injection, the absolute value of the terminal BVdss can also be adjusted. For example, when the BVdss of the terminal is higher than the BVdss of the active area, the BVdss of the device can be increased, and the consistency of the device can be improved, thereby enhancing the EAS capability.

[0170] The following takes a 600V trench gate super junction N-type MOSFET as an example to further illustrate the first embodiment of the present invention in combination with corresponding parameters:

[0171] In step S101 , the semiconductor substrate 101 is a low-resistivity N-type substrate. For example, the resistivity of the semiconductor substrate 101 is less than 0.003 ohm.cm.

[0172] The thickness of the first epitaxial layer 102 is 45 microns to 50 microns. The design of the resistivity of the first epitaxial layer 102 is related to the stepping of the subsequent P-type column and N-type column, and can be designed by simulation using computer-aided software. For example, the stepping of the PN column is set to 5 microns, and the resistivity is 0.5 ohm.cm.

[0173] In step S102, the protective film 301 is injected into the

[0174] The implanted impurity of the first P-type impurity 204 is B, the implantation energy is 50keV~2MeV, and the dose is set according to the impurity concentration of the first epitaxial layer 102 of the device. Generally, the highest impurity concentration of B after all subsequent processes is set not to exceed 20% of the N-type impurity concentration. In some examples, the process parameters of the first P-type impurity 204 ion implantation are B600keV8E11 atoms / cm -2 , B60keV8E11 atoms / cm -2 Indicates that the injected impurity is B, the injection capacity is 60keV, and the injection dose is 8E11 atoms / cm -2 After that, a high temperature annealing process is performed, for example, 1100°C for 60-180 minutes, or 1175°C for 60-180 minutes. 1100°C for 60-180 minutes means that the annealing temperature is 1100°C and the time is 60 minutes to 180 minutes.

[0175] In step S103 , the thickness of the first dielectric layer 201 is 0.5-2 microns.

[0176] The width and depth of the gate trench 103 can be set according to the device performance, for example, the width of the gate trench 103 is set to 0.8-1.5 microns, and the depth is set to 2.5-4 microns. The gate trench 103 is not formed in the transition region 202 and the terminal region 203. Afterwards, the first dielectric layer 304 as a hard mask is completely removed, generally by wet etching.

[0177] The thickness of the gate oxide layer 104 is set to be 500 angstroms to 1500 angstroms;

[0178] The resistivity of the polysilicon of the gate conductive material layer 105 is generally set at about 10 ohm.cm to 30 ohm.cm. Before or after the polysilicon planarization of the gate conductive material layer 105 is completed, a high temperature RTO or high temperature RTA can be performed to improve the leakage between the gate and the drain of the product.

[0179] In step S104, the ions of the well region 106 are implanted in the active region 201 and the transition region 202, and the terminal region 203 is not implanted. The impurity of the ion implantation in the well region 106 is generally B, the implantation energy is 100 KeV, and the implantation dose is designed according to the device threshold voltage requirement, for example, the implantation dose is 1E13 atoms / cm 2The ion implantation of the well region 106 can also be achieved by using two B implantations with different energies, so that different P-type wells, namely the well region 106, can be constructed, and the performance parameters of the device including the threshold voltage and EAS can be adjusted. After the ion implantation of the well region 106 is formed, a high-temperature annealing can be performed, such as annealing at 1100°C for 30 minutes or at a higher temperature. 1100°C for 30 minutes means a thermal annealing at a temperature of 1100°C for 30 minutes. This can push the P-type well to the set position on the one hand, and can also repair some damage caused during the ion implantation process.

[0180] Before B is implanted in the well region 106, the dielectric film on the surface of the silicon, i.e., the semiconductor substrate 101, and the first epitaxial layer 102 is generally thinned to about 200 angstroms to serve as a protective film 205 during ion implantation. This oxide film, i.e., the protective film 205, can be the film left after the previous polysilicon CMP, i.e., the first chemical mechanical polishing, obtained by dry or wet etching. It can also be a thermal oxide film or CVD film generated after all the polysilicon CMP films are removed. The latter has the function of increasing the consistency of the ion implantation protective film and improving the consistency of device parameters, especially the threshold voltage.

[0181] In step S105, the thickness of the bottom silicon dioxide layer is The thickness of the middle silicon nitride layer is The thickness of the top silicon dioxide layer is 2 to 5 microns.

[0182] The width of the deep trench, namely the second trench 107, is 2.5 microns, the size of the N region between adjacent trenches, namely the spacing between the second trenches 107, is 2.5 microns, and the depth of the second trench 107 is 40-42 microns, which can be set according to the BVdss requirement of the device.

[0183] After etching the second trench 107, the top SIO2 and SIN of the hard mask, i.e., the top silicon dioxide layer and the middle silicon nitride layer, are completely removed, and the bottom SIO2, i.e., the bottom silicon dioxide layer, is kept as a protective layer on the Si surface. The second trench 107 is then completely filled by P-type epitaxial deposition, and then all the Si on the surface is removed by chemical mechanical polishing.

[0184] Here, the P-type column and the N-type column are adjacent, and the same stepping, the same P-type column width, and the same N-type column width can be set in the active area 201, the transition area 202, and the terminal area 203. For example, the stepping is set to 5μm, the P-type column top width is 2.5μm, and the N-type column top width is 2.5μm. The stepping in the transition area 202 and the terminal area 203 can also be set to be different from the stepping in the active area. Generally, the stepping in the transition area 202 and the terminal area 203 is set to be smaller than the stepping in the active area. For example, the stepping in the transition area 202 and the terminal area 203 is set to be 4.8μm, the P-type column top width is 2.5μm, and the N-type column top width is 2.3.μm. The outermost P-type column in the terminal area 203 is a certain distance from the outermost periphery of the chip, for example, 15-30 microns.

[0185] In step S107, Figure 2F As shown, the surface oxide film, that is, the bottom silicon dioxide layer, is partially removed, leaving about A thick film is used as a protective film 206 for subsequent N+ implantation, i.e., the implantation of the source region 109, or the oxide film on the surface is completely removed first and then a layer of about 1000 nm is deposited by RTO. The oxide film is used as the protective film 206, or a relatively low temperature process such as a thermal oxidation process at 800°C to 950°C is used to deposit about The thermal oxide film is used as the protective film 206. The high temperature or long-time thermal process is not used here to reduce the mutual diffusion of impurities between the P-type column and the N-type column. Then, the N+ region, i.e., the cut-off region 109a closest to the chip periphery of the source region 109 and the terminal region 203, is formed by photolithography and ion implantation. The transition region 202 and the other regions of the terminal region 203 are not provided with N+ regions. Here, N+ can be phosphorus implantation or arsenic As implantation, for example, As 60keV1~5E15 atoms / cm 2 ,As 60Kev 1~5E15 atoms / cm 2 Indicates that the implanted impurity is As, the implantation energy is 60keV, and the implantation dose is 1 atom / cm 2 ~5E15 atoms / cm 2 After the ion implantation of the source region 109, an activation process at a temperature below 950°C, for example, 900°C for 30 min, may be performed, or RTA activation may be used.

[0186] In the step of forming the interlayer film 110, a 2000 angstrom undoped silicon dioxide layer is first deposited, and then a 8000-10000 angstrom BPSG layer is deposited.

[0187] In the step of forming the contact hole, the contact hole opening 111 can penetrate into the Si middle of the first epitaxial layer 102. arrive

[0188] The bottom of the contact hole opening 111 can be formed into a P-type region, namely the contact region 207, by injecting B or BF2. For example, when the contact region 207 is injected with B, the injection energy can be 30-60 KeV, and the injection dose can be 5E14-1E15 / cm 2 This better ensures the ohmic contact between the metal in the subsequent contact hole opening 111 and the Si at the bottom of the contact hole opening 111 and reduces the contact resistance.

[0189] In the step of forming the barrier layer 112, the thickness of the Ti layer is The thickness of the TiN layer is

[0190] In the step of forming the tungsten layer 113, the process of metal tungsten filling the contact hole opening 111 is to grow along the sidewalls of the contact hole opening 111 and contact the central area of ​​the contact hole opening 111. The contacted portion may have some gaps or no gaps. The tungsten may completely fill the contact hole opening 111, or may not completely fill it, as long as the subsequent metal can cover the hole well.

[0191] In the step of forming the front metal layer 114, the deposition temperature of AlCu can be set to 250-450°C, and the thickness can be set to 2-6 microns. Then, by metal photolithography and dry etching, the metal AL-CU, i.e. AlCu, the W, i.e. tungsten layer 113, and the barrier layer 112 are all removed.

[0192] In addition, as an alternative embodiment, it can be replaced by:

[0193] Before forming the front metal layer 114, the W on the silicon surface is completely removed by dry etching, and then the barrier layer 112 film under the W is also completely etched away, and then Ti / TiN / Alcu, i.e., the second barrier layer 112a and the front metal layer 114, are deposited. The thickness of the film can be set as follows: 5 microns, other settings are also possible, including 5 microns means the thickness of the Ti layer is The thickness of the TiN layer is The thickness of AlCu is 5 microns. Alternatively, after the W on the surface is completely etched, only AlCu is deposited, for example, 5 microns of AlCu is deposited. After the AlCu deposition is completed, metal photolithography and dry etching are performed.

[0194] It also includes the front passivation protection process, which includes:

[0195] A 1-2 micron dielectric protection layer can be deposited. The dielectric protection layer can be SiON, SiO2, SiN, a Si-rich silicon oxide film, or a combination of them. Then, through photolithography and dry etching, the gate electrode lead-out area and the source lead-out area are opened, while other areas including the terminal area that bears the lateral voltage are protected, which can improve the reliability of the product.

[0196] The front passivation protection process also includes:

[0197] A polyimide film can be deposited on the surface of the silicon wafer. The polyimide film can be formed on the surface of the dielectric protection layer, or the dielectric protection layer can be omitted. Then, through photolithography and development, the electrode lead-out area of ​​the gate is opened, the lead-out area of ​​the source is opened, and other areas including the terminal area that bears the lateral voltage are protected, which can improve the reliability of the product. After the photolithography and development are completed, it can be baked at 300-400°C (30-90 minutes). After baking, the thickness of the polyimide is 4-15 microns.

[0198] In step S108 , the back side is thinned to reduce the thickness of the entire silicon wafer, ie, the overall thickness of the semiconductor substrate 101 and the first epitaxial layer 102 , to 60 to 200 microns.

[0199] The thickness of the TiNiAg of the back metal layer 115 can be Ti layer Ni layer Ag layer

[0200] The above process can realize the manufacture of a super junction MOSFET, which can form the separation of the active area, the transition area and the terminal area that bears the lateral voltage. The electrode in the source area is Figure 2L The gate is connected to the front metal layer 114. Figure 2L The trench gate is designed through layout, and the contact holes at the ends of the trench gate are connected and led out through metal. The drain is the back metal layer 115.

[0201] In the first embodiment of the present invention, the following further optimizations can be performed:

[0202] In step S101, the setting of the first epitaxial layer 102 can be set according to the inclination angle and depth of the trench, i.e., the second trench 107, in step S104. For example, if the trench is vertical, the resistivity of the first epitaxial layer 102 can be set to be constant, i.e., consistent from top to bottom. If the trench is an inclined trench with a large top and a small bottom, then the concentration of the N epitaxial layer, i.e., the first epitaxial layer 102, can be set to be high at the top and low at the bottom according to the degree of inclination, and the concentration in the middle can change linearly, that is, at each position perpendicular to the trench, when the impurity concentration of the p-type column, i.e., the P-type column, is a single concentration, the PN balance can be achieved, so that the source-drain breakdown voltage (BVdss) and Rdson of the device can be better balanced.

[0203] It can also be: the filling of the groove in step S106, that is, filling the second epitaxial layer 108 in the second groove 107, can be set in combination with the setting of the first epitaxial layer 102 and the inclination angle of the groove. For example, if the groove is vertical, then the resistivity of the first epitaxial layer 102 can be set to be constant, that is, it is consistent from top to bottom, then the impurity concentration of the P-type column can also be constant. If the resistivity of the first epitaxial layer 102 can be set to be constant, and the groove is an inclined groove with a large top and a small bottom, then according to the degree of inclination, in the P-type epitaxial deposition process, a high P-type impurity concentration can be set first for deposition, and the deposition concentration can be gradually reduced. Afterwards, the specific process conditions are determined by evaluating the window relationship between the BVdss of the device and the P-type impurity setting, with the goal of expanding the process window of the P-type epitaxial process.

[0204] In the first embodiment of the present invention, in order to reduce the mutual diffusion of PN impurities after the formation of the P-type column, the temperature is limited to not exceed 950C during the thermal process after the formation of the P-type column for more than 10 minutes.

[0205] Compared with the prior art, the first embodiment of the present invention adopts a new process flow without increasing the process complexity and cost. Before the formation of the trench of the P-type column, i.e., the second trench 107, the gate oxide process of the high-temperature process, i.e., the formation process of the gate oxide layer 104, and the push-well process of the P-type well formation are placed before the P-type column trench. After the P-type column is formed, the stability of the thermal process is set to below 950°C, or only a very short time activation process such as RTA is used. The first embodiment of the present invention also adds a P-type ion implantation area in the terminal area to expand the process window of BVdss and P-type impurity concentration. By setting the terminal injection, the absolute value of the terminal BVdss can also be adjusted. For example, when the BVdss of the terminal is higher than the BVdss of the active area, the BVdss of the device can be increased, the consistency of the device can be improved, and the EAS capability can be enhanced.

[0206] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for manufacturing a super junction device, characterized in that: The steps include: Growing a first N-type doped epitaxial layer on the surface of the semiconductor substrate; Implanting a first P-type impurity into a surface region of the first epitaxial layer of a first selected region by photolithography and ion implantation, wherein the super junction device comprises an active region, a transition region and a terminal region, wherein the terminal region surrounds the periphery of the active region, the transition region is located between the active region and the terminal region, and the first selected region at least comprises a partial region of the terminal region close to the transition region; forming a plurality of trench gates in the first epitaxial layer of the active region, wherein the trench gates include a gate oxide layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench; Each of the trench gates is located in a subsequent corresponding N-type column; The gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer inside the gate trench is flat, so as to ensure the subsequent second trench formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process; Forming a P-type doped well region in the active region and the transition region by photolithography and ion implantation and annealing the well region, each of the trench gates passes through the well region, and adjusting the thermal process of the annealing of the well region so that the well region is pushed to a set position and ion implantation damage is repaired; Performing photolithography and etching to form a plurality of second trenches in the first epitaxial layer, wherein the first epitaxial layer between the second trenches serves as an N-type column; The second trench is located in a partial region of the active region, the transition region and the terminal region close to the transition region; A P-type doped second epitaxial layer is grown in the second trench, the second epitaxial layer outside the second trench is completely removed and the surface of the second epitaxial layer in the second trench is flattened, a P-type column is formed by the second epitaxial layer filled in the second trench, and a super junction structure is formed by alternating the N-type column and the P-type column; outside the well region, the first P-type impurity is used to compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation; A subsequent front process after the super junction structure is completed, wherein a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super junction structure so that the on-resistance of the super junction device meets the requirement; Complete the backside process of super junction devices.

2. The method for manufacturing a super junction device according to claim 1, wherein: The steps of forming the trench gate include: forming a first dielectric layer on a top surface of the first epitaxial layer; Photolithography defines a formation region of the gate trench; Sequentially etching the first dielectric layer and the first epitaxial layer in the formation region of the gate trench to form the gate trench; Forming the gate oxide layer by a thermal oxidation process; forming the gate conductive material layer; A first chemical mechanical polishing process is performed to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer within the gate trench.

3. The method for manufacturing a super junction device according to claim 2, characterized in that: Before or after the first chemical mechanical polishing process, the method further includes: Perform a rapid thermal oxidation or a rapid thermal annealing.

4. The method for manufacturing a super junction device according to claim 1, wherein: The maximum annealing temperature of the well region is above 1100° C. and the annealing time is above 30 minutes.

5. The method for manufacturing a super junction device according to claim 1, wherein: Before performing the photolithography process of the second trench, the method further includes: forming a hard mask layer; In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

6. The method for manufacturing a super junction device according to claim 5, characterized in that: The hard mask layer comprises a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence; After the etching of the second trench is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench are removed, and then the second epitaxial layer is grown; Afterwards, a second chemical mechanical polishing process is used to planarize the second epitaxial layer, so as to completely remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

7. The method for manufacturing a super junction device according to claim 1, wherein: The subsequent front surface process includes: Performing photolithography and ion implantation to form an N-type heavily doped source region, wherein the source region and the corresponding side of the gate trench are self-aligned; Annealing and activating the source region, wherein the annealing of the source region is performed in a furnace tube at a temperature below 950° C. or by rapid thermal annealing; forming an interlayer film, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer; forming a contact hole opening through the interlayer film; forming a P-type heavily doped contact region at the bottom of the contact hole opening; Filling a metal layer in the contact hole opening to form a contact hole; A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

8. The method for manufacturing a super junction device according to claim 7, characterized in that: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: Forming a dielectric protection layer; the dielectric protection layer is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer; The dielectric protection layer is patterned by photolithography and dry etching to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

9. The method for manufacturing a super junction device according to claim 7 or 8, characterized in that: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: forming a polyimide layer; Performing photolithography and development to pattern the polyimide layer to open the lead-out region of the source electrode and the lead-out region of the gate electrode; The polyimide layer is baked.

10. The method for manufacturing a super junction device according to claim 7, characterized in that: The metal layer forming the contact hole comprises: forming a barrier layer, wherein the barrier layer is formed on the inner surface of the contact hole opening; forming a tungsten layer, wherein the tungsten layer fills the contact hole opening; The barrier layer and the tungsten layer also extend onto the surface of the interlayer film outside the contact hole opening; The front metal layer is formed on the surface of the tungsten layer. When the front metal layer is patterned, the tungsten layer and the barrier layer are also removed in the front metal layer removal area, and the tungsten layer and the barrier layer are also retained in the front metal layer retention area. Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before forming the front metal layer, and then a second barrier layer and the front metal layer are formed or the front metal layer is directly formed.

11. The method for manufacturing a super junction device according to claim 1, wherein: The setting of the thermal process corresponding to the subsequent front process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

12. The method for manufacturing a super junction device according to claim 1, characterized in that: The second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the second epitaxial layer is constant, the doping concentration of the first epitaxial layer is set according to the side inclination angle and the depth of the second trench, and the doping concentration of the first epitaxial layer at the corresponding depth gradually increases from the bottom to the top of the second trench, so that the charge balance of each adjacent N-type column and the corresponding P-type column at each longitudinal position meets the requirement; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side inclination angle and depth of the second trench, and the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases from the bottom to the top of the second trench.

13. The method for manufacturing a super junction device according to claim 2, characterized in that: After the first chemical mechanical polishing process, the process further includes making the top surface of the gate conductive material layer in the gate trench below the top surface of the first epitaxial layer outside the gate trench. to facilitate the subsequent formation of the second groove.

14. The method for manufacturing a super junction device according to claim 7, characterized in that: When the source region is formed, a heavily N-type doped cutoff region is formed in the surface region of the first epitaxial layer at the outer edge of the terminal region.

15. The method for manufacturing a super junction device according to claim 1 or 14, characterized in that: The inner edge of the first selected area is located between the inner edge and the outer edge of the transition zone; The outer edge of the first selected area is located inside the outer edge of the outermost P-type column; Alternatively, the outer edge of the first selected area is flush with the outer edge of the outermost P-type column; Alternatively, the outer edge of the first selected area is located outside the outer edge of the outermost P-type column, and there is a first distance between the outer edge of the first selected area and the outer edge of the terminal area, and the first distance is greater than the maximum distance at which penetration occurs between the outer edge of the first selected area and the outer edge of the terminal area.

16. The method for manufacturing a super junction device according to claim 15, characterized in that: The first selected area is an open area of ​​the photoresist pattern formed by photolithography of the first P-type impurity; Between the inner edge and the outer edge of the first selected area, the first selected area is completely open; Alternatively, between the inner edge and the outer edge of the first selected region, the subsequent formation region of the P-type column is covered, and the outer region of the P-type column is opened.

17. The method for manufacturing a super junction device according to claim 1, characterized in that: The implanted impurities of the first P-type impurity ion implantation include boron, and the implantation energy is 50keV to 2MeV; The implantation dose of the first P-type impurity ion implantation ensures that after the backside process is completed, the impurity concentration of the first P-type impurity is not higher than 20% of the N-type impurity concentration of the N-type region outside the P-type column, and the net doping of the N-type region outside the P-type column remains N-type doping.

18. The method for manufacturing a super junction device according to claim 17, characterized in that: After the ion implantation of the first P-type impurity is completed, the method further comprises: The first P-type impurity is annealed and activated, and the maximum value of the annealing temperature of the first P-type impurity is greater than 1100° C., and the minimum value of the annealing time is 60 minutes to 180 minutes.

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