Method of processing a semiconductor structure, semiconductor structure and semiconductor processing apparatus

Abstract

This invention discloses a semiconductor structure processing method, a semiconductor structure, and a semiconductor processing apparatus. The processing method includes: providing a substrate, including a base layer disposed on the substrate, having a sloped structure extending gradually outward from the top surface toward the substrate, a cutoff layer covering the sloped structure, and a dielectric layer disposed on the cutoff layer; turning on a source radio frequency (RF) and a bias radio frequency (RF), introducing a first etching gas, and etching the dielectric layer until a third type of via exposes the cutoff layer; reducing the power of the bias RF to cause lateral etching of the openings of the first, second, and third types of vias; introducing a second etching gas to etch the cutoff layer exposed by the third type of via, the flow rate of the second etching gas increasing linearly with etching time at a slope k, until the cutoff layer of the third type of via is etched to a preset depth. This invention expands the process window for subsequent cutoff layer fabrication processes by controlling the cutoff layer margin in vias of different depths and aspect ratios.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device processing, and specifically relates to a method for processing semiconductor structures, a semiconductor structure, and a semiconductor processing apparatus. Background Technology

[0002] With the advent of the big data era, the demand for storage has grown exponentially. To meet this demand, storage chip technology has shifted from 2D NAND to 3D NAND, which has higher storage density but a more complex structure.

[0003] For high-density or ultra-high-density structures, one of the challenges in plasma etching is the ever-increasing aspect ratio required to meet design requirements, especially when etching holes or trenches of different depths and aspect ratios simultaneously on the same structure, with at least some of these holes or trenches having high aspect ratios. Current techniques struggle to ensure that holes or trenches of varying depths and aspect ratios within the same structure meet predetermined depths, often resulting in over-etching or under-etching. This leads to a narrower process window in subsequent processes for etching the protective layer at the bottom of the holes or trenches. Summary of the Invention

[0004] The purpose of this invention is to expand the process window for forming semiconductor structures with holes or trenches of different depths and aspect ratios. By adjusting the bias RF power and the type and flow rate of the etching gas, the amount of the cut-off layer in holes of different depths and aspect ratios can be controlled, so that the amount of the cut-off layer in deep holes with large aspect ratios is slightly smaller or equivalent to that in medium-depth holes with small aspect ratios.

[0005] To achieve the above objectives, the present invention provides a method for processing a semiconductor structure, comprising the following steps:

[0006] A substrate is provided, the substrate including a base layer disposed on a substrate, the base layer having a slope structure formed by the side gradually extending outward from the top surface toward the substrate, a stop layer covering the slope structure, and a dielectric layer disposed on the stop layer;

[0007] The source radio frequency and bias radio frequency are turned on, and a first etching gas is introduced to etch the dielectric layer, forming a plurality of first-type, second-type, and third-type vias with different aspect ratios, until the third-type vias expose the cutoff layer; wherein, the third-type vias 深宽比 > Type II holes 深宽比 >Class I hole 深宽比 ;

[0008] Reduce the power of the bias radio frequency to allow the openings of the first type of aperture, the second type of aperture, and the third type of aperture to be laterally etched for a preset time;

[0009] A second etching gas is introduced to etch the stop layer exposed by the third type of hole. During the etching process, the flow rate of the second etching gas increases linearly with the etching time at a slope k until the stop layer of the third type of hole is etched to a preset depth.

[0010] Optionally, the slope k is 0.6 to 1.2.

[0011] Optionally, the second etching gas includes C x H y F z For gases, 0 ≤ x < 2, y > 0, z ≥ 0.

[0012] Optionally, the second etching gas includes at least one of difluoromethane (CH2F2), trifluoromethane (CHF3), monofluoromethane (CH3F), and hydrogen (H2).

[0013] Optionally, the second etching gas includes CH2F2, wherein the flow rate of CH2F2 is 15 sccm to 30 sccm.

[0014] Optionally, the second etching gas may further include oxygen (O2).

[0015] Optionally, the volume ratio of CH2F2 to O2 is 0.4:1 to 0.6:1.

[0016] Optionally, the combined volume of CH2F2 and O2 accounts for 10% to 20% of the total volume of the first etching gas and the second etching gas.

[0017] Optionally, the process gas pressure is 20mT to 30mT.

[0018] Optionally, when the source radio frequency and the bias radio frequency are turned on, the frequency of the source radio frequency is 60MHz and the power is 2500W to 3000W; the frequency of the bias radio frequency is 400kHz and the power is 15000 to 18000W.

[0019] Optionally, when reducing the power of the bias radio frequency, the power of the bias radio frequency is reduced by 1000W to 1500W to form a carbon-containing deposition layer at the bottom of the second type of aperture.

[0020] Optionally, the first etching gas includes hexafluorobutadiene (C4F6).

[0021] Optionally, the first etching gas further includes at least one of octafluorocyclobutane (C4F8), O2, octafluoropropane (C3F8), octafluorocyclopentene (C5F8), and hexafluorobenzene (C6F6).

[0022] Optionally, the first etching gas further includes an auxiliary gas, which includes a rare gas, namely at least one of argon (Ar), krypton (Kr), and xenon (Xe).

[0023] Optionally, the auxiliary gas is a mixture of Ar, nitrogen (N2) and carbon monoxide (CO).

[0024] Optionally, 19:1 ≤ depth-to-width ratio of the third type of hole ≤ 25:1; 14:1 ≤ depth-to-width ratio of the second type of hole ≤ 19:1; depth-to-width ratio of the first type of hole < 8:1.

[0025] Optionally, when the stop layer of the third type of via is etched to the preset depth, the bottom of the first type of via has a carbon-containing deposition layer with a thickness of 600 nm to 1000 nm; the bottom of the second type of via has a carbon-containing deposition layer with a thickness of 35 nm to 45 nm; and the bottom of the third type of via has a carbon-containing deposition layer with a thickness of 1 nm to 10 nm.

[0026] Optionally, the base layer is a stacked structure. In the slope structure, the side edge of each stack extends outward relative to the side edge of the stack above it. The upper surface of the extension formed by each stack is farther from the top outer surface of the dielectric layer than the upper surface of the extension formed by the stack above it. Multiple extensions form a step shape, making the slope structure step-like.

[0027] Optionally, the stack includes at least a conductor layer and an insulating layer, the uppermost layer of the stack is a conductor layer, the conductor layer is a polycrystalline silicon layer or a conductive metal layer, and the insulating layer is a silicon oxide layer.

[0028] The present invention also provides a semiconductor structure, comprising:

[0029] Substrate;

[0030] A base layer is formed on a substrate, the base layer having a sloped structure that gradually extends outward from the top surface toward the substrate;

[0031] A stop layer, covering the slope structure; and

[0032] A dielectric layer is disposed on the cutoff layer, and a plurality of first-type holes, second-type holes and third-type holes with different aspect ratios are formed on the dielectric layer by the processing method described in any one of the above, and a carbon-containing deposition layer of a predetermined thickness is formed on the cutoff layer.

[0033] Optionally, the stop layer comprises a nitride, wherein the nitride is selected from at least one of SiN, AlN, GaN, InN, AlN, AlGaN, InGaN, and InGaAlN.

[0034] Optionally, the dielectric layer is a silicon oxide layer.

[0035] The present invention also provides a semiconductor processing apparatus, comprising:

[0036] Etching chamber, used to process the substrate;

[0037] Gas supply assembly, used to introduce reaction gases;

[0038] Source RF and bias RF; and

[0039] The control unit is used to control the steps of the processing method for the semiconductor structure described in any one of the above-mentioned methods.

[0040] Compared with the prior art, the technical solution of the present invention has at least the following technical effects:

[0041] The present invention reduces the power of the bias radio frequency until the third type of via exposes the cutoff layer, which can open the bottom feature size (BCD) at the bottom of the third type of via, making it easier to etch the cutoff layer inside the third type of via, and can increase the carbon-containing deposition layer of the second type of via, thus delaying the etching of the cutoff layer in the second type of via.

[0042] Furthermore, the present invention also introduces a second etching gas that is beneficial for etching deep holes. The flow rate of the second etching gas is linearly increased, which can etch the stop layer in the third type of hole to a set depth while only consuming the carbon-containing deposition layer in the second type of hole. The stop layer in the second type of hole is almost unetched, thereby realizing the control of the remaining amount of stop layer in through holes or trenches of different depths and aspect ratios, and expanding the process window for the process of breaking through the stop layer. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of a semiconductor structure for a three-dimensional storage device.

[0044] Figure 2 This is a schematic diagram of an open-circuit semiconductor structure for a three-dimensional storage device.

[0045] Figure 3 This is a schematic diagram of a short-circuit semiconductor structure for a three-dimensional storage device.

[0046] Figure 4 This is a flowchart of a semiconductor structure processing method according to the present invention.

[0047] Figure 5 This is a schematic diagram of the etching morphology at the bottom of each hole in a semiconductor structure during the processing of a semiconductor structure according to the present invention.

[0048] Figure 6This is a schematic diagram illustrating the linear increase in the flow rate of the second etching gas in a semiconductor structure processing method according to the present invention.

[0049] Figure 7 This is a schematic diagram of a semiconductor structure according to the present invention.

[0050] Figure 8 The figures above are comparison diagrams of the semiconductor structure before and after the experiment of an embodiment of the present invention. In the figure, a is a schematic diagram of the structure of the substrate to be processed, b is a distribution diagram of the residual amount of silicon nitride at different steps in the semiconductor structure processed in the embodiment as a function of the depth of the contact via, c is a schematic diagram of the morphology of the semiconductor structure prepared in the embodiment after the removal of the carbon-containing deposition layer, and d is a schematic diagram of the morphology of the semiconductor structure prepared in the embodiment after the removal of the carbon-containing deposition layer and the silicon nitride penetration step.

[0051] Figure 9 This is a diagram showing the distribution of residual silicon nitride at different steps in a semiconductor structure as a function of the depth of the contact via, used for comparative analysis.

[0052] Attached image labels:

[0053] Substrate 10

[0054] basal layer 11

[0055] Stacked 110

[0056] Oxide layer 111

[0057] Polycrystalline silicon layer 112

[0058] Extension 113

[0059] Cut-off layer 12

[0060] Dielectric layer 13

[0061] Contact via 131

[0062] Type I hole 1311

[0063] Type II Hole 1312

[0064] Type III Hole 1313

[0065] Sediment layer 132

[0066] Mask layer 14

[0067] Mask opening 141. Detailed Implementation

[0068] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0069] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0070] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0071] Currently, there are two technical routes for 3D NAND: Gate All Around (GAA) + Charge Trap and Gate All Around (GAA) + Floating Gate.

[0072] Taking the floating gate technology route as an example, three-dimensional memory devices have the following characteristics: Figure 1The semiconductor structure shown includes a substrate 10, a base layer 11, a stop layer 12, and a dielectric layer 13. In this example, the substrate 10 is made of polysilicon. The base layer 11 is a stacked structure formed by stacking several layers 110. Each stack 110 includes an oxide layer 111 and a polysilicon layer 112. The upper surface of each stack 110 is the upper surface of the polysilicon layer 112. One side edge of each stack 110 extends outward relative to the side edge of the previous stack 110. The upper surface of the extension portion 113 formed by each stack 110 is further vertically from the top of the dielectric layer 13 than the upper surface of the extension portion 113 formed by the previous stack 110. The multiple extension portions 113 form a step, giving one side of the base layer 11 a stepped slope structure. The stop layer 12 covers the slope structure. The dielectric layer 13 is formed on the stop layer 12, and the upper surface of the dielectric layer 13 is flush with the upper surface of the base layer 11. The cutoff layer 12 physically isolates the dielectric layer 13 from the substrate layer 11. The dielectric layer 13 has several contact vias 131 of varying depths. The bottom of each contact via 131 is a polysilicon layer 112. Metal can be filled into the contact vias 131, allowing independent connection of polysilicon layers 112 of different depths to the outside. Adjacent contact vias 131 are isolated from each other by the dielectric layer 13. This structure allows for independent read and write operations on memory cells of different pages by electrically connecting them to external circuits using mutually insulated contact vias.

[0073] The process flow for forming the above-mentioned memory cell structure is as follows: First, a stacked structure of alternating oxide (Oxide) layer 111 and polysilicon (Poly Si) layer 112 is deposited as the base layer 11. Then, a stepped slope structure is etched on one side of the stacked structure using a mask. To prevent damage to the polysilicon layer 112 during the etching process, a stop layer 12 is deposited on the slope structure for protection. In this example, the stop layer 12 is a silicon nitride (SiN) stop layer. Next, a dielectric layer 13 is deposited on the stop layer 12. Then, the dielectric layer 13 is etched to simultaneously form contact vias 131 of different depths. After etching the dielectric layer 13, a silicon nitride punchstep with a high silicon nitride selectivity to polysilicon is used to open the silicon nitride cutoff layers at different heights, exposing the polysilicon layer 112 at the bottom of the contact via 131. Conductive materials such as metal are then filled into the contact via 131, so that the contact via 131 can power on the polysilicon layers 112 at different depths and connect them to the peripheral circuit.

[0074] For ease of description, this invention classifies the contact vias 131 formed at different depths into three types based on different depth ranges (see...). Figure 1 ):

[0075] Shallow holes, such as those with a depth-to-width ratio of <8:1, are designated as Class I holes 1311.

[0076] Holes of medium depth, such as those with a depth-to-width ratio between 14:1 and 19:1, are designated as Class II holes 1312; and

[0077] Deep holes, such as those with a depth-to-width ratio between 19:1 and 25:1, are designated as Class III holes 1313.

[0078] The distance between the exposed stop layer of the first type hole 1311 and the edge of the hole opening is the depth of the first type hole 1311, denoted as h1; the distance between the exposed stop layer of the second type hole 1312 and the edge of the hole opening is the depth of the second type hole 1312, denoted as h2; the distance between the exposed stop layer of the third type hole 1313 and the edge of the hole opening is the depth of the third type hole 1313, denoted as h3; where h1 < h2 < h3.

[0079] In traditional processes, after the via etching (CT etch) of the dielectric layer 13, the recess range of the stop layer 12 within the contact vias 131 at different depths is relatively large. As the depth of the contact vias 131 increases, the remaining amount of the stop layer in each via generally exhibits a U-shaped distribution; that is, the remaining amount of the stop layer in the first type of vias 1311 and the third type of vias 1313 is relatively thick, while the remaining amount of the stop layer in the second type of vias 1312 is relatively thin. This is because during the etching process of the dielectric layer 13, the stop layer at the bottom of the first type of via 1311 is first exposed to the plasma. Due to the relatively small aspect ratio of the first type of via 1311, the non-volatile reaction byproducts generated during etching easily enter the bottom of the via, forming a thicker carbon-containing deposition layer. The reaction byproducts are mainly carbon-containing polymers, and their general formula can be C... x F y x and y represent the number of atoms. A thicker deposition layer can mask the stop layer at the bottom of the first type of hole 1311, protecting it from strong ion bombardment and damage. Therefore, the remaining amount of the stop layer in the first type of hole 1311 is relatively thick. For the second type of hole 1312, when the etching of the dielectric layer 13 continues and the stop layer at the bottom of the second type of hole 1312 is exposed, its hole depth is greater than that of the first type of hole 1311, and its aspect ratio is also larger. At this time, the reaction byproduct C x F y The distance traveled by molecular thermal motion to the bottom of the second type of pore increases, allowing C to reach the bottom of the second type of pore. x F yThe amount of free radicals decreases. Therefore, the deposited layer on the surface of the stop layer at the bottom of the second type of hole 1312 will be relatively thin. Ion bombardment and small fluorine (F) radicals can still penetrate to the bottom of the second type of hole 1312. Ion bombardment can easily penetrate the thin deposited layer, causing the F radicals to react with the stop layer, resulting in more etching of the stop layer, which leads to a relatively thin stop layer at the bottom of the second type of hole, or even the stop layer being broken down and damaging the underlying polysilicon layer. For the third type of hole 1313, when the etching of the dielectric layer 13 continues and the stop layer at the bottom of the third type of hole 1313 is exposed, its aspect ratio is already large enough, and the sidewalls of the third type of hole 1313 are longer, which will consume more F radicals, so very few radicals can reach the bottom of the third type of hole 1313. Although the deposition layer on the surface of the stop layer in the third type of via 1313 is less than that in the second type of via 1312, the amount of the reactive precursor F radicals is also insufficient. Therefore, the reaction with the stop layer is slow, resulting in less etching of the stop layer and a larger amount of residual stop layer in the third type of via 1313. After the dielectric layer contact via etching is completed, the excessive amount of residual stop layer in the third type of via 1313 will affect the subsequent process of breaking through the stop layer.

[0080] The process of penetrating the cutoff layer is used to selectively bombard and remove the cutoff layer 12 without damaging the underlying polysilicon layer 112; it is primarily a physical bombardment process. Under the same process conditions, the impact force on the bottom of the contact via 131 is directly related to the via depth; that is, the greater the via depth, the smaller the impact force. Since the depth h3 of the third type via 1313 is greater than the depth h2 of the second type via 1312 and the depth h1 of the first type via 1311, the cutoff layer at the bottom of the third type via 1313 will experience the least impact force under the same power. When the thickness of the cutoff layers of all vias is the same, penetrating the cutoff layer of the third type via 1313 requires the longest process time. Because the cut-off layer penetration process is performed simultaneously on contact vias 131 of different depths, when the remaining amount of the cut-off layer in contact vias 131 of different depths exhibits a U-shaped distribution (i.e., the remaining amount of the cut-off layer in the first type of via 1311 and the third type of via 1313 is relatively thick, while the remaining amount of the cut-off layer in the second type of via is relatively thin), after a certain period of time during the penetration step, the cut-off layer in the second type of via 1312 has been penetrated, exposing the underlying polysilicon layer. Continuing the penetration step would damage the polysilicon layer at the bottom of the second type of via 1312. At this time, the cut-off layer in the third type of via 1313 has not yet been penetrated, and the penetration step needs to continue. If the penetration step is stopped at this point, because the cut-off layer in the third type of via 1313 is not fully opened, the contact via 131 will experience an open circuit, thus losing control of the word line (WL). Figure 2 As shown; if the drilling process continues until the stop layer inside the third type of via 1313 is removed, the polysilicon layer at the bottom of the second type of via 1312 may be damaged or even drilled through, connecting with the next polysilicon layer, causing a short circuit between adjacent WL layers, as shown. Figure 3 As shown. Therefore, when the remaining amount of the stop layer in the contact via 131 is distributed in a U-shape, or when the remaining amount of the stop layer in the second type of via 1312 is less than that in the third type of via 1313, the process window for penetrating the stop layer will be relatively narrow under the same process conditions.

[0081] Therefore, controlling the amount of the remaining stop layer in contact vias of different depths becomes the key and challenge of this staircase CT etch process.

[0082] To achieve different penetration depths using uniform process conditions in the process of penetrating the stop layer, this invention proposes a novel etching method that allows for precise control of the remaining thickness of the stop layer in contact vias of different depths during stepped via etching. This ensures that the remaining amount of the stop layer in the third type of via 1313 is no higher than that in the second type of via 1312, thereby expanding the process window for penetrating the stop layer. The following is combined with… Figure 4-7 The process steps of the present invention, the etching morphology of the holes in each step, and the reaction mechanism are described respectively.

[0083] like Figure 4 As shown, a semiconductor structure processing method of the present invention includes the following steps:

[0084] Step S1: A substrate is provided, the substrate including a base layer disposed on a substrate, the base layer having a slope structure formed by the side gradually extending outward from the top surface toward the substrate, a stop layer covering the slope structure, and a dielectric layer disposed on the stop layer.

[0085] The substrate material can be at least one of silicon (Si), gallium arsenide (GaAs), and silicon carbide (SiC).

[0086] The substrate layer can be a polycrystalline silicon layer, a silicon oxide layer, or a stacked structure composed of alternating conductive and insulating layers. The conductive layer is made of polycrystalline silicon or a conductive metal, such as tungsten (W). The insulating layer is made of a dielectric material such as silicon oxide. In this example, the conductive layer is a polycrystalline silicon layer, and the insulating layer is a silicon oxide layer.

[0087] In this article, slope is defined as the ratio between the basal layer height H of the transition segment from the sidewall profile to the horizontal distance L of the sidewall of the transition segment (see...). Figure 7The slope on one side of the substrate layer is designed to create contact vias of varying depths. By filling these vias with conductive material, polysilicon layers of different depths can be connected to peripheral circuits. In this example, the substrate layer has a slope on one side, but this is not a limitation; slopes can also be present on both sides. In this example, the horizontal length of the substrate layer gradually increases from the top of the substrate to the substrate. It is understood that this invention also applies to substrates where the horizontal length gradually decreases from the top of the substrate to the substrate.

[0088] The stop layer is provided to prevent damage to the substrate layer during etching of the dielectric layer. The stop layer comprises a nitride and can be selected from at least one of SiN, AlN, GaN, InN, AlN, AlGaN, InGaN, and InGaAlN. As an example, the stop layer can be silicon nitride.

[0089] A dielectric layer is formed on the cutoff layer. The side of the dielectric layer in contact with the cutoff layer has a slope extending from the top surface toward the substrate. The cross-sectional length of the dielectric layer gradually decreases in the horizontal direction. The slope of the dielectric layer side is the same as the slope of the substrate layer side, but in the opposite direction. Therefore, the upper surface of the dielectric layer is flush with the upper surface of the substrate layer. By etching the dielectric layer, contact vias of different depths that are mutually insulated can be formed. The bottom of the contact vias formed by penetrating the cutoff layer is a conductor layer. When the contact vias are filled with conductive material, the conductor layers at different depths can be electrically connected to external circuits through the contact vias. In this example, the dielectric layer is made of silicon oxide.

[0090] Step S2: Turn on the source radio frequency and bias radio frequency, introduce the first etching gas, and etch the dielectric layer to form a plurality of first-type, second-type, and third-type vias with different aspect ratios, until the third-type vias expose the cutoff layer; wherein, the third-type vias... 深宽比 > Type II holes 深宽比 >Class I hole 深宽比 .

[0091] The source radio frequency (RF) is used to dissociate the first etching gas to form plasma. This plasma is highly reactive and can react with the dielectric layer to etch and form contact vias. The bias RF is used to physically bombard the dielectric layer of the substrate to assist in etching. When the source RF and bias RF are activated, the frequency of the source RF is 60MHz and the power is 2500W to 3000W; the frequency of the bias RF is 400kHz and the power is 15000W to 18000W.

[0092] To avoid etching the first type of via 1311 too quickly, the first etching gas is selected to form a deposition layer simultaneously with the etching of the dielectric layer. The deposition layer is mainly carbon-containing C. xF y Polymers, whose molecules readily deposit into the first type of vias to form a deposition layer, mask the etched layer and slow down the etching rate. The first etching gas typically includes C4F6. Depending on the aspect ratio of the contact vias and the distribution of the first, second, and third types of vias, the first etching gas may also include at least one of C4F8, O2, C3F8, C5F8, and C6F6.

[0093] In some embodiments, the first etching gas further includes an auxiliary gas, which includes a rare gas, at least one of argon (Ar), krypton (Kr), and xenon (Xe). The rare gas has a large molecular weight, and the positive ions dissociated from it by the source radio frequency can assist in physical bombardment.

[0094] In some embodiments, the auxiliary gas is a mixture of Ar, nitrogen (N2), and carbon monoxide (CO). The nitrogen, when the source radio frequency is turned on, dissociates into positive ions that can modify the mask, preventing the mask openings from being blocked. CO can provide carbon ions to assist in the formation of the deposition layer.

[0095] The main gas dissociation equation for the first etching gas is as follows:

[0096] e - +C4F6→CF * +CF2 * +CF3 * +F * +C2F4 + +e -

[0097] C4F8→CF * +CF2 * +CF3 * +C2F4 + +F * +e -

[0098] e - +O2→O * +O * +e -

[0099] Ar→Ar + +e -

[0100] N2→N2 + +e -

[0101] e - +CO→C+O+e -

[0102] Step S2 is the first stage of etching, and the etching morphology of the contact vias 131 (first type vias 1311, second type vias 1312, and third type vias 1313) is as follows: Figure 5 As shown in Figure a, to clearly show the bottom morphology of each hole, only the part of each hole near the stop layer 12 is shown in the figure.

[0103] The following reactions mainly occur in the first type of pore 1311:

[0104] e - +CF2 * +C2F4 + +CF * +SiO2→CO↑+SiF4↑+C+C+e -

[0105] Initially, the first etching gas etches the silicon oxide dielectric layer within the first type of hole 1311, while simultaneously generating a small amount of byproduct C. x F y Polymer byproducts are deposited at the bottom of the wells, where the etching rate is greater than the deposition rate. This is because the distance h1 from the bottom of the stop layer at the bottom of the first type of well 1311 to the well opening (see...) Figure 7 Because the depth-to-width ratio of the first type of via 1311 is relatively small when etching reaches the stop layer, byproducts generated during etching easily fall into the first type of via 1311 and deposit at its bottom. The deposited layer at the bottom masks the stop layer at the bottom of the via, thus slowing down the etching rate of the stop layer. Furthermore, due to the etching selectivity of the stop layer, the downward etching rate slows down further until the etching rate is less than the deposition rate, and the net deposited layer gradually increases. As an example, in the first stage of etching, the thickness of the net deposited layer in the first type of via 1311 is 400 nm to 800 nm.

[0106] The following reactions mainly occur in the second type of pore 1312:

[0107] e - +CF2*+CF*+SiO2→CO↑+SiF4↑+C+e -

[0108] Initially, the first etching gas etches the silicon oxide dielectric layer within the second type of hole 1312, while simultaneously generating a small amount of byproduct C. x F y Polymer and byproducts are deposited at the bottom of the wells, where the etching rate is greater than the deposition rate. Because the distance h2 between the exposed stop layer of the second-type well 1312 and the well opening edge of the second-type well is greater than h1 (see...),... Figure 7When etching reaches the cutoff layer, the aspect ratio of the second type of via 1312 is larger than that of the first type of via 1311. Larger molecules are less likely to enter the second type of via 1312, resulting in relatively fewer byproducts falling into and depositing at the bottom. The deposited layer at the bottom of the second type of via is very thin, in this example, 10 nm to 20 nm thick, which is insufficient to resist ion bombardment and small fluorine-containing free radicals. Therefore, while the cutoff layer of the first type of via 1311 has stopped being etched, the etching of the cutoff layer of the second type of via 1312 continues slowly. To prevent the cutoff layer of the second type of via 1312 from being over-etched and easily broken down in the subsequent cutoff layer penetration process, measures need to be taken.

[0109] The following reactions mainly occur in the third type of pore 1313:

[0110] e - +CF * +SiO2→CO↑+SiF4↑+e -

[0111] Initially, the first etching gas etches the dielectric layer within the third type of hole 1313, generating a very small amount of byproduct C. x H y Polymer and byproducts are deposited at the bottom of the wells, where the etching rate is greater than the deposition rate. The distance h3 between the exposed stop layer of the third-type well 1313 and the well opening edge is the largest (see...). Figure 7 The third type of via 1313, formed by etching to the stop layer, has a greater depth and width than the first type of via 1311 and the second type of via 1312. Only very small molecules can enter the third type of via 1313, resulting in very few byproducts falling into the third type of via 1313 and depositing at its bottom. Therefore, there is almost no deposited layer at the bottom of the third type of via 1313. Furthermore, due to the etching selectivity of the stop layer, the downward etching rate almost stops when the stop layer is reached. Measures need to be taken to continue etching the stop layer of the third type of via 1313 to ensure that the remaining thickness of the stop layer meets the requirements. Further, since the first etching gas has difficulty entering the third type of via 1313 with its high aspect ratio, there may be dielectric layer residue at the bottom of the third type of via 1313, forming a V-shape. Measures need to be taken to open the bottom BCD of the third type of via.

[0112] Step S3: Reduce the power of the bias radio frequency to allow the openings of the first type of hole 1311, the second type of hole 1312 and the third type of hole 1313 to be laterally etched for a preset time.

[0113] The preset time can be preset based on the over-etching amount of the third type of hole, or it can be preset based on the time it takes for the BCD of the first type of hole, the second type of hole, and the third type of hole to reach the target size.

[0114] To open the bottom BCD of the third type of via 1313 and achieve an ideally flat bottom, the power of the bias RF is reduced while the flow rate and type of the first etching gas remain unchanged. The dissociation equation for the first etching gas is the same as in step 1, and therefore will not be repeated.

[0115] Step S3 is the second stage of etching, and the etching morphology of each hole is as follows: Figure 5 As shown in b.

[0116] The following reactions mainly occur within the first type of pore 1311 (forming a carbonaceous deposition layer):

[0117] e- + CO → C + O + e-

[0118] e - +C2F4+→CF3*+C+e -

[0119] The reduced power of the bias RF weakens the bombardment force, further slowing down the downward etching rate in the first type of via 1311. This primarily results in the formation of a carbon-containing deposition layer, increasing the net deposition layer at the bottom of the first type of via 1311, with a thickness reaching 450nm–850nm. Due to the masking of the bottom cutoff layer by the net deposition layer, the first etching gas has difficulty etching downwards, instead etching the sidewalls of the first type of via 1311 to some extent, thus increasing the bottom BCD of the first type of via 1311. To maintain feature size consistency, the bottom BCD of the first type of via 1311 can be designed to be slightly smaller than the target size, so that the target size is reached precisely when the bottom BCD of the first type of via 1311 increases.

[0120] The following reaction mainly occurs within the second type of hole 1312 (forming a carbon-containing deposition layer while etching the sidewall dielectric layer):

[0121] e-+CF2*+CF*+SiO2→CO↑+SiF4↑+C+e-

[0122] The reduced power of the bias RF reduces the bombardment intensity, further slowing down the downward etching rate in the second type of via 1312. The first etching gas also etches the sidewalls of the second type of via 1312 to some extent, increasing the bottom BCD of the second type of via 1312. To maintain feature size consistency, the bottom BCD of the second type of via 1312 can be designed to be slightly smaller than the target size, reaching the target size precisely when the bottom BCD of the second type of via 1312 increases. Furthermore, due to the formation of carbon-containing byproducts during the etching reaction, the net deposited layer at the bottom of the second type of via 1312 increases, and the thickness of the net deposited layer can reach 15nm to 20nm.

[0123] The following reactions mainly occur within the third type of hole 1313 (etching the residual dielectric layer on the bottom sidewall, without forming a carbon-containing deposition layer):

[0124] e-+CF*+SiO2→CO↑+SiF4↑+e-

[0125] The reduced power of the bias RF weakens the bombardment force, further slowing down the downward etching rate in the third-type via 1313. The first etching gas does some etching of the residual dielectric layer on the bottom sidewall of the third-type via 1313, increasing the bottom BCD of the third-type via 1313. Furthermore, since the molecules entering the third-type via 1313 are small molecules, such as CF*, almost no carbon-containing carbon is formed when they react with the dielectric layer. x F y As a byproduct, the bottom of the third-type hole 1313 has almost no net deposit layer. In this example, the over-etching amount of the third-type hole 1313 reaches 3%, that is, taking the etching time of 100 seconds in step S2 as an example, the etching time in step S3 is about 3 seconds. It can also be determined based on the observed BCD condition of the third-type hole 1313. The bottom of the third-type hole 1313 is basically flat, and the BCD can reach the target size.

[0126] In order to open the bottom BCD of the third type of via 1313 while forming a net carbon-containing deposition layer at the bottom of the second type of via 1312 to mask the cutoff layer and avoid excessive etching of the cutoff layer inside the second type of via 1312, the present invention can reduce the power of the bias radio frequency by 1000w to 1500w when reducing the power of the bias radio frequency.

[0127] Step S4: Introduce a second etching gas to etch the stop layer exposed by the third type of hole 1313. During the etching process, the flow rate of the second etching gas increases linearly with the etching time at a slope k until the stop layer of the third type of hole 1313 is etched to a preset depth.

[0128] The second etching gas primarily functions to etch the stop layer in the third type of via 1313, which has a large depth-to-width ratio. Generally, the molecules of the second etching gas are relatively small, making it easy to enter holes or trenches with large depth-to-width ratios, thus facilitating deep-hole etching. The second etching gas includes C. x H y F z The gas, 0 ≤ x < 2, y > 0, z ≥ 0. As an example, the second etching gas may include at least one of CH2F2, CHF3, CH3F, and H2.

[0129] In some embodiments, the second etching gas includes CH2F2, wherein the flow rate of CH2F2 is 15 sccm to 30 sccm. The etching state of each hole in step S4 is illustrated below using CH2F2 as an example.

[0130] Step S4 includes both a first etching gas and a second etching gas. The gas dissociation equations, besides the parts identical to those in step S1, also include the dissociation of the newly added second etching gas, CH2F2. The dissociation equation is as follows:

[0131] e - +CH2F2→CHF2 + +CH2F + +H * +F * +e -

[0132] Step S4 can be divided into two stages: the third stage of etching and the fourth stage of etching. When the flow rate of the second etching gas increases linearly with the etching process at a slope k, the etching process transitions from the third stage to the fourth stage, marked by the cessation of net deposition within the second type of borehole 1312. As an example, the slope k can be between 0.6 and 1.2. The etching morphology of each borehole in the third stage of etching is as follows... Figure 5 As shown in c, the etching morphology of each hole in the fourth stage of etching is as follows: Figure 5 As shown in d.

[0133] In the third stage of etching, the amount of the second etching gas is relatively small. At this time, the following reaction mainly occurs in the first type of hole 1311 (forming a deposition layer):

[0134] e- + CO → C + O + e -

[0135] e - +C2F4 + →CF3 * +C+e -

[0136] A deposition layer continues to form within the first type of pore 1311, increasing the net deposition layer thickness to 500 nm to 900 nm.

[0137] The following reactions (forming a deposition layer) mainly occur within the second type of pore 1312:

[0138] e - +CHF2 + +CH2F + →C+HF↑+e -

[0139] The active ions formed after the small CH2F2 molecules in the second etching gas dissociate enter the second type of pore 1312, forming a carbon-containing deposition layer. Due to the masking effect of the deposition layer, the second etching gas forms a deposition layer before contacting the stop layer, increasing the net deposition layer thickness. The net deposition layer thickness within the second type of pore 1312 reaches 35 nm to 45 nm.

[0140] The following reaction mainly occurs within the third type of via 1313 (etching the stop layer):

[0141] e - +CHF2 + +CH2F + +Si3N4→SiF4↑+NH3↑+HCN↑+e -

[0142] Because the third type of pore 1313 did not form a deposition layer to shield it, the CHF2 formed by the dissociation of small molecule CH2F2... + CH2F + After entering the third type of hole 1313 with a high depth-to-width ratio, it is easy to react with the stop layer to form volatile products, which are then extracted from the reaction chamber without forming a net deposit layer. That is, the thickness of the net deposit layer in the third type of hole 1313 is 0.

[0143] As the flow rate of the second etching gas increases linearly, the etching process enters the fourth stage. In the fourth stage, the gas dissociation equation is the same as that in the third stage.

[0144] The main reactions within the first type of pore 1311 are the same as in the third stage. The net deposited layer within the first type of pore 1311 continues to increase, reaching a thickness of 600 nm to 1000 nm.

[0145] The following reactions mainly occur within the second type of pore 1312:

[0146] C+H*+CF2*→CF2+CH↑+e -

[0147] The net deposition layer within the second type of via 1312 no longer increases. Small molecules consume the carbon-containing deposition layer and simultaneously generate a new fluorocarbon deposition layer. The thickness of the net deposition layer within the second type of via 1312 remains approximately 35 nm to 45 nm, preventing the second etching gas from contacting the stop layer and thus avoiding over-etching of the stop layer.

[0148] The following reactions mainly occur within the third type of pore 1313:

[0149] e - +CHF2++CH2F++Si3N4→SiF4↑+NH3↑+HCN+e - +C

[0150] C+H*+CF2*→CF2+CH↑+e -

[0151] A thin layer of C is formed simultaneously with the etching of the stop layer. x F yThe thickness of the deposited layer within the third type of via 1313 is approximately 5 nm, varying from 1 nm to 10 nm depending on the amount of CH2F2. Etching ends when the thickness of the stop layer in the third type of via 1313 is etched to the required level, for example, comparable to the thickness of the stop layer in the second type of via 1312.

[0152] In some embodiments, the second etching gas further includes O2. The combined volume of CH2F2 and O2 accounts for 10% to 20% of the total volume of the first and second etching gases. The mixture of CH2F2 and O2 increases linearly, such as... Figure 6 As shown, as an example, the slope k can be 0.6–1.2 sccm / min. The volume ratio of CH2F2 to O2 is 0.4:1–0.6:1. The amount and proportion of the second etching gas can be adjusted according to the etching condition of the third type of hole 1313.

[0153] In this invention, the process air pressure can also be controlled to be 20mT to 30mT by controlling the opening degree of the air pump.

[0154] like Figure 7 As shown, the semiconductor structure formed by the method of the present invention includes: a substrate 10, a base layer 11, a cutoff layer 12, and a dielectric layer 13.

[0155] A substrate layer 11 is formed on a substrate 10. In this example, the substrate layer 11 is a stacked structure, formed by stacking several layers 110. The side edge of each layer 110 extends outward relative to the side edge of the layer above it, and the upper surface of the extension portion 113 formed by each layer 110 is further from the top outer surface of the dielectric layer than the upper surface of the extension portion 113 formed by the layer above it, such that one side of the substrate layer 11 has a slope structure that gradually extends outward from the top surface toward the substrate.

[0156] The stop layer 12 covers the slope structure.

[0157] A dielectric layer 13 is disposed on the cutoff layer 12. A plurality of first-type holes 1311, second-type holes 1312 and third-type holes 1313 with different aspect ratios are formed on the dielectric layer 13 by the above method. A carbon-containing deposition layer 132 of a predetermined thickness is formed on the cutoff layer 12 in each hole.

[0158] In some embodiments, the bottom of the first type of pore 1311 has a carbon-containing deposition layer 132 with a thickness of 600 nm to 1000 nm; the bottom of the second type of pore 1312 has a carbon-containing deposition layer 132 with a thickness of 35 nm to 45 nm; and the bottom of the third type of pore 1313 has a carbon-containing deposition layer 132 with a thickness of 1 nm to 10 nm.

[0159] In this example, the multiple extensions 113 form a stepped shape, giving the base layer 11 a stepped slope structure. On this slope structure, the stop layer 12 covers the sidewalls of the stack and the extensions 113. The stop layer 12 has a higher etching selectivity for the dielectric layer 13 than the stack 110, thus protecting the stack 110 during the etching process to form contact vias in the dielectric layer.

[0160] The stack 110 includes at least a conductor layer and an insulating layer, with the uppermost layer being a conductor layer. The conductor layer is a polysilicon layer or a conductive metal layer, and the insulating layer is a silicon oxide layer. In some embodiments, the stack 110 includes at least a silicon oxide layer 111 and a polysilicon layer 112, with the uppermost layer being the polysilicon layer 112.

[0161] The following specific embodiments and comparative examples illustrate the beneficial effects of the present invention.

[0162] Example

[0163] Provide a substrate, such as Figure 8 As shown in Figure a, the substrate includes a base layer 11 disposed on a substrate 10. The base layer 11 has a slope structure that gradually extends outward from the top surface toward the substrate. A stop layer 12 is covered on the slope structure, and a dielectric layer 13 is disposed on the stop layer 12. In this example, the base layer 11 is a stacked structure composed of alternating conductor layers and insulating layers, wherein the conductor layer is a polysilicon layer 112, the insulating layer is a silicon oxide layer 111, the stop layer 12 is a silicon nitride layer, and the dielectric layer 13 is a silicon oxide layer. The top of the base layer 11 and the top of the dielectric layer 13 are on the same plane and are both covered with a patterned mask layer 14. The mask layer 14 has an opening 141, through which the dielectric layer 13 to be etched can be exposed for etching to form contact vias 131 (see Figure a). Figure 8 d).

[0164] The source RF and bias RF are activated. The source RF frequency is 60MHz with a power of 3000W, and the bias RF frequency is 400kHz with a power of 17000W. The process temperature is 70℃. The opening of the vacuum pump is controlled to maintain the cavity pressure at 30mT. A first etching gas is introduced, which contains: 37sccm of C4F6, 40sccm of C4F8, 35sccm of O2, 50sccm of N2, 270sccm of CO, and 80sccm of Ar. The dielectric layer is etched for 928s, forming several first-type vias 1311, second-type vias 1312, and third-type vias 1313 with different aspect ratios. The third-type vias 1313 expose the cutoff layer 12.

[0165] Continue to introduce the first etching gas at the above flow rate, keep the source RF power unchanged, keep the cavity pressure and process temperature unchanged, and reduce the power of the bias RF to 15000w, so that the openings of the first type of hole 1311, the second type of hole 1312 and the third type of hole 1313 are laterally etched for 60s.

[0166] The first etching gas is continued to be introduced at the above flow rate, while the source RF power, bias RF power, cavity pressure, and process temperature remain constant. Then, 15 sccm of O2 and 20 sccm of CH2F2 are introduced to etch the cutoff layer exposed by the third type of via 1313. During etching, the flow rates of O2 and CH2F2 gradually increase with etching time until the cutoff layer of the third type of via 1313 is etched to a preset depth. At this point, the total flow rate of O2 is 54 sccm, and the flow rate of CH2F2 is 28 sccm. The distribution of residual silicon nitride at different steps in the semiconductor structure obtained after the above treatment with the depth of the contact via 131 is shown in the figure below. Figure 8 As shown in Figure b, the experimental results of this embodiment are illustrated: by linearly increasing the flow rate of CH2F2 / O2, the residual silicon nitride in the third type of via 1313 can be minimized, and the residual silicon nitride distribution maps of the third type of via 1313 and the second type of via 1312 can be flattened, resulting in a smaller recessed area of ​​residual silicon nitride. This significantly increases the process window for the next silicon nitride penetration process. The morphology after removing the carbon-containing deposited layer is shown in Figure b. Figure 8 As shown in Figure c, the thickness of the remaining silicon nitride stop layer gradually decreases as the depth of the contact via increases. After the silicon nitride penetration step, the morphology of the semiconductor structure is as follows: Figure 8 As shown in d, each contact via 131 stops at the surface of the polysilicon layer 112, with neither short circuit nor open circuit occurring.

[0167] Comparative Example

[0168] The same substrate as in the embodiment is provided, and conventional capacitively coupled plasma (CCP) etching is used for processing. The etching gas used throughout is the first etching gas from the embodiment, C4F6 / C4F8 / O2 / Ar / CO / N2 (each gas flow rate is the same as in the embodiment). By adjusting the cavity pressure and the combination of high and low frequency power, the distribution of residual silicon nitride in the formed stepped vias with the depth of the contact via 131 is shown in the figure. Figure 9 As shown, the residual amount of silicon nitride is distributed in a U-shape. The residual amount of silicon nitride is relatively thick in the shallowest hole (first type hole 1311) and the deepest hole (third type hole 1313), while the residual amount of silicon nitride in the middle depth hole (second type hole 1312) is relatively thin. The recessed range of the residual amount of silicon nitride is relatively large, resulting in a relatively small process window for the silicon nitride penetration step.

[0169] In summary, by adjusting the power of the bias radio frequency, introducing a second etching gas, and controlling the flow rate of the second etching gas, this invention can control the thickness of the carbon-containing deposition layer on the stop layer in the stepped via, thereby achieving the regulation of the remaining amount of the stop layer in holes of different depths after etching. This can result in uniform distribution in each hole, or the deepest hole (third type hole) may have the least remaining amount of the stop layer, or it may be comparable to the remaining amount of the stop layer in the medium-depth hole (second type hole), thus effectively expanding the process window for forming stepped vias.

[0170] Furthermore, the present invention also discloses a semiconductor structure in which a substrate containing a base layer, a stop layer and a dielectric layer is etched using the above-mentioned plasma processing method to obtain first-type holes, second-type holes and third-type holes with different aspect ratios and depths, and a carbon-containing deposition layer of a predetermined thickness is formed on the stop layer at the bottom of the hole to facilitate the next step of etching through the stop layer.

[0171] Furthermore, the present invention also discloses a semiconductor processing apparatus, including an etching chamber in which an etching process can be performed to process a substrate; a gas supply assembly for introducing reactive gas into the etching chamber; a source radio frequency and a bias radio frequency for generating plasma in the etching chamber; and a control unit for controlling the processing method of the above-mentioned semiconductor structure to obtain a suitable cutoff layer state.

[0172] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for processing a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a base layer disposed on a substrate, the base layer having a slope structure formed by the side gradually extending outward from the top surface toward the substrate, a stop layer covering the slope structure, and a dielectric layer disposed on the stop layer; The source radio frequency and bias radio frequency are turned on, and a first etching gas is introduced to etch the dielectric layer, forming a number of first-type holes, second-type holes and third-type holes of different depths, until the third-type holes expose the cutoff layer; wherein, the depth of the third-type holes is greater than the depth of the second-type holes and the depth of the first-type holes; the first etching gas includes fluorocarbon gas. Reduce the power of the bias radio frequency to allow the openings of the first type of aperture, the second type of aperture, and the third type of aperture to be laterally etched for a preset time; A second etching gas is introduced to etch the stop layer exposed by the third type of via. During the etching process, the flow rate of the second etching gas increases linearly with the etching time at a slope k until the stop layer of the third type of via is etched to a preset depth, such that the remaining amount of the stop layer in the third type of via is not higher than the remaining amount of the stop layer in the second type of via. The second etching gas includes C. x H y F z For gases, 0 ≤ x < 2, y > 0, z ≥ 0.

2. The semiconductor structure processing method as described in claim 1, characterized in that, The slope k is 0.6~1.

2.

3. The semiconductor structure processing method as described in claim 1, characterized in that, The second etching gas includes at least one of CH2F2, CHF3, CH3F and H2.

4. The semiconductor structure processing method as described in claim 1, characterized in that, The second etching gas includes CH2F2, wherein the flow rate of CH2F2 is 15 sccm ~ 30 sccm.

5. The semiconductor structure processing method as described in claim 4, characterized in that, The second etching gas also includes O2.

6. The semiconductor structure processing method as described in claim 5, characterized in that, The volume ratio of CH2F2 to O2 is 0.4:1 to 0.6:

1.

7. The semiconductor structure processing method as described in claim 6, characterized in that, The combined volume of CH2F2 and O2 accounts for 10% to 20% of the total volume of the first and second etching gases.

8. The semiconductor structure processing method as described in claim 1, characterized in that, The process gas pressure is 20mT~30mT.

9. The semiconductor structure processing method as described in claim 1, characterized in that, When the source radio frequency and the bias radio frequency are turned on, the frequency of the source radio frequency is 60MHz and the power is 2500W~3000W; the frequency of the bias radio frequency is 400Khz and the power is 15000W~18000W.

10. The method for processing a semiconductor structure as described in claim 1, characterized in that, When the power of the bias radio frequency is reduced, the power of the bias radio frequency is reduced by 1000W to 1500W to form a carbon-containing deposition layer at the bottom of the second type of aperture.

11. The method for processing a semiconductor structure as described in claim 1, characterized in that, The first etching gas includes C4F6.

12. The method for processing a semiconductor structure as described in claim 11, characterized in that, The first etching gas also includes at least one of C4F8, O2, C3F8, C5F8 and C6F6.

13. The method for processing a semiconductor structure as described in claim 1 or 11, characterized in that, The first etching gas also includes an auxiliary gas, which includes a rare gas, namely at least one of argon, krypton, and xenon.

14. The method for processing a semiconductor structure as described in claim 13, characterized in that, The auxiliary gas is a mixture of argon, nitrogen, and carbon monoxide.

15. The method for processing a semiconductor structure as described in claim 1, characterized in that, 19:1≤Third type hole 深宽比 ≤25:1; 14:1≤Second type hole 深宽比 ≤19:1; Class I hole 深宽比 <8:

1.

16. The method for processing a semiconductor structure as described in claim 1, characterized in that, When the stop layer of the third type of hole is etched to the preset depth, the bottom of the first type of hole has a carbon-containing deposition layer with a thickness of 600nm~1000nm; the bottom of the second type of hole has a carbon-containing deposition layer with a thickness of 35nm~45nm; and the bottom of the third type of hole has a carbon-containing deposition layer with a thickness of 1nm~10nm.

17. The method for processing a semiconductor structure as described in claim 1, characterized in that, The base layer is a stacked structure. In the slope structure, the side edge of each stack extends outward relative to the side edge of the stack above it. The upper surface of the extension formed by each stack is farther from the top outer surface of the dielectric layer than the upper surface of the extension formed by the stack above it. Multiple extensions form a step shape, making the slope structure step-like.

18. The method for processing a semiconductor structure as described in claim 17, characterized in that, The stacked layer comprises at least a conductor layer and an insulating layer, the uppermost layer of the stacked structure is a conductor layer, the conductor layer is a polycrystalline silicon layer or a conductive metal layer, and the insulating layer is a silicon oxide layer.

19. A semiconductor structure, characterized in that, include: Substrate; A base layer is formed on a substrate, the base layer having a sloped structure that gradually extends outward from the top surface toward the substrate; A stop layer is applied over the slope structure. as well as A dielectric layer is disposed on the cutoff layer, and a plurality of first-type holes, second-type holes and third-type holes with different aspect ratios are formed on the dielectric layer by the method described in any one of claims 1-18, and a carbon-containing deposition layer of a predetermined thickness is formed on the cutoff layer.

20. The semiconductor structure as claimed in claim 19, characterized in that, The stop layer comprises a nitride, which is selected from at least one of SiN, AlN, GaN, InN, AlN, AlGaN, InGaN, and InGaAlN.

21. The semiconductor structure as claimed in claim 19, characterized in that, The dielectric layer is a silicon oxide layer.

22. A semiconductor processing apparatus, characterized in that, include: Etching cavity, used to process the substrate; Gas supply assembly for introducing reaction gases; Source RF and bias RF; as well as A control unit is used to control the steps of the processing method as described in any one of claims 1-18.

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