Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to reduce the thickness of the semiconductor structure. A semiconductor layer of the semiconductor structure is arranged on the stacked structure in a stacked mode, the channel structure comprises a semiconductor column, the semiconductor column penetrates through the stacked structure, and the semiconductor column extends into the semiconductor layer; and the lengths of the semiconductor columns of the plurality of channel structures extending into the semiconductor layer are the same. According to the semiconductor structure provided by the embodiment of the invention, the lengths of the channel structures extending into the semiconductor layer are the same, the lengths of the channel structures are unequal, and the thickness of the semiconductor layer is set to be larger in order to adapt to the channel structures with larger lengths, so that the thickness of the semiconductor layer can be reduced by the semiconductor structure provided by the embodiment of the invention, and the thickness of the semiconductor structure is further reduced. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to increase storage density by arranging storage cells three-dimensionally on a substrate.

[0004] During the preparation of the semiconductor structure, a channel structure needs to be formed on the stacked structure. However, the lengths of the multiple channel structures formed are different, which results in a relatively large thickness of the semiconductor structure. Summary of the invention

[0005] Embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, a storage system, and an electronic device, aiming to reduce the thickness of the semiconductor structure.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] On the one hand, an embodiment of the present application provides a semiconductor structure. The semiconductor structure includes a stacked structure, a semiconductor layer, and a channel structure, wherein the semiconductor layer is stacked on the stacked structure; the channel structure includes a semiconductor column and a dielectric layer covering the sidewall of the semiconductor column, the semiconductor column penetrates the stacked structure and extends into the semiconductor layer, and there are multiple channel structures, and the semiconductor columns of each channel structure extend into the semiconductor layer by the same length, and the dielectric layer is located between the semiconductor column and the stacked structure; the semiconductor column includes a first column covered by the dielectric layer, and a second column located outside the dielectric layer, the first column penetrates the stacked structure, the second column is located at one end of the first column, and the second column is located in the semiconductor layer.

[0008] The semiconductor structure provided by the embodiment of the present application, the semiconductor layers are stacked and arranged on the stack structure, the channel structure includes a semiconductor column and a dielectric layer covering the side wall of the semiconductor column, the semiconductor column passes through the stack structure, the dielectric layer is located between the semiconductor column and the stack structure, and the semiconductor column extends into the semiconductor layer; the semiconductor column includes a first column covered by the dielectric layer, and a second column located outside the dielectric layer, the first column passes through the stack structure, the second column is located at one end of the first column, and the second column is located in the semiconductor layer; there are multiple channel structures, and the semiconductor columns of the multiple channel structures extend into the semiconductor layer with the same length. Through the above-mentioned setting, the length of each channel structure extending into the semiconductor layer is the same, and the length of each channel structure is different. In order to adapt to the longer channel structure, the thickness of the semiconductor layer is set to be larger. Compared with the semiconductor structure provided by the embodiment of the present application, the thickness of the semiconductor layer can be reduced, thereby reducing the thickness of the semiconductor structure.

[0009] In some embodiments, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer which are stacked, the first semiconductor layer is located between the second semiconductor layer and the stacked structure, and at least a portion of the second column is located in the second semiconductor layer.

[0010] During the preparation of the semiconductor structure, the second column is located on the side of the first semiconductor layer away from the stacking structure. During the formation of the second semiconductor layer, it can be ensured that the second semiconductor layer wraps part of the second column after formation to achieve the connection between the semiconductor layer and the semiconductor column.

[0011] In some embodiments, a portion of the first pillar is located within the first semiconductor layer.

[0012] Through the above arrangement, the second column connected to the first column can be at least partially located on the side of the first semiconductor layer away from the stacking structure, thereby ensuring the connection between the second column and the second semiconductor layer.

[0013] In some embodiments, the semiconductor structure further includes a first gate gap structure and a second gate gap structure, both of which penetrate the stacked structure, and the first gate gap structure and the second gate gap structure are spaced apart.

[0014] Through the above arrangement, the first gate gap structure and the second gate gap structure can support the stacked structure and improve the stability of the semiconductor structure.

[0015] In some embodiments, the channel structure includes a storage channel structure and a dummy channel structure, the storage channel structure is located between the first gate gap structure and the second gate gap structure, and the dummy channel structure is spaced apart from the storage channel structure.

[0016] Through the above arrangement, the storage channel structure is located between the first gate gap structure and the second gate gap structure, the storage channel structure is used for writing or reading through the storage unit, the virtual channel structure is spaced apart from the storage channel structure, and the virtual channel structure is used to support the semiconductor structure and improve the stability of the semiconductor structure.

[0017] In some embodiments, the first gate gap structure includes a filling column and an insulating isolation layer, and the insulating isolation layer is disposed between the filling column and a sidewall of the stack structure.

[0018] Through the above arrangement, the filling column can be used to support the semiconductor structure, and the insulating isolation layer is arranged between the filling column and the side wall of the stacked structure, so that the filling column can be insulated from the gate line layer through the insulating isolation layer to separate the gate line layer.

[0019] In some embodiments, the filling column includes a first filling column covered by the insulating isolation layer and a second filling column located outside the insulating isolation layer, the first filling column penetrates the stacked structure, and the second filling column is located in the semiconductor layer.

[0020] Through the above setting, the insulating isolation layer is located between the first filling column and the stacking structure to achieve insulation between the first filling column and the gate line layer. The first filling column runs through the stacking structure, and the first filling column is connected to the semiconductor layer through the second filling column, so that the entire filling column provides support for the semiconductor layer, thereby improving the stability of the semiconductor layer.

[0021] In some embodiments, a semiconductor layer corresponding to the second filling column has a protrusion.

[0022] Through the above arrangement, the semiconductor layer covers the second filling column to form a protrusion, ensuring that the semiconductor layer covers the top and side walls of the second filling column, increasing the connection area between the second filling column and the semiconductor layer, and improving the stability of the connection between the second filling column and the semiconductor layer.

[0023] In some embodiments, the semiconductor structure also includes a connecting structure and an insulating covering layer, the connecting structure passes through the stacking structure, the insulating covering layer is stacked on the semiconductor layer, and part of the insulating covering layer passes through the semiconductor layer and covers the connecting structure; the semiconductor structure also includes a conductive column, which passes through the insulating covering layer and is connected to the connecting structure.

[0024] Through the above-mentioned arrangement, the connection structure passes through the stacking structure and is used to be electrically connected to the gate line layer. The insulating covering layer is stacked on the semiconductor layer and is used to insulate and package the semiconductor structure. Part of the insulating covering layer is located between the conductive column and the semiconductor layer to achieve insulation between the conductive column and the semiconductor layer. The other end of the conductive column is located at one end of the insulating covering layer away from the stacking structure 310, and is used to achieve electrical connection between the connection structure and the peripheral circuit.

[0025] On the other hand, an embodiment of the present application further provides a method for preparing a semiconductor structure, comprising:

[0026] A first intermediate layer and an initial stacking structure are stacked on the substrate, wherein the first intermediate layer is located between the substrate and the stacking structure;

[0027] forming a channel hole on the initial stacked structure so that the channel hole extends into the substrate;

[0028] An initial channel structure is formed in the channel hole, the initial channel structure comprising a semiconductor column and a dielectric layer covering the side wall of the semiconductor column, the semiconductor column is arranged in the channel hole, and the dielectric layer is located between the semiconductor column and the hole wall of the channel hole;

[0029] forming a stacked structure;

[0030] Removing the substrate and a portion of the initial channel structure in the substrate, and removing a portion of the first intermediate layer and a portion of the dielectric layer corresponding to the first intermediate layer, so as to expose a portion of the semiconductor column to form a channel structure;

[0031] A semiconductor layer is stacked on the stack structure, and the semiconductor layer wraps the exposed portion of the semiconductor column so that the exposed portion of the semiconductor column is located in the semiconductor layer.

[0032] In some embodiments, removing the substrate and a portion of the channel structure in the substrate, and removing the first intermediate layer and a dielectric layer corresponding to the first intermediate layer includes:

[0033] Remove the substrate;

[0034] Part of the initial channel structure is removed by a one-step isotropic gas etching method.

[0035] The first intermediate layer is exposed by removing the substrate, and a portion of the channel structure located in the first intermediate layer away from the stacking structure is exposed, so that a portion of the initial channel structure is removed by a one-step isotropic gas etching method. After the one-step isotropic gas etching method, the end of the remaining initial channel structure away from the stacking structure is flush with the remaining first intermediate layer.

[0036] In some embodiments, before forming the stacked structure on the substrate, the method further includes: forming a first semiconductor layer on the first intermediate layer;

[0037] Forming a semiconductor layer stacked on the stacked structure includes: forming a second semiconductor layer on the first semiconductor layer, and the second semiconductor layer wraps the exposed part of the semiconductor column.

[0038] Through the above arrangement, in the process of forming the second semiconductor layer, it can be ensured that the second semiconductor layer wraps part of the semiconductor column after formation, thereby realizing the connection between the semiconductor layer and the semiconductor column.

[0039] In some embodiments, the second semiconductor layer is annealed.

[0040] Through the above arrangement, single crystal silicon can be converted into polycrystalline silicon, the stability of the second semiconductor layer can be improved, and the first semiconductor layer and the second semiconductor layer can be made into an integrated structure.

[0041] In some embodiments, before forming the second semiconductor layer, the method further includes: forming a second intermediate layer on the first semiconductor layer, partially filling the second intermediate layer in the hole, and removing the second intermediate layer on the first semiconductor layer.

[0042] Through the above arrangement, in the process of forming the second intermediate layer, part of the second intermediate layer completely fills the semiconductor column to form a supporting portion of the channel structure, providing support for the channel structure. Part of the second intermediate layer is filled in the hole, and the second intermediate layer on the first semiconductor layer is removed, so as to facilitate the formation of the second semiconductor layer on the first semiconductor layer.

[0043] In some embodiments, forming an initial channel structure in the channel hole includes:

[0044] A dielectric layer is formed on the hole wall of the channel hole, and a semiconductor column is formed on the dielectric layer, wherein the semiconductor column surrounds the hole;

[0045] Fill the hole with intermediate supports.

[0046] Through the above arrangement, the intermediate support portion can support the initial channel structure, thereby improving the stability of the initial channel structure during the process of removing a portion of the initial channel structure located in the substrate.

[0047] In some embodiments, during the process of removing the first intermediate layer and the dielectric layer corresponding to the first intermediate layer, the intermediate support portion is removed to simplify the preparation process of the semiconductor structure.

[0048] In some embodiments, after forming the second semiconductor layer, the method further includes: forming a third intermediate layer on the semiconductor layer, forming a through hole on the third intermediate layer, and penetrating the through hole to a connection structure in the stacked structure, wherein the connection structure is located inside a projection of the through hole on the stacked structure;

[0049] An insulating cover layer is formed on the third intermediate layer, and a portion of the insulating cover layer fills the through hole.

[0050] Through the above arrangement, the third intermediate layer can achieve insulation on the side of the semiconductor layer away from the stacked structure. The connection structure is located inside the projection of the through hole on the stacked structure, so that one end of the connection structure extending out of the stacked structure is completely located in the through hole, so that there is no connection between the connection structure and the semiconductor layer, and electrical connection between the connection structure and the semiconductor layer is prevented. Part of the insulating cover layer is filled in the through hole to form a conductive column connected to the connection structure.

[0051] In some embodiments, a first gate gap and a second gate gap are arranged at intervals on the initial stack structure, the channel hole is located between the first gate gap and the second gate gap, the first gate gap is arranged in the first gate gap, and the second gate gap structure is arranged in the second gate gap; the first gate gap structure includes a filling column and an insulating isolation layer;

[0052] Removing the substrate and the channel structure in the substrate further includes: removing the insulating isolation layer in the substrate and a portion of the filling column in the substrate to expose a portion of the filling column;

[0053] The forming of the semiconductor layer stacked on the stacked structure further includes: the semiconductor layer covers the exposed portion of the filling column, so that the filling column forms a protrusion on the semiconductor layer.

[0054] During the preparation process of the semiconductor structure, an initial stacking structure is provided with a first gate gap and a second gate gap that penetrate the initial stacking structure. The gate replacement layer in the initial stacking structure can be replaced with a gate line layer through the first gate gap and the second gate gap. Then, a first gate gap structure is formed in the first gate gap and a second gate gap structure is formed in the second gate gap. Since the first gate gap and the second gate gap are arranged at intervals, the first gate gap structure and the second gate gap structure are arranged at intervals. The interval-arranged first gate gap and the second gate gap increase the efficiency of replacing the gate replacement layer with the gate line layer.

[0055] On the other hand, an embodiment of the present application further provides a storage system, including a semiconductor structure and a controller, wherein the semiconductor structure is the semiconductor structure as described above; the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0056] On the other hand, an embodiment of the present application further provides an electronic device, comprising the above storage system.

[0057] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method, storage system and electronic device provided by the above embodiments of the present application can refer to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0059] Figure 1 A schematic diagram of a three-dimensional structure of a three-dimensional memory in some embodiments of the present application;

[0060] Figure 2 A cross-sectional view of a three-dimensional memory in some embodiments of the present application;

[0061] Figure 3 for Figure 1 A cross-sectional view of a memory cell string in the three-dimensional memory along the section line AA' shown;

[0062] Figure 4 An equivalent circuit diagram of a memory cell string in some embodiments of the present application;

[0063] Figure 5 A schematic cross-sectional view of a semiconductor structure in some embodiments of the present application;

[0064] Figure 6 for Figure 5 The enlarged view of point A in the middle;

[0065] Figure 7 A flowchart of a method for preparing a semiconductor structure in some embodiments of the present application;

[0066] Fig. 8A A schematic structural diagram of an initial semiconductor structure provided in the method provided in an embodiment of the present application;

[0067] Figure 8B This is a schematic diagram of the structure after the substrate is removed in the method provided in an embodiment of the present application;

[0068] Figure 8C A schematic diagram of the structure after one step of isotropic gas etching in the method provided in an embodiment of the present application;

[0069] Fig.8D This is a schematic diagram of the structure after the remaining intermediate support portion is removed in the method provided in an embodiment of the present application;

[0070] Fig. 8E A schematic diagram of the structure after the second intermediate layer is formed in the method provided in an embodiment of the present application;

[0071] Fig.8F This is a schematic diagram of the structure after a portion of the second intermediate layer is removed in the method provided in an embodiment of the present application;

[0072] Figure 8G A schematic diagram of the structure after the second semiconductor layer is formed in the method provided in an embodiment of the present application;

[0073] Figure 8H This is a schematic diagram of the structure after the third intermediate layer is formed in the method provided in an embodiment of the present application;

[0074] Figure 8I A schematic diagram of the structure after a through hole is formed on the third intermediate layer in the method provided in an embodiment of the present application;

[0075] Figure 8J A schematic diagram of the structure after a through hole is formed on a semiconductor in the method provided in an embodiment of the present application;

[0076] Figure 8K A schematic diagram of the structure after a conductive column is formed in the method provided in an embodiment of the present application;

[0077] Fig. 9 is a block diagram of a storage system according to some embodiments;

[0078] Fig.10 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0079] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0080] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0081] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0082] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0083] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments invented here are not necessarily limited to the contents of this document.

[0084] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0085] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0086] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0087] In the context of this application, the meaning of "on", "above", and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intervening features or layers in between (i.e., directly on something).

[0088] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0089] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0090] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0091] Please refer to Figure 1 and Figure 2 , the three-dimensional memory 10 extends in the XY plane, the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (for example, the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XY plane.

[0092] As used in this application, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor device in a third direction Z when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concept is applied throughout the content of this application to describe spatial relationships.

[0093] In order to more clearly illustrate the structure of the device, Figure 2In the figure, a view of the array area CA and a view of the connection area SS are shown. The view of the array area CA is based on the left coordinate system, and the view of the connection area SS is based on the right coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Y direction, and the view of the connection area SS shows the cross-sectional structure along the X direction.

[0094] Reference Figure 1 and Figure 2 Some embodiments of the present application provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The three-dimensional memory 10 may also include a peripheral device 100 coupled to the semiconductor structure 200. The semiconductor structure 200 includes a source layer SL, and the peripheral device 100 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

[0095] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0096] The semiconductor structure 200 may include memory cell transistor strings (referred to herein as “channel structures”) 400 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400 .

[0097] In some embodiments, please refer to Figure 3 and Figure 4 , the memory cell string 400 may include a plurality of transistors T, a transistor T (eg Figure 4 The transistors T1 to T6 in the figure can be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (for example, each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor.

[0098] Understandably, Figure 1 to Figure 4 The number of transistors is only illustrative. The storage cell string of the three-dimensional memory provided in the embodiment of the present application may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0099] In some embodiments, along the third direction Z, the gate line located at the bottom of the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. The gate line located at the top of the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The gate line located in the middle of the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. Data writing, reading, and erasing of corresponding memory cells (for example, transistors T) in the memory cell string 400 can be completed through the word lines WL.

[0100] Continue to refer to Figure 1 and Figure 2 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 400, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

[0101] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292, the contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0102] The peripheral device 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0103] In some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0104] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0105] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The material of the second interconnect conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0106] The peripheral interconnect layer 130 may be coupled to the array interconnect layer 290, so that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the peripheral device 100 may be coupled to the memory cell string in the semiconductor structure 200 to achieve transmission of electrical signals between the peripheral circuit and the memory cell string. In some possible implementations, a bonding interface 500 may be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 may be bonded and coupled to each other through the bonding interface 500.

[0107] Please refer to Figure 5 , Figure 5 is a schematic cross-sectional view of a semiconductor structure according to some embodiments.

[0108] The semiconductor structure 200 provided in the embodiment of the present application may include a stacked structure 310, and one side of the stacked structure 310 is used to couple with a wafer layer 280. The wafer layer 280 includes a peripheral circuit wafer, which may also be called a complementary metal oxide semiconductor (CMOS) wafer. The CMOS wafer includes a peripheral circuit for signal transmission to a storage unit.

[0109] The stacked structure 310 may include alternately stacked gate line layers 311 and gate dielectric layers 312. In some embodiments, the gate line layers 311 may include a conductive material, for example, at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. The gate dielectric layer 312 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0110] For ease of description, Figure 5 The number of gate line layers 311 in the stacked structure 310 is three. In some embodiments, the stacked structure 310 may include multiple gate line layers 311 and multiple gate dielectric layers 312. Exemplarily, the number of gate line layers 311 in the stacked structure 310 may be 32, 48, 64, 96, 128, 256, 300, etc., and the number of gate dielectric layers 312 in the stacked structure 310 may be 32, 48, 64, 96, 128, 256, 300, etc.

[0111] Continue to refer to Figure 5In the above embodiment, the semiconductor structure 200 may further include a semiconductor layer 320 and a channel structure 330, wherein the semiconductor layer 320 is stacked on the stack structure 310, and the semiconductor layer 320 is located on the side of the stack structure 310 away from the wafer layer 280. The channel structure 330 runs through the stack structure 310, one end of the channel structure 330 is connected to the wafer layer 280, and the other end of the channel structure 330 extends into the semiconductor layer 320; the channel structure 330 may be provided with multiple, and the ends of each channel structure 330 extending into the semiconductor layer 320 are all located on the same plane. It should be noted that when the height difference of each channel structure 330 is less than or equal to 20nm, it can be considered that the ends of each channel structure extending into the semiconductor layer 320 are located in the same plane. Multiple channel structures 330 are electrically connected through the semiconductor layer 320. A storage unit is formed between the channel structure 330 and each gate line layer 311 to realize data storage, and at the same time, the semiconductor structure has a higher storage density.

[0112] In some embodiments, the channel structure 330 may include a semiconductor column 340 , which penetrates the stack structure 310 and has one end extending into the semiconductor layer 320 . The semiconductor columns 340 of each channel structure 330 extend into the semiconductor layer 320 by the same length.

[0113] Please refer to Figure 6 , wherein the semiconductor column 340 includes a first column 341 and a second column 342, the first column 341 passes through the stacked structure 310, and one end of the first column 341 extends into the semiconductor layer 320, the second column 342 is located in the semiconductor layer 320, and is connected to the end of the first column 341 extending into the semiconductor layer 320, the second column 342 and the first column 341 have the same extension direction, and the first column 341 and the second column 342 can be an integral structure.

[0114] Exemplarily, the semiconductor pillar 340 may include at least one of polycrystalline silicon or single crystal silicon; that is, the material of the first pillar 341 and the second pillar 342 may include at least one of polycrystalline silicon or single crystal silicon. In some embodiments, the material of the first pillar 341 and the second pillar 342 may be the same.

[0115] Continue to refer to Figure 6In the above implementation, the semiconductor column 340 can be a solid column or a hollow column. When the semiconductor column 340 is a hollow column, the channel structure 330 can also include a support portion 331. The support portion 331 can be located inside the semiconductor column 340, that is, the semiconductor column 340 surrounds the support portion 331, and the support portion 331 can provide support for the channel structure 330. Among them, the support portion 331 can include an insulating material, such as silicon oxide. In the implementation in which the semiconductor column 340 includes a first column 341 and a second column 342, the hollow column formed by the first column 341 has the support portion 331 inside, and the hollow column formed by the second column 342 has the semiconductor layer 320 inside. The inner wall, outer wall of the hollow column formed by the second column 342 and the end of the second column 342 away from the first column 341 can all be connected to the semiconductor layer 320, thereby increasing the connection area between the entire semiconductor column 340 and the semiconductor layer 320.

[0116] The semiconductor structure 200 provided in the embodiment of the present application has a semiconductor layer 320 stacked on a stack structure 310, and a channel structure 330 includes a semiconductor column 340 and a dielectric layer 332 covering the side wall of the semiconductor column 340, the semiconductor column 340 passes through the stack structure, the dielectric layer is located between the semiconductor column 340 and the stack structure 310, and the semiconductor column 340 extends into the semiconductor layer 320; the semiconductor column 340 includes a first column 341 covered by the dielectric layer, and a second column 342 located outside the dielectric layer, the first column 341 passes through the stack structure 310, the second column 342 is located at one end of the first column 341, and the second column 342 is located in the semiconductor layer 320; there are multiple channel structures 330, and the semiconductor columns 340 of the multiple channel structures 330 extend into the semiconductor layer 320 by the same length. Through the above-mentioned setting, the lengths of each channel structure 330 extending into the semiconductor layer 320 are the same, and the lengths of each channel structure 330 are different. In order to adapt to the longer channel structure 330, the thickness of the semiconductor layer 320 is set to be larger. The semiconductor structure 200 provided in the embodiment of the present application can reduce the thickness of the semiconductor layer 320, and thus reduce the thickness of the semiconductor structure 200.

[0117] Please refer to Figure 5 and Figure 6 In the above implementation, the channel structure 330 may also include a dielectric layer 332 covering the side wall of the semiconductor column 340, and the dielectric layer 332 is located between the semiconductor column 340 and the stacked structure 310. In the implementation in which the semiconductor column 340 includes a first column 341 and a second column 342, the dielectric layer 332 may cover the first column 341, that is, the dielectric layer 332 is located between the first column 341 and the stacked structure 310.

[0118] The above-mentioned dielectric layer 332 may include a tunneling layer 3321, a charge storage layer 3322 and a blocking layer 3323, wherein the tunneling layer 3321, the charge storage layer 3322 and the blocking layer 3323 are arranged in sequence in the direction from the semiconductor column 340 to the stacked structure 310, wherein the tunneling layer 3321 covers the side wall of the semiconductor column 340, the charge storage layer 3322 is located between the tunneling layer 3321 and the blocking layer 3323, and the blocking layer 3323 is located between the charge storage layer 3322 and the stacked structure 310.

[0119] Exemplarily, the tunneling layer 3321 may include at least one of silicon oxide and metal oxide; the charge storage layer 3322 may include at least one of silicon nitride and silicon oxynitride; the blocking layer 3323 may include at least one of silicon oxide and metal oxide. In some embodiments, the dielectric layer 332 may have a layered structure of oxide-nitride-oxide.

[0120] Continue to refer to Figure 5 and Figure 6 In the embodiment of the present application, the semiconductor layer 320 includes a first semiconductor layer 321 and a second semiconductor layer 322 which are stacked, and the first semiconductor layer 321 is located between the second semiconductor layer 322 and the stack structure 310; at least part of the second pillar 342 is located in the second semiconductor layer 322. During the preparation of the semiconductor structure 200, the second pillar 342 is located on a side of the first semiconductor layer 321 away from the stack structure. During the formation of the second semiconductor layer 322, it can be ensured that the second semiconductor layer 322 wraps part of the second pillar 342 after formation, thereby achieving the connection between the semiconductor layer 320 and the semiconductor pillar 340.

[0121] In which, the semiconductor layer 320 may include at least one of polycrystalline silicon or single crystal silicon, the first semiconductor layer 321 and the second semiconductor layer 322 are made of the same material. In some embodiments, the first semiconductor layer 321 and the second semiconductor layer 322 are an integrated structure. During the preparation process of the semiconductor structure 200, the second semiconductor layer 322 is formed on the first semiconductor layer 321 to form the semiconductor layer 320.

[0122] In the implementation method in which the semiconductor column 340 includes a first column 341 and a second column 342, part of the first column 341 is located in the first semiconductor layer 321; through the above-mentioned arrangement, the second column 342 connected to the first column 341 can be at least partially located on the side of the first semiconductor layer 321 away from the stacking structure 310, thereby ensuring the connection between the second column 342 and the second semiconductor layer 322.

[0123] Continue to refer to Figure 5 and Figure 6In the embodiment of the present application, the semiconductor structure 200 also includes a first gate gap structure 350 and a second gate gap structure 360, and the first gate gap structure 350 and the second gate gap structure 360 ​​both penetrate the stacking structure 310, that is, the first gate gap structure 350 and the second gate gap structure 360 ​​can disconnect the gate line layer 311 and the gate dielectric layer 312, and the first gate gap structure 350 and the second gate gap structure 360 ​​are arranged at intervals to support the stacking structure 310 and improve the stability of the semiconductor structure 200.

[0124] In the above embodiment, the first gate gap structure 350 includes a filling column 351 and an insulating isolation layer 352. The filling column 351 can support the semiconductor structure 200. The filling column 351 can include at least one of metal (such as tungsten, copper, aluminum, etc.), metal silicide, metal nitride, and doped polysilicon. The insulating isolation layer 352 is disposed between the filling column 351 and the sidewall of the stacked structure 310. The filling column 351 can be insulated from the gate line layer 311 by the insulating isolation layer 352 to divide the gate line layer 311. The insulating isolation layer 352 can include at least one of silicon oxide and metal oxide. It can be understood that the second gate gap structure 360 ​​has the same structure as the first gate gap structure 350.

[0125] Continue to refer to Figure 5 and Figure 6 In the above embodiment, the filling column 351 includes a first filling column 3511 and a second filling column 3512. The first filling column 3511 penetrates the stacking structure 310, and one end of the first filling column 3511 extends into the semiconductor layer 320. The second filling column 3512 is located in the semiconductor layer 320 and is connected to one end of the first filling column 3511 extending into the semiconductor layer 320. The second filling column 3512 extends in the same direction as the first filling column 3511. The first filling column 3511 and the second filling column 3512 can be an integral structure. Through the above arrangement, the first filling column 3511 penetrates the stacking structure 310, and the first filling column 3511 is connected to the semiconductor layer 320 through the second filling column 3512, so that the entire filling column 351 provides support for the semiconductor layer 320, thereby improving the stability of the semiconductor layer 320.

[0126] In the implementation mode where the filling column 351 includes a first filling column 3511 and a second filling column 3512, the sidewall of the first filling column 3511 is covered by the insulating isolation layer 352, that is, the insulating isolation layer 352 is located between the first filling column 3511 and the stacked structure 310 to achieve insulation between the first filling column 3511 and the gate line layer 311. The second filling column 3512 is located in the semiconductor layer 320. Through the above arrangement, the first filling column 3511 penetrates the stacked structure 310, and the first filling column 3511 is connected to the semiconductor layer 320 through the second filling column 3512, so that the entire filling column 351 provides support for the semiconductor layer 320, thereby improving the stability of the semiconductor layer 320.

[0127] In some embodiments, there is a protrusion on the semiconductor layer 320 corresponding to the second filling column 3512. That is, the semiconductor layer 320 covers the second filling column 3512 to form a protrusion, ensuring that the semiconductor layer 320 covers the top and sidewall of the second filling column 3512, increasing the connection area between the second filling column 3512 and the semiconductor layer 320, and improving the stability of the connection between the second filling column 3512 and the semiconductor layer 320.

[0128] In an implementation in which the semiconductor structure 200 further includes a first gate gap structure 350 and a second gate gap structure 360, the channel structure 330 includes a storage channel structure and a virtual channel structure, the storage channel structure is located between the first gate gap structure 350 and the second gate gap structure 360, and the storage channel structure is used for writing or reading through a storage unit; the virtual channel structure is spaced apart from the storage channel structure, and the structure of the virtual channel structure is consistent with that of the storage channel structure, but the virtual channel structure is located in a connection area, and is used to support the semiconductor structure 200 and improve the stability of the semiconductor structure 200.

[0129] Continue to refer to Figure 5In the embodiment of the present application, the semiconductor structure 200 further includes a connection structure 370 and an insulating cover layer 380. The connection structure 370 penetrates the stacked structure 310 and is used to be electrically connected to the gate line layer 311. The connection structure 370 may include at least one of metal (such as tungsten, copper, aluminum, etc.), metal silicide, metal nitride, and doped polysilicon. The insulating cover layer 380 is stacked on the semiconductor layer 320 to insulate and package the semiconductor structure 200. The insulating cover layer 380 may include at least one of silicon oxide and metal oxide. Part of the insulating covering layer 380 passes through the semiconductor layer 320 and covers the connecting structure 370; the semiconductor structure 200 also includes a conductive column 390, one end of the conductive column 390 passes through the insulating covering layer 380 and is connected to the connecting structure 370, and part of the insulating covering layer 380 is located between the conductive column 390 and the semiconductor layer 320 to achieve insulation between the conductive column 390 and the semiconductor layer 320, and the other end of the conductive column 390 is located at one end of the insulating covering layer 380 away from the stacking structure 310, which is used to achieve electrical connection between the connecting structure 370 and the peripheral circuit.

[0130] In the above implementation, the semiconductor structure 200 may further include a lead-out structure (not shown), which passes through the insulating cover layer 380 and the third intermediate layer 510 located between the insulating cover layer 380 and the semiconductor layer 320, so that one end of the lead-out structure is connected to the semiconductor layer 320, and the lead-out structure is used to lead out the semiconductor layer 320 to achieve connection between the semiconductor layer 320 and the peripheral circuit.

[0131] The present application also provides a method for preparing a semiconductor structure. Figure 7 , the preparation method may include steps S100 to S600:

[0132] S100: forming a first intermediate layer and an initial stacking structure by stacking on a substrate, wherein the first intermediate layer is located between the substrate and the initial stacking structure.

[0133] Please refer to Fig. 8A In step S100, forming a first intermediate layer and an initial stacking structure by stacking on a substrate may include:

[0134] The first intermediate layer 420, the first semiconductor layer 321 and the initial stacking structure are formed on the substrate 410 by a thin film deposition process. The material of the first intermediate layer 420 is oxide, for example, silicon oxide or metal oxide.

[0135] The initial stacking structure may include alternately stacked gate replacement layers (not shown) and gate dielectric layers 312. "Alternately stacking" means that after a gate dielectric layer 312 is formed on the substrate, a gate replacement layer is formed on the gate dielectric layer 312, and then a gate dielectric layer 312 is formed on the gate replacement layer, and then the above steps are repeated.

[0136] Exemplarily, the thin film deposition process may include a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electroplating processes.

[0137] S200: forming a channel hole on the initial stacked structure, so that the channel hole extends into the substrate.

[0138] Continue to refer to Fig. 8A In step S200, a channel hole (not shown) is formed on the alternately stacked gate replacement layer and gate dielectric layer 312. The channel hole can be formed by etching. The etched channel hole extends into the substrate 410 to ensure that the channel structure 330 formed in the channel hole can penetrate the initial stacking structure.

[0139] S300: forming an initial channel structure in the channel hole, the initial channel structure comprising a semiconductor column and a dielectric layer covering the sidewall of the semiconductor column, the semiconductor column penetrates the channel hole, and the dielectric layer is located between the semiconductor column and the hole wall of the channel hole.

[0140] In step S300, forming an initial channel structure in the channel hole includes:

[0141] Continue to refer to Fig. 8A , a dielectric layer 332 is formed on the hole wall of the channel hole, and a semiconductor column 340 is formed on the dielectric layer 332, and the semiconductor column 340 surrounds the hole. Then, an intermediate support portion 430 is filled in the hole. The intermediate support portion 430 can support the initial channel structure 330a, and improve the stability of the initial channel structure 330a in the process of removing a portion of the initial channel structure 330a located in the substrate 410.

[0142] Continue to refer to Fig. 8A In some embodiments, the semiconductor column 340 may be a hollow column, and a hole is formed inside the semiconductor column 340. The hole formed by the semiconductor column 340 may be filled with an intermediate support portion 430, wherein the intermediate support portion 430 may completely fill the semiconductor column 340 or partially fill the semiconductor column 340. Fig. 8A In the embodiment, the intermediate supporting portion 430 fills a portion of the interior of the semiconductor pillar 340 .

[0143] S400: forming a stacking structure.

[0144] Continue to refer to Fig. 8AAfter forming the channel structure 330, a first gate gap (not shown) and a second gate gap (not shown) can also be formed on the initial stacking structure, wherein the first gate gap and the second gate gap both penetrate the alternately stacked gate replacement layer and the gate dielectric layer 312 and extend into the substrate 410, and the first gate gap and the second gate gap are arranged at intervals on the initial stacking structure so that the channel hole is located between the first gate gap and the second gate gap.

[0145] The gate replacement layer is replaced with a gate line layer 311 through the first gate slit and the second gate slit to form a stacked structure 310 .

[0146] After the stacked structure 310 is formed, a first gate gap structure 350 is formed in the first gate gap, and a second gate gap structure 360 ​​is formed in the second gate gap. Since both the first gate gap and the second gate gap pass through the alternately stacked gate replacement layer and the gate dielectric layer 312 and extend into the substrate 410, one end of the first gate gap structure 350 is located in the substrate 410, and one end of the second gate gap structure 360 ​​is also located in the substrate 410.

[0147] After forming the stack structure 310, a connection structure 370 may be formed in the stack structure 310. The connection structure 370 penetrates the stack structure 310, and one end of the connection structure 370 extends out of the stack structure 310 and is connected to the first column 341. The stack structure 310 is coupled to the wafer layer 280, so that the substrate 410 is located at the top, and the first intermediate layer 420, the first semiconductor layer 321, and the stack structure 310 are arranged downward in sequence.

[0148] S500: removing the substrate and a portion of the initial channel structure in the substrate, and removing a portion of the first intermediate layer and a portion of the dielectric layer corresponding to the first intermediate layer to expose a portion of the semiconductor pillar to form a channel structure.

[0149] Step S500 may include:

[0150] Remove the substrate. Figure 8B After removing the substrate 410 , the first intermediate layer 420 is exposed, and a portion of the channel structure, a portion of the first gate gap structure 350 , and a portion of the second gate gap structure 360 ​​located in the first intermediate layer 420 away from the stack structure 310 are exposed.

[0151] A portion of the initial channel structure 330a is removed by a one-step isotropic gas etching method.

[0152] Please compare Figure 8B and Figure 8C The direction of the one-step isotropic gas etching is parallel to the stacked structure 310, and the one-step isotropic gas etching includes ONOPO RM, which removes oxide, nitride, oxide, silicon, and oxide in sequence.

[0153] Removing the oxide layer in a one-step isotropic gas etching process can remove a portion of the first intermediate layer 420, a portion of the barrier layer 3323 of the initial channel structure 330a (eg, Figure 6 As shown), a portion of the insulating isolation layer 352 of the first gate gap structure 350 and the second gate gap structure 360.

[0154] Removing the nitride layer in a one-step isotropic gas etch may remove a portion of the charge storage layer 3322 (eg, Figure 6 shown).

[0155] Removing the oxide layer in a one-step isotropic gas etch may remove a portion of the tunneling layer 3321 (eg, Figure 6 shown).

[0156] Removing silicon in a one-step isotropic gas etching can remove part of the semiconductor column 340 of the initial channel structure 330a, and remove part of the filling column 351 of the first gate gap structure 350 and the second gate gap structure 360. In the process of removing silicon, the volume of the semiconductor column 340 is smaller than the volume of the filling column 351. When the part of the semiconductor column 340 located in the second intermediate layer away from the stacking structure 310 is completely removed, the part of the filling column 351 located in the remaining first intermediate layer 420 away from the stacking structure 310 is not completely removed, so that the filling column 351 includes the first filling column 3511 (such as the first filling column 3511) located on the side of the remaining first intermediate layer 420 close to the stacking structure 310. Figure 6 ) and a second filling column 3512 (as shown) located in the remaining first intermediate layer 420 away from the stacked structure 310 Figure 6 As shown in FIG. 35 , the lateral width of the second filling column 3512 is smaller than the lateral width of the first filling column 3511. In some embodiments, the second filling column 3512 can be completely removed by extending the time for removing silicon.

[0157] Removing the oxide layer in a one-step isotropic gas etch may remove the intermediate support portion 430 within the initial channel structure 330 a .

[0158] After one step of isotropic gas etching, refer to Figure 8C , one end of the remaining initial channel structure 330 a away from the stack structure 310 is flush with the remaining first intermediate layer 420 .

[0159] In the above implementation, the sequential removal of oxide, nitride, oxide, silicon, and oxide can be performed in the same etching process.

[0160] Please compare Figure 8C and Fig.8D, remove the remaining first intermediate layer 420 and a portion of the dielectric layer located in the remaining first intermediate layer 420 to expose a portion of the semiconductor pillar 340, thereby forming a channel structure 330. A portion of the semiconductor pillar 340 in the channel structure 330 is located on a side of the first semiconductor layer 321 away from the stacking structure, so that the semiconductor pillar 340 includes a first pillar 341 (such as Figure 6 ) and a second column 342 (as shown) located on the side of the first semiconductor layer 321 away from the stacked structure Figure 6 shown).

[0161] In the process of removing the first intermediate layer 420 and the dielectric layer 332 corresponding to the first intermediate layer 420, the intermediate support portion 430 is removed. In some embodiments, the first intermediate layer 420 and the intermediate support portion 430 (eg, Figure 8C ) are removed simultaneously in the same removal process to simplify the preparation process of the semiconductor structure.

[0162] After the above-mentioned isotropic gas etching step, the lengths of the multiple channel structures 330 are consistent, and the channel structures 330 slightly extend out of the first semiconductor layer 321, wherein the length of the channel structure 330 extending out of the first semiconductor layer 321 can be approximately equal to the length of the second column 342, and the length of the second column 342 is determined according to the thickness of the remaining portion of the first intermediate layer 420 after removing the oxide layer in the first step. Therefore, the length of the channel structure 330 can be adjusted by adjusting the thickness of the removed portion of the first intermediate layer 420 and then adjusting the length of the second column 342.

[0163] During step S200 and step S300, that is, forming a channel hole on the stacked structure 310 so that the channel hole extends into the substrate 410 and forming the channel structure 330 in the channel hole, the length of the etched channel hole is equal to the length of the channel structure 330. Since the length of the channel structure 330 can be adjusted during the one-step isotropic gas etching process, the problem of increased thickness of the semiconductor due to excessive length of the etched channel hole is avoided, and there is no need to adjust the lengths of multiple channel holes to be consistent, which simplifies the process of etching the channel holes and opens the process window for forming the channel structure 330.

[0164] Please refer to Fig. 8E , remove the first intermediate layer 420 and the intermediate support portion 430 in the semiconductor column (such as Figure 8C After that, a second intermediate layer 440 is formed on the first semiconductor layer 321. During the formation of the second intermediate layer 440, a portion of the second intermediate layer 440 completely fills the semiconductor pillar 340 to form a supporting portion 331 of the channel structure 330, providing support for the channel structure 330.

[0165] Please refer to Fig.8F After a portion of the second intermediate layer 440 is filled in the hole, the second intermediate layer 440 on the first semiconductor layer 321 is removed to facilitate forming a second semiconductor layer on the first semiconductor layer.

[0166] S600: forming a semiconductor layer on the stacked structure, wherein the semiconductor layer wraps the exposed portion of the semiconductor column, so that the exposed portion of the semiconductor column is located in the semiconductor layer.

[0167] Please refer to Figure 8G , step S500 may include:

[0168] A second semiconductor layer 322 is formed on the first semiconductor layer 321 , and the second semiconductor layer 322 wraps the exposed portion of the semiconductor pillar 340 .

[0169] In the above steps, single crystal silicon can be deposited on the first semiconductor layer 321 to form the second semiconductor layer 322 . During the formation of the second semiconductor layer 322 , it can be ensured that the second semiconductor layer 322 wraps part of the semiconductor column 340 after formation, thereby achieving the connection between the semiconductor layer 320 and the semiconductor column 340 .

[0170] Then, the second semiconductor layer 322 may be annealed to convert the single crystal silicon into polycrystalline silicon, thereby improving the stability of the second semiconductor layer 322 and making the first semiconductor layer 321 and the second semiconductor layer 322 an integrated structure.

[0171] The packing column 351 includes a first packing column 3511 (such as Figure 6 as shown) and a second filling column 3512 (as shown Figure 6 In the embodiment shown in FIG. 1 , since the second filling column 3512 is not completely removed, a protrusion is formed on the semiconductor layer 320 corresponding to the second filling column 3512 .

[0172] The preparation method provided in the embodiment of the present application may further include, after forming the second semiconductor layer 322:

[0173] Please refer to Figure 8H , a third intermediate layer 510 is formed on the semiconductor layer 320 , wherein the third intermediate layer 510 is an insulating material, and the third intermediate layer 510 can achieve insulation of the side of the semiconductor layer 320 away from the stacked structure 310 .

[0174] Please refer to Figure 8I and Figure 8JA through hole 520 is formed on the third intermediate layer 510 and the semiconductor layer 320, and the through hole 520 penetrates to the connection structure 370 in the stacked structure 310. The connection structure 370 is located inside the projection of the through hole 520 on the stacked structure 310, so that one end of the connection structure 370 extending out of the stacked structure 310 can be completely located in the through hole 520, so that there is no connection between the connection structure 370 and the semiconductor layer 320, thereby preventing electrical connection between the connection structure 370 and the semiconductor layer 320.

[0175] An insulating cover layer 380 is formed on the third intermediate layer 510 , and a portion of the insulating cover layer 380 fills the through hole 520 .

[0176] After forming the insulating cover layer 380, the following steps may also be performed:

[0177] Please refer to Figure 8K A conductive hole may be formed on the insulating cover layer 380 , and a conductive material may be filled in the conductive hole to form a conductive column 390 .

[0178] Among them, the conductive hole penetrates the insulating covering layer 380, and one end of the conductive hole penetrates to the connecting structure 370, so that the conductive column 390 formed in the conductive hole is connected to the connecting structure 370; there is a partial insulating covering layer 380 between the formed conductive column 390 and the semiconductor layer 320 to avoid electrical connection between the conductive column 390 and the semiconductor layer 320.

[0179] Fig. 9 is a block diagram of a storage system according to some embodiments. Fig.10 is a block diagram of a storage system according to some other embodiments.

[0180] Please refer to Fig. 9 and Fig.10 Some embodiments of the present application further provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10, wherein the three-dimensional memory 10 may include the semiconductor structure 200 as described above, and the controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0181] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0182] In some embodiments, reference Fig. 9 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0183] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0184] In other embodiments, reference Fig.10 The storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0185] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0186] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0187] In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 10.

[0188] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0189] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0190] Some embodiments of the present application also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0191] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0192] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: Stacked structure; A semiconductor layer, wherein the semiconductor layer is stacked on the stack structure; A channel structure, wherein the channel structure includes a semiconductor column and a dielectric layer covering the side wall of the semiconductor column, the semiconductor column penetrates the stacked structure and extends into the semiconductor layer, the channel structure is provided with a plurality of semiconductor columns of each channel structure extending into the semiconductor layer by the same length, and the dielectric layer is located between the semiconductor column and the stacked structure; the semiconductor column includes a first column covered by the dielectric layer, and a second column located outside the dielectric layer, the first column penetrates the stacked structure, the second column is located at one end of the first column, and the second column is located in the semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor layer includes a first semiconductor layer and a second semiconductor layer which are stacked, the first semiconductor layer is located between the second semiconductor layer and the stacked structure, and at least a portion of the second column is located in the second semiconductor layer.

3. The semiconductor structure according to claim 2, characterized in that: Part of the first pillar is located in the first semiconductor layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes a first gate gap structure and a second gate gap structure. The first gate gap structure and the second gate gap structure both penetrate the stacked structure, and the first gate gap structure and the second gate gap structure are spaced apart.

5. The semiconductor structure according to claim 4, characterized in that: The channel structure includes a storage channel structure and a dummy channel structure. The storage channel structure is located between the first gate gap structure and the second gate gap structure. The dummy channel structure is spaced apart from the storage channel structure.

6. The semiconductor structure according to claim 4, characterized in that: The first gate gap structure includes a filling column and an insulating isolation layer, and the insulating isolation layer is arranged between the filling column and a side wall of the stack structure.

7. The semiconductor structure according to claim 6, characterized in that: The filling column includes a first filling column covered by the insulating isolation layer and a second filling column located outside the insulating isolation layer, the first filling column penetrates the stacked structure, and the second filling column is located in the semiconductor layer.

8. The semiconductor structure according to claim 7, characterized in that: The semiconductor layer corresponding to the second filling column has a protrusion.

9. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes a connection structure and an insulating covering layer, wherein the connection structure penetrates the stacked structure, the insulating covering layer is stacked on the semiconductor layer, and a portion of the insulating covering layer penetrates the semiconductor layer and covers the connection structure; The semiconductor structure further includes a conductive column, which passes through the insulating cover layer and is connected to the connection structure.

10. A method for preparing a semiconductor structure, characterized in that: include: Forming a first intermediate layer and an initial stacking structure by stacking on the substrate, wherein the first intermediate layer is located between the substrate and the stacking structure; forming a channel hole on the initial stacking structure so that the channel hole extends into the substrate; An initial channel structure is formed in the channel hole, wherein the initial channel structure includes a semiconductor column and a dielectric layer covering the sidewall of the semiconductor column, wherein the semiconductor column is disposed in the channel hole, and the dielectric layer is located between the semiconductor column and the hole wall of the channel hole; forming a stacked structure; Removing the substrate and a portion of the initial channel structure located in the substrate, and removing a portion of the first intermediate layer and a portion of the dielectric layer corresponding to the first intermediate layer, so as to expose a portion of the semiconductor column to form a channel structure; A semiconductor layer is stacked on the stack structure, and the semiconductor layer wraps the exposed portion of the semiconductor column so that the exposed portion of the semiconductor column is located in the semiconductor layer.

11. The method according to claim 10, characterized in that Removing the substrate and a portion of the channel structure located in the substrate, and removing the first intermediate layer and the dielectric layer corresponding to the first intermediate layer includes: removing the substrate; A portion of the initial channel structure is removed by one-step isotropic gas etching.

12. The method according to claim 10 or 11, characterized in that: Before forming the stacked structure on the substrate, the method further includes: forming a first semiconductor layer on the first intermediate layer; Forming a semiconductor layer stacked on the stacked structure includes: forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer wraps the exposed portion of the semiconductor column.

13. The method according to claim 12, characterized in that The second semiconductor layer is annealed.

14. The method according to claim 12, characterized in that Before forming the second semiconductor layer, the method further includes: forming a second intermediate layer on the first semiconductor layer, partially filling the second intermediate layer in the hole, and removing the second intermediate layer on the first semiconductor layer.

15. The method according to any one of claims 10 to 12, characterized in that: Forming an initial channel structure in the channel hole includes: Forming a dielectric layer on the hole wall of the channel hole, and forming a semiconductor column on the dielectric layer, wherein the semiconductor column surrounds a hole; The hole is filled with an intermediate support portion.

16. The method according to claim 15, characterized in that In the process of removing the first intermediate layer and the dielectric layer corresponding to the first intermediate layer, the intermediate supporting portion is removed.

17. The method according to any one of claims 10 to 12, characterized in that: After forming the second semiconductor layer, the method further includes: forming a third intermediate layer on the semiconductor layer, forming a through hole on the third intermediate layer, and penetrating the through hole to a connection structure in the stacked structure, wherein the connection structure is located inside a projection of the through hole on the stacked structure; An insulating cover layer is formed on the third intermediate layer, and a portion of the insulating cover layer fills the through hole.

18. The method according to any one of claims 10 to 12, characterized in that: A first gate gap and a second gate gap are arranged on the initial stack structure at intervals, the channel hole is located between the first gate gap and the second gate gap, a first gate gap structure is arranged in the first gate gap, and a second gate gap structure is arranged in the second gate gap; The first gate gap structure includes a filling column and an insulating isolation layer; Removing the substrate and the channel structure located in the substrate further comprises: removing the insulating isolation layer located in the substrate and a portion of the filling column located in the substrate to expose a portion of the filling column; The forming of a semiconductor layer stacked on the stacked structure further includes: the semiconductor layer covers the exposed portion of the filling column, so that the filling column forms a protrusion corresponding to the semiconductor layer.

19. A storage system, characterized in that: include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 9; A controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

20. An electronic device, characterized in that: Comprising the storage system as claimed in claim 19.

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