Three-dimensional memory device and manufacturing method thereof
By adding ferroelectric film to the storage layer of the three-dimensional memory device, and optimizing interlayer isolation using a sandwich structure, the problems of carrier lateral drift and interlayer leakage are solved, and the reliability of the device is significantly improved.
Patent Information
- Application Number
- CN202411703253.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-02-21
AI Technical Summary
During the programming process, existing three-dimensional memory devices are prone to carrier lateral drift and interlayer leakage, resulting in data distortion and poor reliability.
The ferroelectric film is added to the storage layer to optimize the interlayer isolation through a sandwich structure and improve the reliability of the device.
By using ferroelectric film in the storage layer, inter-layer isolation is optimized, which significantly improves the reliability of three-dimensional memory devices and reduces the occurrence of data distortion and storage errors.
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Figure CN119497390A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices, and in particular to a three-dimensional storage device and a manufacturing method thereof. Background Art
[0002] Three-dimensional memory uses a vertically stacked storage unit design to expand the dimensions of the storage unit from the original two dimensions to three dimensions, thereby greatly improving the storage density and storage capacity.
[0003] Existing three-dimensional memory devices mostly use oxide-silicon nitride-oxide (ONO) structures. Especially when programming three-dimensional flash memory devices, carrier lateral drift and other phenomena will occur, resulting in data distortion and storage errors of the memory devices. In addition, in the three-dimensional stacked structure, due to the existing structure and material characteristics, the three-dimensional memory device will cause interlayer leakage at a certain stage of operation, resulting in poor reliability of the memory device.
[0004] Therefore, how to improve the reliability of three-dimensional memory devices is an issue that those skilled in the art need to solve urgently. Summary of the invention
[0005] Based on the above problems, the present application provides a three-dimensional memory device and a method for manufacturing the same, in which a ferroelectric film is added to the memory layer, and the interlayer isolation is optimized through a sandwich structure, thereby improving the reliability of the device.
[0006] In a first aspect, an embodiment of the present application provides a three-dimensional memory device, comprising: a silicon substrate layer, a metal and oxide stacked structure, a memory layer, a channel layer, and an isolation layer;
[0007] The metal and oxide stacked structure is arranged on one side of the silicon substrate layer;
[0008] A ferroelectric film is arranged inside the storage layer, one side of the storage layer is arranged on the side surface of the word line metal layer in the metal and oxide stacked structure, and the other side of the storage layer is in contact with one side of the channel layer;
[0009] The other side of the channel layer contacts the isolation layer.
[0010] Optionally, the three-dimensional memory device further includes an epitaxial layer;
[0011] The epitaxial layer is grown on the silicon substrate layer, on the same side as the metal and oxide stacked structure, and is in contact with the channel layer and the isolation layer respectively.
[0012] Optionally, the storage layer includes: a barrier layer, a capture layer and a tunneling layer;
[0013] One side of the barrier layer contacts the side surface of the word line metal layer in the metal and oxide stacked structure, and the other side contacts one side of the capture layer;
[0014] One side of the tunnel layer contacts the other side of the capture layer, and the other side of the tunnel layer contacts one side of the channel layer.
[0015] Optionally, the capture layer includes: a silicon nitride layer disposed as an inner layer and a hafnium zirconium oxide layer disposed as an outer layer;
[0016] The inner surface of the hafnium zirconium oxide layer contacts the silicon nitride layer, and both sides of the outer surface contact the barrier layer and the tunneling layer respectively.
[0017] Optionally, the word line metal layer in the metal and oxide stacked structure is a titanium nitride layer.
[0018] Optionally, the outer layer of the metal and oxide stacked structure is an oxide layer;
[0019] The oxide is silicon dioxide.
[0020] In a second aspect, an embodiment of the present application provides a method for manufacturing a three-dimensional memory device, comprising:
[0021] providing a silicon substrate;
[0022] Alternately depositing stacked thin films on the silicon substrate to form a metal and oxide stacked structure;
[0023] Partially etching the metal and oxide stacked structure to form a groove;
[0024] Carving back the word line metal layer on the side of the trench in the metal and oxide stacked structure based on a wet etching process to form a groove;
[0025] A storage layer is deposited in the groove; a ferroelectric thin film exists inside the storage layer;
[0026] A channel layer is deposited along the inner wall of the trench, and an insulating layer is deposited inside the trench.
[0027] Optionally, before depositing the insulating layer inside the trench, the method further includes:
[0028] An epitaxial layer is grown at the bottom of the trench.
[0029] Optionally, depositing a storage layer in the groove includes:
[0030] Depositing a barrier layer on the side surface of the word line metal layer in the groove;
[0031] depositing a capture layer outside the barrier layer;
[0032] A tunneling layer is deposited outside the trapping layer.
[0033] Optionally, depositing a capture layer outside the barrier layer comprises:
[0034] A hafnium zirconium oxide layer, a silicon nitride layer and the hafnium zirconium oxide layer are sequentially deposited outside the barrier layer, so that the hafnium zirconium oxide layer wraps the silicon nitride layer.
[0035] It can be seen from the above technical solutions that compared with the prior art, the present application has the following advantages:
[0036] The device provided by the present application includes a silicon substrate layer, a metal and oxide stacking structure, a storage layer, a channel layer and an isolation layer. The metal and oxide stacking structure is arranged on one side of the silicon substrate layer; a ferroelectric film is arranged inside the storage layer, one side of the storage layer is arranged on the side surface of the word line metal layer in the metal and oxide stacking structure, and the other side is in contact with one side of the channel layer; the other side of the channel layer is in contact with the isolation layer. In this way, by adding a ferroelectric film to the storage layer, the interlayer isolation is optimized through a sandwich structure, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0038] Figure 1 A schematic diagram of the structure of a three-dimensional storage device provided in an embodiment of the present application;
[0039] Figure 2 A schematic structural diagram of a three-dimensional memory device including an epitaxial layer provided in an embodiment of the present application;
[0040] Figure 3 A schematic diagram of the structure of a storage layer provided in an embodiment of the present application;
[0041] Figure 4 A schematic diagram of the structure of a capture layer provided in an embodiment of the present application;
[0042] Figure 5 A flowchart of a method for manufacturing a three-dimensional memory device provided in an embodiment of the present application;
[0043] Figure 6 A manufacturing flow chart of an epitaxial layer provided in an embodiment of the present application;
[0044] Figure 7A manufacturing flow chart of a storage layer provided in an embodiment of the present application. DETAILED DESCRIPTION
[0045] As mentioned above, existing three-dimensional memories have the problem of poor reliability. Specifically, three-dimensional memory technology provides a solid foundation for modern data processing with its unique architectural design and efficient storage mechanism. Its core lies in vertically stacking multiple storage units, allowing more storage capacity to be integrated on the same chip and improving storage density. However, the existing three-dimensional memory adopts an oxide-silicon nitride-oxide structure, which will cause carrier lateral drift and other phenomena during programming. In addition, in the existing three-dimensional stacking structure, due to the existing structure and material characteristics, the three-dimensional memory device will experience interlayer leakage when it works to a certain stage, which in turn leads to the problem of poor reliability of the memory device.
[0046] To solve the above problems, the embodiment of the present application provides a three-dimensional memory device and a manufacturing method thereof, wherein the device comprises: a silicon substrate layer, a metal and oxide stacking structure, a memory layer, a channel layer and an isolation layer. The metal and oxide stacking structure is arranged on one side of the silicon substrate layer; a ferroelectric film is arranged inside the memory layer, one side of the memory layer is arranged on the side surface of the word line metal layer in the metal and oxide stacking structure, and the other side is in contact with one side of the channel layer; the other side of the channel layer is in contact with the isolation layer.
[0047] In this way, a ferroelectric film is added to the storage layer, and the interlayer isolation is optimized through a sandwich structure, thereby improving the reliability of the device.
[0048] It should be noted that the three-dimensional memory device and the manufacturing method thereof provided by the present application can be applied to the field of semiconductor device technology. The above is only an example and does not limit the application field of the three-dimensional memory device and the manufacturing method thereof provided by the present application.
[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0050] Figure 1 A schematic diagram of the structure of a three-dimensional storage device provided in an embodiment of the present application. Figure 1 As shown, the device includes: a silicon substrate layer 101, a metal and oxide stacked structure 102, a storage layer 103, a channel layer 104 and an isolation layer 105;
[0051] The metal and oxide stacked structure 102 is disposed on one side of the silicon substrate layer 101;
[0052] A ferroelectric thin film is disposed inside the storage layer 103. One side of the storage layer 103 is disposed on the side surface of the word line metal layer in the metal and oxide stacked structure 102, and the other side is in contact with one side of the channel layer 104.
[0053] The other side of the channel layer 104 is in contact with the isolation layer 105 .
[0054] Specifically, a ferroelectric film is provided in the storage layer 103 of the three-dimensional storage device provided in the present application. Due to its spontaneous polarization characteristics, it can be reversed under the action of an external electric field, and thus information can be maintained without the need for continuous power supply. In addition, ferroelectric materials have extremely fast read and write speeds, and have excellent durability and low power consumption. Therefore, the storage layer 103 with a ferroelectric film added is applied to the three-dimensional storage device, and the interlayer isolation can be optimized through its "sandwich type" structure to improve the reliability of the device. The channel layer 104 covers the storage layer 103, providing a transmission channel for the charge, so that the charge can be effectively transmitted between the source and the drain. The material of the channel layer 104 provided in the embodiment of the present application is polysilicon. The isolation layer 105 is located between different components of the storage unit to provide electrical isolation to prevent the charge from leaking or interfering between non-adjacent storage units or components. The material of the isolation layer provided in the embodiment of the present application is oxide.
[0055] Figure 2 A schematic diagram of the structure of a three-dimensional memory device including an epitaxial layer provided in an embodiment of the present application. Figure 2 As shown, the three-dimensional memory device further includes an epitaxial layer 106;
[0056] The epitaxial layer 106 is grown on the silicon substrate layer 101 , on the same side as the metal and oxide stacked structure 102 , and is in contact with the channel layer 104 and the isolation layer 105 , respectively.
[0057] Specifically, the epitaxial layer 106 is deposited on the silicon substrate layer 101 by epitaxial growth technology, and has the same crystal structure as the silicon substrate layer 101. The doping concentration, resistivity and other electrical properties can be precisely controlled, thereby achieving the effect of improving material quality and purity, optimizing electrical properties, improving resistance to conduction voltage and enhancing device stability.
[0058] Figure 3 A schematic diagram of a storage layer structure provided in an embodiment of the present application. Figure 3 As shown, the storage layer 103 includes: a barrier layer 201, a capture layer 202 and a tunneling layer 203;
[0059] One side of the barrier layer 201 contacts the side surface of the word line metal layer in the metal and oxide stacked structure 102, and the other side contacts one side of the capture layer 202;
[0060] One side of the tunneling layer 203 contacts the other side of the capture layer 202 , and the other side contacts one side of the channel layer 104 .
[0061] Specifically, the storage layer 103 provided in the embodiment of the present application includes a blocking layer 201, a trapping layer 202 and a tunneling layer 203. The blocking layer 201 is made of silicon oxide and contacts the side surface of the word line metal layer in the metal and oxide stacked structure 102, and is used to block the flow of charge and prevent the charge from leaking from the storage layer 103. The tunneling layer 203 is located between the charge storage layer 103 and the channel layer 104 and contacts the channel layer 104. The tunneling layer 203 is made of silicon oxide and can provide sufficient tunneling current during read and write operations while maintaining sufficient electrical isolation to prevent the charge from leaking when it is not needed. The trapping layer 202 is sandwiched between the blocking layer 201 and the tunneling layer 203, and includes a ferroelectric film for trapping and storing charge. When an external electric field is applied, the charge can enter the trapping layer 202 through the tunneling layer 203 and be trapped by defects or traps therein. The trapped charge can change the electrical properties of the storage unit, thereby realizing the storage of information.
[0062] Figure 4 A schematic diagram of the structure of a capture layer provided in an embodiment of the present application. Figure 4 As shown, the capture layer 202 includes: an inner silicon nitride layer 301 and an outer hafnium zirconium oxide layer 302;
[0063] The inner surface of the hafnium zirconium oxide layer 302 contacts the silicon nitride layer 301 , and both sides of the outer surface contact the barrier layer 201 and the tunneling layer 203 respectively.
[0064] Specifically, the capture layer 202 is composed of an inner silicon nitride layer 301 and an outer hafnium zirconium oxide layer 302, the hafnium zirconium oxide layer 302 wraps the silicon nitride layer 301 to form a sandwich structure, and then forms a storage layer 103 with the barrier layer 201 and the tunneling layer 203. The material of the hafnium zirconium oxide layer 302 is hafnium zirconium oxide. Based on the perfect compatibility of hafnium-based ferroelectric materials with CMOS processes and high dielectric constants, while improving the reliability of single devices (leakage between word lines, signal interference between units, etc.), it can also use its own spontaneous polarization, miniaturization and other characteristics to enable the three-dimensional memory to achieve high-density, low-power storage in a smaller size.
[0065] In addition, with regard to how to design the metal and oxide stacked structure 102, the word line metal layer in the metal and oxide stacked structure 102 is a titanium nitride layer.
[0066] Specifically, the word line metal layer in the metal and oxide stacked structure 102 provided in the embodiment of the present application is a titanium nitride layer, the material of which is titanium nitride, and each titanium nitride layer is protected by two layers of oxide.
[0067] In addition, with respect to how to design the metal and oxide stacked structure 102, the outer layer of the metal and oxide stacked structure 102 is an oxide layer;
[0068] The oxide is silicon dioxide.
[0069] Specifically, the metal and oxide stacked structure 102 provided in the embodiment of the present application is formed by stacking and depositing a titanium nitride layer and an oxide layer. The material of the oxide layer is silicon dioxide, and the outer layers of the metal and oxide stacked structure 102 (the stack closest to the silicon substrate layer 101 and the stack farthest from the silicon substrate layer 101) are both oxide layers.
[0070] In summary, the device provided by the present application includes a silicon substrate layer, a metal and oxide stacking structure, a storage layer, a channel layer and an isolation layer. Among them, the metal and oxide stacking structure is arranged on one side of the silicon substrate layer; a ferroelectric film is arranged inside the storage layer, one side of the storage layer is arranged on the side surface of the word line metal layer in the metal and oxide stacking structure, and the other side is in contact with one side of the channel layer; the other side of the channel layer is in contact with the isolation layer. In this way, by adding a ferroelectric film to the storage layer, the interlayer isolation is optimized through a sandwich structure, and the reliability of the device is improved.
[0071] Figure 5 A flowchart of a method for manufacturing a three-dimensional memory device provided in an embodiment of the present application. Figure 5 As shown, the method may include:
[0072] S1: Provide a silicon substrate.
[0073] In practical applications, smooth, flat and high-purity silicon crystals are used as the silicon substrate layer, which serves as the base and support of the semiconductor chip. Processes are carried out on it to manufacture three-dimensional memory devices.
[0074] S2: Alternately depositing stacked thin films on the silicon substrate to form a metal and oxide stacked structure.
[0075] In practical applications, a deposition process is used to alternately deposit a stacked film on a silicon substrate layer to form a metal word line and an isolation layer. Specifically, a chemical vapor deposition method can be used to evaporate or decompose the raw material in an atmosphere of high temperature, high pressure and inert gas, so that the generated gas reacts synergistically and is deposited on the silicon substrate to form an oxide film. Then continue to deposit the word line metal layer in the same way, and then deposit the oxide layer. By alternating deposition in this way, a metal and oxide stacked structure is formed on the silicon substrate. It should be noted that the metal and oxide stacked structure is generated by alternating deposition of word line metal layers and oxide layers, and the outermost layer of the structure is an oxide layer, and the number of word line metal layers can be controlled as needed. The embodiment of the present application provides a metal and oxide stacked structure with 5 word line metal layers.
[0076] S3: Partially etching the metal and oxide stacked structure to form a groove.
[0077] In practical applications, a local etching method is used to etch the word line metal layer (titanium nitride) and the oxide layer (silicon dioxide), forming a groove in the center of the metal and oxide stacked structure, thereby forming a stacked structure.
[0078] S4: etching back the word line metal layer on the trench side of the metal and oxide stacked structure based on a wet etching process to form a groove.
[0079] In practical applications, a wet etching process is adopted, and the difference in the selectivity ratio of different acidic solutions for different materials is utilized to etch back the side surface of the word line metal layer close to the groove in the metal and oxide stacked structure, so as to form a metal layer groove under the contrast of the oxide layer, so as to prepare for the subsequent preparation of the storage layer in the groove.
[0080] S5: depositing a storage layer in the groove; a ferroelectric thin film exists inside the storage layer.
[0081] In practical applications, a storage layer is generated inside the groove by repeatedly adopting the process of deposition followed by etching, in which a ferroelectric thin film made of hafnium zirconium oxide is deposited in the storage layer to improve the reliability problems of the single element (leakage between word lines, signal interference between units, etc.). At the same time, it can also utilize its own spontaneous polarization and miniaturization characteristics to enable the three-dimensional memory to achieve high-density and low-power storage in a smaller size.
[0082] S6: depositing a channel layer along the inner wall of the trench, and depositing an insulating layer inside the trench.
[0083] In practical applications, after the storage layer is generated, polysilicon is deposited on the inner wall of the trench to form a channel layer. It should be noted that the channel layer needs to be in contact with the tunneling layer in the storage layer. After the channel layer is deposited, oxide is deposited in the trench to form an isolation layer, thereby providing electrical isolation to prevent charge leakage or interference between non-adjacent storage cells or components. Finally, a chemical polishing process is performed to flatten the top layer and complete the storage array pre-device, and then the completed pre-device is connected to the metal electrode to obtain a complete three-dimensional array storage device.
[0084] In addition, since the design methods of three-dimensional memory devices are not the same, the embodiments of the present application can be described with respect to a possible design method.
[0085] In one embodiment, before depositing the insulating layer inside the trench, the method further includes:
[0086] An epitaxial layer is grown at the bottom of the trench.
[0087] Figure 6 A manufacturing flow chart of an epitaxial layer provided in an embodiment of the present application. Figure 6 As shown, after the storage layer is deposited in the groove, that is, after step S5, step S7 can be performed first: polysilicon is deposited along the inner wall of the groove to form a channel layer, and the tunnel layer in the storage layer is contacted. Then step S8 is performed: a new silicon layer is grown on the upper layer of the silicon substrate in the groove by chemical vapor deposition or molecular beam epitaxy, so that the epitaxial silicon is in contact with the channel layer, which is used to improve device performance, reduce parasitic effects and increase integration. Finally, step S9 is performed: oxide is deposited on the epitaxial layer to form a channel isolation layer, and a chemical grinding process is performed at the same time to flatten the top layer, complete the storage array pre-device, and then the completed pre-device is connected to the metal electrode to obtain a complete three-dimensional array storage device.
[0088] In addition, since the methods of depositing the storage layer in the groove are not the same, the embodiment of the present application can be described with respect to a possible deposition method.
[0089] In one embodiment, depositing a storage layer in the groove includes:
[0090] Depositing a barrier layer on the side surface of the word line metal layer in the groove;
[0091] depositing a capture layer outside the barrier layer;
[0092] A tunneling layer is deposited outside the trapping layer.
[0093] In practical applications, the manufacture of the storage layer requires the deposition of silicon oxide at the innermost part of the groove to form a barrier layer, which contacts the side surface of the word line metal layer in the metal and oxide stacked structure to block the flow of charge and prevent the charge from leaking from the storage layer. Then a capture layer is deposited on the outside of the barrier layer so that the capture layer contacts the barrier layer. Finally, silicon oxide is deposited on the outside of the capture layer to form a tunnel layer so that the tunnel layer contacts the capture layer. In this way, the tunnel layer can provide sufficient tunneling current during read and write operations while maintaining sufficient electrical isolation to prevent charge leakage when it is not needed. The capture layer is sandwiched between the barrier layer and the tunnel layer, and includes a ferroelectric film for capturing and storing charge. When an external electric field is applied, the charge can enter the capture layer through the tunnel layer and be captured by defects or traps therein. The captured charge can change the electrical properties of the storage unit, thereby realizing the storage of information.
[0094] In addition, since there are different ways to deposit the capture layer outside the barrier layer, the embodiments of the present application can be described with respect to one possible deposition method.
[0095] In one embodiment, depositing a capture layer outside the barrier layer comprises:
[0096] A hafnium zirconium oxide layer, a silicon nitride layer and the hafnium zirconium oxide layer are sequentially deposited outside the barrier layer, so that the hafnium zirconium oxide layer wraps the silicon nitride layer.
[0097] Figure 7 A manufacturing flow chart of a storage layer provided in an embodiment of the present application. Figure 7 As shown, first, silicon oxide, silicon nitride and hafnium zirconium oxide are sequentially deposited inside the groove, so that a barrier layer and a partial capture layer (the hafnium zirconium oxide layer wrapped on the left and the silicon nitride layer arranged in the inner layer) are sequentially generated inside the groove, as shown in step S501. Then, step S502 is performed, and the outer deposition layer in the groove and the deposition layer outside the groove are rapidly wet-etched using an acidic solution with a high selectivity ratio to obtain a left half storage layer. Finally, step S503 is performed, and a ferroelectric layer (hafnium zirconium oxide) is deposited again in the groove and rapidly wet-etched with a high selectivity ratio to obtain a complete capture layer, forming a wrapping structure in which the hafnium zirconium oxide layer wraps the silicon nitride layer. Then, a tunneling layer is deposited and rapidly wet-etched with a high selectivity ratio to obtain a complete storage layer. The interlayer isolation is optimized through the sandwich structure, thereby improving the reliability of the device.
[0098] In summary, the device provided by the present application includes a silicon substrate layer, a metal and oxide stacking structure, a storage layer, a channel layer and an isolation layer. Among them, the metal and oxide stacking structure is arranged on one side of the silicon substrate layer; a ferroelectric film is arranged inside the storage layer, one side of the storage layer is arranged on the side surface of the word line metal layer in the metal and oxide stacking structure, and the other side is in contact with one side of the channel layer; the other side of the channel layer is in contact with the isolation layer. In this way, by adding a ferroelectric film to the storage layer, the interlayer isolation is optimized through a sandwich structure, and the reliability of the device is improved.
[0099] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A three-dimensional storage device, characterized in that: The device comprises: a silicon substrate layer, a metal and oxide stacked structure, a storage layer, a channel layer and an isolation layer; The metal and oxide stacked structure is arranged on one side of the silicon substrate layer; A ferroelectric film is arranged inside the storage layer, one side of the storage layer is arranged on the side surface of the word line metal layer in the metal and oxide stacked structure, and the other side of the storage layer is in contact with one side of the channel layer; The other side of the channel layer contacts the isolation layer.
2. The three-dimensional memory device according to claim 1, characterized in that: The three-dimensional memory device further includes an epitaxial layer; The epitaxial layer is grown on the silicon substrate layer, on the same side as the metal and oxide stacked structure, and is in contact with the channel layer and the isolation layer respectively.
3. The three-dimensional memory device according to claim 1, characterized in that: The storage layer includes: a barrier layer, a capture layer and a tunneling layer; One side of the barrier layer contacts the side surface of the word line metal layer in the metal and oxide stacked structure, and the other side contacts one side of the capture layer; One side of the tunnel layer contacts the other side of the capture layer, and the other side of the tunnel layer contacts one side of the channel layer.
4. The three-dimensional memory device according to claim 3, characterized in that: The capture layer comprises: a silicon nitride layer arranged as an inner layer and a hafnium zirconium oxide layer arranged as an outer layer; The inner surface of the hafnium zirconium oxide layer contacts the silicon nitride layer, and both sides of the outer surface contact the barrier layer and the tunneling layer respectively.
5. The three-dimensional memory device according to claim 1, characterized in that: The word line metal layer in the metal and oxide stacked structure is a titanium nitride layer.
6. The three-dimensional memory device according to claim 5, characterized in that: The outer layer of the metal and oxide stacked structure is an oxide layer; The oxide is silicon dioxide.
7. A method for manufacturing a three-dimensional memory device, characterized in that: For manufacturing the three-dimensional memory device according to claims 1-6, the method comprises: providing a silicon substrate; Alternately depositing stacked thin films on the silicon substrate to form a metal and oxide stacked structure; Partially etching the metal and oxide stacked structure to form a groove; Carving back the word line metal layer on the side of the trench in the metal and oxide stacked structure based on a wet etching process to form a groove; A storage layer is deposited in the groove; a ferroelectric thin film exists inside the storage layer; A channel layer is deposited along the inner wall of the trench, and an insulating layer is deposited inside the trench.
8. The method according to claim 7, characterized in that: Before depositing the insulating layer inside the trench, the method further includes: An epitaxial layer is grown at the bottom of the trench.
9. The method according to claim 7, characterized in that: The step of depositing a storage layer in the groove comprises: Depositing a barrier layer on the side surface of the word line metal layer in the groove; depositing a capture layer outside the barrier layer; A tunneling layer is deposited outside the trapping layer.
10. The method according to claim 9, characterized in that: The step of depositing a capture layer outside the barrier layer comprises: A hafnium zirconium oxide layer, a silicon nitride layer and the hafnium zirconium oxide layer are sequentially deposited outside the barrier layer, so that the hafnium zirconium oxide layer wraps the silicon nitride layer.