Display device

Abstract

Provided herein is a display device including: a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; a plurality of transistors in the plurality of sub-pixels; a planarization layer covering the plurality of transistors; a light emitting element on the planarization layer; a plurality of first pad electrodes in the non-display area; and an organic film on the plurality of first pad electrodes, in which the planarization layer covers edges of the plurality of first pad electrodes and is spaced apart from the organic film. The reliability of the display device provided herein is improved by suppressing damage to the pad electrode caused by an arc.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0108180, filed on August 18, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that minimizes or at least reduces damage to a pad electrode. Background Art

[0004] Recently, with the full entry into the information age, display devices that visually display electrical information signals are rapidly developing. Various studies are being conducted to develop various display devices that are light and thin, have low power consumption, and have improved performance.

[0005] Among various display devices, a light-emitting display device refers to a self-luminous display device. Unlike a liquid crystal display device, a light-emitting display device does not require a separate light source, and thus can be manufactured as a thin and light display device. In addition, since the light-emitting display device operates at a low voltage, the light-emitting display device has an advantage in power consumption. In addition, since the light-emitting display device is also excellent in achieving color, response speed, viewing angle, and contrast (CR), the light-emitting display device is expected to be adopted in various fields. Summary of the invention

[0006] One object to be achieved by the present disclosure is to provide a display device that minimizes or at least reduces damage to a pad electrode.

[0007] Another object to be achieved by the present disclosure is to provide a display device that minimizes or at least reduces the occurrence of static electricity on a pad electrode.

[0008] Still another object to be achieved by the present disclosure is to provide a display device capable of suppressing arcing and improving reliability.

[0009] The purpose of the present disclosure is not limited to the above-mentioned purpose. Through the following description, those skilled in the art can clearly understand other purposes not mentioned above.

[0010] In one or more embodiments of the present disclosure, a display device is provided, comprising: a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; a plurality of transistors in the plurality of sub-pixels; a planarization layer covering the plurality of transistors; a light-emitting element on the planarization layer; a plurality of first pad electrodes in the non-display area; and an organic film on the plurality of first pad electrodes, wherein the planarization layer covers edges of the plurality of first pad electrodes and is spaced apart from the organic film. Therefore, the reliability of the display device can be improved by suppressing arcs caused by damage to the pad electrodes.

[0011] Additional details of embodiments of the disclosure are included in the detailed description and accompanying drawings.

[0012] The present disclosure may minimize or at least reduce damage to pad electrodes.

[0013] The present disclosure may minimize or at least reduce the occurrence of static electricity on the pad electrode.

[0014] The present disclosure can improve the reliability of a display device by suppressing arcing.

[0015] The effects according to the present disclosure are not limited to the contents exemplified above, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other embodiments, features and other advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a schematic top plan view of a display device according to one or more embodiments of the present disclosure;

[0018] Figure 2 According to one or more embodiments of the present disclosure Figure 1 An enlarged top plan view of area A in FIG.

[0019] Figure 3 According to one or more embodiments of the present disclosure, Figure 1 A cross-sectional view taken along line III-III';

[0020] Figure 4 According to one or more embodiments of the present disclosure, Figure 2 A cross-sectional view taken along line IV-IV';

[0021] Figure 5 According to one or more embodiments of the present disclosure, Figure 2 A cross-sectional view taken along line VV′ in FIG.

[0022] Figure 6is a cross-sectional view of a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] By referring to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to the embodiments disclosed herein, but will be implemented in various forms. The embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0024] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the disclosure, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "comprising" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0025] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0026] When terms such as “on,” “above,” “below,” and “near” are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the terms “immediately” or “directly.”

[0027] When one element or one layer is disposed “on” another element or another layer, the another layer or another element may be directly disposed on the another element or interposed therebetween.

[0028] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0029] Like reference numbers generally refer to like elements throughout the disclosure.

[0030] The sizes and thicknesses of the respective components shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the sizes and thicknesses of the components shown.

[0031] The features of various embodiments of the present disclosure may be partially or completely coupled or combined with each other, and may be technically interconnected and operated in various ways, and the embodiments may be performed independently or in association with each other.

[0032] Hereinafter, a display device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 is a schematic top plan view of a display device according to one or more embodiments of the present disclosure.

[0034] Figure 2 According to one or more embodiments of the present disclosure Figure 1 An enlarged top plan view of area A in FIG.

[0035] Figure 3 According to one or more embodiments of the present disclosure, Figure 1 A cross-sectional view taken along line III-III′ in FIG. Figure 1 Only the substrate 110, the connection line LL, and the flexible film COF are shown among the constituent elements of the display device 100, and Figure 2 The flexible film COF is not shown.

[0036] Reference Figure 1 and Figure 2 , the display device 100 according to one or more embodiments of the present disclosure may include a substrate 110 , a signal line SL, a connection line LL, a pad electrode PAD, and a flexible film COF.

[0037] Refer to Figure 3 The substrate 110 may include a first substrate 107 , an interlayer insulating film 109 and a second substrate 108 .

[0038] The first substrate 107 and the second substrate 108 may be substrates configured to support constituent elements disposed on the substrate 110, that is, insulating substrates. For example, the first substrate 107 and the second substrate 108 may be made of glass, resin, etc. In addition, the first substrate 107 and the second substrate 108 may include a polymer or plastic. In some embodiments, the first substrate 107 and the second substrate 108 may be made of a plastic material having flexibility.

[0039] An interlayer insulating film 109 may be disposed between the first substrate 107 and the second substrate 108. The interlayer insulating film 109 may protect the first substrate 107 and the second substrate 108 from penetration of moisture.

[0040] A plurality of pixels may be formed on the substrate 110 so that an image may be displayed. The substrate 110 may include a display area AA and a non-display area NA configured to surround the display area AA.

[0041] The display area AA is an area in the display device 100 where an image is displayed. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels and a plurality of signal lines SL configured to operate the plurality of sub-pixels SP. The plurality of sub-pixels SP are the minimum units constituting the display area AA. n sub-pixels SP may constitute a single pixel. A light-emitting element, a thin film transistor for operating the light-emitting element, etc. may be provided in each of the plurality of sub-pixels SP. The plurality of light-emitting elements may be differently defined according to the type of the display panel. For example, the light-emitting element may be an organic light-emitting diode (OLED).

[0042] The plurality of signal lines SL may extend from the display area AA to the non-display area NA and be electrically connected to the pad electrode PAD. The plurality of signal lines SL may be respectively connected to the plurality of sub-pixels SP and transmit various types of signals. For example, the plurality of signal lines SL may be gate lines, data lines, power lines, or scan lines. However, the present disclosure is not limited thereto.

[0043] The non-display area NA may be defined as an area where an image is not displayed, that is, an area extending from the display area AA. The non-display area NA may include a pad area PA and a connection area LA.

[0044] The connection area LA may be disposed between the display area AA and the pad area PA. The connection area LA is an area in which connection lines LL are disposed to transmit signals to the signal lines SL disposed in the display area AA, and various connection lines LL may be disposed in the connection area LA. A plurality of connection lines LL may be respectively connected to a plurality of pad electrodes PAD in the pad area PA. For example, the plurality of connection lines LL may be gate connection lines, data connection lines, power connection lines, or power lines. However, the present disclosure is not limited thereto. In addition, the plurality of connection lines LL may be made of the same material as the first metal layer and the second metal layer to be described below. However, the present disclosure is not limited thereto.

[0045] The pad area PA is an area where no image is displayed. A plurality of pad electrodes PAD may be provided in the pad area PA. The pad area PA may be an area extending from one side of the connection area LA. For example, the pad area PA may be an area where a power pad electrode, a data pad electrode, a gate pad electrode, etc. are provided.

[0046] In addition, a flexible film COF on which a driving chip IC for transmitting signals to the sub-pixels SP in the display area AA is mounted may be disposed in the non-display area NA. The flexible film COF may include a base film COF_B, a driving chip IC, and a pad portion.

[0047] The base film COF_B is a layer for supporting the flexible film COF. The base film COF_B may be made of an insulating material (eg, an insulating material having flexibility).

[0048] The driver chip IC is a component configured to process data for displaying an image and process a driving signal for processing the data. The driver chip IC may be electrically connected to the substrate 110 through a pad portion. The driver chip IC may be mounted in a chip on film (COF) manner. However, the present disclosure is not limited thereto.

[0049] Meanwhile, although not shown in the drawings, the pad portion may supply a power voltage, a data voltage, etc. to a plurality of sub-pixels SP in the display area AA through a pad electrode PAD disposed in the pad area PA. The pad portion may be made of a conductive material such as copper (Cu). However, the present disclosure is not limited thereto.

[0050] Reference Figure 3 , a light shielding layer BSM may be provided on the substrate 110. The light shielding layer BSM may block light entering the active layer ACT of the plurality of transistors, thereby minimizing leakage current. For example, the light shielding layer BSM may be provided below the active layer ACT of the transistor DT, and block light entering the active layer ACT. If light is incident on the active layer ACT, leakage current occurs, which may deteriorate the reliability of the transistor DT. Therefore, a light shielding layer BSM for blocking light may be provided on the substrate 110, thereby improving the reliability of the transistor DT. The light shielding layer BSM may be made of an opaque conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals. However, the present disclosure is not limited thereto.

[0051] The buffer layer 111 may be disposed on the light shielding layer BSM. The buffer layer 111 may reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 may be configured to be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is a single layer or a multilayer made of. However, the present disclosure is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor DT, the buffer layer 111 may not be included. However, the present disclosure is not limited thereto.

[0052] A transistor DT including an active layer ACT, a gate GE, a source electrode SE, and a drain electrode DE may be disposed on the buffer layer 111 .

[0053] At the same time, despite Figure 3 Although not shown in the figure, an additional buffer layer may be provided between the substrate 110 and the light shielding layer BSM. For example, similar to the buffer layer 111, the additional buffer layer may be configured to be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed into a single layer or multiple layers to reduce the penetration of moisture or impurities through the substrate 110. However, the present disclosure is not limited thereto.

[0054] First, the active layer ACT of the transistor DT can be arranged on the buffer layer 111. The active layer ACT can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon or polycrystalline silicon. However, the present disclosure is not limited to this. In addition, although not shown in the drawings, in addition to the transistor DT, other transistors such as a switching transistor, a sensing transistor, and a light-emitting control transistor can be additionally provided. The active layers of these transistors can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon or polycrystalline silicon. However, the present disclosure is not limited to this. In addition, the active layers of the transistors included in the pixel circuit (for example, the transistor DT, the switching transistor, the sensing transistor, and the light-emitting control transistor) can be made of the same material or different materials.

[0055] The gate insulating layer 112 may be disposed on the active layer ACT. The gate insulating layer 112 may be an insulating layer for electrically insulating the active layer ACT and the gate GE. The gate insulating layer 112 may be configured of silicon oxide (SiO x ) or silicon nitride (SiN x ) is a single layer or multiple layers. However, the present disclosure is not limited thereto.

[0056] The gate GE may be disposed on the gate insulating layer 112. The gate GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0057] In addition, a connection electrode CNT may be disposed on the gate insulating layer 112. The connection electrode CNT may be made of the same material as the gate electrode GE, and be electrically connected to the source electrode SE and the light shielding layer BSM.

[0058] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be disposed on the gate GE. Contact holes are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and the source electrode SE and the drain electrode DE are connected to the active layer ACT through the contact holes. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting components disposed thereunder. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 may each be configured of silicon oxide (SiO x ) or silicon nitride (SiN x ) is a single layer or multiple layers. However, the present disclosure is not limited thereto.

[0059] The storage capacitor Cst may be disposed on the gate insulating layer 112. The storage capacitor Cst may be implemented by using the intermediate electrode TM and the gate electrode GE as capacitor electrodes. However, the present disclosure is not limited thereto. The storage capacitor Cst may be implemented in various ways.

[0060] The middle electrode TM may be disposed on the first interlayer insulating layer 113. The middle electrode TM may be disposed to overlap the gate electrode GE with the first interlayer insulating layer 113 interposed therebetween.

[0061] The source electrode SE and the drain electrode DE are disposed on the second interlayer insulating layer 114 and are electrically connected to the active layer ACT. The drain electrode DE may be electrically connected to the storage capacitor Cst, and the source electrode SE may be connected to the first electrode 121 of the light emitting element 120. The source electrode SE and the drain electrode DE may each be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals. However, the present disclosure is not limited thereto.

[0062] The planarization layer 115 may be disposed on the source electrode SE and the drain electrode DE. The planarization layer 115 may planarize the upper portion of the pixel circuit including the transistor DT. For example, the planarization layer 115 may be configured as a single layer or multiple layers and may be made of benzocyclobutene (BCB) or an acrylic-based organic material. However, the present disclosure is not limited thereto.

[0063] A plurality of light emitting elements 120 are disposed on the planarization layer 115 and are respectively disposed in a plurality of sub-pixels SP. The light emitting element 120 may be an element configured to emit light by current, and include a red light emitting element configured to emit red light, a green light emitting element configured to emit green light, and a blue light emitting element configured to emit blue light. The combination of the light emitting element 120 may realize various colors including white. For example, the light emitting element 120 may be an organic light emitting diode (OLED). However, the present disclosure is not limited thereto.

[0064] The light emitting element 120 may include a first electrode 121 , a light emitting layer 122 , and a second electrode 123 .

[0065] The first electrode 121 may be disposed on the planarization layer 115. The first electrode 121 may include a reflective layer 121a and a transparent conductive layer 121b. Specifically, the transparent conductive layer 121b may be disposed on the reflective layer 121a. The reflective layer 121a and the transparent conductive layer 121b are layers for supplying holes to the light emitting layer 122. The reflective layer 121a and the transparent conductive layer 121b may each be made of a conductive material having a high work function. For example, the reflective layer 121a may have a layered structure made of an alloy of silver (Ag), palladium (Pd) and copper (Cu) which are metal materials with high reflectivity. However, the present disclosure is not limited thereto. For example, the transparent conductive layer 121b may be made of indium tin oxide (ITO) as a transparent conductive oxide (TCO). However, the present disclosure is not limited thereto.

[0066] The embankment 116 may be disposed on the reflective layer 121a and the planarization layer 115. The embankment 116 may cover the edge of the reflective layer 121a of the light emitting element 120 and define a light emitting region. That is, the embankment 116 may separate a plurality of sub-pixels SP. The embankment 116 may be made of an insulating material to insulate the first electrodes 121 of adjacent sub-pixels SP. In addition, the embankment 116 may be configured as a black embankment having a high light absorption rate to suppress color mixing between adjacent sub-pixels SP. For example, the embankment 116 may be made of a polyimide resin, an acrylic resin, or a benzocyclobutene (BCB) resin. However, the present disclosure is not limited thereto.

[0067] The spacer 117 may be disposed on the bank 116. The spacer 117 refers to a layer that maintains a predetermined distance between the deposition mask and the bank 116 to suppress damage caused by contact with the deposition mask. Similar to the bank 116, the spacer 117 may be made of a polyimide resin, an acrylic resin, or a benzocyclobutene (BCB) resin. However, the present disclosure is not limited thereto. Figure 3 1 and 2. The bank 116 and the spacer 117 are shown separately in FIG. However, the bank 116 and the spacer 117 may be formed integrally and simultaneously through a single process.

[0068] The light emitting layer 122 may be provided on the first electrode 121. The light emitting layer 122 is a layer that emits light by combining electrons and holes.

[0069] The second electrode 123 may be disposed on the light emitting layer 122. The second electrode 123 may be made of a metal material having a low work function to smoothly supply electrons to the light emitting layer 122. For example, the second electrode 123 may be made of a metal material selected from calcium (Ca), barium (Ba), aluminum (Al), silver (Ag), and an alloy containing one or more of the above elements. However, the present disclosure is not limited thereto.

[0070] The light-emitting element 120 may further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc., to improve the light-emitting efficiency of the light-emitting element 120. For example, the hole injection layer and the hole transport layer may be disposed between the first electrode 121 and the light-emitting layer 122, and the electron transport layer and the electron injection layer may be disposed between the light-emitting layer 122 and the second electrode 123. In addition, a hole blocking layer or an electron blocking layer may be disposed on the light-emitting layer 122 to further improve the efficiency of the recombination of holes and electrons.

[0071] The encapsulation layer 130 may be disposed on the light emitting element 120. The encapsulation layer 130 may protect the light emitting element 120 from external moisture, oxygen, impact, and the like. The encapsulation layer 130 may have a multilayer structure in which an inorganic layer made of an inorganic insulating material and an organic layer made of an organic material are stacked. For example, the encapsulation layer 130 may have a multilayer structure including at least one organic layer and at least two inorganic layers, and may be made by alternately stacking inorganic layers and organic layers. However, the present disclosure is not limited thereto. For example, the encapsulation layer 130 may have a three-layer structure including a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133. In this case, the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may each be selected from silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (AlO x ) and silicon oxynitride (SiON) are made of one or more materials in the group consisting of. However, the present disclosure is not limited thereto. Meanwhile, the organic encapsulation layer 132 may be made of one or more materials selected from the group consisting of epoxy resin, polyimide resin, polyethylene resin and silicon oxycarbide (SiOC). However, the present disclosure is not limited thereto.

[0072] The touch detection part 140 may be disposed on the encapsulation layer 130 to recognize a user's touch. The touch detection part 140 may include a touch buffer layer 141 , a touch bridge electrode 142 , a touch insulating layer 143 , a touch electrode 144 , a touch protection layer 145 , and a touch line 146 .

[0073] The touch buffer layer 141 may be disposed on the encapsulation layer 130. The touch buffer layer 141 may be a layer for suppressing damage to the light emitting element 120 and the encapsulation layer 130, and may be made of an inorganic material having excellent barrier properties. Therefore, the penetration of moisture or oxygen may be minimized or at least reduced. For example, the touch buffer layer 141 may be configured to be made of silicon nitride (SiN x ) or silicon oxide (SiO x ) is a single layer or multiple layers. However, the present disclosure is not limited thereto.

[0074] The touch bridge electrode 142 may be disposed on the touch buffer layer 141 . The touch bridge electrode 142 may connect the touch electrodes 144 .

[0075] The touch insulating layer 143 may be disposed on the touch buffer layer 141 and the touch bridge electrode 142. The touch insulating layer 143 may be a layer for insulating the touch bridge electrode 142 and the touch electrode 144, and may be made of an inorganic material. For example, the touch insulating layer 143 may be configured to be made of silicon oxide (SiO x ) or silicon nitride (SiN x) is a single layer or multiple layers. However, the present disclosure is not limited thereto.

[0076] The touch electrode 144 may be disposed on the touch insulating layer 143. The touch electrode 144 is an electrode configured to detect a touch input. The touch electrode 144 may include a sensing electrode and a driving electrode, and the touch coordinates are detected by sensing a change in capacitance between the sensing electrode and the driving electrode. For example, the touch electrode 144 may be made of a transparent metal material such as indium tin oxide (ITO) or indium zinc oxide (IZO) that can transmit light. However, the present disclosure is not limited thereto.

[0077] In addition, the touch wire 146 may be disposed on the touch insulating layer 143. The touch wire 146 may electrically connect the touch electrode 144 with the touch circuit. The touch wire 146 may be disposed on the same layer as the touch electrode 144. However, the present disclosure is not limited thereto.

[0078] The touch protection layer 145 may be disposed on the touch electrode 144. The touch protection layer 145 is a layer that suppresses short circuit or damage of the touch electrode 144 and flattens the top surface of the touch electrode 144. For example, the touch protection layer 145 may be made of a transparent insulating resin such as an acrylic resin, a polyester resin, or an epoxy resin. However, the present disclosure is not limited thereto.

[0079] Next, a common power line VSS connected to the second electrode 123 may be provided in the non-display area NA. The common power line VSS may be electrically connected to the second electrode 123 of the light emitting element 120 and apply a power supply voltage to the light emitting element 120.

[0080] The weir 150 may be disposed on the common power line VSS. The weir 150 is disposed to prevent overflow of the organic encapsulation layer 132 of the encapsulation layer 130. The weir 150 may include a lower layer made of the same material as the planarization layer 115 and an upper layer made of the same material as the dam 116. However, the present disclosure is not limited thereto. The weir 150 may include three or more layers. In addition, Figure 3 Only one dam 150 is shown. However, the present disclosure is not limited thereto. The encapsulation layer 130 , the touch buffer layer 141 , and the touch insulation layer 143 may be disposed above the dam 150 .

[0081] The crack suppression layer 160 may be disposed outside the dam 150. The crack suppression layer 160 may mitigate external impact and suppress crack propagation to the display area AA. Therefore, the crack suppression layer 160 may be made of an organic insulating material having a high strain rate and impact resistance. For example, the crack suppression layer 160 may be made of the same material as the planarization layer 115 or the dam 116. However, the present disclosure is not limited thereto.

[0082] In the following, reference will be made to Figures 4 to 5The pad electrode PAD of the display device 100 according to one or more embodiments of the present disclosure is described in detail.

[0083] Figure 4 According to one or more embodiments of the present disclosure, Figure 2 A cross-sectional view taken along line IV-IV'. Figure 5 According to one or more embodiments of the present disclosure, Figure 2 A cross-sectional view taken along line VV′ in FIG. Figure 4 : is a figure which shows the state where the flexible film COF is joined. Figure 5 It is a cross-sectional view of a portion where the organic film OF is not provided.

[0084] Refer to Figures 4 to 5 , a buffer layer 111 and a gate insulating layer 112 may be disposed on the substrate 110 .

[0085] Among the plurality of metal layers, the first metal layer ML1 may be disposed on the gate insulating layer 112. The first metal layer ML1 may be electrically connected to the first pad electrode PAD1 to transmit a signal to the display area AA. The first metal layer ML1 may be made of the same material as the gate GE of the transistor DT. However, the present disclosure is not limited thereto.

[0086] The first interlayer insulating layer 113 may be disposed on the first metal layer ML1 .

[0087] Reference Figure 5 , a second metal layer ML2 among the plurality of metal layers may be disposed on the first interlayer insulating layer 113. Similar to the first metal layer ML1, the second metal layer ML2 may be electrically connected to the first pad electrode PAD1 to transmit a signal to the display area AA. The second metal layer ML2 may be made of the same material as the intermediate electrode TM among the electrodes of the storage capacitor Cst. However, the present disclosure is not limited thereto.

[0088] In the pad electrode, the first pad electrode PAD1 may be disposed on a plurality of metal layers. The first pad electrode PAD1 may transmit signals to a plurality of sub-pixels SP, or the first pad electrode PAD1 may be electrically connected to a printed circuit board. In this case, an edge of the first pad electrode PAD1 may be covered by a planarization layer 115. Specifically, the first pad electrode PAD1 may be disposed on the same layer as the source SE and drain DE of the transistor DT and may be made of the same material as the source SE and drain DE.

[0089] The organic film OF may be disposed on the first pad electrode PAD1 . The organic film OF may be spaced apart from the planarization layer 115 and protect a portion of the first pad electrode PAD1 that is not covered by the planarization layer 115 and is exposed. In this case, the organic film OF may be made of the same material as the planarization layer 115 .

[0090] The touch buffer layer 141 and the touch insulating layer 143 may be disposed on the organic film OF to cover the organic film OF. In this case, the touch buffer layer 141 and the touch insulating layer 143 may be disposed to expose a portion of the first pad electrode PAD1 to connect the first pad electrode PAD1 with the second pad electrode PAD2.

[0091] In the pad electrode, the second pad electrode PAD2 may be disposed on the organic film OF, the touch insulating layer 143, and the first pad electrode PAD1. In one or more embodiments, the touch buffer layer 141 and the touch insulating layer 143 may not be disposed in the non-display area NA. In these cases, the second pad electrode PAD2 may be disposed on the organic film OF and the first pad electrode PAD1. Similar to the first pad electrode PAD1, the second pad electrode PAD2 may transmit a signal to a plurality of sub-pixels SP, or the second pad electrode PAD2 may be electrically connected to a printed circuit board. In these cases, the second pad electrode PAD2 may be connected to the first pad electrode PAD1 through a contact hole of the touch buffer layer 141 and the touch insulating layer 143. The second pad electrode PAD2 may be made of the same material as one of the touch bridge electrode 142 and the touch electrode 144. However, the present disclosure is not limited thereto.

[0092] Reference Figure 4 , the flexible film COF may be disposed on the second pad electrode PAD2, and the pad portion COF_P of the flexible film COF may be electrically connected to the second pad electrode PAD2 through the conductive bonding layer ACF.

[0093] The conductive bonding layer ACF may be disposed on the plurality of second pad electrodes PAD2 to bond the plurality of second pad electrodes PAD2 with the flexible film COF. The conductive bonding layer ACF may be in a state where conductive balls SB for bonding and electrical connection are dispersed in the resin RE.

[0094] In the case where the light-emitting layer is an organic layer in the display device, the light-emitting layer can be formed by thermal vapor deposition using a mask. Specifically, in order to form the light-emitting layers respectively disposed in the red sub-pixel, the green sub-pixel, and the blue sub-pixel, a fine metal mask (FMM) is used. In these cases, the display device may have a defect that the pad electrode is sunken due to the sagging of the fine metal mask.

[0095] Specifically, in the case of a display device using a touch-on-encapsulation (ToE) method in which a touch detection unit is disposed on an encapsulation layer, a recessed pad electrode may be more problematic. The touch bridge electrode is formed by a deposition process, a photolithography process, and an etching process. In the case where the etching process is performed in a state where the pad electrode is recessed due to the sagging of the mask, the touch insulating layer may be over-etched and the pad electrode may be exposed. In this case, the exposed pad electrode may act as a lightning rod, and an arc may occur. In the event of an arc, a high current introduced into the pad electrode flows into the display device along the pad electrode, and static electricity occurs, which may cause defects in the display device.

[0096] Therefore, in the display device 100 according to one or more embodiments of the present disclosure, the organic film OF is disposed on the exposed portions of the plurality of first pad electrodes PAD1 that are not covered by the planarization layer 115. Therefore, even if the mask sags, the mask first contacts the organic film OF, which can prevent the first pad electrodes PAD1 from being recessed due to the mask.

[0097] Therefore, in the display device 100 according to one or more embodiments of the present disclosure, the organic film OF is arranged on a plurality of first pad electrodes PAD1, and the exposure of the first pad electrodes PAD1 is minimized or at least reduced, so that the current flowing into the first pad electrode PAD1 caused by the drooping mask is suppressed, which can minimize or at least reduce static electricity, suppress arcing, and improve reliability.

[0098] That is, in the display device 100 according to one or more embodiments of the present disclosure, the organic film OF is disposed on the plurality of first pad electrodes PAD1 , which can suppress damage to the first pad electrodes PAD1 .

[0099] Figure 6 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure. In addition to the organic film OF, Figure 6 The display device in the Figures 1 to 5 The display device 100 in FIG. 1 is substantially the same as that in FIG. 1 . Therefore, repeated description of the same components will be omitted.

[0100] Reference Figure 6 , an organic film having a slit pattern may be disposed on the first pad electrode PAD1. That is, the organic film OF may include a plurality of organic patterns. The plurality of organic patterns may be disposed on the first pad electrode PAD1 and spaced apart from each other at a predetermined interval to protect a portion that is not covered by the planarization layer 115 and is exposed. The plurality of organic patterns may be spaced apart from the planarization layer 115 and may be made of the same material as the planarization layer 115.

[0101] In these cases, a plurality of organic patterns are disposed on the first pad electrode PAD1 and spaced apart from each other, and the second pad electrode PAD2 is disposed on the plurality of organic patterns so that the second pad electrode PAD2 may be electrically connected to the first pad electrode PAD1 exposed by the plurality of organic patterns.

[0102] Therefore, in the display device 100 according to one or more embodiments of the present disclosure, the organic film OF is disposed on the exposed portions of the plurality of first pad electrodes PAD1 that are not covered by the planarization layer 115. Therefore, even if the mask sags, the mask first contacts the organic film OF, which can prevent the first pad electrode PAD1 from being recessed due to the mask. In these cases, the plurality of organic patterns can be disposed to be spaced apart from the planarization layer 115 and made of the same material as the planarization layer 115.

[0103] Therefore, in the display device 100 according to one or more embodiments of the present disclosure, a plurality of organic films OF are disposed on the first pad electrode PAD1, and exposure of the first pad electrode PAD1 is minimized or at least reduced, so that current flowing into the first pad electrode PAD1 caused by the drooping mask is suppressed, which can minimize or at least reduce static electricity, suppress arcing, and improve reliability.

[0104] That is, in the display device 100 according to one or more embodiments of the present disclosure, the organic film OF is disposed on the plurality of first pad electrodes PAD1 , which can suppress damage to the first pad electrodes PAD1 .

[0105] The embodiments of the present disclosure may also be described as follows:

[0106] According to one or more embodiments of the present disclosure, a display device is provided. The display device includes: a substrate, including a display area provided with a plurality of sub-pixels and a non-display area configured to surround the display area; a plurality of transistors, respectively provided in the plurality of sub-pixels; a planarization layer, configured to cover the plurality of transistors; a light-emitting element, provided on the planarization layer; a plurality of first pad electrodes, provided in the non-display area; and an organic film, provided on the plurality of first pad electrodes. The planarization layer covers the edges of the plurality of first pad electrodes and is spaced apart from the organic film.

[0107] The organic film may include a plurality of organic patterns spaced apart from each other.

[0108] The organic film may be made of the same material as the planarization layer.

[0109] The display device may further include a plurality of second pad electrodes disposed on the plurality of first pad electrodes and the organic film and configured to be adjacent to the plurality of first pad electrodes.

[0110] The display device may further include a touch detection unit disposed on the light emitting element in the display area. The touch detection unit may further include an insulating layer, a plurality of touch electrodes, and a plurality of touch bridge electrodes. The plurality of second pad electrodes may be made of the same material as one of the plurality of touch electrodes and the plurality of touch bridge electrodes.

[0111] The insulating layer may be disposed on the plurality of first pad electrodes and cover the organic film. The plurality of second pad electrodes may be connected to the plurality of first pad electrodes through contact holes of the insulating layer.

[0112] The display device may further include a conductive bonding layer disposed on the plurality of second pad electrodes, and a flexible film electrically connected to the plurality of second pad electrodes through the conductive bonding layer.

[0113] The plurality of first pad electrodes may be disposed on the same layer and made of the same material as the source and drain of each of the plurality of transistors.

[0114] The display device may further include a plurality of metal layers disposed between the plurality of first pad electrodes and the substrate and connected to the plurality of first pad electrodes. The plurality of metal layers may include a first metal layer and a second metal layer disposed on the first metal layer.

[0115] The display device may further include a plurality of capacitors disposed in the plurality of sub-pixels. The first metal layer may be made of the same material as a gate electrode of each of the plurality of transistors. The second metal layer may be made of the same material as a capacitor electrode of the plurality of capacitors.

[0116] The display device may further include a plurality of connection lines connected to the plurality of first pad electrodes and extending to the display area. The plurality of connection lines may be made of the same material as the first metal layer and the second metal layer.

[0117] Although the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; a plurality of transistors in the plurality of sub-pixels; a planarization layer covering the plurality of transistors; A light emitting element, on the planarization layer; A plurality of first pad electrodes in the non-display area; as well as an organic film on the plurality of first pad electrodes, The planarization layer covers edges of the plurality of first pad electrodes and is spaced apart from the organic film.

2. The display device according to claim 1, wherein: The organic film includes a plurality of organic patterns spaced apart from each other.

3. The display device according to claim 1, wherein: The organic film includes the same material as the planarization layer. 4 . The display device according to claim 3 , further comprising a plurality of second pad electrodes on the plurality of first pad electrodes and the organic film, and the plurality of second pad electrodes are arranged adjacent to the plurality of first pad electrodes.

5. The display device according to claim 4, further comprising a touch detection unit, wherein the touch detection unit is in the display area and on the light emitting element. in, The touch detection unit includes an insulating layer, a plurality of touch electrodes and a plurality of touch bridge electrodes, and The plurality of second pad electrodes include a same material as that of one of the plurality of touch electrodes and the plurality of touch bridge electrodes.

6. The display device according to claim 5, wherein: The insulating layer is on the plurality of first pad electrodes and covers the organic film, and The plurality of second pad electrodes are connected to the plurality of first pad electrodes through contact holes of the insulating layer.

7. The display device according to claim 4, further comprising: a conductive bonding layer on the plurality of second pad electrodes; as well as A flexible film is electrically connected to the plurality of second pad electrodes through the conductive bonding layer.

8. The display device according to claim 1, wherein: The plurality of first pad electrodes are on a same layer and include a same material as a source and a drain of each of the plurality of transistors.

9. The display device according to claim 1 , further comprising a plurality of metal layers between the plurality of first pad electrodes and the substrate, and the plurality of metal layers are connected to the plurality of first pad electrodes, in, The plurality of metal layers include: a first metal layer; and The second metal layer is on the first metal layer.

10. The display device according to claim 9, further comprising a plurality of capacitors in the plurality of sub-pixels, in, The first metal layer includes the same material as the gate of each of the plurality of transistors, and The second metal layer includes a same material as a capacitor electrode of the plurality of capacitors.

11. The display device according to claim 9, further comprising a plurality of connection lines connected to the plurality of first pad electrodes, and the plurality of connection lines extend to the display area, in, The plurality of connection lines include the same material as the first metal layer and the second metal layer.

12. A display device, comprising: A substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; A first pad electrode, in the non-display area; a planarization layer, on the first pad electrode, the planarization layer covering an edge portion of the first pad electrode; as well as an organic film on a portion of the first pad electrode, the portion of the first pad electrode not being covered by the planarization layer, The planarization layer is spaced apart from the organic film so that the portion of the first pad electrode is exposed.

13. The display device according to claim 12, wherein: The organic film includes a plurality of organic patterns spaced apart from each other.

14. The display device according to claim 12, wherein: The organic film includes the same material as the planarization layer. 15 . The display device of claim 12 , further comprising a second pad electrode on the organic film and the exposed portion of the first pad electrode.

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