PMUT based on piezoelectric MEMS chip and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor technology, in particular to a piezoelectric MEMS chip-based PMUT and a preparation method thereof, the piezoelectric MEMS chip-based PMUT comprises a substrate, the substrate is provided with a front surface and a back surface which are opposite to each other, a piezoelectric layer is formed on the front surface of the substrate, the substrate is provided with a back cavity in a penetrating manner, a structural layer is formed on the surface of the piezoelectric layer, and the thickness of the structural layer is greater than that of a piezoelectric film in the piezoelectric layer; the neutral surface is located in the transverse projection area range of the structural layer; an isolation groove is formed in the area, located in the vibrating diaphragm, of the top electrode of the piezoelectric layer, and the isolation groove divides the top electrode into an internal electrode and an external electrode which are independent of each other. The preparation method comprises the following steps: growing the piezoelectric layer on the front surface of the substrate; etching the top electrode; growing a structural layer; and penetrating through the etching substrate to form a back cavity. The silicon oxide is used as the structural layer, the Young modulus of the silicon oxide is low, the process stress is low, the resonant frequency can be effectively reduced, on the basis, the top electrode is etched to form the slit, and stress release is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor process technology, and in particular to a PMUT based on a piezoelectric MEMS chip and a preparation method thereof. Background Art

[0002] Ultrasonic sensors are sensors that convert ultrasonic signals into other energy signals (usually electrical signals). Ultrasonic waves are mechanical waves with a vibration frequency higher than 20kHz. They have the characteristics of high frequency, short wavelength, small diffraction phenomenon, especially good directionality, and the ability to propagate in a directional manner as rays. Ultrasonic waves have a great ability to penetrate liquids and solids, especially in solids that are opaque to sunlight. When ultrasonic waves encounter impurities or interfaces, they will produce significant reflections to form reflected echoes, and when they encounter moving objects, they can produce the Doppler effect. Ultrasonic sensors are widely used in industry, national defense, biomedicine, etc.

[0003] In the prior art, low-frequency ultrasonic sensors are needed in the technical fields of long-distance measurement, monitoring, and remote information transmission using ultrasound. Therefore, low-frequency MEMS chip devices also have a large market. However, traditional piezoelectric MEMS chips are composed of a stacked SOI substrate with a back cavity and a piezoelectric layer. The top silicon in the SOI substrate serves as a structural layer and assumes the function of a neutral plane. The Young's modulus of silicon is high and the process stress is high, which leads to a high resonant frequency, which is not conducive to the production design and manufacturing of low-frequency devices. On this basis, the electrode layer of the chip cannot be stress-released, and the stress is relatively concentrated, which is not conducive to the chip achieving optimal performance.

[0004] In summary, the present application now proposes a PMUT based on a piezoelectric MEMS chip and a preparation method thereof to solve the above-mentioned problems. Summary of the invention

[0005] The present invention aims to solve the problems raised in the background technology. The purpose of one or more embodiments of this specification is to propose a PMUT based on a piezoelectric MEMS chip and a preparation method thereof, using silicon oxide as a structural layer to replace traditional top silicon. Silicon oxide has a low Young's modulus and low process stress, which can effectively reduce the resonant frequency. On this basis, the top electrode is etched to form a slit to achieve stress release.

[0006] Based on the above purpose, one or more embodiments of the present specification provide a PMUT based on a piezoelectric MEMS chip, comprising a substrate, wherein the substrate has a front side and a back side opposite to each other, a piezoelectric layer is formed on the front side of the substrate, a back cavity is formed through the substrate, the piezoelectric layer and the structural layer within the longitudinal projection area of ​​the back cavity are a diaphragm, a structural layer is formed on the surface of the piezoelectric layer, the thickness of the structural layer is greater than the thickness of the piezoelectric film in the piezoelectric layer, so that the neutral plane is located within the lateral projection area of ​​the structural layer;

[0007] Wherein, an isolation groove is provided in the region where the top electrode of the piezoelectric layer is located at the diaphragm, and the isolation groove separates the top electrode into an internal electrode and an external electrode which are independent of each other.

[0008] According to the PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention, the material of the structural layer is silicon oxide.

[0009] According to the PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention, the structural layer is a double-layer structure or a triple-layer structure in which silicon nitride and silicon oxide are alternately stacked.

[0010] According to the PMUT based on the piezoelectric MEMS chip proposed in an embodiment of the present invention, the top electrode of the piezoelectric layer forms a lead-out electrode in the non-diaphragm area of ​​the piezoelectric film surface of the piezoelectric layer, and the lead-out electrode is connected to the internal electrode or the external electrode. The structural layer corresponds to the position of the lead-out electrode and has a through hole for exposing the lead-out electrode. The structural layer, the top electrode of the piezoelectric layer, and the non-diaphragm area of ​​the piezoelectric film also have a through hole for exposing part of the bottom electrode.

[0011] According to the PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention, the external electrode is electrically connected to the lead-out electrode to serve as a driving electrode.

[0012] According to the PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention, a plurality of strip-shaped grooves penetrating the external electrodes are symmetrically provided on the external electrodes.

[0013] According to the PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention, the external electrode is divided into a plurality of right-angled trapezoidal structures of equal specifications by a plurality of strip-shaped grooves, and adjacent right-angled trapezoidal structures are electrically connected.

[0014] According to the PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention, the internal electrode is electrically connected to the lead-out electrode to serve as a driving electrode.

[0015] According to the PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention, the internal electrodes are symmetrically provided with arc grooves.

[0016] According to the PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention, a hole-shaped groove is provided at the center of the internal electrode diaphragm and / or a plurality of hole-shaped grooves are provided in a ring array around the center of the diaphragm.

[0017] According to the PMUT based on the piezoelectric MEMS chip proposed in an embodiment of the present invention, the internal electrode is provided with a plurality of arrow-shaped grooves in a ring array around the center of the diaphragm.

[0018] A preparation method according to an embodiment of the present invention is used to prepare the PMUT based on the piezoelectric MEMS chip as described above, comprising the following steps:

[0019] Prepare a substrate, wherein the substrate has a front side and a back side opposite to each other, and the piezoelectric layer and the structural layer within the longitudinal projection area of ​​the back cavity are diaphragms;

[0020] growing a piezoelectric layer on the front side of the substrate;

[0021] The top electrode of the piezoelectric layer is etched to pattern the piezoelectric layer, and an isolation groove is formed in the top electrode diaphragm region due to the etching, and the isolation groove separates the top electrode into an inner electrode and an outer electrode which are independent of each other;

[0022] Growing a structural layer on the surface of the patterned piezoelectric layer, wherein the bottom of the structural layer is embedded in the area where the top electrode is etched away;

[0023] Etching the structural layer to pattern the structural layer;

[0024] Etching through the substrate to form a back cavity;

[0025] The thickness of the structural layer is greater than the thickness of the piezoelectric film in the piezoelectric layer, so that the neutral plane is located within the lateral projection area of ​​the structural layer.

[0026] The PMUT based on the piezoelectric MEMS chip and the manufacturing method thereof disclosed in the present invention release the stress of the top electrode by opening an isolation groove a, and at the same time, the ungrooved area of ​​the top electrode is used to balance the thermal expansion stress during the process to achieve film leveling.

[0027] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate one or more embodiments of the present specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic diagram of the structure of a PMUT based on a piezoelectric MEMS chip proposed in an embodiment of the present invention;

[0030] Figure 2 for Figure 1 Exploded diagram of the structure;

[0031] Figure 3 for Figure 1 A front view of

[0032] Figure 4 for Figure 1 A top view of

[0033] Figure 5 for Figure 1 Bottom view of

[0034] Figure 6 A schematic diagram of the structure of the top electrode proposed in Example 2 of the present invention;

[0035] Figure 7 This is a schematic diagram of a better technical solution structure of Embodiment 2 of the present invention;

[0036] Figure 8 This is a schematic diagram of the structure of the top electrode proposed in Example 3 of the present invention;

[0037] Fig. 9 This is a schematic diagram of a better technical solution structure of Embodiment 3 of the present invention;

[0038] Fig.10 This is a schematic diagram of the structure of the top electrode proposed in Example 4 of the present invention;

[0039] Fig.11 This is a schematic diagram of the S1 process of the method for preparing a PMUT based on a piezoelectric MEMS chip according to an embodiment of the present invention;

[0040] Fig.12a This is a schematic diagram of the S2 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0041] Figure 12b This is a schematic diagram of the S2 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 2 of the present invention;

[0042] Fig.12c This is a schematic diagram of the S2 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 3 of the present invention;

[0043] Fig.12d This is a schematic diagram of the S2 process of the method for preparing a PMUT based on a piezoelectric MEMS chip according to Embodiment 4 of the present invention;

[0044] Fig.13a This is a schematic diagram of the S3 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0045] Fig.13b This is a schematic diagram of the S3 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0046] Fig.13c This is a schematic diagram of the S3 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0047] Fig.13d This is a schematic diagram of the S3 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0048] Fig.14a This is a schematic diagram of the S4 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0049] Fig.14b This is a schematic diagram of the S4 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0050] Fig.14c This is a schematic diagram of the S4 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0051] Fig.14d This is a schematic diagram of the S4 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0052] Fig.15a This is a schematic diagram of the S5 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0053] Fig.15b This is a schematic diagram of the S5 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0054] Fig.15c This is a schematic diagram of the S5 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;

[0055] Fig.15d This is a schematic diagram of the S5 process of the method for preparing a PMUT based on a piezoelectric MEMS chip proposed in Example 1 of the present invention;.

[0056] In the figure, the following are the numerals: 1. substrate; 2. piezoelectric layer; 21. bottom electrode; 22. piezoelectric film; 23. top electrode; 231. internal electrode; 232. external electrode; 233. lead-out electrode; 234. connection portion; 3. structural layer; 31. first structural layer; 32. second structural layer; 33. third structural layer; a. separation groove; b. 1 .Hole-shaped groove; b 2 . Arc groove; b 3 .Arrow groove; c.Strip groove. DETAILED DESCRIPTION

[0057] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0058] Example 1

[0059] See also Figure 1-Figure 5 The PMUT based on the piezoelectric MEMS chip proposed in an embodiment of the present invention includes a substrate 1, a piezoelectric layer 2 and a structural layer 3 which are stacked in sequence.

[0060] The substrate 1 has a front side and a back side opposite to each other. A back cavity is opened from the back side of the substrate 1 through the substrate 1. The piezoelectric layer 2 and the structural layer 3 within the longitudinal projection range of the back cavity are diaphragms. The back cavity provides a vibration space for the diaphragm.

[0061] The piezoelectric layer 2 includes a bottom electrode 21, a piezoelectric film 22 and a top electrode 23 which are sequentially stacked on the surface of the substrate 1. The thickness of the structural layer 3 is greater than that of the piezoelectric film 12, so that the neutral plane is located within the lateral projection area of ​​the structural layer 3.

[0062] The material of the structural layer 3 is silicon oxide, and the Young's modulus of silicon oxide is lower than that of silicon.

[0063] The MEMS chip-based piezoelectric PMUT proposed in the embodiment of the present invention uses silicon oxide instead of silicon as the material of the structural layer. Silicon oxide has a low Young's modulus and low process stress, which can effectively reduce the resonant frequency and is useful for the design and manufacture of low-frequency devices.

[0064] Optionally, the substrate 1 is a silicon wafer substrate, and the cost is reduced by replacing the SOI substrate with the silicon wafer substrate.

[0065] Optionally, the structural layer 3 includes a first structural layer 31 and a second structural layer 32 , and the thickness of the second structural layer 32 is much greater than the thickness of the first structural layer 31 .

[0066] Preferably, the material of the first structure layer 31 is silicon nitride (Si3N4), and the material of the second structure layer 32 is silicon oxide (SiO2).

[0067] It should be noted that, in some embodiments, those skilled in the art may optionally select, when the material of the first structure layer 31 is silicon oxide, the material of the second structure layer 32 is silicon nitride.

[0068] Preferably, the structure layer 3 includes a first structure layer 31, a second structure layer 32 and a third structure layer 33, and the thickness of the second structure layer 32 is much greater than the thickness of the first structure layer 31 and / or the third structure layer 33. Preferably, the material of the first structure layer 31 is silicon nitride (Si3N4), the material of the second structure layer 32 is silicon oxide (SiO2), and the material of the third structure layer 33 is silicon nitride.

[0069] It should be noted that, in some embodiments, those skilled in the art may optionally select, when the material of the first structure layer 31 is silicon oxide, the material of the second structure layer 32 is silicon nitride, and the material of the third structure layer 33 is silicon oxide.

[0070] The main structure of the structural layer 3 in the embodiment of the present invention is the second structural layer 32. The second structural layer 32 mainly has the function of adjusting the neutral plane of the chip. The device performance is mainly determined by the material and thickness of the second structural layer 32. The main function of the first structural layer 31 is to improve the adhesion of the middle layer and improve the film forming quality. The third structural layer 33 increases the flexibility of the structural layer 3. The three-layer structure is more stable and reliable, and the yield rate is improved.

[0071] An isolation groove a is provided in the region of the top electrode 23 located on the diaphragm. The isolation groove a separates the top electrode 23 into an inner electrode 231 and an outer electrode 232 that are independent of each other. The isolation groove a is provided on the top electrode 23 and penetrates the top electrode 23 .

[0072] The PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention releases the stress of the top electrode 23 by opening the isolation groove a. Meanwhile, the ungrooved area of ​​the top electrode 23 is used to balance the thermal expansion stress during the process to achieve film leveling.

[0073] Example 2

[0074] For better film leveling, see Figure 6 As a preferred solution of Example 1, an extraction electrode 233 is formed in the non-diaphragm region of the top electrode 23, a through hole for exposing the extraction electrode 233 is provided at a position of the structural layer 3 corresponding to the extraction electrode 233, and a through hole for exposing the bottom electrode 21 is provided in the non-diaphragm region of the structural layer 3, the top electrode 23 and the piezoelectric film 22 (specifically, Figure 4 shown).

[0075] The external electrode 232 is electrically connected to the lead-out electrode 233 to serve as a driving electrode.

[0076] like Figure 7As shown, preferably, a plurality of strip grooves c are provided on the external electrode 232 and penetrate the external electrode 232. Optionally, the strip grooves c are connected to the isolation groove a. Optionally, the plurality of strip grooves c are arranged axially symmetrically. Optionally, the plurality of strip grooves c are arranged centrally symmetrically around the center of the diaphragm. Optionally, the external electrode 232 is divided into a plurality of right-angled trapezoidal structures of equal specifications by the plurality of strip grooves c. The corners of adjacent right-angled trapezoidal structures are electrically connected by arc-shaped connecting portions 234. Stress release is achieved by etching the strip grooves c formed by the top electrode 23 and the isolation groove a (i.e., the formed slits).

[0077] Example 3

[0078] For better film leveling, see Figure 8 As a preferred solution of Example 1, a lead-out electrode 233 is formed in the non-diaphragm area of ​​the top electrode 23, a through hole for exposing the lead-out electrode 233 is opened in the position of the structural layer 3 corresponding to the lead-out electrode 233, and a through hole for exposing the bottom electrode 21 is opened in the non-diaphragm area of ​​the structural layer 3, the top electrode 23 and the piezoelectric film 22.

[0079] The internal electrode 231 is electrically connected to the lead-out electrode 233 to serve as a driving electrode.

[0080] In order to achieve better film leveling effect, such as Fig. 9 In some embodiments, the inner electrode 231 preferably has arc-shaped grooves b symmetrically formed therein. 2 , two arc grooves b 2 Optionally, a hole-shaped groove b is provided at the center of the diaphragm of the internal electrode 231. 1 and a plurality of hole-shaped slots b are provided in a circular array around the center of the diaphragm 1 , hole-shaped groove b 1 Located in the arc groove.

[0081] Example 4

[0082] like Fig.10 As shown in the figure, in order to achieve a better film leveling effect, as a preferred solution of Example 1, an extraction electrode 233 is formed in the non-diaphragm area of ​​the top electrode 23, a through hole for exposing the extraction electrode 233 is opened at the position of the structural layer 3 corresponding to the extraction electrode 233, and a through hole for exposing the bottom electrode 21 is opened in the non-diaphragm area of ​​the structural layer 3, the top electrode 23 and the piezoelectric film 22, and the internal electrode 231 is electrically connected to the extraction electrode 233 as a driving electrode; the internal electrode 231 is provided with a plurality of arrow grooves b in a ring array around the center of the diaphragm. 3 , arrow slot b 3 The arrow portion is connected to the separation groove a. In this embodiment, the arrow groove b 3 There are four groups, each group of arrow grooves b 3The arrow part of the arrow points to the separation groove a, and the arrow groove b 3 The connection line points to the center of the inner electrode 231 .

[0083] Example 5

[0084] The preparation method proposed in the embodiment of the present invention is used to prepare the PMUT based on the piezoelectric MEMS chip proposed in embodiments 1-3, comprising the following steps:

[0085] See also Fig.11 S1, preparing a substrate 1, the substrate 1 having a front side and a back side opposite to each other, and growing a piezoelectric layer 2 on the front side of the substrate 1, specifically comprising:

[0086] S1-1, sputtering and growing a bottom electrode 21 on the front surface of the substrate 1;

[0087] S1-2, sputtering and growing a piezoelectric film 22 on the surface of the bottom electrode 21;

[0088] S1 - 3 , a top electrode 23 is sputtered and grown on the surface of the piezoelectric film 22 .

[0089] See also Figure 12a-12d , S2, etching the piezoelectric layer 2 to pattern the piezoelectric layer 2, specifically including: using IBE dry method to etch the top electrode 23 to pattern the top electrode 23, the diaphragm area of ​​the top electrode 23 is etched to form an isolation groove a, and the isolation groove a separates the top electrode 23 into an internal electrode 231 and an external electrode 232 that are independent of each other.

[0090] See also Figure 13a-13d , S3, using PECVD process to deposit the structural layer 3 on the surface of the piezoelectric layer 2, the thickness of the structural layer 3 is greater than the thickness of the piezoelectric film 22, so that the neutral plane is located within the lateral projection area of ​​the structural layer 3.

[0091] Preferably, the structural layer 3 includes a first structural layer 31, a second structural layer 32 and a third structural layer 33, the material of the first structural layer 31 and the third structural layer 33 is silicon nitride, the material of the second structural layer 32 is silicon oxide, and the thickness of the second structural layer 32 is much greater than the thickness of the first structural layer 31 and / or the third structural layer 33.

[0092] See also Figure 14a-14d , S4, etching the structural layer 3 to pattern the structural layer 3;

[0093] See also Figure 15a-Figure 15d S5, etching the substrate 1 from the back side of the substrate 1 to form a back cavity, the piezoelectric layer 2 and the structural layer 3 within the longitudinal projection area of ​​the back cavity are the diaphragm, and the back cavity provides a vibration space for the diaphragm, specifically including:

[0094] S5-1, etching the back side of the substrate 1 by DIRE. The substrate 1 will not be penetrated here because the piezoelectric layer 2 will be damaged by DIRE etching. Therefore, 5-15% of the thickness of the substrate 1 will remain after DIRE etching.

[0095] S5-2, etching the back side of the substrate 1 by a wet process, completely penetrating the remaining 5-15% thickness of the substrate 1, forming a U-shaped support structure, and forming a back cavity.

[0096] The preparation method of the present invention is for a piezoelectric MEMS chip based on a silicon wafer substrate. When the SOI substrate is etched, the buried oxide layer serves as a cutoff line, and a back cavity can be formed by penetrating the buried oxide layer. Pure dry etching may damage the piezoelectric layer 2. In order to improve the yield rate, a part of the silicon wafer substrate is dry-etched, and then the remaining part is etched through by a wet process. The wet process will not affect the piezoelectric layer 2.

[0097] Compared with the traditional preparation process, the preparation method of the piezoelectric PMUT based on the MEMS chip proposed in the embodiment of the present invention first grows the piezoelectric layer 2 and patterns it, then grows the structural layer 3 on the surface of the piezoelectric layer 2, and then patterns the structural layer 3. Therefore, the patterning steps of the piezoelectric layer 2 and the structural layer 3 are independent and do not interfere with each other. The piezoelectric layer 2 does not need to be unnecessary hollowed out due to the pattern of the structural layer 3, thereby ensuring the integrity of the piezoelectric layer 2 to the greatest extent.

[0098] The PMUT based on the piezoelectric MEMS chip proposed in the embodiment of the present invention realizes stress release of the top electrode 23 by etching an isolation groove a in the top electrode 23. At the same time, the ungrooved area of ​​the top electrode 23 is used to balance the thermal expansion stress during the process to achieve film leveling.

[0099] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0100] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0101] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0102] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0103] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A PMUT based on a piezoelectric MEMS chip, comprising a substrate (1), wherein the substrate (1) has a front side and a back side opposite to each other, and a piezoelectric layer (2) is formed on the front side of the substrate (1), characterized in that: The substrate (1) is provided with a back cavity through it, the piezoelectric layer (2) and the structural layer (3) within the longitudinal projection area of ​​the back cavity are diaphragms, a structural layer (3) is formed on the surface of the piezoelectric layer (2), the thickness of the structural layer (3) is greater than the thickness of the piezoelectric film (22) in the piezoelectric layer (2), so that the neutral plane is located within the transverse projection area of ​​the structural layer (3); The top electrode (23) of the piezoelectric layer (2) is located in the region of the diaphragm and an isolation groove (a) is provided, and the isolation groove (a) separates the top electrode (23) into an internal electrode (231) and an external electrode (232) which are independent of each other.

2. The PMUT based on the piezoelectric MEMS chip according to claim 1, characterized in that: The top electrode (23) of the piezoelectric layer (2) forms an extraction electrode (233) in the non-diaphragm area of ​​the surface of the piezoelectric film (22) of the piezoelectric layer (2); the extraction electrode (233) is electrically connected to the internal electrode (231) or the external electrode (232); the structural layer (3) is provided with a through hole for exposing the extraction electrode (233) at the position corresponding to the extraction electrode (233); the structural layer (3) and the top electrode (23) of the piezoelectric layer (2) and the non-diaphragm area of ​​the piezoelectric film (22) are all provided with a through hole for exposing a portion of the bottom electrode (21).

3. The PMUT based on the piezoelectric MEMS chip according to claim 2, characterized in that: The external electrode (232) is electrically connected to the lead-out electrode (233) to serve as a driving electrode.

4. The PMUT based on the piezoelectric MEMS chip according to claim 3, characterized in that: A plurality of strip-shaped grooves (c) penetrating the external electrode (232) are symmetrically arranged on the external electrode (232).

5. The PMUT based on the piezoelectric MEMS chip according to claim 4, characterized in that: The external electrode (232) is divided into a plurality of right-angled trapezoidal structures of equal specifications by a plurality of strip-shaped grooves (c), and adjacent right-angled trapezoidal structures are electrically connected.

6. The PMUT based on the piezoelectric MEMS chip according to claim 2, characterized in that: The internal electrode (231) is electrically connected to the lead-out electrode (233) to serve as a driving electrode.

7. The PMUT based on the piezoelectric MEMS chip according to claim 6, characterized in that: The inner electrode (231) is symmetrically provided with arc-shaped grooves (b2).

8. The PMUT based on the piezoelectric MEMS chip according to claim 7, characterized in that: The inner electrode (231) has a hole-shaped groove (b1) at the center of the diaphragm and / or has a plurality of hole-shaped grooves (b1) in a ring array around the center of the diaphragm.

9. The PMUT based on the piezoelectric MEMS chip according to claim 6, characterized in that: The internal electrode (231) is provided with a plurality of arrow-shaped grooves (b3) in a ring array around the center of the diaphragm.

10. A preparation method for preparing the PMUT based on the piezoelectric MEMS chip as claimed in any one of claims 1 to 11, characterized in that: The following steps are involved: A substrate (1) is prepared, wherein the substrate (1) has a front side and a back side opposite to each other, and the piezoelectric layer (2) and the structural layer (3) within the longitudinal projection area of ​​the back cavity are diaphragms; Growing a piezoelectric layer (2) on the front side of the substrate (1); Etching the top electrode (23) of the piezoelectric layer (2) to pattern the piezoelectric layer (2), forming an isolation groove (a) in the diaphragm region of the top electrode (23) due to the etching, and the isolation groove (a) separates the top electrode (23) into an internal electrode (231) and an external electrode (232) that are independent of each other; A structural layer (3) is grown on the surface of the patterned piezoelectric layer (2), and the bottom of the structural layer (3) is embedded in the area where the top electrode (23) is etched away; Etching the structural layer (3) to pattern the structural layer (3); Etching through the substrate (1) to form a back cavity; The thickness of the structural layer (3) is greater than the thickness of the piezoelectric film (22) in the piezoelectric layer (2), so that the neutral plane is located within the lateral projection area of ​​the structural layer (3).

Images