Regeneration chip for ink box and manufacturing method thereof

Abstract

The invention discloses a regeneration chip for an ink box and a manufacturing method, the regeneration chip comprises a substrate, a memory and a plurality of regeneration terminals, the substrate comprises a front surface and a back surface, the memory is arranged on the back surface of the substrate, and the plurality of regeneration terminals are arranged on the front surface of the substrate; a plurality of regeneration terminals arranged in a plurality of rows, the plurality of regeneration terminals including a first regeneration terminal, a second regeneration terminal, a third regeneration terminal, a fourth regeneration terminal, a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal, and a ninth regeneration terminal; the first regeneration terminal is electrically connected with any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal; the regeneration chip with the structure can be suitable for new imaging equipment and can be reused.

Description

[0001] The present invention claims the priority of the prior Chinese application with the application date of August 22, 2023, the invention name of “A regeneration chip and its manufacturing method” and the application number of 202311063126.9, the prior Chinese application with the application date of August 24, 2023, the invention name of “A regeneration chip for ink cartridge and its manufacturing method” and the application number of 202311078271.4, and the prior Chinese application with the application date of August 25, 2023, the invention name of “A regeneration chip for ink cartridge and its manufacturing method” and the application number of 202311089094.X. All contents of the prior Chinese applications are cross-referenced in this application. Technical Field

[0002] The present invention relates to the technical field of printers, and in particular to a regeneration chip for an ink cartridge and a manufacturing method thereof. Background Art

[0003] At present, in order to enable the imaging device (printer) to timely identify the relevant information of the ink cartridge to avoid incorrect installation of the ink cartridge, and to record the consumption of the printing material in real time to avoid damage to the imaging device, a storage chip is often provided on the ink cartridge. The storage chip stores the relevant information of the ink cartridge, such as the printing material capacity, ink cartridge identification information, production date, etc., and its cost is relatively high.

[0004] However, with the continuous development of imaging technology, the size of imaging devices is getting smaller and smaller. Correspondingly, the size of ink cartridges as storage containers for printing materials is also limited. Therefore, users need to constantly replace ink cartridges. However, most old ink cartridges are discarded, and these discarded ink cartridges include plastics, chips, etc. Most of them cannot be naturally degraded, especially chips, whose circuits and metals will cause great pollution to the environment. Moreover, due to their high cost, discarding old ink cartridges means that users must spend a high price to buy the chips in new ink cartridges, which will undoubtedly cause users' printing costs to be too high.

[0005] Therefore, the prior art has proposed to recycle the chips on the ink cartridges for reuse, thereby reducing pollution to the environment and reducing the printing costs of users. At present, the number of nine-terminal chips disclosed in Chinese patent CN101712239B is far greater than the five-terminal chips disclosed in patent US11535038B1. Such five-terminal chips are currently scarce on the market. How to modify and recycle the nine-terminal chips and apply them to new imaging devices (printers) is an important topic for researchers in this field. Summary of the invention

[0006] The invention provides a chip for an ink cartridge and a manufacturing method thereof, so as to solve the technical problem of recycling and remanufacturing the existing nine-terminal chip for the ink cartridge.

[0007] In order to achieve the first purpose, the present invention discloses a regeneration chip for an ink cartridge, comprising: a substrate, a memory and a plurality of regeneration terminals, the substrate comprising a front side and a back side, the memory being arranged on the back side of the substrate, and the plurality of regeneration terminals being arranged on the front side of the substrate; the plurality of regeneration terminals being arranged in a plurality of rows, the plurality of regeneration terminals comprising a first regeneration terminal, a second regeneration terminal, a third regeneration terminal, a fourth regeneration terminal, a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal; the first regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal.

[0008] Preferably, the regeneration terminals are arranged into a first row and a second row, the first row including a first regeneration terminal, a second regeneration terminal, a third regeneration terminal and a fourth regeneration terminal arranged from left to right; the second row including a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal arranged from left to right.

[0009] Preferably, at least one of the fifth regeneration terminal and the ninth regeneration terminal is electrically connected to the memory.

[0010] Preferably, the fifth regeneration terminal is electrically connected to the memory via a third conductor, and the third conductor is at least partially located on the back side of the substrate.

[0011] Preferably, the ninth regeneration terminal is electrically connected to the memory via a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate.

[0012] Preferably, at least one of the third regeneration terminal, the seventh regeneration terminal and the eighth regeneration terminal is electrically connected to the memory via a fifth conductor, and the fifth conductor is at least partially located on the back side of the substrate.

[0013] Preferably, the fifth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a third conductor, and the third conductor is at least partially located on the back side of the substrate.

[0014] Preferably, the fifth regeneration terminal is electrically connected to any one of the fifth conductors via a third conductor, and the third conductor is at least partially located on the back side of the substrate.

[0015] Preferably, the ninth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate.

[0016] Preferably, the ninth regeneration terminal is electrically connected to any one of the fifth conductors via a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate.

[0017] Preferably, the first regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a first conductor, and the first conductor is at least partially located on the front surface of the substrate.

[0018] Preferably, the first regeneration terminal is electrically connected to the fourth regeneration terminal through the second conductor, the fourth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through the first conductor, the first conductor is at least partially located on the front side of the substrate, and the second conductor is at least partially located on the front side of the substrate.

[0019] Preferably, the first regeneration terminal is electrically connected to any one of the fifth conductors through the first conductor.

[0020] Preferably, the first regeneration terminal is electrically connected to the fourth regeneration terminal through the second conductor, the fourth regeneration terminal is electrically connected to any fifth conductor through the first conductor, the first conductor is at least partially located on the front surface of the substrate, and the second conductor is at least partially located on the front surface of the substrate.

[0021] Preferably, the first regeneration terminal is a data terminal, which is configured to contact a corresponding data contact pin among a plurality of imaging device contact pins; the second regeneration terminal is a reset terminal, which is configured to contact a corresponding reset contact pin among a plurality of imaging device contact pins; the fifth regeneration terminal is a clock terminal, which is configured to contact a corresponding clock contact pin among a plurality of imaging device contact pins; the sixth regeneration terminal is a power terminal, which is configured to contact a corresponding power contact pin among a plurality of imaging device contact pins; and the ninth regeneration terminal is a ground terminal, which is configured to contact a corresponding ground contact pin among a plurality of imaging device contact pins.

[0022] Preferably, the memory includes a data pin, a reset pin, a clock pin, a power pin and a ground pin, the fifth regeneration terminal is electrically connected to the clock pin through a third conductor, and the ninth regeneration terminal is electrically connected to the ground pin through a fourth conductor.

[0023] In order to achieve the second objective, the present invention discloses a method for manufacturing a regeneration chip for an ink cartridge, the manufacturing method comprising the following steps:

[0024] A. Remove the nine-terminal chip from the ink cartridge;

[0025] B. electrically connecting the first terminal to the eighth terminal;

[0026] C. electrically connecting the fifth terminal to a clock pin of the memory;

[0027] D. Electrically connect the ninth terminal to the ground pin of the memory.

[0028] Preferably, the manufacturing method further comprises: before electrically connecting the fifth terminal and the clock pin of the memory, providing an insulating isolation layer on the back side of the substrate, wherein the isolation layer is used to isolate the conductor electrically connected between the fifth terminal and the clock pin from other conductors.

[0029] Preferably, the manufacturing method further comprises: before electrically connecting the ninth terminal and the ground pin of the memory, providing an insulating isolation layer on the back side of the substrate, wherein the isolation layer is used to isolate the conductor electrically connected between the ninth terminal and the ground pin from other conductors.

[0030] Preferably, the manufacturing method further comprises rewriting the program inside the memory.

[0031] Preferably, the manufacturing method according to claim 7 is characterized in that the manufacturing method also includes replacing the memory.

[0032] Preferably, the manufacturing method further comprises welding an insulating layer on the back side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a front view schematic diagram of a nine-terminal chip in the prior art;

[0034] Figure 2 It is a schematic diagram of the back side of a nine-terminal chip in the prior art;

[0035] Figure 3 is a front schematic diagram of the regeneration chip of Example 1 of the present invention;

[0036] Figure 4 It is a schematic diagram of the back side of the regeneration chip according to Example 1 of the present invention.

[0037] Figure 5 It is a structural schematic diagram of the combination state of the regeneration chip and the external substrate in Example 2 of the present invention.

[0038] Figure 6 This is an exploded schematic diagram of the regeneration chip and the external substrate of Example 2 of the present invention.

[0039] Figure 7 It is a front schematic diagram of the external substrate of Example 2 of the present invention.

[0040] Figure 8 This is a schematic diagram of the back side of the external substrate of Example 2 of the present invention. DETAILED DESCRIPTION

[0041] In the following description, many specific details are explained in conjunction with the embodiments to facilitate a full understanding of the present invention. However, it should be understood that the following embodiments and detailed descriptions are only for illustrative purposes and do not limit the scope of protection of the present invention.

[0042] Existing nine-terminal chips

[0043] Figure 1-Figure 2 An existing nine-terminal chip 10 (part of the circuit and structure are hidden) that is detachably mounted on an ink cartridge is shown. The structure and principle of the nine-terminal chip 10 are basically the same as the structure and principle of the circuit board disclosed in Chinese patent CN101712239B, and the same parts will not be repeated.

[0044] like Figure 1 As shown, the nine-terminal chip 10 can be removed from the chip mounting seat of the ink cartridge, and the nine-terminal chip 10 includes a substrate 101, terminals arranged on the substrate 101, and a memory 102, wherein the substrate 101 includes a front side and a back side arranged opposite to the front side, a plurality of terminals are arranged on the front side of the substrate 101, and a memory 102 is arranged on the back side of the substrate 101. The plurality of terminals arranged on the front side of the substrate 101 are arranged in two rows, the first row is arranged with four terminals, which can be defined as a first terminal 11, a second terminal 12, a third terminal 13 and a fourth terminal 14 from left to right; the second row is arranged with five terminals, which can be defined as a fifth terminal 15, a sixth terminal 16, a seventh terminal 17, an eighth terminal 18 and a ninth terminal 19 from left to right; wherein the first terminal 11, the second terminal 12, the third terminal 13, the fourth terminal 14, the sixth terminal 16, the seventh terminal 17, and the eighth terminal 18 are defined as low-voltage terminals, and the fifth terminal 15 and the ninth terminal 19 are defined as high-voltage terminals, that is, the voltage received by the high-voltage terminal from the imaging device is higher than the voltage received by the low-voltage terminal from the imaging device. Preferably, a plurality of terminals are electrically connected to the memory 102. More preferably, the second terminal 12, the third terminal 13, the sixth terminal 16, the seventh terminal 17 and the eighth terminal 18 are electrically connected to the memory 102 respectively; the first terminal 11, the fourth terminal 14, the fifth terminal 15 and the ninth terminal 19 are not electrically connected to the memory 102.

[0045] exist Figure 2 In the figure, the second terminal 12, the third terminal 13, the fifth terminal 15, the sixth terminal 16, the seventh terminal 17, the eighth terminal 18 and the ninth terminal 19 respectively have circuits extending to the back side of the substrate 101. For ease of understanding, the circuit on the back side of the substrate 101 can be understood as a part of the terminal electrically connected thereto.

[0046] Preferably, Figure 1 The first terminal 11 and the fourth terminal 14 are electrically connected through the first conductor 101 on the substrate 101 ; more preferably, the first conductor 101 is located on the front side of the substrate 10 .

[0047] Preferably, Figure 2 The fifth terminal 15 is connected to the second circuit portion 102, the second circuit portion 102 has a conductive function, and at least a portion of the second circuit portion 102 is arranged on a surface of the substrate 101 other than the front surface. For example, at least a portion of the second circuit portion 102 is located on the back surface of the substrate 101 or at least a portion of the second circuit portion 102 is located on the side wall adjacent to the back surface of the substrate 101; more preferably, at least a portion of the second circuit portion 102 is located on the back surface of the substrate 101, wherein neither the fifth terminal 15 nor the second circuit portion 102 forms an electrical connection with the memory 102.

[0048] Preferably, Figure 2 The ninth terminal 19 is connected to the third circuit portion 103, the third circuit portion 103 has a conductive function, and at least a portion of the third circuit portion 103 is arranged on a surface of the substrate 101 other than the front surface. For example, at least a portion of the third circuit portion 103 is located on the back surface of the substrate 101 or at least a portion of the third circuit portion 103 is located on the side wall adjacent to the back surface of the substrate 101; more preferably, at least a portion of the third circuit portion 103 is located on the back surface of the substrate 101; wherein, neither the ninth terminal 19 nor the third circuit portion 103 forms an electrical connection with the memory 102.

[0049] Specifically, in the first row, the first terminal 11, the second terminal 12, the third terminal 13 and the fourth terminal 14 are respectively the first detection terminal, the reset terminal, the clock terminal and the second detection terminal. In the second row, the fifth terminal 15, the sixth terminal 16, the seventh terminal 17, the eighth terminal 18 and the ninth terminal 19 correspond to the first high-voltage terminal, the power terminal, the ground terminal, the data terminal and the second high-voltage terminal respectively; more specifically, the first detection terminal and the second detection terminal are electrically connected by the first circuit part 101 arranged on the front of the substrate 101; the first high-voltage terminal 101 and the second circuit part 102 are not electrically connected to the memory; the second high-voltage terminal and the third circuit part 103 are not electrically connected to the memory. Among them, the first high-voltage terminal can be connected to the resistor element / sensor element through the second circuit part 102, and the second high-voltage terminal can be connected to the resistor element / sensor element through the third circuit part 103.

[0050] Example 1

[0051] The regeneration chip provided by the present invention is applicable to a new imaging device, the structure and working principle of which are basically the same as those of the imaging device disclosed in US11535038B1. That is, the regeneration chip provided by the present invention can be used with the coupling mechanism 400 described in the specification of US11535038B1 (refer to the patent Figure 7B-7C) is electrically connected and works. It can be understood that the regeneration chip provided by the present invention has basically the same function as the circuit board 120 recorded in patent No. US11535038B1.

[0052] The coupling mechanism 400 described in the above document (US11535038B1) includes a terminal holding part and a plurality of contact part forming components 403 (referred to as contact pins) held by the terminal holding part 405. The contact pins 403 are conductive and elastic. In the present embodiment, each coupling mechanism 400 has five contact pins 403. When the regeneration chip is installed in the new imaging device, the five contact pins 403 are electrically connected to the corresponding terminals on the regeneration chip respectively. The five contact pins 403 include a data contact pin for electrically connecting to a data terminal, a clock contact pin for electrically connecting to a clock terminal, a reset contact pin for electrically connecting to a reset terminal, a power contact pin for electrically connecting to a power terminal, and a ground contact pin for electrically contacting a ground terminal.

[0053] The circuit board 120 described in the above document (US11535038B1) includes a substrate 120bd, a plurality of terminals 290, a device 130 (storage device / controller) and wiring (not shown), and the circuit board 120 may also include other components; the substrate 120bd has a front surface 120fa and a rear surface 120fb. The plurality of terminals 290 include a data terminal 210, a clock terminal 220, a power terminal 230, a reset terminal 240 and a ground terminal 250. Each of the terminals 210, 220, 230, 240 and 250 is connected to the device 130; each of the terminals 210, 220, 230, 240 and 250 is connected to the device 130, and each of the terminals 210 to 250 is electrically coupled to the device 130 through a wiring pattern layer and a through hole (not shown), and the wiring pattern layer is provided on the front surface 120fa and the rear surface 120fb of the base part 120bd.

[0054] Figure 3 and Figure 4 The schematic diagram of the regeneration chip of the present invention is shown (part of the circuit and structure are hidden), as shown in FIG. Figure 3 and Figure 4As shown, an embodiment of the present invention provides a regeneration chip 20, which includes a substrate 101, terminals arranged on the substrate 101, and a part of the circuit, wherein the substrate 101 includes a front side and a back side arranged opposite to the front side, a plurality of terminals are arranged on the front side of the substrate 101, and a memory 102 (equivalent to the device 130 in patent No. US11535038B1) is arranged on the back side of the substrate 101. The terminals arranged on the front side of the substrate 101 are arranged in two rows, wherein the first row is, from left to right, the first regeneration terminal 21, the second regeneration terminal 22, the third regeneration terminal 23, and the fourth regeneration terminal 24, and the second row is, from left to right, the fifth regeneration terminal 25, the sixth regeneration terminal 26, the seventh regeneration terminal 27, the eighth regeneration terminal 28, and the ninth regeneration terminal 29. Figure 4 In the figure, the second regeneration terminal 22, the third regeneration terminal 23, the fifth regeneration terminal 25, the eighth regeneration terminal 28 and the ninth regeneration terminal 29 respectively have circuits extending to the back side of the substrate 101. For ease of understanding, the circuit on the back side of the substrate 101 can be understood as a part of the terminal electrically connected thereto.

[0055] The memory includes multiple pins. In this embodiment, the multiple pins include a data pin, a reset pin, a clock pin, a power pin and a ground pin. The first regeneration terminal 21 is electrically connected to the data pin, the fifth regeneration terminal 25 is electrically connected to the clock pin, and the ninth regeneration terminal 29 is electrically connected to the ground pin.

[0056] Specifically, the first regeneration terminal 21 is electrically connected to the data pin by being electrically connected to the eighth regeneration terminal 28 , the fifth regeneration terminal is electrically connected to the clock pin through the third conductor, and the ninth regeneration terminal is electrically connected to the ground pin through the fourth conductor.

[0057] In some embodiments, the first regeneration terminal 21 is electrically connected to the eighth regeneration terminal 28 via the first conductor 31. Preferably, the first regeneration terminal 21 is electrically connected to the eighth regeneration terminal 28 via the fourth regeneration terminal 28. More preferably, the first regeneration terminal 21 is electrically connected to the fourth regeneration terminal 24 via the second conductor 32, and the fourth regeneration terminal 24 is electrically connected to the eighth regeneration terminal 28 via the first conductor 31. Specifically, the first conductor 31 and the second conductor 32 are at least partially located on the front surface of the substrate 101.

[0058] In some embodiments, the fifth regeneration terminal 25 is electrically connected to the clock pin through the third conductor 33. In another embodiment, the fifth regeneration terminal 25 is electrically connected to the third regeneration terminal 23 through the third conductor 33, and the third regeneration terminal 23 is electrically connected to the clock pin through the fifth conductor electrically connected thereto. More specifically, the fifth regeneration terminal 25 is electrically connected to the circuit portion of the third regeneration terminal 23 located on the back side of the substrate 20 through the third conductor 33.

[0059] In some embodiments, the ninth regeneration terminal 29 is electrically connected to the ground pin through the fourth conductor 34. In other embodiments, the ninth regeneration terminal 29 is electrically connected to the seventh regeneration terminal 27 through the fourth conductor 34, and the seventh regeneration terminal 27 is electrically connected to the ground pin through the fifth conductor electrically connected thereto. More specifically, the ninth regeneration terminal 29 is electrically connected to the circuit portion of the seventh regeneration terminal 27 located on the back side of the substrate 20 through the fourth conductor 34.

[0060] The specific way of electrically connecting the first regeneration terminal 21 to the data pin, the specific way of electrically connecting the fifth regeneration terminal 25 to the clock pin, and the specific way of electrically connecting the ninth regeneration terminal 29 to the ground pin can be freely combined based on the above specific ways and are not limited here.

[0061] Regarding the specific arrangement of the first conductor 31, in some specific embodiments, the first conductor 31 is entirely arranged on the front surface of the substrate 101. In other specific embodiments, one end of the first conductor 31 is arranged on the front surface of the substrate 101 and is electrically connected to the first regeneration terminal 21, and the other end of the first conductor 31 extends to the back surface of the substrate 101 and is electrically connected to the eighth regeneration terminal 28; wherein, the extension may be that the first conductor 31 extends from the front surface of the substrate 101 through the side surface adjacent to the front surface of the substrate 101 to the back surface of the substrate 101, and the extension may also be that a through hole is arranged on the front surface of the substrate 101, and the first conductor 31 extends from the front surface of the substrate 101 through the through hole to the back surface of the substrate 101 and is electrically connected to the eighth regeneration terminal 28. wherein, the first conductor may specifically be a wire portion formed by a soldering process, or may be a metal wire arranged on the substrate.

[0062] It is understandable that the configuration of the second conductor 32 , the third conductor 33 and the fourth conductor 34 may refer to the configuration of the first conductor 31 .

[0063] Preferably, the first regeneration terminal 21 is configured as a data terminal, which is configured to contact a corresponding data contact pin among a plurality of imaging device contact pins (the imaging device is equivalent to the aforementioned "new imaging device"); the second regeneration terminal 22 is configured as a reset terminal, which is configured to contact a corresponding reset contact pin among a plurality of imaging device contact pins; the fifth regeneration terminal 25 is configured as a clock terminal, which is configured to contact a corresponding clock contact pin among a plurality of imaging device contact pins; the sixth regeneration terminal 26 is configured as a power terminal, which is configured to contact a corresponding power contact pin among a plurality of imaging device contact pins; the ninth regeneration terminal 29 is configured as a ground terminal, which is configured to contact a corresponding ground contact pin among a plurality of imaging device contact pins.

[0064] The regeneration chip having the above structure, the first regeneration terminal 21, the second regeneration terminal 22, the fifth regeneration terminal 25, the sixth regeneration terminal 26 and the ninth regeneration terminal 29 are configured to be electrically connected to a new imaging device (such as the device disclosed in US11535038B1), wherein the first regeneration terminal 21 is configured as a data terminal, the second regeneration terminal 22 is configured as a reset terminal, the fifth regeneration terminal 25 is configured as a clock terminal, the sixth regeneration terminal 26 is configured as a power terminal, and the ninth regeneration terminal 29 is configured as a ground terminal. It can be seen that the nine-terminal chip can be recycled and can be applied to a new imaging device having the above-mentioned coupling mechanism 400.

[0065] In some implementations, a new memory may be replaced according to actual needs, and the new memory has at least a data pin, a reset pin, a clock pin, a power pin, and a ground pin.

[0066] Next, combine Figure 1-Figure 3 A method of manufacturing the regeneration chip 20 is described.

[0067] The first method for manufacturing the regeneration chip 20 comprises the following steps:

[0068] A. Remove the nine-terminal chip 10 from the ink cartridge; preferably, clean the surface dirt of the nine-terminal chip 10, such as ink, impurities and other foreign matter;

[0069] B. removing the insulating layer on the back side of the substrate 101 of the nine-terminal chip 10 (e.g., milling it off);

[0070] C. The first terminal 11 is electrically connected to the eighth terminal 18, and preferably, the fourth terminal 12 is electrically connected to the eighth terminal 18. Since the first terminal 11 and the fourth terminal 14 are electrically connected via the first circuit portion 101, the first terminal 11 and the eighth terminal 18 can be electrically connected via the first circuit portion 101 and the fourth terminal 14. It is understandable that the first circuit portion 101 can also be directly electrically connected to the eighth terminal 18. Preferably, the electrical connection is performed by soldering.

[0071] D. The fifth terminal 15 is electrically connected to the clock pin of the memory 102. Preferably, the fifth terminal 15 is electrically connected to and extends to the second circuit portion 102 on the back of the substrate 101 and is electrically connected to the clock pin. More preferably, when an insulating isolation layer 35 (such as Figure 3The dotted line portion in the figure), and the conductor electrically connecting the second circuit portion 102 and the clock pin is arranged on the isolation layer 35, and the isolation layer 35 is used to isolate the conductor electrically connected between the fifth terminal 15 and the clock pin (the third conductor) from other conductors (conductors electrically connected to other terminals); optionally, the fifth terminal 15 can also be electrically connected to the clock pin of the memory 102 through the third terminal 13; preferably, the electrical connection is performed by soldering or external metal wire;

[0072] E. The ninth terminal 19 is electrically connected to the ground pin of the memory 102. Preferably, the ninth terminal 19 is electrically connected to the ground pin through the third circuit portion 103 electrically connected to the ninth terminal 19 and extending to the back of the substrate 101. More preferably, when an insulating isolation layer 35 (such as Figure 3 The dotted line portion in the figure), and the conductor electrically connected to the third circuit portion 103 and the ground pin is arranged on the isolation layer 35, and the isolation layer is used to isolate the conductor electrically connected between the fifth terminal 15 and the ground pin (the fourth conductor) from other conductors (conductors electrically connected to other terminals); Optionally, the ninth terminal 19 is electrically connected to the ground pin of the memory 102 through the seventh terminal 17, and the electrical connection is performed by soldering; More preferably, an insulating isolation layer 35 is arranged on the back of the substrate, and the isolation layer is used to isolate the conductor electrically connected between the ninth terminal 15 and the ground pin from other conductors, and a conductor is arranged on the isolation layer 35 to be electrically connected to the ground pin of the memory;

[0073] F. Rewrite the program in the memory 102 according to actual needs;

[0074] G. Solder an insulating layer on the back side of the substrate 101.

[0075] The second method for manufacturing the regeneration chip 20 comprises the following steps:

[0076] A. Remove the nine-terminal chip 10 from the ink cartridge; preferably, clean the surface dirt of the nine-terminal chip 10, such as ink, impurities and other foreign matter; B. Remove the insulating layer on the back of the substrate 101 of the nine-terminal chip 10 (such as milling off);

[0077] C. The first terminal 11 is electrically connected to the eighth terminal 18, and preferably, the fourth terminal 12 is electrically connected to the eighth terminal 18. Since the first terminal 11 and the fourth terminal are electrically connected via the first circuit portion 101, the first terminal 11 and the eighth terminal 18 can be electrically connected via the first circuit portion 101 and the fourth terminal 14. It is understandable that the first circuit portion 101 can also be directly electrically connected to the eighth terminal 18. Preferably, the electrical connection is performed by soldering.

[0078] D. The fifth terminal 15 is electrically connected to the clock pin of the memory 102. Preferably, the fifth terminal 15 is electrically connected to and extends to the second circuit portion 102 on the back of the substrate 101 and is electrically connected to the clock pin. More preferably, when an insulating isolation layer 35 (such as Figure 3 The dotted line portion in the figure), and the conductor electrically connecting the second circuit portion 102 and the clock pin is arranged on the isolation layer 35, and the isolation layer 35 is used to isolate the conductor electrically connected between the fifth terminal 15 and the clock pin (the third conductor) from other conductors (conductors electrically connected to other terminals); optionally, the fifth terminal 15 can also be electrically connected to the clock pin of the memory 102 through the third terminal 13; preferably, the electrical connection is performed by soldering or external metal wire;

[0079] E. The ninth terminal 19 is electrically connected to the ground pin of the memory 102. Preferably, the ninth terminal 19 is electrically connected to the ground pin through the third circuit portion 103 electrically connected to the ninth terminal 19 and extending to the back of the substrate 101. More preferably, when an insulating isolation layer 35 (such as Figure 3 The dotted line portion in the figure), and the conductor electrically connected to the third circuit portion 103 and the ground pin is arranged on the isolation layer 35, and the isolation layer is used to isolate the conductor electrically connected between the fifth terminal 15 and the ground pin (the fourth conductor) from other conductors (conductors electrically connected to other terminals); Optionally, the ninth terminal 19 is electrically connected to the ground pin of the memory 102 through the seventh terminal 17, and the electrical connection is performed by soldering; More preferably, an insulating isolation layer 35 is arranged on the back of the substrate, and the isolation layer is used to isolate the conductor electrically connected between the ninth terminal 19 and the clock pin from other conductors, and a conductor is arranged on the isolation layer to be electrically connected to the ground pin of the memory;

[0080] F. Replace the memory 102 according to actual needs;

[0081] G. Solder an insulating layer on the back side of the substrate 101.

[0082] This shows that the nine-terminal chip can be recycled and used in new imaging devices.

[0083] It should be noted that, unless there are any contradictions or exclusions, the different embodiments disclosed above may be quoted, referenced or combined with each other, and the technical features / components of different embodiments may also be combined and / or replaced with each other.

[0084] Example 2

[0085] like Figure 5-Figure 8The difference between this embodiment and embodiment 1 is that this embodiment further includes an external substrate 40 and a plurality of contact portions arranged on the external substrate, the external substrate 40 is attached to the regeneration chip 20, and a plurality of pins of the memory are electrically connected to the plurality of contact portions to form components 403 (referred to as contact pins) through electrical connection with the plurality of contact portions. That is to say, this embodiment does not need to change the circuit connection relationship on the back side of the regeneration chip 20; wherein, the first conductor 31, the third conductor 33 and the fourth conductor 34 are all arranged on the external substrate 40.

[0086] Figure 5 This is a schematic structural diagram of the combination state of the regeneration chip and the external substrate in Example 2 of the present invention; Figure 6 This is an exploded schematic diagram of the regeneration chip and the external substrate of Example 2 of the present invention; Figure 7 It is a front view schematic diagram of an external substrate of Embodiment 2 of the present invention; Figure 8 This is a schematic diagram of the back side of the external substrate of Example 2 of the present invention.

[0087] Preferably, the external substrate 40 includes a front side 401 away from the regeneration chip 20 , a back side 402 close to the regeneration chip and opposite to the front side 401 , and a side side 403 between the front side 401 and the back side 402 .

[0088] Preferably, the number of the plurality of contact portions is set to five, and the plurality of contact portions include a first contact portion 41, a second contact portion 42, a third contact portion 43, a fourth contact portion 44, and a fifth contact portion 45. The plurality of contact portions are respectively used to electrically connect with the five contact pins 403 of the coupling mechanism 400. Therefore, the arrangement of the plurality of contact portions is preferably arranged corresponding to the positions of the five contact pins 403 of the coupling mechanism 400. More preferably, the plurality of contact portions are all arranged on the front side 401; in some embodiments, at least a portion of at least one of the plurality of contact portions may be arranged on the back side 402 and / or the side 403.

[0089] Preferably, the first conductor 31, the third conductor 33 and the fourth conductor 34 are all disposed on the back surface 402 of the external substrate 40, but may also be disposed on the side surface 403 of the external substrate.

[0090] Preferably, the eighth regeneration terminal 28 is electrically connected to the first contact portion 41 through the first conductor 31; more preferably, the first conductor 31 includes a first conductive portion 311, a first conductive end portion 312 located at one end of the first conductive portion 311, and a second conductive end portion 313 located at the other end of the first conductive portion 311, the first conductive end portion 312 is arranged at a position on the back side 402 corresponding to the eighth regeneration terminal 28, and the second conductive end portion 312 is electrically connected to the first contact portion; optionally, the second conductive end portion 313 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the first contact portion 41.

[0091] Preferably, the third regeneration terminal 23 is electrically connected to the third contact portion 43 through the third conductor 33; more preferably, the third conductor 33 includes a third conductive portion 331, a third conductive end portion 332 located at one end of the third conductive portion 331, and a fourth conductive end portion 333 located at the other end of the third conductive portion 331, the third conductive end portion 332 is arranged at a position corresponding to the third regeneration terminal 23 on the back side 402, and the fourth conductive end portion 333 is electrically connected to the third contact portion 43; optionally, the fourth conductive end portion 333 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the third contact portion 43.

[0092] Preferably, the seventh regeneration terminal 27 is electrically connected to the fifth contact portion 45 through the fourth conductor 34; more preferably, the fourth conductor 34 includes a fourth conductive portion 341, a fifth conductive end portion 342 located at one end of the fourth conductive portion 341, and a sixth conductor end portion 343 located at the other end of the fourth conductive portion 341, the fifth conductive end portion 342 is arranged at a position corresponding to the seventh regeneration terminal 27 on the back side 402, and the sixth conductive end portion 343 is electrically connected to the fifth contact portion 45. Optionally, the sixth conductive end portion 343 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the fifth contact portion 45.

[0093] In this embodiment, an insulating layer is formed on the first conductive portion 311 , the third conductive portion 331 and the fourth conductive portion 341 , thereby avoiding the terminal ends on the regeneration chip.

[0094] Preferably, a sixth conductor 36 is provided on the back side 402 of the external substrate 40, and the second contact portion 42 is electrically connected to the second regeneration terminal 22 through the sixth conductor 36. The position of the sixth conductor 36 corresponds to the position of the second regeneration terminal 22. Optionally, the sixth conductor 36 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the second contact portion 42.

[0095] Preferably, a seventh conductor 37 is provided on the back side 402 of the external substrate 40, and the fourth contact portion 44 is electrically connected to the sixth regeneration terminal 26 through the seventh conductor 37. The position of the seventh conductor 37 corresponds to the position of the sixth regeneration terminal 26. Optionally, the seventh conductor 37 extends along the thickness direction of the external substrate 40 and passes through the external substrate 40 to be electrically connected to the fourth contact portion 44.

[0096] Preferably, the external substrate 40 can be connected to the regeneration chip 20 by bonding, welding or engaging other components.

[0097] [Beneficial Effects]

[0098] This embodiment pre-arranges the multiple contact parts and wirings (i.e., the first conductor, the third conductor, the fourth conductor, the sixth conductor and the seventh conductor) on the external substrate 40, eliminating the need to scrape the insulating layer on the back of the regenerated chip for the regeneration process, thereby simplifying the chip regeneration steps and costs.

[0099] Although the present invention has been described above through embodiments, it should be understood that the above embodiments are only used to exemplarily describe the feasible implementation schemes of the present invention and should not be interpreted as limiting the scope of protection of the present invention. That is, any substitution or change made by those skilled in the art in accordance with the present invention should also be covered by the scope of protection of the claims of the present invention.

Claims

1. A regeneration chip for an ink cartridge, comprising: A substrate, a memory and a plurality of regeneration terminals, wherein the substrate includes a front side and a back side, the memory is arranged on the back side of the substrate, and the plurality of regeneration terminals are arranged on the front side of the substrate; characterized in that: The plurality of regeneration terminals are arranged in a plurality of rows, the plurality of regeneration terminals comprising a first regeneration terminal, a second regeneration terminal, a third regeneration terminal, a fourth regeneration terminal, a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal; The first regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal, or the eighth regeneration terminal.

2. The ink cartridge regeneration chip according to claim 1, wherein: The regeneration terminals are arranged into a first row and a second row, the first row includes a first regeneration terminal, a second regeneration terminal, a third regeneration terminal and a fourth regeneration terminal arranged from left to right; the second row includes a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal and a ninth regeneration terminal arranged from left to right.

3. The ink cartridge regeneration chip according to claim 1, wherein: At least one of the fifth regeneration terminal and the ninth regeneration terminal is electrically connected to the memory.

4. The ink cartridge regeneration chip according to claim 1, wherein: The fifth regeneration terminal is electrically connected to the memory through a third conductor, and the third conductor is at least partially located on the back side of the substrate; the ninth regeneration terminal is electrically connected to the memory through a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate.

5. The ink cartridge regeneration chip according to claim 1, wherein: At least one of the third regeneration terminal, the seventh regeneration terminal and the eighth regeneration terminal is electrically connected to the memory through a fifth conductor, and the fifth conductor is at least partially located on the back side of the substrate.

6. The ink cartridge regeneration chip according to claim 5, wherein: The fifth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a third conductor, and the third conductor is at least partially located on the back side of the substrate; The fifth regeneration terminal is electrically connected to any one of the fifth conductors through a third conductor, and the third conductor is at least partially located on the back side of the substrate.

7. The ink cartridge regeneration chip according to claim 6, wherein: The ninth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate; The ninth regeneration terminal is electrically connected to any one of the fifth conductors through a fourth conductor, and the fourth conductor is at least partially located on the back side of the substrate; The first regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through a first conductor, and the first conductor is at least partially located on the front surface of the substrate; The first regeneration terminal is electrically connected to the fourth regeneration terminal through the second conductor, the fourth regeneration terminal is electrically connected to any one of the third regeneration terminal, the seventh regeneration terminal or the eighth regeneration terminal through the first conductor, the first conductor is at least partially located on the front surface of the substrate, and the second conductor is at least partially located on the front surface of the substrate; The first regeneration terminal is electrically connected to any one of the fifth conductors through the first conductor; The first regeneration terminal is electrically connected to the fourth regeneration terminal through the second conductor, the fourth regeneration terminal is electrically connected to any fifth conductor through the first conductor, the first conductor is at least partially located on the front surface of the substrate, and the second conductor is at least partially located on the front surface of the substrate; The first regeneration terminal is a data terminal configured to contact a corresponding data contact pin of the plurality of imaging device contact pins; The second regeneration terminal is a reset terminal configured to contact a corresponding reset contact pin among the plurality of imaging device contact pins; The fifth regeneration terminal is a clock terminal configured to contact a corresponding clock contact pin of the plurality of imaging device contact pins; The sixth regeneration terminal is a power supply terminal configured to contact a corresponding power supply contact pin of the plurality of imaging device contact pins; The ninth regeneration terminal is a ground terminal configured to contact a corresponding ground contact pin of the plurality of imaging device contact pins; The memory includes a data pin, a reset pin, a clock pin, a power pin and a ground pin. The fifth regeneration terminal is electrically connected to the clock pin through a third conductor, and the ninth regeneration terminal is electrically connected to the ground pin through a fourth conductor.

8. A method for manufacturing a regeneration chip for an ink cartridge, the method comprising the following steps: A. Remove the nine-terminal chip from the ink cartridge; B. electrically connecting the first terminal to the eighth terminal; C. electrically connecting the fifth terminal to a clock pin of the memory; D. Electrically connect the ninth terminal to the ground pin of the memory.

9. The manufacturing method according to claim 8, characterized in that: The manufacturing method further comprises: before electrically connecting the fifth terminal and the clock pin of the memory, providing an insulating isolation layer on the back side of the substrate, the isolation layer being used to isolate the conductor electrically connected between the fifth terminal and the clock pin from other conductors; The manufacturing method further comprises: before electrically connecting the ninth terminal to the ground pin of the memory, providing an insulating isolation layer on the back side of the substrate, the isolation layer being used to isolate the conductor electrically connected between the ninth terminal and the ground pin from other conductors; The manufacturing method further includes rewriting the program inside the memory; The manufacturing method further comprises replacing the memory; The manufacturing method also includes welding an insulating layer on the back side of the substrate.

10. A regeneration chip for an ink cartridge, comprising: A substrate, a memory and a plurality of regeneration terminals, wherein the substrate includes a front side and a back side, the memory is arranged on the back side of the substrate, and the plurality of regeneration terminals are arranged on the front side of the substrate; characterized in that: The regeneration chip further comprises an external substrate and a plurality of contact parts arranged on the external substrate, the external substrate is attached to the substrate, and the memory is electrically connected to a plurality of contact pins on the imaging device by being electrically connected to the plurality of contact parts; The plurality of regeneration terminals are arranged in a plurality of rows, and the plurality of regeneration terminals include a first regeneration terminal, a second regeneration terminal, a third regeneration terminal, a fourth regeneration terminal, a fifth regeneration terminal, a sixth regeneration terminal, a seventh regeneration terminal, an eighth regeneration terminal, and a ninth regeneration terminal.

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