Pressure sensor and preparation method thereof

Abstract

The invention provides a pressure sensor and a preparation method thereof, the pressure sensor comprises a first wafer, a top semiconductor layer, a lead structure, a lead hole and a conductive column, the upper surface layer of the first wafer is provided with an absolute pressure cavity and an isolation groove; the top semiconductor layer is stacked on the upper surface of the first wafer, the lower surface layer of the top semiconductor layer is provided with a sensor functional area, the edge area of the sensor functional area is provided with four varistors which are uniformly and symmetrically distributed, each varistor comprises at least one resistance area, and the edge and the peripheral area of the sensor functional area are provided with a plurality of connecting areas connected with the two ends of each varistor; the plurality of lead structures are located on the lower surface of the top semiconductor layer and located in the isolation groove, and one end of each lead structure is electrically connected with the connection area; the lead hole is opened from the bottom surface of the first wafer and the lead structure is exposed from the bottom surface; the conductive pillar fills the lead hole. The sensor structure is improved, and the functional area of the sensor covers the opening of the absolute pressure cavity, so that the device is prevented from being influenced by the external environment, and the sensitivity of the device is ensured.

Description

Technical Field

[0001] The invention belongs to the technical field of sensors and relates to a pressure sensor and a preparation method thereof. Background Art

[0002] At present, piezoresistive pressure sensors are mostly made by silicon-glass bonding. Due to the different thermal expansion coefficients of silicon and glass, the thermal stress caused in high-temperature environments is mismatched, which affects the temperature performance of the sensor. In addition, in harsh environments, they usually face measurement problems such as high temperature and high humidity. Since the piezoresistors and metal leads in the piezoresistive pressure sensor structure are usually exposed outside the sensor, or an additional insulating layer is set on the outside of the sensor to protect the piezoresistors, even if an insulating layer is set to protect the piezoresistors, the sensor will fail if it works in a harsh environment for a long time. When preparing the pressure sensor, it is usually done by opening an opening on the back of the substrate and then etching the pressure sensitive film with a wet etching process. The depth of this corrosion is generally above 350μm. Due to the lateral corrosion characteristics of the corrosive liquid, the size of the absolute pressure cavity will deviate greatly from the design value, which will seriously affect the performance of the sensor, or even cause the sensor to be unresponsive. In addition, since the sensitive film is relatively thin, when a passivation layer is introduced to protect the sensitive film, the sensitivity of the sensor will be reduced.

[0003] Therefore, there is an urgent need to find a pressure sensor that can match the thermal stress of the sensor material while improving the sensitivity and performance of the sensor. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a pressure sensor and a preparation method thereof, which are used to solve the problem in the prior art that it is difficult to improve the sensitivity and performance of the sensor while improving the material thermal stress matching of the piezoresistive pressure sensor.

[0005] To achieve the above object and other related objects, the present invention provides a method for preparing a pressure sensor, comprising the following steps:

[0006] Providing a first wafer having a first dielectric layer formed on the bottom surface, and forming at least one absolute pressure cavity and a plurality of isolation grooves surrounding the periphery of the absolute pressure cavity on the upper surface of the first wafer;

[0007] Providing a second wafer having a second dielectric layer disposed on its upper surface, and forming a top semiconductor layer with a preset thickness on the upper surface of the second dielectric layer;

[0008] At least one sensor function area corresponding to the absolute pressure cavity is defined on the upper surface of the top semiconductor layer, and four uniformly and symmetrically distributed piezoresistors are formed at the edge of the sensor function area, wherein the piezoresistors include at least one resistance area;

[0009] A plurality of connection areas respectively connected to the piezoresistors are formed on the upper surface of the top semiconductor layer at the edge and the peripheral area of ​​the sensor functional area, and a plurality of lead structures corresponding to the isolation grooves are formed on the upper surface of the top semiconductor layer at the periphery of the sensor functional area, and one end of the lead structure close to the connection area is electrically connected to the connection area;

[0010] The second wafer is placed flip-chip on the upper surface of the first wafer and bonded, the sensor functional area covers the opening of the absolute pressure cavity, and the lead structure is located in the isolation groove;

[0011] The second wafer, the second dielectric layer and the first dielectric layer are removed, and a lead hole with a bottom surface exposing the lead structure is formed on a side of the first wafer away from the isolation groove, thereby forming a conductive column filling the lead hole.

[0012] Optionally, the method of forming the top semiconductor layer comprises smart lift-off.

[0013] Optionally, the varistor includes a plurality of the resistance areas, and a plurality of interconnection areas are formed in the varistor, and two ends of the interconnection area are respectively connected to two adjacent resistance areas, so that the plurality of resistance areas in the varistor form a series structure.

[0014] Optionally, the doping type of the interconnection region is the same as the doping type of the resistance region, and the doping concentration of the interconnection region is higher than the doping concentration of the resistance region.

[0015] Optionally, the connection region has a doping concentration greater than that of the resistance region, and / or the connection region and the resistance region have the same doping type.

[0016] Optionally, removing the second wafer, the second dielectric layer and the first dielectric layer comprises the following steps:

[0017] Thinning the second wafer from a side of the second wafer away from the second dielectric layer, and removing the second wafer remaining after thinning by an etching process to expose the second dielectric layer;

[0018] The second dielectric layer and the first dielectric layer are removed simultaneously.

[0019] Optionally, after forming the conductive pillar, the method further includes a step of electrically connecting the conductive pillar to a PCB board.

[0020] The present invention also provides a pressure sensor, comprising:

[0021] A first wafer, the upper surface of which is provided with at least one absolute pressure cavity and a plurality of isolation grooves surrounding the periphery of the absolute pressure cavity;

[0022] A top semiconductor layer is stacked on the upper surface of the first wafer, the lower surface of the top semiconductor layer is provided with at least one open sensor functional area covering the absolute pressure cavity, the edge area of ​​the sensor functional area is provided with four uniformly and symmetrically distributed varistors, the varistors include at least one resistance area, and the lower surface of the top semiconductor layer at the edge and peripheral area of ​​the sensor functional area is provided with a plurality of connection areas respectively connected to the two ends of the varistors;

[0023] A plurality of lead structures are located on the lower surface of the top semiconductor layer outside the sensor functional area, and the lead structures are located in the isolation grooves, and one end of the lead structure close to the connection area is electrically connected to the connection area;

[0024] A lead hole, opening from the bottom surface of the first wafer and exposing the lead structure on the bottom surface;

[0025] A conductive column fills the lead hole.

[0026] Optionally, the two varistors arranged opposite to each other are symmetrically distributed.

[0027] Optionally, the lead structure includes a conductive lead and a pad, the isolation groove includes a lead groove and a pad groove connected to the lead groove, one end of the conductive lead close to the connection area is electrically connected to the connection area, and one end of the conductive lead away from the connection area is electrically connected to the pad, the conductive lead protrudes from the upper surface of the top semiconductor layer and is located in the lead groove, the pad protrudes from the upper surface of the top semiconductor layer and is located in the pad groove, and the lead hole exposes the pad.

[0028] As described above, the pressure sensor and the preparation method thereof of the present invention improve the process of manufacturing the pressure sensor, form the absolute pressure cavity and the isolation groove on the upper surface of the first wafer, form the top semiconductor layer of a preset thickness on the upper surface of the second dielectric layer above the second wafer, define the sensor functional area corresponding to the absolute pressure cavity on the upper surface of the top semiconductor layer, form four uniformly and symmetrically distributed varistors in the edge area of ​​the sensor functional area, form the lead structure corresponding to the isolation groove on the periphery of the sensor functional area, and the isolation groove is used to accommodate the lead structure to avoid the lead structure affecting the bonding of the top semiconductor layer and the first wafer, so that the bonding surface of the top semiconductor layer and the first wafer is in a flat state; use smart peeling technology (Smart The top semiconductor layer as the sensitive film layer of the sensor is formed by cutting the top semiconductor layer as the sensitive film layer of the sensor, so that the thickness of the sensitive film layer of the sensor is controllable and the consistency is good, thereby improving the consistency and stability of the sensor; the top semiconductor layer is bonded to the first wafer through a flip-chip bonding process, and after bonding, the varistor is located inside the device and faces the absolute pressure cavity, and the lead structure is located in the isolation groove, so that the varistor is protected by the top semiconductor layer, thereby preventing the sensor from being affected by the external environment, eliminating the need for an additional passivation layer process for protecting the varistor, simplifying the process steps, saving manufacturing costs, improving the output of the sensor, and ensuring the sensitivity of the sensor. In addition, since the top semiconductor layer and the first wafer are made of the same material, the thermal stress of the top semiconductor layer and the first wafer are matched, thereby improving the reliability of the sensor at high temperatures, improving the performance of the sensor, and having a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a process flow chart of a method for preparing a pressure sensor of the present invention.

[0030] Figure 2 It is a schematic diagram showing the cross-sectional structure after forming the first dielectric layer in the method for preparing the pressure sensor of the present invention.

[0031] Figure 3 It is a schematic diagram of the cross-sectional structure after forming the absolute pressure cavity and the isolation groove in the method for preparing the pressure sensor of the present invention.

[0032] Figure 4 It is a schematic diagram of the top surface structure after forming the absolute pressure cavity and the isolation groove in the method for preparing the pressure sensor of the present invention.

[0033] Figure 5 It is a schematic diagram of the three-dimensional structure after forming the absolute pressure cavity and the isolation groove in the method for preparing the pressure sensor of the present invention.

[0034] Figure 6 It is a schematic diagram showing the cross-sectional structure after forming the top semiconductor layer in the method for preparing the pressure sensor of the present invention.

[0035] Figure 7 It is a schematic diagram showing the cross-sectional structure after forming the connection area in the method for preparing the pressure sensor of the present invention.

[0036] Figure 8 It is a schematic diagram showing the cross-sectional structure after forming the lead structure in the method for preparing the pressure sensor of the present invention.

[0037] Fig. 9 It is a schematic diagram of the top surface structure after forming the lead structure in the method for preparing the pressure sensor of the present invention.

[0038] Fig.10 It is a schematic diagram of the cross-sectional structure after the top semiconductor layer and the first wafer are bonded in the method for preparing the pressure sensor of the present invention.

[0039] Fig.11 It is a schematic diagram showing the cross-sectional structure after thinning the second wafer in the method for preparing the pressure sensor of the present invention.

[0040] Fig.12 It is a schematic diagram of the cross-sectional structure of the method for manufacturing the pressure sensor of the present invention after removing the second wafer.

[0041] Fig.13 It is a schematic diagram of the cross-sectional structure after removing the first dielectric layer and the second dielectric layer in the method for preparing the pressure sensor of the present invention.

[0042] Fig.14 It is a schematic diagram showing the cross-sectional structure after forming the lead holes in the method for preparing the pressure sensor of the present invention.

[0043] Fig.15 It is a schematic diagram of the three-dimensional structure after forming the lead holes in the method for preparing the pressure sensor of the present invention.

[0044] Fig.16 It is a schematic diagram of the cross-sectional structure after the conductive bump is formed in the manufacturing method of the pressure sensor of the present invention.

[0045] Fig.17 It is a schematic diagram of the cross-sectional structure after the pressure sensor is electrically connected to the PCB board in the method for preparing the pressure sensor of the present invention.

[0046] Description of Figure Numbers

[0047] 1. First Wafer

[0048] 11. First dielectric layer

[0049] 12 Absolute pressure chamber

[0050] 13 Isolation slot

[0051] 131 Lead duct

[0052] 132 pad slot

[0053] 14 Lead hole

[0054] 2. Second Wafer

[0055] 21 Second dielectric layer

[0056] 22 Top semiconductor layer

[0057] 23 Sensor function area

[0058] 24 Varistor

[0059] 25 Resistance Zone

[0060] 26 Interconnection Zone

[0061] 27 Connection Zone

[0062] 3 Lead structure

[0063] 31 Conductive lead

[0064] 32 pads

[0065] 4 Conductive pillars

[0066] 41 Conductive bump

[0067] 5 PCB board DETAILED DESCRIPTION

[0068] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] See also Figures 1 to 17 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0070] Embodiment 1

[0071] This embodiment provides a method for preparing a pressure sensor, such as Figure 1 FIG. 1 is a process flow chart of a method for preparing the pressure sensor, comprising the following steps:

[0072] S1: providing a first wafer having a first dielectric layer formed on the bottom surface, and forming at least one absolute pressure cavity and a plurality of isolation groove structures surrounding the periphery of the absolute pressure cavity on the upper surface of the first wafer;

[0073] S2: providing a second wafer having a second dielectric layer formed on its upper surface, and forming a top semiconductor layer with a preset thickness on the upper surface of the second dielectric layer;

[0074] S3: defining at least one sensor function area corresponding to the absolute pressure cavity on the upper surface layer of the top semiconductor layer, and forming four uniformly and symmetrically distributed piezoresistors at the edge of the sensor function area, wherein the piezoresistors include at least one resistance area;

[0075] S4: forming a plurality of connection areas, one end of which is respectively connected to the varistor, on the upper surface of the top semiconductor layer at the edge and the peripheral area of ​​the sensor functional area, and forming a plurality of lead structures corresponding to the isolation grooves on the upper surface of the top semiconductor layer at the periphery of the sensor functional area, wherein one end of the lead structure close to the connection area is electrically connected to the connection area;

[0076] S5: placing the second wafer flip-chip on the upper surface of the first wafer and bonding them, the sensor functional area covers the opening of the absolute pressure cavity, and the lead structure is located in the isolation groove;

[0077] S6: removing the second wafer, the second dielectric layer and the first dielectric layer, and forming a lead hole with a bottom surface exposing the lead structure on a side of the first wafer away from the isolation groove, thereby forming a conductive column filling the lead hole.

[0078] See also Figures 2 to 6 , perform step S1, step S2 and step S3: provide a first wafer 1 with a first dielectric layer 11 formed on the bottom surface, and form at least one absolute pressure cavity 12 and a plurality of isolation grooves 13 surrounding the periphery of the absolute pressure cavity 12 on the upper surface of the first wafer 1; provide a second wafer 2 with a second dielectric layer 21 formed on the upper surface, and form a top semiconductor layer 22 of a preset thickness on the upper surface of the second dielectric layer 21; define at least one sensor function area 23 corresponding to the absolute pressure cavity 12 on the upper surface of the top semiconductor layer 22, and form four uniformly and symmetrically distributed varistors 24 in the edge area of ​​the sensor function area 23, and the varistors 24 include at least one resistance area 25.

[0079] Specifically, the material of the first wafer 1 includes silicon, silicon germanium, silicon carbide or other suitable semiconductor materials. In this embodiment, a silicon wafer is used as the first wafer 1.

[0080] Specifically, Figure 2 , which is a schematic diagram of a cross-sectional structure after forming the first dielectric layer 11, wherein the method for forming the first dielectric layer 11 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods. In this embodiment, the first dielectric layer 11 is formed on the lower surface of the first wafer 1 by thermal oxidation.

[0081] Specifically, the material of the first dielectric layer 11 includes silicon oxide, silicon nitride or other suitable materials. In this embodiment, silicon oxide is used as the first dielectric layer 11.

[0082] Specifically, the thickness of the first dielectric layer 11 is in the range of 200 nm to 300 nm. For example, the thickness of the first dielectric layer 11 may be 200 nm, 220 nm, 240 nm, 260 nm, 280 nm or 300 nm.

[0083] Specifically, the first dielectric layer 11 is used to protect the first wafer 1 to prevent the first wafer 1 from being damaged by subsequent processes.

[0084] Specifically, Figure 3 , Figure 4 and Figure 5 As shown, they are respectively a schematic diagram of the cross-sectional structure after the absolute pressure cavity 12 and the isolation groove 13 are formed, a schematic diagram of the top surface structure after the absolute pressure cavity 12 and the isolation groove 13 are formed, and a schematic diagram of the three-dimensional structure after the absolute pressure cavity 12 and the isolation groove 13 are formed. The formation of the absolute pressure cavity 12 includes the following steps: forming a patterned first shielding layer (not shown) on the upper surface of the first wafer 1; etching the first wafer based on the patterned first shielding layer to obtain the absolute pressure cavity 12 of a preset depth.

[0085] Specifically, the material of the first shielding layer includes photoresist or other suitable photoresist materials. In this embodiment, photoresist is used as the first shielding layer.

[0086] Specifically, the method of forming the first shielding layer and the patterned first shielding layer is a commonly used photoresist coating, exposure, and development method, which will not be described in detail here.

[0087] Specifically, the method of forming the absolute pressure cavity 12 includes dry etching, wet etching or other suitable methods.

[0088] As an example, the depth of the absolute pressure cavity 12 ranges from 10 μm to 20 μm, for example, the depth of the insulating groove 12 may be 10 μm, 15 μm or 20 μm. The depth here refers to the distance from the bottom surface of the absolute pressure cavity 12 to the opening of the absolute pressure cavity 12 .

[0089] Specifically, the absolute pressure cavity 12 is used to prevent the pressure in the functional area of ​​the sensor from being overloaded, which causes the functional area of ​​the device to contact the bottom surface of the absolute pressure cavity 12 .

[0090] Specifically, under the condition of ensuring the performance of the sensor, the opening size of the absolute pressure chamber 12 can be selected according to actual conditions and is not limited here.

[0091] Specifically, after forming the absolute pressure cavity 12 and before forming the isolation groove 13, a step of removing the first shielding layer is also included.

[0092] Specifically, the method for removing the first shielding layer is a commonly used photoresist stripping method, which will not be described in detail here.

[0093] Specifically, forming the isolation groove 13 includes the following steps: forming a patterned second shielding layer (not shown) on the upper surface of the first wafer 1; etching the first wafer based on the patterned second shielding layer to obtain the isolation groove 13 with a preset depth and located outside the absolute pressure cavity 12.

[0094] Specifically, the material of the second shielding layer includes photoresist or other suitable photoresist materials. In this embodiment, photoresist is used as the second shielding layer.

[0095] Specifically, the method for forming the second shielding layer and the patterned second shielding layer is a commonly used photoresist coating, exposure, and development method, which will not be described in detail here.

[0096] Specifically, the method of forming the isolation trench 13 includes dry etching, wet etching or other suitable methods.

[0097] As an example, the depth of the isolation trench 13 ranges from 2 μm to 3 μm. The depth here refers to the distance between the bottom surface of the isolation trench 13 and the opening of the isolation trench 13 .

[0098] Specifically, the isolation groove 13 is used to accommodate the lead structure in the subsequent process (see the subsequent Fig.10 ) to avoid the lead structure affecting the subsequent bonding process, facilitating the subsequent bonding process.

[0099] Specifically, after forming the isolation trench 13 , the method further includes a step of removing the second shielding layer.

[0100] Specifically, the method for removing the second shielding layer is a commonly used photoresist stripping method, which will not be described in detail here.

[0101] Specifically, the material of the second wafer 2 includes silicon, silicon germanium, silicon carbide or other suitable semiconductor materials. In this embodiment, a silicon wafer is used as the second wafer 2.

[0102] Specifically, while ensuring device performance, the thickness, size and shape of the second wafer 2 can be selected according to actual conditions and are not limited here; the thickness of the second dielectric layer 21 can be selected according to actual conditions and is not limited here.

[0103] Specifically, the material of the second dielectric layer 21 includes silicon oxide, silicon nitride or other suitable materials.

[0104] Specifically, Figure 6 , which is a schematic diagram of the cross-sectional structure after the top semiconductor layer 22 is formed, and the method for forming the top semiconductor layer 22 includes smart stripping or other suitable methods. In this embodiment, a top semiconductor material layer is deposited on the upper surface of the second dielectric layer 21 by a deposition process, and then the top semiconductor material layer is thinned by smart stripping technology to obtain the top semiconductor layer 22 of a preset thickness.

[0105] Specifically, the material of the top semiconductor layer 22 includes silicon, silicon germanium, silicon carbide or other suitable semiconductor materials. In this embodiment, a silicon layer is used as the top semiconductor layer 22 .

[0106] Specifically, the sensor functional area 23 is used to form a piezoresistor in the pressure sensor, and the sensor functional area 23 has the same opening shape and size as the absolute pressure cavity 12 .

[0107] As an example, a method of forming the resistance region 25 includes ion implantation or other suitable methods.

[0108] Specifically, under the condition of ensuring the performance of the sensor, the size of the resistance area 25 can be selected according to actual conditions and is not limited here.

[0109] As an example, the doping type of the resistor region 25 includes a P type, and the doping concentration of the resistor region 25 is in the range of 4×10 16 cm -3 ~3.5×10 18 cm -3 .

[0110] As an example, the varistor 24 includes a plurality of the resistance areas 25, and a plurality of interconnection areas 26 are formed in the varistor 24, and the two ends of the interconnection area 26 are respectively connected to two adjacent resistance areas 25, so that the plurality of resistance areas 25 in the varistor 24 form a series structure.

[0111] Specifically, the interconnection area 26 is used to connect two adjacent resistance areas 25 in series, and the resistance areas 25 in the varistor 24 are connected through the interconnection area 26 to form the varistor 24 with a series structure.

[0112] Specifically, under the condition that the sensor performance is guaranteed and the multiple resistance areas 25 in each varistor 24 form a series structure, the arrangement of the multiple resistance areas 25 in the same varistor 24 and the sizes of the different resistance areas 25 can be selected according to actual conditions, and are not limited here. For example, the multiple resistance areas 25 in the same varistor 24 can be arranged in parallel along the same direction, and two adjacent interconnection areas 26 are respectively connected to the two ends of the same resistance area 25.

[0113] As an example, the doping type of the interconnection region 26 is the same as the doping type of the resistance region 25 , and the doping concentration of the interconnection region 26 is higher than the doping concentration of the resistance region 25 .

[0114] Specifically, under the condition that the performance of the varistor 24 is guaranteed and the doping concentration of the interconnection area 26 is higher than the doping concentration of the resistance area 25 , the doping concentration and size of the interconnection area 26 can be selected according to actual conditions and are not limited here.

[0115] Specifically, the four varistors 24 are evenly distributed in the edge area of ​​the sensor functional area 23, and the distance between any two adjacent varistors 24 is the same, and the resistance values ​​of the four varistors 24 are all the same or are the same in pairs.

[0116] As an example, the two varistors 24 are symmetrically distributed, that is, the resistance areas 25 in the two relatively arranged varistors 24 are symmetrically distributed.

[0117] Specifically, when the resistance values ​​of the four varistors 24 are the same in pairs, two of the varistors 24 with the same resistance value are arranged opposite to each other, and because the resistance areas 25 in the two varistors 24 arranged opposite to each other are symmetrically distributed, after the sensor functional area 23 is deformed, the deformation degrees of the two varistors 24 with the same resistance value are the same, and then the resistance value changes of the two varistors 24 with the same resistance value after deformation are the same.

[0118] Specifically, when the resistance values ​​of the four varistors 24 are the same, since the resistance areas 25 in the two relatively arranged varistors 24 are symmetrically distributed, after the sensor functional area 23 is deformed, the deformation degrees of the resistance areas 25 in the relatively arranged varistors 24 are the same, and then the resistance value changes of the varistors 24 are the same, which facilitates the calculation of pressure.

[0119] See also Figures 7 to 17 , perform the steps S4, S5 and S6: form a plurality of connection areas 27, one end of which is respectively connected to the varistor 24, on the upper surface of the top semiconductor layer 22 at the edge and peripheral area of ​​the sensor functional area 23, and form a plurality of lead structures 3 corresponding to the isolation groove 13 on the upper surface of the top semiconductor layer 22 outside the sensor functional area 23, and the end of the lead structure 3 close to the connection area 27 is electrically connected to the connection area 27; place the second wafer 2 upside down on the upper surface of the first wafer 1 and bond it, the sensor functional area 23 covers the opening of the absolute pressure cavity 12, and the lead structure 3 is located in the isolation groove 13; remove the second wafer 2, the second dielectric layer 21 and the first dielectric layer 11, and form a lead hole 14 with a bottom surface exposing the lead structure 3 on the side of the first wafer 1 away from the isolation groove 13, and form a conductive column 4 filling the lead hole 14.

[0120] Specifically, Figure 7 , which is a schematic diagram of the cross-sectional structure after the connection region 27 is formed. The method for forming the connection region 27 includes ion implantation or other suitable methods.

[0121] As an example, the doping concentration of the connection region 27 is greater than that of the resistance region 25 , and / or the connection region 27 and the resistance region 25 have the same doping type.

[0122] Specifically, the connection area 27 is located in the edge area of ​​the sensor functional area 23 and the peripheral area of ​​the sensor functional area 23, and one end of the connection area 27 is electrically connected to one end of the varistor 24, that is, the part of the connection area 27 located in the edge area of ​​the sensor functional area 23 is electrically connected to the varistor 24, so as to facilitate the varistor 24 to be led out of the periphery of the sensor functional area 23.

[0123] Specifically, at least eight connection areas 27 are formed in the edge area of ​​the sensor functional area 23 , that is, both ends of each varistor 24 are connected to different connection areas 27 , so as to lead out each varistor 24 .

[0124] As an example, Figure 8 and Fig. 9 As shown, they are respectively a schematic diagram of a cross-sectional structure after the lead structure 3 is formed and a schematic diagram of a top surface structure after the lead structure 3 is formed, wherein the lead structure 3 includes a conductive lead 31 and a pad 32, the isolation groove 13 includes a lead groove 131 and a pad groove 132 connected to the lead groove 131, the end of the conductive lead 31 close to the connection area 27 is electrically connected to the connection area 27, the end of the conductive lead 31 away from the connection area 27 is electrically connected to the pad 32, the conductive lead 31 protrudes from the upper surface of the top semiconductor layer 22 and is located in the lead groove 131, the pad 32 protrudes from the upper surface of the top semiconductor layer 22 and is located in the pad groove 132, the lead hole (see the subsequent Fig.14 ) reveals the pad 32.

[0125] Specifically, the material of the conductive lead 31 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the pad 32 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0126] Specifically, the method for forming the conductive lead 31 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the pad 32 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0127] Specifically, the electrical contact type between the conductive lead 31 and the connection area 27 is ohmic junction contact; the endpoint of the electrical connection between the connection area 27 and the conductive lead 31 is located in the peripheral area of ​​the sensor functional area 23, each connection area 27 corresponds to one conductive lead 31, and one pad 32 is electrically connected to at least one conductive lead 31 to facilitate the lead-out of the varistor 24.

[0128] Specifically, under the condition that the sensor performance is guaranteed and the pad 32 can be placed in the pad groove 132 , the size and shape of the pad 32 can be selected according to actual conditions and are not limited here.

[0129] Specifically, after the second wafer 2 is flip-chip placed on the upper surface of the first wafer 1, an alignment step is also included so that the surface of the sensor functional area 23 faces downward to cover the opening of the absolute pressure cavity 12, and the lead structure 3 is placed in the isolation groove 13. The flip-chip placement here means that the surface of the second wafer 2 on which the lead structure 3 is formed is placed face downward on the surface of the first wafer 1 on which the absolute pressure cavity 12 is formed.

[0130] Specifically, Fig.10 As shown, it is a schematic diagram of the cross-sectional structure after the top semiconductor layer 22 is bonded to the first wafer 1. The method of placing the second wafer 2 upside down on the upper surface of the first wafer 1 and bonding them is a commonly used wafer bonding method, which will not be repeated here.

[0131] As an example, removing the second wafer 2, the second dielectric layer 21 and the first dielectric layer 11 includes the following steps: thinning the second wafer 2 from the side of the second wafer 2 away from the second dielectric layer 21, and using an etching process to remove the remaining second wafer 2 after thinning to expose the second dielectric layer 21; and simultaneously removing the second dielectric layer 21 and the first dielectric layer 11.

[0132] Specifically, Fig.11 , which is a schematic diagram of the cross-sectional structure of the second wafer 2 after thinning, and the method of thinning the second wafer 2 from the side of the second wafer 2 away from the second dielectric layer 21 includes mechanical grinding or other suitable methods. In this embodiment, the second wafer 2 is thinned by mechanical grinding.

[0133] Specifically, the remaining thickness of the second wafer 2 after thinning is in the range of 30 μm to 50 μm.

[0134] Specifically, Fig.12 As shown, it is a schematic diagram of the cross-sectional structure after removing the second wafer 2, and the etching process for removing the remaining second wafer 2 includes wet etching or other suitable processes.

[0135] Specifically, after the second wafer 2 is quickly thinned by mechanical grinding, the remaining second wafer 2 is removed by wet etching, thereby avoiding damage to the top semiconductor layer 22 and shortening the time for removing the second wafer 2, thereby reducing costs. In this embodiment, the second wafer 2 is first thinned by mechanical grinding, and then the second wafer 2 is completely removed by wet etching.

[0136] Specifically, under the condition of ensuring the device performance, only the dry etching method is used to remove the second wafer 2 .

[0137] Specifically, Fig.13As shown, it is a schematic diagram of the cross-sectional structure after removing the first dielectric layer 11 and the second dielectric layer 21. The method of synchronously removing the second dielectric layer 21 and the first dielectric layer 11 includes wet etching or other suitable methods. In this embodiment, a buffered oxide etchant (BOE) is used to synchronously remove the first dielectric layer 11 and the second dielectric layer 21. By utilizing the high selectivity of wet etching, the first dielectric layer 11 and the second dielectric layer 21 can be removed while avoiding damage to the first wafer 1 and the top semiconductor layer 22.

[0138] Specifically, Fig.14 and Fig.15 As shown, they are respectively a schematic diagram of the cross-sectional structure after the lead hole 14 is formed and a schematic diagram of the three-dimensional structure after the lead hole 14 is formed. The method of forming the lead hole 14 includes laser drilling, dry etching or other suitable methods.

[0139] Specifically, the method of forming the conductive pillar 4 includes electroplating, chemical plating, magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0140] As an example, after forming the conductive pillar 4 , the method further includes a step of electrically connecting the conductive pillar to the PCB board 5 .

[0141] Specifically, Fig.16 , which is a schematic diagram of the cross-sectional structure after the conductive bump 41 is formed, includes a step of forming a conductive bump 41 at one end of the conductive pillar 4 away from the pad 32 before electrically connecting the conductive pillar 4 to the PCB board 5 .

[0142] Specifically, the method of forming the conductive bump 41 includes ball implantation or other suitable methods.

[0143] Specifically, the conductive bump 41 is made of copper, aluminum, nickel, gold, silver, tin, titanium or other suitable conductive materials.

[0144] Specifically, Fig.17 , which is a schematic diagram of the cross-sectional structure after the pressure sensor is electrically connected to the PCB board 5. The PCB board 5 is used to electrically connect the pressure sensor to an external circuit and process the change of the varistor 24 to convert it into pressure data.

[0145] Specifically, the conductive pillar 4 is electrically connected to the PCB board 5 through the conductive bump 41 .

[0146] Specifically, by using the top semiconductor layer 22 formed by the intelligent stripping technology as the sensitive film layer of the pressure sensor, it is convenient to control the thickness of the sensitive film layer of the sensor according to actual needs, that is, the thickness of the top semiconductor layer 22 is easy to control, and the consistency of the obtained top semiconductor layer 22 is good, which can improve the consistency and stability of the pressure sensor.

[0147] Specifically, by optimizing the manufacturing process and structure of the sensor, the absolute pressure cavity 12 and the isolation groove are formed in the first wafer 1, the top semiconductor layer 22 is formed on the upper surface of the second wafer 2, and the varistor 24 and the lead structure 3 are formed on the upper surface and upper surface of the top semiconductor layer 22 respectively, and then the top semiconductor layer 22 is flip-chip bonded to the upper surface of the first wafer 1, the sensor functional area 23 covers the absolute pressure cavity 12, and the isolation groove 13 accommodates the lead structure 3, so that the top semiconductor layer 22 is away from the surface of the varistor 24 and faces outward, and the top semiconductor layer 22 is used to protect the varistor 24 and the lead structure 3 from the influence of harsh environment, and there is no need to deposit an additional passivation layer, which simplifies the process, saves the cost of manufacturing devices, improves the output of the sensor, and ensures the sensitivity of the sensor.

[0148] Specifically, by forming the isolation groove 13 for accommodating the lead structure 3 on the upper surface of the first wafer 1, the bonding surface between the top semiconductor layer 22 and the first wafer 1 is in a flat state, which facilitates the complete bonding of the top semiconductor layer 22 and the first wafer 1.

[0149] Specifically, since the top semiconductor layer 22 is made of the same material as the first wafer 1, the problem of thermal stress mismatch between the top semiconductor layer 22 and the first wafer 1 in a high temperature environment, which affects the performance of the sensor, can be avoided, thereby improving the reliability of the sensor at high temperatures and improving the performance of the sensor.

[0150] The manufacturing method of the pressure sensor of the present embodiment improves the process of manufacturing the pressure sensor, forms the isolation groove 13 and the absolute pressure cavity 12 on the upper surface of the first wafer 1, forms the top semiconductor layer 22 of a preset thickness on the upper surface of the second dielectric layer 21 above the second wafer 2, defines the sensor function area 23 corresponding to the absolute pressure cavity 12 on the upper surface of the top semiconductor layer 22, forms the varistor 24 in the edge area of ​​the sensor function area 23, forms the lead structure 3 corresponding to the isolation groove 13 on the periphery of the sensor function area 23, and the isolation groove 13 is used to accommodate the lead structure 3, so as to facilitate The bonding surface between the top semiconductor layer 22 and the first wafer 1 is in a flat state; the top semiconductor layer 22 is formed by intelligent stripping technology, and the top semiconductor layer 22 is used as the sensitive film layer of the sensor, which is convenient for thickness control, and the formed top semiconductor layer 22 has good consistency, which improves the consistency and stability of the sensor; through flip-chip bonding, the varistor 24 is directly opposite to the absolute pressure cavity 13, and the isolation groove 13 accommodates the lead structure 3, which avoids the sensor from being affected by the external environment. At the same time, there is no need to form a passivation layer, which simplifies the process steps, saves production costs, improves the output of the sensor, and ensures the sensitivity of the sensor. In addition, since the material of the top semiconductor layer 22 is the same as that of the first wafer 1, the thermal stress of the top semiconductor layer 22 matches that of the first wafer 1, which improves the reliability of the sensor at high temperature, thereby improving the performance of the device.

[0151] Embodiment 2

[0152] This embodiment provides a pressure sensor, such as Fig.16As shown, it is a schematic diagram of the cross-sectional structure of the pressure sensor, including: a first wafer 1, a top semiconductor layer 22, a lead structure 3, a lead hole 14 and a conductive column 4, wherein the upper surface layer of the first wafer 1 is provided with at least one absolute pressure cavity 12 and a plurality of isolation grooves 13 surrounding the periphery of the absolute pressure cavity 12; the top semiconductor layer 22 is stacked on the upper surface of the first wafer 1, and the lower surface layer of the top semiconductor layer 22 is provided with at least one opening sensor function area 23 covering the absolute pressure cavity 12, and the edge area of ​​the sensor function area 23 is provided with four uniformly and symmetrically distributed varistors 24, and the varistors 24 include The sensor functional area 23 includes at least one resistance area 25, and the lower surface layer of the top semiconductor layer 22 at the edge and peripheral area of ​​the sensor functional area 23 is provided with a plurality of connection areas 27 respectively connected to the varistor 24; a plurality of lead structures 3 are located on the lower surface of the top semiconductor layer 22 outside the sensor functional area 23, and the lead structure 3 is located in the isolation groove 13, and one end of the lead structure 3 close to the connection area 27 forms an electrical connection with the connection area 27; the lead hole 14 opens from the bottom surface of the first wafer 1 and the lead structure 3 is exposed on the bottom surface; the conductive column 4 fills the lead hole 14.

[0153] Specifically, under the condition of ensuring the performance of the sensor, the thickness, size and shape of the first wafer 1 can be selected according to actual conditions and are not limited here.

[0154] Specifically, the absolute pressure cavity 12 is used to prevent the pressure of the sensor functional area 23 from being overloaded, causing the sensor functional area 23 to contact the bottom surface of the absolute pressure cavity 12 and affect the pressure measurement; the isolation groove 13 is used to accommodate the lead structure 3 to prevent the lead structure 3 from affecting the bonding between the top semiconductor layer 22 and the first wafer 1.

[0155] Specifically, the top semiconductor layer 22 serves as a sensitive film layer of the pressure sensor, and its thickness is related to the sensitivity of the pressure sensor. That is, under the condition of ensuring that there is enough area to form the varistor 24, the thinner the thickness of the top semiconductor layer 22, relatively speaking, the higher the sensitivity of the sensor. The thickness of the top semiconductor layer 22 can be adjusted according to the actual application scenario and the actual demand for sensitivity.

[0156] Specifically, under the condition of ensuring the performance of the sensor, the shape of the top semiconductor layer 22 can be selected according to actual conditions and is not limited here.

[0157] Specifically, the four varistors 24 are evenly distributed around the edge area of ​​the sensor functional area 22 , that is, the distance between any two adjacent varistors 24 is the same.

[0158] As an example, the two varistors 24 that are arranged opposite to each other are symmetrically distributed, that is, the resistance areas 25 in the two varistors 24 that are arranged opposite to each other are symmetrically distributed.

[0159] Specifically, in order to ensure the performance of the sensor, the resistance values ​​of the relatively arranged varistors 24 are the same, and the region sizes and doping concentrations of the resistance regions 25 are the same.

[0160] Specifically, when the varistor 24 includes a plurality of the resistance areas 25, the varistor 24 also includes an interconnection area 26 connecting two adjacent resistance areas 25, and the resistance areas 25 in the varistor 24 form a series resistance structure through the interconnection area 26, and the interconnection areas 26 in the relatively arranged varistors 24 are also symmetrically distributed, and the symmetrically distributed interconnection areas 26 have the same size, shape and doping concentration.

[0161] Specifically, the doping concentration of the interconnection area 26 is greater than the doping concentration of the resistance area 25, so as to avoid excessive change in the resistance value of the interconnection area 26 after the sensor functional area 23 is deformed, thereby affecting the performance of the sensor.

[0162] Specifically, the connection area 27 is located in the edge area and the peripheral area of ​​the sensor functional area 23, and is used to lead out the varistor 24. One end of the connection area 27 located in the edge area of ​​the sensor functional area 23 is only connected to the end point of the varistor 24, that is, one connection area 27 is correspondingly arranged at each end of each varistor 24.

[0163] Specifically, the doping concentration of the connection area 27 is greater than the doping concentration of the resistance area 25 to avoid excessive changes in the resistance value of the portion of the connection area 27 located at the edge of the sensor functional area 23 when the sensor functional area 23 is deformed, thereby affecting the performance of the sensor. At the same time, the portion of the connection area 27 located outside the sensor functional area 23 can form an ohmic contact with the lead structure 3.

[0164] As an example, the lead structure 3 includes a conductive lead 31 and a pad 32, the isolation groove 13 includes a lead groove 131 and a pad groove 132 connected to the lead groove 131, the end of the conductive lead 31 close to the connection area 27 is electrically connected to the connection area 27, the end of the conductive lead 31 away from the connection area 27 is electrically connected to the pad 32, the conductive lead 31 protrudes from the upper surface of the top semiconductor layer 22 and is located in the lead groove 131, the pad 32 protrudes from the upper surface of the top semiconductor layer 22 and is located in the pad groove 132, and the lead hole 14 exposes the pad 32.

[0165] Specifically, each of the connection areas 27 corresponds to one of the conductive leads 31 , and one of the pads 32 is electrically connected to at least one of the conductive leads 31 .

[0166] Specifically, while ensuring the performance of the sensor, the size and shape of the conductive lead 31 can be selected according to actual conditions and are not limited here.

[0167] Specifically, while ensuring the sensor performance and the conductive lead 31 and the pad 32 can be placed in the lead groove 131 and the pad groove 132 respectively, the size and shape of the lead groove 131 can be selected according to actual conditions and are no longer restricted here; the size and shape of the pad groove 132 can be selected according to actual conditions and are no longer restricted here.

[0168] Specifically, under the condition of ensuring the performance of the sensor, the opening size and shape of the lead hole 14 can be selected according to actual conditions and are not limited here.

[0169] Specifically, the conductive pillar 4 filling the lead hole 14 is electrically connected to the pad 32 , and the conductive pillar 4 is made of copper, aluminum, nickel, gold, silver, titanium or other suitable conductive materials.

[0170] Specifically, the pressure sensor is further provided with a PCB board 5 electrically connected to the conductive pillar 4 , and the PCB board 5 is used to electrically connect the pressure sensor to an external circuit.

[0171] Specifically, a conductive bump 41 is further provided between the conductive pillar 4 and the PCB board 5 , and the conductive pillar 4 is electrically connected to the PCB board 5 via the conductive bump 41 .

[0172] Specifically, by improving the structure of the sensor, the sensor functional area 23 is used to cover the opening of the absolute pressure cavity 12, and the varistor 24 is located on the lower surface layer of the sensor functional area 23, so that the varistor 24 is isolated from the external environment, thereby avoiding the influence of the external environment on the varistor 24. The varistor 24 is protected by the top semiconductor layer 22, and there is no need to additionally set up a protective structure (passivation layer) to protect the varistor 24, thereby improving the sensitivity of the device.

[0173] Specifically, by providing the isolation groove 13 for accommodating the lead structure 3, the lead structure 3 is prevented from affecting the bonding between the top semiconductor layer 22 and the first wafer 1, so that a good bonding interface is formed between the top semiconductor layer 22 and the first wafer 1, which facilitates the sensor functional area 23 to tightly seal the opening of the absolute pressure cavity 12, thereby ensuring the performance of the sensor.

[0174] The pressure sensor of the present embodiment improves the structure of the sensor, and provides the isolation groove 13 for accommodating the lead structure 3, so as to prevent the lead structure 3 from affecting the bonding between the top semiconductor layer 22 and the first wafer 1, so that a good bonding interface is formed between the top semiconductor layer 22 and the first wafer 1, so that the sensor functional area 23 can tightly seal the opening of the absolute pressure cavity 12. At the same time, since the varistor 24 is located at the lower surface layer of the sensor functional area 23, the varistor 24 is isolated from the external environment, thereby avoiding the influence of the external environment on the varistor 24, and there is no need to additionally provide a protective structure for protecting the varistor 24, thereby improving the sensitivity of the device.

[0175] In summary, the pressure sensor and the preparation method thereof of the present invention improve the process of manufacturing the pressure sensor, form an absolute pressure cavity and an isolation groove for accommodating a lead structure on the upper surface of a first wafer, form a top semiconductor layer with a preset thickness and a sensor functional area corresponding to the absolute pressure cavity on the upper surface of a second dielectric layer above a second wafer, form four uniformly and symmetrically distributed varistors in the edge area of ​​the sensor functional area, form a lead structure corresponding to the isolation groove on the periphery of the sensor functional area, and the isolation groove can be set to make the bonding surface of the top semiconductor layer and the first wafer in a flat state; use the intelligent peeling technology to form the top semiconductor layer, and place the top semiconductor layer on the top surface of the second dielectric layer. The semiconductor layer is used as the sensitive film layer of the sensor, which is convenient for forming a film layer with controllable thickness and good consistency, thereby improving the consistency and stability of the sensor; through the flip-chip bonding method, the varistor is located inside the device and directly facing the absolute pressure cavity, and the lead structure is located in the isolation groove, thereby preventing the sensor from being affected by the external environment, eliminating the need to set up a passivation layer to protect the varistor, simplifying the process steps, saving costs, improving the output of the sensor, and ensuring the sensitivity of the sensor; because the top semiconductor layer is made of the same material as the first wafer, the thermal stress of the top semiconductor layer matches that of the first wafer, thereby improving the reliability of the sensor at high temperatures and improving the performance of the sensor. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0176] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a pressure sensor, characterized in that: The following steps are involved: Providing a first wafer having a first dielectric layer formed on the bottom surface, and forming at least one absolute pressure cavity and a plurality of isolation grooves surrounding the periphery of the absolute pressure cavity on the upper surface of the first wafer; Providing a second wafer having a second dielectric layer disposed on its upper surface, and forming a top semiconductor layer with a preset thickness on the upper surface of the second dielectric layer; At least one sensor function area corresponding to the absolute pressure cavity is defined on the upper surface of the top semiconductor layer, and four uniformly and symmetrically distributed piezoresistors are formed at the edge of the sensor function area, wherein the piezoresistors include at least one resistance area; A plurality of connection areas respectively connected to the piezoresistors are formed on the upper surface of the top semiconductor layer at the edge and the peripheral area of ​​the sensor functional area, and a plurality of lead structures corresponding to the isolation grooves are formed on the upper surface of the top semiconductor layer at the periphery of the sensor functional area, and one end of the lead structure close to the connection area is electrically connected to the connection area; The second wafer is placed flip-chip on the upper surface of the first wafer and bonded, the sensor functional area covers the opening of the absolute pressure cavity, and the lead structure is located in the isolation groove; The second wafer, the second dielectric layer and the first dielectric layer are removed, and a lead hole with a bottom surface exposing the lead structure is formed on a side of the first wafer away from the isolation groove, thereby forming a conductive column filling the lead hole.

2. The method for preparing a pressure sensor according to claim 1, characterized in that: The method of forming the top semiconductor layer includes smart lift-off.

3. The method for preparing a pressure sensor according to claim 1, characterized in that: The varistor includes a plurality of resistance areas, and a plurality of interconnection areas are formed in the varistor, and two ends of the interconnection area are respectively connected to two adjacent resistance areas, so that the plurality of resistance areas in the varistor form a series structure.

4. The method for preparing a pressure sensor according to claim 3, characterized in that: The doping type of the interconnection region is the same as the doping type of the resistance region, and the doping concentration of the interconnection region is higher than the doping concentration of the resistance region.

5. The method for preparing a pressure sensor according to claim 1, characterized in that: The doping concentration of the connection region is greater than that of the resistance region, and / or the connection region and the resistance region have the same doping type.

6. The method for preparing a pressure sensor according to claim 1, characterized in that: Removing the second wafer, the second dielectric layer and the first dielectric layer comprises the following steps: Thinning the second wafer from a side of the second wafer away from the second dielectric layer, and removing the second wafer remaining after thinning by an etching process to expose the second dielectric layer; The second dielectric layer and the first dielectric layer are removed simultaneously.

7. The method for preparing a pressure sensor according to claim 1, characterized in that: After the conductive pillars are formed, the method further includes a step of electrically connecting the conductive pillars to a PCB board.

8. A pressure sensor, characterized in that: include: A first wafer, the upper surface of which is provided with at least one absolute pressure cavity and a plurality of isolation grooves surrounding the periphery of the absolute pressure cavity; A top semiconductor layer is stacked on the upper surface of the first wafer, the lower surface of the top semiconductor layer is provided with at least one open sensor functional area covering the absolute pressure cavity, the edge area of ​​the sensor functional area is provided with four uniformly and symmetrically distributed varistors, the varistors include at least one resistance area, and the lower surface of the top semiconductor layer at the edge and peripheral area of ​​the sensor functional area is provided with a plurality of connection areas respectively connected to the varistors; A plurality of lead structures are located on the lower surface of the top semiconductor layer outside the sensor functional area, and the lead structures are located in the isolation grooves, and one end of the lead structure close to the connection area is electrically connected to the connection area; A lead hole, opening from the bottom surface of the first wafer and exposing the lead structure on the bottom surface; A conductive column fills the lead hole.

9. The pressure sensor according to claim 8, characterized in that: The two varistors arranged opposite to each other are symmetrically distributed.

10. The pressure sensor according to claim 8, characterized in that: The lead structure includes a conductive lead and a pad, the isolation groove includes a lead groove and a pad groove connected to the lead groove, the end of the conductive lead close to the connection area is electrically connected to the connection area, the end of the conductive lead away from the connection area is electrically connected to the pad, the conductive lead protrudes from the upper surface of the top semiconductor layer and is located in the lead groove, the pad protrudes from the upper surface of the top semiconductor layer and is located in the pad groove, and the lead hole exposes the pad.

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