Chip testing method, device and system
By pre-stored test data and read directly from the storage module, the problem of time-consuming testing data grouping and parsing in the prior art is solved, and more efficient chip testing is achieved.
Patent Information
- Application Number
- CN202411864329.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-02-25
AI Technical Summary
In the prior art, due to the increase in the number of test channels, the packet grouping and parsing of test data takes longer, resulting in low measurement efficiency.
By pre-stored test data, the target device under test is tested, and no need to group packets and parse the test data, it is read directly from the storage module and sent to the multi-channel module for testing.
Reduces test time, improves test efficiency, and avoids the problem of inefficiency in measurement caused by excessive packet grouping and parsing.
Smart Images
Figure CN119511047A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing method, device and system. Background Art
[0002] Chip testing is the use of automatic test equipment (ATE) to detect various parameters of the device under test, eliminate defective products and control the quality of the device under test. Improving the testing efficiency of the testing equipment can reduce the time of the chip testing link, thereby increasing the chip production capacity.
[0003] In the related art, when testing a device under test, it is necessary to first set the test data of the device under test, and then send the test data to the execution end of the test equipment through a communication bus. The execution end determines the device under test that needs to be measured through the channel information in the test data, and writes the test data into the register to perform the test operation of the device under test. After the test is completed, the test data is collected and sent back to complete the entire test process.
[0004] In the above technical solution, because the test data involves a large amount of data, it is necessary to package the test data to achieve data transmission. The execution end also needs to perform data analysis after receiving the packaged test data; and the result data collected after the test is completed also needs to be packaged and transmitted back. As the number of measurement channels increases, the time spent on test data packaging and analysis becomes longer, and the measurement efficiency is lower. Summary of the invention
[0005] The embodiments of the present application provide a chip testing method, device and system, which can test the target device under test by using pre-stored test data without packaging and parsing the test data, thereby reducing test time and improving test efficiency.
[0006] In a first aspect, an embodiment of the present application provides a chip testing method, which is applied to an execution module in a chip testing system, wherein the chip testing system further includes a host computer module, a storage module, a multi-channel module, and a sampling module, including:
[0007] Receiving a test instruction sent by the host computer module, wherein the test instruction includes a data identification number;
[0008] Reading corresponding test data from the storage module based on the test instruction, and sending the test data to the multi-channel module, so that the multi-channel module tests the target device under test based on the test data;
[0009] receiving result data sent by the sampling module, and storing the result data in the storage module based on the data identification number;
[0010] In response to the result data being stored in the storage module, the result data is sent to the host computer module.
[0011] In a second aspect, an embodiment of the present application provides a chip testing device, which is applied to a chip testing system. The chip testing system includes a host computer module, a storage module, a multi-channel module and a sampling module. The device includes:
[0012] A receiving module, used for receiving a test instruction sent by the host computer module, wherein the test instruction includes a data identification number;
[0013] A sending module, configured to read corresponding test data from the storage module based on the test instruction, and send the test data to the multi-channel module, so that the multi-channel module tests the target device under test based on the test data;
[0014] A collection and storage module, used for receiving the result data sent by the sampling module, and storing the result data in the storage module based on the data identification number;
[0015] A sending module is used for sending the result data to the host computer module in response to the result data being stored in the storage module.
[0016] In a third aspect, an embodiment of the present application provides a chip testing system, including a host computer module, a storage module, a multi-channel module and a sampling module, and the chip testing system also includes the above-mentioned chip testing device.
[0017] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the above-mentioned test method when executed by a processor.
[0018] In a fifth aspect, an embodiment of the present application provides a computer program product, including computer program instructions, which implement the above-mentioned testing method when executed by a processor.
[0019] The embodiment of the present application provides a chip testing method, which is applied to an execution module in a chip testing system, wherein the chip testing system also includes a host computer module, a storage module, a multi-channel module and a sampling module, and includes: receiving a test instruction sent by the host computer module, wherein the test instruction includes a data identification number; reading corresponding test data from the storage module based on the test instruction, and sending the test data to the multi-channel module, so that the multi-channel module tests a target device under test based on the test data; receiving result data sent by the sampling module, and storing the result data in the storage module based on the data identification number; sending the result data to the host computer module in response to the result data being stored in the storage module; solving the problem in the prior art that test data packaging and parsing take a long time and measurement efficiency is low due to an increase in the number of test channels; testing the target device under test by pre-storing test data, without the need to package and parse the test data, thereby reducing test time and improving test efficiency.
[0020] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0022] Figure 1 A flowchart of a chip testing method provided for an exemplary embodiment of the present application;
[0023] Figure 2 A structural diagram of a chip testing system provided for an exemplary embodiment of the present application;
[0024] Figure 3 A structural diagram of a chip testing system provided for an exemplary embodiment of the present application;
[0025] Figure 4 A schematic diagram of the structure of a chip testing device provided by an exemplary embodiment of the present application;
[0026] Figure 5 A framework diagram of a chip testing system provided for an exemplary embodiment of the present application;
[0027] Figure 6 An operation flow chart of a chip testing system provided for an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0028] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.
[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0030] It is understandable that before using the technical solutions disclosed in the embodiments of the present disclosure, the types, scope of use, usage scenarios, etc. of the personal information involved in the present disclosure should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.
[0031] In the related art, when testing the device under test, it is necessary to first set the test data of the device under test, and then send the test data to the execution end of the test equipment through the communication bus. The execution end determines the device under test that needs to be measured through the channel information in the test data, and writes the test data into the register to perform the test operation of the device under test. After the test is completed, the test data is collected and returned to complete the entire test process. Because the test data involves a large amount of data, it is necessary to package the test data to realize data transmission. After receiving the packaged test data, the execution end also needs to perform data analysis; and the result data collected after the test is completed also needs to be packaged and returned. As the number of measurement channels increases, the time spent on test data packaging and analysis becomes longer, and the measurement efficiency is lower.
[0032] In order to solve the above problems to a certain extent, a chip testing method is provided in an embodiment of the present disclosure, such as Figure 1As shown in the flowchart, this embodiment is applied to a chip test system, and the chip test system is used to test the functions and / or performance of chips, wafers or integrated circuits. For example, the chip test system can be an integrated circuit automatic tester (Automatic Test Equipment, ATE). The chip test system includes a host computer module, an execution module, a multi-channel module, a sampling module and a storage module. The host computer module can be a software platform in an industrial computer in the test equipment, which is used to control and send various test instructions, and collect and display test results. The industrial computer can include at least one of the following: a computer, a server, a smart phone and a tablet computer. The multi-channel module can be a variety of hardware test boards in the test equipment, which is responsible for testing at least one performance and / or function of the chip under test. The sampling module can be an analog-to-digital converter (A / D converter, or ADC for short), which is used to collect test result data. The storage module is used to store test data, for example, the storage module can be a shared memory, or a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), a flash memory, etc. The specific placement form of the test data is not limited in this embodiment.
[0033] like Figure 1 As shown, the method specifically comprises the following steps:
[0034] S110, receiving a test instruction sent by the host computer module, the test instruction including a data identification number.
[0035] Among them, the host computer module is used to control the execution module to test the device under test, and the execution module is used to execute the test instructions for testing the device under test. The execution module can be a field programmable gate array (Field Programmable Gate Array, FPGA). The test instruction refers to a command for testing various parameter indicators of the device under test. Specifically, the test instruction can be a voltage test instruction of the device under test, a current test instruction of the device under test, and can also include instructions for testing other parameters of the device under test, which is not limited in this application; the data identification number can be a channel code number, including a slot number, a board number, a channel number, and a shared pin number, etc., which is a unique identification number, included in the test instruction, for quickly identifying the channel position of the device under test.
[0036] S120, reading corresponding test data from the storage module based on the test instruction, and sending the test data to the multi-channel module, so that the multi-channel module tests the target device under test based on the test data.
[0037] Among them, the test data refers to the parameter index data of the device under test. Specifically, the test data can be package data, and the package data includes: acquisition instructions and configuration parameters, and the configuration parameters include: channel information, output voltage data, output current data, ADC sampling times, measurement mode, etc. Channel information includes slot serial number, hardware serial number in the board, pin serial number, etc. Among them, the board can refer to a hardware device (circuit board) that can expand the function of a computer or server, such as a FE (Front End) board, then the hardware serial number in the board is the FE board number, and the pin serial number can be a shared pin number. The target device under test is a DUT (Device Under Test), a wafer or other integrated circuit. A multi-channel module can refer to a module for measuring multiple DUTs; specifically, since DUTs will inevitably have defective products during the production process, in order to eliminate defective products and control the factory quality of semiconductors, multiple DUTs can be measured through a multi-channel module to improve the measurement efficiency of the target device under test. The multi-channel module at least includes: a bus / BE board (Back End), a FE board (Front End) and a PE chip. Exemplarily, the multi-channel module can be composed of a BE board and a FE board, or a BE board and a PE chip, or a BE board, a FE board and a PE chip. This embodiment does not limit the combination form.
[0038] Specifically, the BE board can receive signals for conversion and processing, transmit and decode sent and received data, monitor and adjust the working status of communication equipment, and identify and process error information, which can ensure the stability and reliability of the communication process. Multiple FE boards can be inserted into the BE board for chip measurement, and multiple PE chips for measuring DUT functions can be connected to the FE board. The PE chip has a multi-channel feature, which is mainly reflected in its internal structure. The channel allows multiple data streams or tasks to be processed in parallel; each programmable logic unit in the FE board contains a certain number of input and output channels, which can be used to receive and send data. Furthermore, by numbering the FE board channels and PE chip channels, the hardware measurement channel position can be accurately located through the data identification number.
[0039] In this embodiment, when the execution module receives a test instruction for testing the DUT sent by the upper computer module, the test data of the DUT is directly read from the storage module according to the data identification number in the test instruction, thereby effectively improving the rate of obtaining the test data; and the configuration parameters in the test data are sent to the multi-channel module, and the current and voltage are provided to the DUT based on the current and voltage in the configuration parameters, so as to test the DUT and determine the test result of the DUT; the DUT is tested in parallel through the multi-channel module, so as to make full use of the multi-channel resources and improve the test efficiency.
[0040] S130, receiving result data sent by the sampling module, and storing the result data in the storage module based on the data identification number.
[0041] The result data is the measurement result obtained by the sampling module sampling the multi-channel module. Specifically, the test data also includes an acquisition instruction. Since the sampling module is connected to the multi-channel module, the sampling module can sample the multi-channel module upon receiving the acquisition instruction in the test data, thereby obtaining the result data of the DUT.
[0042] In this embodiment, the multi-channel module can be sampled by the sampling module to obtain the result data of the DUT. After the execution module receives the result data sent by the sampling module, the result data can be stored in the storage module according to the data identification number.
[0043] S140, in response to the result data being stored in the storage module, sending the result data to the host computer module.
[0044] In the present embodiment, a test instruction sent by a host computer module is received, the test instruction includes a data identification number; based on the test instruction, corresponding test data is read from the storage module, and the test data is sent to the multi-channel module, so that the multi-channel module tests the target device under test based on the test data; result data sent by the sampling module is received, and the result data is stored in the storage module based on the data identification number; in response to the result data being stored in the storage module, the result data is sent to the host computer module; the problem in the prior art that test data packaging and parsing take a long time and measurement efficiency is low due to an increase in the number of test channels is solved; the target device under test is tested by pre-stored test data, and there is no need to package and parse the test data, thereby reducing test time and improving test efficiency.
[0045] In some optional implementations, the test data includes at least one configuration parameter, and before reading the corresponding test data from the storage module based on the test instruction, the method further includes:
[0046] Bind the data identification number to the standard address IP in the storage module;
[0047] The standard address IP may refer to a memory address in the data storage structure table. For example, the standard address IP is the memory address 0x1100. The data storage structure is shown in Table 1.
[0048] Table 1
[0049]
[0050] In this embodiment, the data identification number (ie, the ID in Table 1, such as 10001) can be bound to the standard address IP in the storage module (ie, the memory address in Table 1, such as 0x1100).
[0051] Based on the standard address IP, at least one first offset address IP is obtained; wherein the first offset address IP may refer to a storage location for storing configuration parameters. Specifically, based on the standard address IP, the corresponding offset is determined according to the type of configuration parameters, and based on the offset, an offset is performed on the basis of the standard address IP to obtain multiple first offset address IPs. For example, as shown in Table 1, the offset of the ID is +0x0, the offset of the pin name is +0x10, the offset of the DUT number is +0x20, the offset of the voltage is +0x30, the offset of the current range is +0x40, the offset of the clamp current is +0x50, and the offset of the measurement mode is +0x70. Since ID 10001 is bound to memory address 0x1100, the offset address of the pin name is 0x1110, the offset address of the DUT number is 0x1120, the offset address of the voltage is 0x1130, the offset address of the current range is 0x1140, the offset address of the clamp current is 0x1150, and the offset address of the measurement mode is 0x1170. Based on the standard address IP, an offset is preset, and multiple first offset address IPs are obtained by offsetting based on the preset offset on the basis of the standard address IP.
[0052] Pre-store the configuration parameters in the first offset address IP. Specifically, after obtaining at least one first offset address IP, pre-store the configuration parameters in the first offset address IP. It can be that one configuration parameter is pre-stored in one first offset address IP, or multiple configuration parameters are pre-stored in one first offset address IP, or one configuration parameter is pre-stored in at least two first offset address IPs. In a specific embodiment, the storage method of the configuration parameter can be determined according to the data length of the configuration parameter. For example, if the data length of the configuration parameter is greater than the first length threshold, the configuration parameter can be pre-stored in at least two first offset address IPs; if the data length of the configuration parameter is equal to the first length threshold, the configuration parameter can be pre-stored in one first offset address IP, or multiple configuration parameters with data lengths less than the first length threshold are pre-stored in one first offset address IP.
[0053] In some optional implementations, receiving result data sent by the sampling module and storing the result data in the storage module based on the data identification number includes:
[0054] Based on the data identification number, the standard address IP is obtained; specifically, as shown in Table 1, the corresponding standard address IP (ie, memory address) 0x1100 can be obtained according to the data identification number (ie, ID) 10001.
[0055] Based on the standard address IP, at least one second offset address IP is obtained, and the second offset address IP is different from the first offset address IP; wherein the second offset address IP may refer to a storage location for storing result data, and the result data may specifically be a measurement result in Table 1, for example, measurement results 0.0011, 0.0013, etc.
[0056] The result data is stored in the second offset address IP. Specifically, after obtaining at least one second offset address IP, the result data is pre-stored in the second offset address IP, which may be pre-stored in one second offset address IP, or pre-stored in multiple result data in one second offset address IP, or pre-stored in at least two second offset address IPs.
[0057] Exemplarily, a result data is pre-stored in a second offset address IP, and different result data correspond to different second offset addresses IP. The second offset address IP corresponding to the result data can be determined according to the data type of the result data and the standard address IP.
[0058] In this embodiment, the corresponding standard address IP can be obtained according to the data identification number; based on the standard address IP and the data type of the result data, at least one second offset address IP is obtained, and the result data can be stored in a second offset address IP that is different from the first offset address IP according to the data length of the result data.
[0059] In a specific example, as shown in Table 1, the offset corresponding to the measurement result is +0x80. The data identification number ID is 10001. By querying Table 1, the standard address IP is 0x1100. The standard address IP is offset by +0x80, and the second offset address IP corresponding to the measurement result is 0x1180. The result data is stored at the second offset address 0x1180.
[0060] In some optional implementations, the chip testing method further includes:
[0061] Send the test status identifier to the host computer module, the test status identifier includes a completed state and an uncompleted state; wherein the test status identifier may refer to a state identifier for testing the target device under test; the completed state may refer to a state in which the test of the target device under test has been completed; and the uncompleted state may refer to a state in which the test of the target device under test has not been completed. Specifically, the test status identifier may be determined based on whether the result data is stored in the storage module.
[0062] When the result data is stored in the storage module, the test status flag is updated from the unfinished state to the completed state, and the result data is sent to the host computer module. If the result data is not stored in the storage module, it is in the unfinished state.
[0063] In some optional embodiments, the multi-channel module includes at least one first channel unit, and sending test data to the multi-channel module so that the multi-channel module tests the target device under test based on the test data includes: sending the test data to at least one first channel unit in parallel and synchronously so that the at least one first channel unit tests at least two target devices under test based on the test data.
[0064] The first channel unit may refer to a BE board. Specifically, at least one BE board may be provided in the multi-channel module, and the configuration parameters in the test data may be sent to at least one BE board in parallel and synchronously, so that at least one BE board provides corresponding current and voltage for the target device under test (DUT) based on the current and voltage in the configuration parameters, and samples the channel corresponding to at least one BE board through the sampling module, thereby obtaining the test result data of the DUT.
[0065] In some optional embodiments, the first channel unit includes at least two second channel units, the second channel unit includes at least two third channel units, and the test data is sent to at least one first channel unit in parallel and synchronously, so that at least one first channel unit tests at least two target devices under test based on the test data, including: sending the test data to at least two second channel units in parallel and synchronously, so that at least two second channel units test at least two target devices under test based on the test data; wherein the second channel unit may refer to a FE board. Specifically, at least two FE boards may be provided in the BE board, and the configuration parameters in the test data are sent to at least two FE boards in parallel and synchronously, so that at least two FE boards provide corresponding current and voltage for the target device under test (DUT) based on the current and voltage in the configuration parameters, and the channels corresponding to at least two FEs are sampled through the sampling module, thereby obtaining the test result data of the DUT.
[0066] In some optional implementations, sending the test data to at least two second channel units in parallel and synchronously so that the at least two second channel units test at least two target devices under test based on the test data includes:
[0067] The test data is sent to at least two third channel units in parallel and synchronously, so that the at least two third channel units test at least two target devices under test based on the test data.
[0068] The third channel unit may refer to a PE chip. Specifically, at least two PE chips may be provided in the FE board, and the configuration parameters in the test data may be sent to the at least two PE chips in parallel and synchronously, so that the at least two PE chips provide corresponding current and voltage for the target device under test (DUT) based on the current and voltage in the configuration parameters, and the channels corresponding to the at least two PE chips are sampled through the sampling module to obtain the test result data of the DUT.
[0069] In some optional implementations, the first channel unit includes a first execution subunit, and the second channel unit includes a second execution subunit; and the test data is sent to at least one first channel unit in parallel and synchronously, so that the at least one first channel unit tests at least two target devices under test based on the test data, including:
[0070] The test data is sent to at least one first channel unit in parallel and synchronously through the first execution subunit, so that the at least one first channel unit tests at least two target devices under test based on the test data; wherein the first execution subunit may refer to an FPGA provided in the BE board.
[0071] The test data is sent to at least two second channel units in parallel and synchronously, so that the at least two second channel units test at least two target devices under test based on the test data, including:
[0072] The test data is sent to at least two second channel units in parallel and synchronously through the second execution subunit, so that at least two second channel units test multiple target devices under test based on the test data. The second execution subunit may refer to an FPGA provided in the FE board.
[0073] In some optional implementations, the test data includes: acquisition instructions;
[0074] Before receiving the result data sent by the sampling module and storing the result data in the storage module based on the data identification number, the method further includes:
[0075] The acquisition instruction is sent to the sampling module, so that the sampling module samples the channel of the third channel unit to obtain the result data. The sampling module is connected to the PE chip in the multi-channel module. When the sampling module receives the acquisition instruction in the test data sent by the PE chip, it can sample the channel of the PE chip to obtain the test result data of the DUT.
[0076] Figure 4 The schematic diagram of the structure of a chip testing device provided in the third embodiment of the present application is applied to a chip testing system, which includes a host computer module, a storage module, a multi-channel module and a sampling module, such as Figure 4 As shown, the device comprises:
[0077] The receiving module 310 is used to receive the test instruction sent by the host computer module, and the test instruction includes a data identification number;
[0078] The sending module 320 is used to read the corresponding test data from the storage module based on the test instruction, and send the test data to the multi-channel module, so that the multi-channel module tests the target device under test based on the test data;
[0079] The acquisition storage module 330 is used to receive the result data sent by the sampling module and store the result data in the storage module based on the data identification number;
[0080] The sending module 340 is used for sending the result data to the host computer module in response to the result data being stored in the storage module.
[0081] Optionally, the test data includes at least one configuration parameter, and the chip testing device further includes an acquisition module, configured to:
[0082] Bind the data identification number to the standard address IP in the storage module;
[0083] Based on the standard address IP, obtaining at least one first offset address IP;
[0084] The configuration parameters are pre-stored at the first offset address IP.
[0085] Optionally, the storage module 330 is specifically used for:
[0086] Based on the data identification number, obtain the standard address IP;
[0087] Based on the standard address IP, obtaining at least one second offset address IP, where the second offset address IP is different from the first offset address IP;
[0088] The result data is stored at the second offset address IP.
[0089] Optionally, the chip testing device further includes an updating module, which is used to:
[0090] Send the test status identification to the host computer module, the test status identification includes completion status and unfinished status;
[0091] When the result data is stored in the storage module, the test status flag is updated from an unfinished state to a completed state, and the result data is sent to the host computer module.
[0092] Optionally, the multi-channel module includes at least one first channel unit, the sending module 320, which is specifically used for:
[0093] The test data is sent to at least one first channel unit in parallel and synchronously, so that the at least one first channel unit tests at least two target devices under test based on the test data.
[0094] Optionally, the first channel unit includes at least two second channel units, the second channel unit includes at least two third channel units, and the test data is sent to at least one first channel unit in parallel and synchronously. The sending module 320 is specifically used for:
[0095] Sending the test data to at least two second channel units in parallel and synchronously, so that the at least two second channel units test at least two target devices under test based on the test data;
[0096] The test data is sent to at least two second channel units in parallel and synchronously. The sending module 320 is specifically used for:
[0097] The test data is sent to at least two third channel units in parallel and synchronously, so that the at least two third channel units test at least two target devices under test based on the test data.
[0098] Optionally, the first channel unit includes a first execution subunit, and the second channel unit includes a second execution subunit; the test data is sent to at least one first channel unit in parallel and synchronously, and the sending module 320 is specifically used for:
[0099] The test data is sent to at least one first channel unit in parallel and synchronously through the first execution subunit, so that the at least one first channel unit tests at least two target devices under test based on the test data;
[0100] The test data is sent to at least two second channel units in parallel and synchronously, so that the at least two second channel units test at least two target devices under test based on the test data, including:
[0101] The test data is sent to at least two second channel units in parallel and synchronously through the second execution subunit, so that the at least two second channel units test the multiple target devices under test based on the test data.
[0102] Optionally, the test data includes: acquisition instructions;
[0103] The chip testing device further includes an acquisition module, which is used to:
[0104] The acquisition instruction is sent to the sampling module, so that the sampling module samples the channel of the third channel unit to obtain result data.
[0105] The chip testing device provided in the embodiments of the present application can execute the chip testing method provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method.
[0106] Figure 5 This is a framework diagram of a chip testing system provided in Example 4 of the present application. Figure 5 As shown, the system includes: a host computer module 410, an execution module 420, a multi-channel module 430, a sampling module 440 and a storage module 450. The host computer module 410 is connected to the execution module 420, the execution module 420 is connected to the multi-channel module 430, the multi-channel module 430 is connected to the DUT, the sampling module 440 is connected to both the execution module 420 and the multi-channel module 430, and the storage module 450 is connected to both the execution module 420 and the host computer module 410.
[0107] The execution module is used to execute the chip testing method of any embodiment of the present application.
[0108] For example, Figure 6 The operation flow chart of a chip test system parallel measurement provided in the fourth embodiment of the present application is as follows: Figure 6 As shown, the operation process of parallel measurement through the chip test system is as follows:
[0109] 1. The host computer module (ATE software) generates a detection command in response to the user's operation request and sends it to the execution module (FPGA) through serial operation.
[0110] 2. The execution module reads the test data from the storage module (shared memory) based on the received detection command.
[0111] 3. The execution module sends the read test data in parallel to the multi-channel module (FE board, PE chip) for measurement. The multi-channel module includes multiple FE boards and PE chips.
[0112] 4. The PE chip writes the test data into the DUT. The test data includes channel information and configuration test parameters. The DUT is configured by configuring the parameters in the test data to provide current and voltage for the DUT.
[0113] 5. Sample the PE chip through the sampling module (ADC) to obtain the measurement result data of the DUT.
[0114] 6. After the measurement is completed, the sampling module returns the result data to the execution module, and the execution module stores the returned result data in the storage module.
[0115] 7. After the result data is stored, the host computer module can obtain the result data from the storage module.
[0116] In some embodiments, the chip testing method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium. In some embodiments, part or all of the computer program may be loaded and / or installed on an electronic device via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of a chip testing method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform a chip testing method in any other appropriate manner (e.g., by means of firmware).
[0117] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
[0118] The computer program for implementing the chip testing method of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.
[0119] In the context of the present application, a computer-readable storage medium stores computer instructions, which are used to implement the chip testing method provided by the present application when the processor executes. The computer-readable storage medium may be a tangible medium, which may contain or store a computer program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. The computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the above. Alternatively, the computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.
[0120] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD monitor)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball), through which the user may provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).
[0121] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by digital data communication (e.g., a communication network) in any form or medium. Examples of communication networks include: Local Area Network (LAN), Wide Area Network (WAN), blockchain network, and the Internet.
[0122] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and virtual private servers (VPS) services.
[0123] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution of this application can be achieved, and this document is not limited here.
[0124] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.
Claims
1. A chip testing method, characterized in that: An execution module applied to a chip test system, the chip test system further comprising a host computer module, a storage module, a multi-channel module and a sampling module, including: Receiving a test instruction sent by the host computer module, wherein the test instruction includes a data identification number; Reading corresponding test data from the storage module based on the test instruction, and sending the test data to the multi-channel module, so that the multi-channel module tests the target device under test based on the test data; receiving result data sent by the sampling module, and storing the result data in the storage module based on the data identification number; In response to the result data being stored in the storage module, the result data is sent to the host computer module.
2. The method according to claim 1, characterized in that The test data includes at least one configuration parameter. Before reading the corresponding test data from the storage module based on the test instruction, the method further includes: Binding the data identification number to the standard address IP in the storage module; Based on the standard address IP, obtaining at least one first offset address IP; The configuration parameters are pre-stored in the first offset address IP.
3. The method according to claim 2, characterized in that The receiving the result data sent by the sampling module and storing the result data in the storage module based on the data identification number includes: Based on the data identification number, obtaining the standard address IP; Based on the standard address IP, obtaining at least one second offset address IP, where the second offset address IP is different from the first offset address IP; The result data is stored at the second offset address IP.
4. The method according to claim 1, characterized in that Also includes: Sending a test status identifier to the host computer module, wherein the test status identifier includes a completed state and an uncompleted state; When the result data is stored in the storage module, the test status identifier is updated from the unfinished state to the completed state, and the result data is sent to the host computer module.
5. The method according to claim 1, characterized in that The multi-channel module includes at least one first channel unit, and sending the test data to the multi-channel module so that the multi-channel module tests the target device under test based on the test data includes: The test data is sent to the at least one first channel unit in parallel and synchronously, so that the at least one first channel unit tests at least two target devices under test based on the test data.
6. The method according to claim 5, characterized in that The first channel unit includes at least two second channel units, the second channel unit includes at least two third channel units, and the test data is sent to the at least one first channel unit in parallel and synchronously so that the at least one first channel unit tests at least two target devices under test based on the test data, including: Sending the test data to the at least two second channel units in parallel and synchronously, so that the at least two second channel units test at least two target devices under test based on the test data; The step of sending the test data to the at least two second channel units in parallel and synchronously so that the at least two second channel units test at least two target devices under test based on the test data includes: The test data is sent to the at least two third channel units in parallel and synchronously, so that the at least two third channel units test at least two target devices under test based on the test data.
7. The method according to claim 6, characterized in that The first channel unit includes a first execution subunit, and the second channel unit includes a second execution subunit; the step of sending the test data to the at least one first channel unit in parallel and synchronously so that the at least one first channel unit tests at least two target devices under test based on the test data includes: The test data is sent to the at least one first channel unit in parallel and synchronously through the first execution subunit, so that the at least one first channel unit tests at least two target devices under test based on the test data; The step of sending the test data to the at least two second channel units in parallel and synchronously, so that the at least two second channel units test at least two target devices under test based on the test data, comprises: The test data is sent to the at least two second channel units in parallel and synchronously through the second execution subunit, so that the at least two second channel units test the plurality of target devices under test based on the test data.
8. The method according to claim 6, characterized in that The test data includes: acquisition instructions; Before receiving the result data sent by the sampling module and storing the result data in the storage module based on the data identification number, the method further includes: The acquisition instruction is sent to the sampling module, so that the sampling module samples the channel of the third channel unit to obtain result data.
9. A chip testing device, characterized in that: Applied to a chip testing system, the chip testing system includes a host computer module, a storage module, a multi-channel module and a sampling module, and the device includes: A receiving module, used for receiving a test instruction sent by the host computer module, wherein the test instruction includes a data identification number; A sending module, configured to read corresponding test data from the storage module based on the test instruction, and send the test data to the multi-channel module, so that the multi-channel module tests the target device under test based on the test data; A collection and storage module, used for receiving the result data sent by the sampling module, and storing the result data in the storage module based on the data identification number; A sending module is used for sending the result data to the host computer module in response to the result data being stored in the storage module.
10. A chip testing system, characterized in that: The chip testing system comprises a host computer module, a storage module, a multi-channel module and a sampling module, and the chip testing system also comprises the chip testing device as claimed in claim 9.
Citation Information
Cited By
Metering module detection method and system of ultrasonic water meter
CN121252930A