Inspection method and inspection system for power connection
By extracting the netlist with power supply information in the chip layout and performing power connection checks, the problem of difficulty in positioning the power connection in the prior art is solved, and the errors are quickly and accurately located, reducing the time of fault repair and safety risks.
Patent Information
- Application Number
- CN202411438991.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-02-25
AI Technical Summary
The prior art is difficult to quickly and accurately locate errors in chip power connections, resulting in delays in fault repair and poses a major safety hazard.
By extracting the netlist with power supply information from the chip layout, checking according to the reference correspondence between the voltage domain and the power supply network, identifying mismatch in the power connection, and providing error prompt information to quickly locate the error.
It realizes quick search for power connection-related errors and accurately locates the error, reducing fault repair time and reducing safety hazards.
Smart Images
Figure CN119511153A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of layout design, and in particular to a method and system for checking power connection. Background Art
[0002] As the scale of chip integration increases, the frequency of clock signals that coordinate the work of various components is getting higher and higher. The noise impact of chips has received widespread attention and has become an issue that cannot be ignored in integrated circuit design. Multiple clock signals from the same clock source inside the chip are intertwined on the routing, and the driving units on each clock signal are scattered throughout the chip and powered by the power supply network. Due to the instability of the power supply and the coupling of the power supply and the high-frequency jump signal line, high-frequency jump noise exists on the pins VDD and GND of the power supply.
[0003] The current power connection inspection process can only rely on manual troubleshooting, which has great potential risks. For example, manual inspection is not comprehensive, cannot quickly find connection-related errors, and cannot accurately locate the location of the error, thus delaying the timely repair of the fault and causing great safety hazards. Summary of the invention
[0004] The object of the present invention is to provide a power connection inspection method and inspection system, which use separate voltage domains to power corresponding drive units to isolate the influence of each other's noise, and perform positioning inspection on power connections in multiple voltage domains, so as to quickly find connection-related errors and accurately locate the errors.
[0005] In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a method for checking power connection, the checking method comprising: extracting a netlist with power information from a chip layout, wherein the chip layout includes multiple driving units on a clock network, the multiple driving units are respectively distributed in multiple voltage domains, each voltage domain is provided with an independent power supply network, and the netlist with power information includes an actual correspondence between the voltage domains and the power supply networks; according to a reference correspondence between the voltage domains and the power supply networks, checking the actual correspondence included in the netlist with power information; and in the case that the actual correspondence included in the netlist with power information does not match the reference correspondence, providing an error prompt information, wherein the error prompt information includes the current voltage domain and the reference voltage domain where the unmatched unit is located.
[0006] Preferably, the multiple driving units include a first driving unit on the clock network from the frequency multiplier to the ADC module, and a second driving unit on the clock network from the frequency multiplier to the DAC module, and the multiple voltage domains include a first area and a second area, wherein the first driving unit is distributed in the first area, and the second driving unit is distributed in the second area.
[0007] Preferably, the multiple driving units further include: a third driving unit including the control module on a clock network from an output end of the NAND gate combination logic unit in the first driving unit to the control module, and the multiple voltage domains further include a third area, wherein the third driving unit is distributed in the third area.
[0008] Preferably, the inspection method further comprises: using a unified power supply format file to record the reference corresponding relationship.
[0009] Preferably, the checking the actual corresponding relationship included in the netlist with power supply information comprises: using a VCLP tool to check the actual corresponding relationship included in the netlist with power supply information.
[0010] Preferably, the chip layout is a layout under a non-uniform power supply format process.
[0011] Preferably, the checking method further comprises: determining that the power supply connections in the multiple voltage domains are correct when the actual corresponding relationship included in the netlist with power supply information matches the reference corresponding relationship.
[0012] Preferably, the chip layout is a broadband power line carrier communication chip layout.
[0013] Through the above technical scheme, the present invention creatively extracts a netlist with power supply information from a chip layout; checks the actual correspondence between the voltage domain and the power supply network included in the netlist with power supply information according to the reference correspondence between the voltage domain and the power supply network; and provides error prompt information when the actual correspondence included in the netlist with power supply information does not match the reference correspondence, wherein the error prompt information includes the current voltage domain and the reference voltage domain where the mismatching unit is located, thereby using a separate voltage domain to power the corresponding driving unit to isolate the influence of each other's noise, and performing positioning checks on the power connections in multiple voltage domains, so as to quickly find connection-related errors and accurately locate the errors.
[0014] A second aspect of the present invention provides a power connection inspection system, the inspection system comprising: an extraction device for extracting a netlist with power information from a chip layout, wherein the chip layout includes multiple driving units on a clock network, the multiple driving units are respectively distributed in multiple voltage domains, each voltage domain is provided with an independent power supply network, and the netlist with power information includes an actual correspondence between the voltage domains and the power supply networks; an inspection device for inspecting the actual correspondence included in the netlist with power information according to a reference correspondence between the voltage domains and the power supply networks; and a prompt device for providing an error prompt message when the actual correspondence included in the netlist with power information does not match the reference correspondence, wherein the error prompt message includes the current voltage domain and the reference voltage domain where the unmatched unit is located.
[0015] The specific details and benefits of the power connection inspection system provided by the embodiment of the present invention can be found in the above description of the power connection inspection method, which will not be repeated here.
[0016] A third aspect of the present invention provides a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the power supply connection checking method is implemented.
[0017] A fourth aspect of the present invention provides an electronic device, comprising: a processor; and a memory for storing a computer program, wherein the method for checking power connection is implemented when the computer program is executed by the processor.
[0018] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:
[0020] Figure 1 is a flow chart of a method for checking power connection provided by an embodiment of the present invention;
[0021] Figure 2 is a schematic diagram of a chip layout provided by an embodiment of the present invention;
[0022] Figure 3 is a flow chart of a power connection checking process provided by an embodiment of the present invention; and
[0023] Figure 4It is a schematic diagram of different areas of a chip layout provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0024] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.
[0025] Figure 1 FIG. 1 is a flow chart of a method for checking power connection provided by an embodiment of the present invention. Figure 1 As shown, the inspection method includes: step S101, extracting a netlist with power supply information from a chip layout, wherein the chip layout includes multiple driving units on a clock network, the multiple driving units are respectively distributed in multiple voltage domains, each voltage domain is provided with an independent power supply network, and the netlist with power supply information includes an actual correspondence between the voltage domains and the power supply networks; step S102, checking the actual correspondence included in the netlist with power supply information according to a reference correspondence between the voltage domains and the power supply networks; and step S103, providing error prompt information when the actual correspondence included in the netlist with power supply information does not match the reference correspondence, wherein the error prompt information includes the current voltage domain and the reference voltage domain where the unmatched unit is located.
[0026] The above steps are explained and illustrated below. The netlist with power supply information can be referred to as a PG netlist, which is a table used to describe the connection relationship between circuit elements.
[0027] Step S101, extracting a netlist with power supply information from a chip layout.
[0028] The chip layout includes multiple driving units on the clock network, the multiple driving units are respectively distributed in multiple voltage domains, each voltage domain is provided with an independent power supply network, and the netlist with power supply information includes the actual correspondence between the voltage domains and the power supply networks.
[0029] Wherein, the power supply network includes a power supply and a grounding network.
[0030] Specifically, due to the requirements of ADC (Analog-Digital Converter, analog-to-digital converter) / DAC (Digital-Analog Converter, digital-to-analog converter) for anti-interference ability, stability, and high-precision analog-to-digital / digital-to-analog conversion, the clock path from the frequency multiplier (e.g., phase-locked loop PLL) to the analog-to-digital converter (ADC) can be designed to use a separate voltage domain (e.g., the first region) to power its driving unit. The first region is powered by the following power supply network: power supply ADC_AVDD and ground ADC_AGND.
[0031] Due to the requirements of ADC / DAC anti-interference ability, stability and high-precision analog-to-digital / digital-to-analog conversion, the clock path from the frequency multiplier (e.g., phase-locked loop PLL) to the digital-to-analog converter (DAC) can be designed to use a separate voltage domain (e.g., the second region) to power its driving unit. The second region is powered by the following power supply network: power supply DAC_AVDD and ground DAC_AGND.
[0032] In one embodiment, the chip layout is a broadband power line carrier communication chip layout.
[0033] The broadband power line carrier communication chip can be used for electrical information collection. It is a digital-analog hybrid design chip, which includes high-precision analog circuit functional modules (IP) (for example, ADC / DAC / PLL, etc.). Due to the requirements of ADC / DAC for anti-interference ability, stability, and high-precision analog-to-digital / digital-to-analog conversion, a clean clock without crosstalk is desired. This requires that the clock path from PLL to ADC / DAC is completely clean and pure. Therefore, when this part of the clock is implemented, a separate voltage domain is used to power its transmission drive unit, and a separate power supply network is created to ensure the purity of the power supply, isolate the influence of noise, and ensure that the clock reaching the ADC / DAC is clean and pure.
[0034] In one embodiment, the multiple driving units include a first driving unit on a clock network from the frequency multiplier to the ADC module, and a second driving unit on a clock network from the frequency multiplier to the DAC module; and the multiple voltage domains include a first area and a second area.
[0035] The first driving units are distributed in a first area, and the second driving units are distributed in the second area.
[0036] Specifically, the first area can be an ADC domain; the second area can be a DAC domain. When the chip layout is implemented, in the layout and routing tool of the chip layout, the clock comes from the on-chip or off-chip crystal oscillator, and is multiplied by a frequency multiplier (such as PLL) to output, for example, a high-frequency 1.2G clock. The output clock network of the PLL includes the clock network of the ADC module and the clock network to the DAC module. The ADC domain is divided at the position from the frequency multiplier (such as PLL) to the ADC, and the DAC domain is divided at the position from the PLL to the DAC, such as Figure 2 shown.
[0037] The clock network from PLL 1 to ADC module 2 can be directly connected from PLL 1 to the clock of ADC module 2, without other logic circuits in between, because multiple buffers 3 can be added to the long trace. For the ADC domain, the first driver unit (e.g., multiple buffers 3) on the clock trace from (e.g., PLL) to ADC is placed in the ADC domain, and a separate power network is created for this area: the ADC domain uses ADC_AVDD and ADC_AGND, and the first driver unit is powered separately, such as Figure 4 shown.
[0038] After passing through the divider 4, multiplexer 5 and NAND gate combination logic unit 6, a 100M clock is divided from PLL 1, and then connected to the clock of DAC module 7 through buffer 1 unit. For the DAC domain, the second driving unit (for example, divider 4, multiplexer 5 and NAND gate combination logic unit 6, buffer 3) on the clock routing (for example, PLL) to DAC is placed in the DAC domain, and a separate power supply network is created for this area: the DAC domain uses DAC_AVDD and DAC_AGND, and the second driving unit is powered separately, such as Figure 4 shown.
[0039] In another embodiment, the plurality of driving units further include: a third driving unit including the control module on a clock network from an output end of the NAND gate combination logic unit in the first driving unit to the control module; and the plurality of voltage domains further include a third region.
[0040] Wherein, the third driving units are distributed in the third area.
[0041] The output clock network of the PLL also includes the TOP clock network. For the third area (which may be the Top domain), the third drive unit 10 (for example, a conventional control unit inside a chip such as at least one of the CPU, PLC, and SCU) including the control module 8 and corresponding drive accessories 9 such as QSPI, etc. on the clock routing from the NOT gate combinational logic unit 6 to the control module 8 (for example, at least one of the CPU, PLC, and SCU, etc.) is placed in the Top domain, and a separate power supply network is created for this area: the Top domain uses VDD and GND to supply power to the third drive unit 9 separately, such as Figure 4 shown.
[0042] The specific configuration of the first driving unit, the second driving unit and the third driving unit can be determined according to actual needs and existing methods. It is not the main improvement point of the present invention and will not be described in detail here.
[0043] Due to the requirements of ADC / DAC for anti-interference ability, stability and high-precision analog-to-digital / digital-to-analog conversion, it is hoped to obtain a clean clock without crosstalk. Therefore, in this embodiment, multiple voltage domains are designed and powered by separate power supplies respectively, so that the clock path from PLL to ADC / DAC is completely clean and pure, and a separate power supply network is created to ensure the purity of the power supply, isolate the influence of noise, and ensure that the clock reaching the ADC / DAC is clean and pure.
[0044] After the chip layout design is completed, the corresponding relationship between multiple voltage domains and corresponding power supply networks is obtained based on the chip layout, and stored in the PG (power and ground) netlist. For example, write_verilog is used to write a verilog netlist with PG information (i.e., a netlist with power information).
[0045] In one embodiment, the chip layout is a layout under a non-uniform power format process.
[0046] If each unit in the chip layout is designed to have no low power consumption requirements, the unified power format (UPF) design is no longer required when the front-end design is implemented, so the corresponding chip layout is a layout under a non-UPF process.
[0047] In one embodiment, before executing step S102, the inspection method further includes: recording the reference correspondence relationship in a unified power supply format file.
[0048] For example, a UPF file may be used to record the reference correspondence.
[0049] The reference correspondence between the voltage domains and the power supply networks is the correspondence between the multiple voltage domains to be implemented by the chip layout and the corresponding power supply networks.
[0050] If the circuit is described in Verilog or VHDL, it is impossible to include any chip power supply network information (such as reference correspondence), which will make subsequent processes such as power consumption verification and back-end implementation difficult to handle or prone to errors. The UPF standard can solve this problem very well, because the UPF standard contains a large number of tool command language (TCL) commands for describing power networks, which can be used to easily create the reference correspondence (such as power domains) and even create reference correspondences including power consumption control. The unified power consumption format file written in UPF file can be used not only at the RTL level, but also by back-end tools, which in a sense ensures the consistency of the power consumption process during the entire chip design process.
[0051] Step S102: checking the actual corresponding relationship included in the netlist with power supply information according to the reference corresponding relationship between the voltage domain and the power supply network.
[0052] For step S102, the checking of the actual corresponding relationship included in the netlist with power supply information includes: using a static rule checking tool to check the actual corresponding relationship included in the netlist with power supply information.
[0053] Among them, the static rule checking tool can be a VCLP tool, which refers to a low-power static rule checking tool. In this embodiment, the reference correspondence in UPF / PST is used to check the consistency of the PG netlist and check whether the design / netlist has missing / redundant low-power devices. Checking the consistency of the PG netlist includes checking whether the voltage domain and the power / ground connection in the PG netlist (which carries the voltage domain where the drive unit is located and the corresponding power and ground information) are consistent with the design intent (the reference correspondence), etc.
[0054] Step S103, when the actual corresponding relationship included in the netlist with power supply information does not match the reference corresponding relationship, providing error prompt information, wherein the error prompt information includes the current voltage domain and the reference voltage domain where the mismatching unit is located.
[0055] In one embodiment, the checking method further comprises: determining that the power supply connections in the multiple voltage domains are correct when the actual corresponding relationship included in the netlist with power supply information matches the reference corresponding relationship.
[0056] If the actual correspondence included in the PG netlist matches the reference correspondence (ie, the voltage domain and the power supply network are consistent), it is determined that the power supply connections within the multiple voltage domains are correct.
[0057] If the PG netlist shows that a unit is placed in the first area (such as the ADC domain), and the power supply in the chip layout is ADC_AVDD and ADC_AVSS, but the reference correspondence shows that the unit should be placed in the third area (such as the Top domain) and should be powered by VDD and VSS. At this time, it indicates that the power connection of the unit is wrong, and an error will be reported, and it will be given that the unit is currently in the first area (such as the ADC domain) and should be moved to the third area (such as the Top domain).
[0058] If the PG netlist shows that a unit is placed in the third area (such as the Top domain), and the power supply in the chip layout is VDD and VSS, but the reference correspondence shows that the unit should be placed in the second area (such as the DAC domain) and should be powered by DAC_AVDD and DAC_AVSS. At this time, it indicates that the power connection of the unit is wrong, and an error will be reported, and it will be given that the unit is currently in the third area (such as the Top domain) and should be moved to the second area (such as the DAC domain).
[0059] Then, make corrections on the chip layout according to the above prompts and re-execute the inspection process until no error message is prompted, indicating that the power connections of all units on the chip layout are correct.
[0060] The power connection inspection method for multiple voltage domains under the non-UPF process can avoid the incompleteness of manual inspection, verify the entire chip power network, quickly find connection-related errors, and accurately locate the errors. This method has the characteristics of comprehensive core function coverage, fast and accurate error location, and clear results.
[0061] Specifically, Figure 3 Taking the example of FIG. 1 as an example, the process of checking the power supply connection of multiple voltage domains is explained and illustrated.
[0062] Step 1: Power each voltage domain separately.
[0063] In the placement and routing tool of the chip layout, multiple driver units on the clock network are placed in corresponding voltage domains, and a separate power network is created for each voltage domain for separate power supply.
[0064] Step 2: Extract the PG netlist.
[0065] The PG netlist includes the correspondence between multiple voltage domains on the chip layout and the corresponding power supply networks.
[0066] Step 3: Write out the UPF file.
[0067] Write a UPF file according to the power supply required by the design: create an independent voltage domain for the separate power supply area, and specify the corresponding power supply network (including power supply and ground network). In other words, the UPF file provides a reference correspondence between the voltage domain and the power supply network.
[0068] Step 4: Check consistency using the VCLP tool.
[0069] Step 5: Determine whether an error message appears. If so, make corrections based on the VCLP inspection result (i.e., re-execute step 1 based on the inspection result); otherwise, execute step 6.
[0070] Step 6: Perform STA and PV follow-up operations.
[0071] STA operation refers to static timing analysis operation; PV operation refers to power verification operation.
[0072] Step 7: Send for manufacturing.
[0073] In summary, the present invention creatively extracts a netlist with power supply information from a chip layout; checks the actual correspondence between the voltage domains and the power supply network included in the netlist with power supply information according to the reference correspondence between the voltage domains and the power supply network; and provides error prompt information when the actual correspondence included in the netlist with power supply information does not match the reference correspondence, wherein the error prompt information includes the current voltage domain and the reference voltage domain where the unmatched unit is located, thereby using a separate voltage domain to power the corresponding driving unit to isolate the influence of each other's noise, and performing positioning checks on the power connections within multiple voltage domains, so as to quickly find connection-related errors and accurately locate the errors.
[0074] An embodiment of the present invention provides a power connection inspection system, the inspection system comprising: an extraction device for extracting a netlist with power information from a chip layout, wherein the chip layout comprises a plurality of drive units on a clock network, the plurality of drive units are respectively distributed in a plurality of voltage domains, each voltage domain is provided with an independent power supply network, and the netlist with power information comprises an actual correspondence between the voltage domains and the power supply networks; an inspection device for inspecting the actual correspondence included in the netlist with power information according to a reference correspondence between the voltage domains and the power supply networks; and a prompt device for providing an error prompt message when the actual correspondence included in the netlist with power information does not match the reference correspondence, wherein the error prompt message comprises a current voltage domain and a reference voltage domain where the unmatched unit is located.
[0075] Preferably, the multiple driving units include a first driving unit on the clock network from the frequency multiplier to the ADC module, and a second driving unit on the clock network from the frequency multiplier to the DAC module, and the multiple voltage domains include a first area and a second area, wherein the first driving unit is distributed in the first area, and the second driving unit is distributed in the second area.
[0076] Preferably, the multiple driving units further include: a third driving unit including the control module on a clock network from an output end of the NAND gate combination logic unit in the first driving unit to the control module, and the multiple voltage domains further include a third area, wherein the third driving unit is distributed in the third area.
[0077] Preferably, the inspection system further comprises: a recording device for recording the reference correspondence relationship in a unified power supply format file.
[0078] Preferably, the checking device is used to check the actual corresponding relationship included in the netlist with power supply information, including: using a static rule checking tool to check the actual corresponding relationship included in the netlist with power supply information.
[0079] Preferably, the chip layout is a layout under a non-uniform power supply format process.
[0080] Preferably, the prompting device is further used to determine that the power supply connections in the multiple voltage domains are correct when the actual corresponding relationship included in the netlist with power supply information matches the reference corresponding relationship.
[0081] Preferably, the chip layout is a broadband power line carrier communication chip layout.
[0082] The specific details and benefits of the power connection inspection system provided by the embodiment of the present invention can be found in the above description of the power connection inspection method, which will not be repeated here.
[0083] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the inspection method is implemented.
[0084] An embodiment of the present invention provides an electronic device, comprising: a processor; and a memory for storing a computer program, wherein when the computer program is executed by the processor, the power connection checking method is implemented.
[0085] An embodiment of the present invention provides a computer program product, including a computer program, which implements the power connection checking method when executed by a processor.
[0086] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.
[0087] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.
[0088] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a single-chip microcomputer, a chip or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.
[0089] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0090] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0091] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.
Claims
1. A method for checking power connection, characterized in that: The inspection method comprises: Extracting a netlist with power supply information from a chip layout, wherein the chip layout includes a plurality of driving units on a clock network, the plurality of driving units are respectively distributed in a plurality of voltage domains, each voltage domain is provided with an independent power supply network, and the netlist with power supply information includes an actual correspondence between the voltage domains and the power supply networks; According to the reference correspondence between the voltage domain and the power supply network, checking the actual correspondence included in the netlist with power supply information; and In the case that the actual corresponding relationship included in the netlist with power supply information does not match the reference corresponding relationship, an error prompt information is provided, wherein the error prompt information includes a current voltage domain and a reference voltage domain where the mismatching unit is located.
2. The inspection method according to claim 1, characterized in that: The plurality of driving units include a first driving unit on a clock network from the frequency multiplier to the ADC module, and a second driving unit on a clock network from the frequency multiplier to the DAC module, The plurality of voltage domains include a first region and a second region, The first driving units are distributed in a first area, and the second driving units are distributed in the second area.
3. The inspection method according to claim 2, characterized in that: The plurality of driving units further include: an output end of the NAND gate combination logic unit in the first driving unit to a third driving unit including the control module on the clock network of the control module, The plurality of voltage domains further include a third region, The third driving units are distributed in the third area.
4. The inspection method according to claim 1, characterized in that: The inspection method further includes: using a unified power supply format file to record the reference corresponding relationship.
5. The inspection method according to claim 1, characterized in that: The checking the actual corresponding relationship included in the netlist with power supply information includes: using a static rule checking tool to check the actual corresponding relationship included in the netlist with power supply information.
6. The inspection method according to claim 1, characterized in that: The chip layout is a layout under a non-uniform power supply format process.
7. The inspection method according to claim 1, characterized in that: The inspection method further comprises: In a case where the actual corresponding relationship included in the netlist with power supply information matches the reference corresponding relationship, it is determined that the power supplies in the multiple voltage domains are correctly connected.
8. The inspection method according to claim 1, characterized in that: The chip layout is a broadband power line carrier communication chip layout.
9. A power connection inspection system, characterized in that: The inspection system comprises: An extraction device is used to extract a netlist with power supply information from a chip layout, wherein the chip layout includes a plurality of driving units on a clock network, the plurality of driving units are respectively distributed in a plurality of voltage domains, each voltage domain is provided with an independent power supply network, and the netlist with power supply information includes an actual correspondence between the voltage domains and the power supply networks; A checking device, configured to check the actual corresponding relationship included in the netlist with power supply information according to a reference corresponding relationship between the voltage domain and the power supply network; and A prompt device is used to provide error prompt information when the actual corresponding relationship included in the netlist with power supply information does not match the reference corresponding relationship, wherein the error prompt information includes the current voltage domain and the reference voltage domain where the mismatching unit is located.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the method for checking power connection according to any one of claims 1 to 6.
11. An electronic device, characterized in that: The electronic device comprises: Processor; and A memory for storing a computer program, which, when executed by the processor, implements the method for checking power connection according to any one of claims 1 to 6.